1. General description
The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with
individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary
nQ and nQ out pu ts. Data at the nD-input, th at mee ts the set-u p and ho ld time
requirements on the LOW-to-HIGH clock transition, will be stored in the flip-flop and
appear at the nQ output. The Schmitt-trigger action in the clock input, makes the circuit
highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Spe cified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC74-Q100: CMOS level
For 74HCT74-Q10 0: TTL level
Symmetrical output impedance
Low power dissipation
High noise immunity
Balanced propagation delays
Specified in compliance with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
Rev. 3 — 4 December 2015 Product data sheet
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 2 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC74D-Q100 40 C to +125 C SO14 plastic small outline package; 14 leads; body
width 3.9 mm SOT108-1
74HCT74D-Q100
74HC74PW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package;
14 leads; body width 4.4 m m SOT402-1
74HCT74PW-Q100
74HC74BQ-Q100 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal
enhanced very thin quad flat package; no
leads; 14 terminals; body 2.5 30.85 mm
SOT762-1
74HCT74BQ-Q100
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Functional diagram
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 3 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
5. Pinning information
5.1 Pinning
Fig 4. Logic diagram for one flip-flop
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pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration for SO14 and TSSOP14 Fig 6. Pin configuration for DHVQFN14
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 4 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
[1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition;
X = don’t care.
Table 2. Pin description
Symbol Pin Description
1RD 1 asynchronous reset-direct input (active LOW)
1D 2 data input
1CP 3 clock input (LOW-to-HIGH, edge-triggered)
1SD 4 asynchronou s set-direct input (active LOW)
1Q 5 output
1Q 6 complement output
GND 7 ground (0 V)
2Q 8 complement output
2Q 9 output
2SD 10 asynchronous set-direct input (active LOW)
2CP 11 clock input (LOW-to-HIGH, edge-triggered)
2D 12 data input
2RD 13 asynchronous reset-direct input (active LOW)
VCC 14 supply voltage
Table 3. Function table[1]
Input Output
nSDnRDnCP nD nQ nQ
LHXXHL
HLXXLH
LLXXHH
Table 4. Function table[1]
Input Output
nSDnRDnCP nD nQn+1 nQn+1
HHLLH
HHHHL
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 5 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
7. Limiting values
[1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 packages: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
9. Static characteristics
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V - 20 mA
IOoutput current VO = 0.5 V to (VCC +0.5V) - 25 mA
ICC supply current - +100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation DIP14 package [1] - 750 mW
SO14, TSSOP14 and DHVQFN14
packages [1] - 500 mW
Table 6. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC74-Q100 74HCT74-Q100 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
74HC74-Q100
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - V
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 6 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
[1] All typical values are measured at Tamb =25C.
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=4.0 mA; VCC = 4.5 V 3.84 4.32 - 3.7 - V
IO=5.2 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO=4.0mA; V
CC = 4.5 V - 0.15 0.33 - 0.4 V
IO=5.2mA; V
CC = 6.0 V - 0.16 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =6.0V --1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V --40 - 80A
CIinput
capacitance -3.5- - -pF
74HCT74-Q100
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO=4 mA 3.84 4.32 - 3.7 - V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
IO= 4.0 mA - 0.15 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND;
VCC =5.5V --1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V --40 - 80A
ICC additional
supply current VI=V
CC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO=0A
per input pin; nD, nRD
inputs - 70 315 - 343 A
per input pin; nSD, nCP
input - 80 360 - 392 A
CIinput
capacitance -3.5- - -pF
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 7 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
10. Dynamic characteristics
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
74HC74-Q100
tpd propagation
delay nCP to nQ, nQ; see
Figure 7 [2]
VCC = 2.0 V - 47 220 - 265 ns
VCC = 4.5 V - 17 44 - 53 ns
VCC =5V; C
L=15pF - 14 - - - ns
VCC = 6.0 V - 14 37 - 45 ns
nSD to nQ, nQ; see
Figure 8 [2]
VCC = 2.0 V - 50 250 - 300 ns
VCC = 4.5 V - 18 50 - 60 ns
VCC =5V; C
L=15pF - 15 - - - ns
VCC = 6.0 V - 14 43 - 51 ns
nRD to nQ, nQ; see
Figure 8 [2]
VCC = 2.0 V - 52 250 - 300 ns
VCC = 4.5 V - 19 50 - 60 ns
VCC =5V; C
L=15pF - 16 - - - ns
VCC = 6.0 V - 15 43 - 51 ns
tttransition
time nQ, nQ; see Figure 7 [3]
VCC = 2.0 V - 19 95 - 110 ns
VCC = 4.5 V - 7 19 - 22 ns
VCC = 6.0 V - 6 16 - 19 ns
tWpulse width nCP HIGH or LOW;
see Figure 7
VCC = 2.0 V 100 19 - 120 - ns
VCC = 4.5 V 20 7 - 24 - ns
VCC = 6.0 V 17 6 - 20 - ns
nSD, nRD LOW;
see Figure 8
VCC = 2.0 V 100 19 - 120 - ns
VCC = 4.5 V 20 7 - 24 - ns
VCC = 6.0 V 17 6 - 20 - ns
trec recovery
time nSD, nRD; see Figure 8
VCC = 2.0 V 40 3 - 45 - ns
VCC = 4.5 V 8 1 - 9 - ns
VCC = 6.0 V 7 1 - 8 - ns
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 8 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
tsu set-up time nD to nCP; see Figure 7
VCC = 2.0 V 75 6 - 90 - ns
VCC = 4.5 V 15 2 - 18 - ns
VCC = 6.0 V 13 2 - 15 - ns
thhold time nD to nCP; see Figure 7
VCC = 2.0 V 3 6- 3 -ns
VCC = 4.5 V 3 2- 3 -ns
VCC = 6.0 V 3 2- 3 -ns
fmax maximum
frequency nCP; see Figure 7
VCC = 2.0 V 4.8 23 - 4.0 - MHz
VCC = 4.5 V 24 69 - 20 - MHz
VCC =5V; C
L=15pF - 76 - - - MHz
VCC = 6.0 V 28 82 - 24 - MHz
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC
[4] -24 - - -pF
74HCT74-Q100
tpd propagation
delay nCP to nQ, nQ; see
Figure 7 [2]
VCC = 4.5 V - 18 44 - 53 ns
VCC =5V; C
L=15pF - 15 - - - ns
nSD to nQ, nQ; see
Figure 8 [2]
VCC = 4.5 V - 23 50 - 60 ns
VCC =5V; C
L=15pF - 18 - - - ns
nRD to nQ, nQ; see
Figure 8 [2]
VCC = 4.5 V - 24 50 - 60 ns
VCC =5V; C
L=15pF - 18 - - - ns
tttransition
time nQ, nQ; see Figure 7 [3]
VCC = 4.5 V - 7 19 - 22 ns
tWpulse width nCP HIGH or LOW;
see Figure 7
VCC = 4.5 V 23 9 - 27 - ns
nSD, nRD LOW;
see Figure 8
VCC = 4.5 V 20 9 - 24 - ns
trec recovery
time nSD, nRD; see Figure 8
VCC = 4.5 V 8 1 - 9 - ns
tsu set-up time nD to nCP; see Figure 7
VCC = 4.5 V 15 5 - 18 - ns
Table 8. Dynamic characteristics …continu ed
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 9 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
[1] All typical values are measured at Tamb =25C.
[2] tpd is the same as tPLH and tPHL.
[3] tt is the same as tTHL and tTLH.
[4] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi = input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
thhold time nD to nCP; see Figure 7
VCC = 4.5 V 3 3- 3 -ns
fmax maximum
frequency nCP; see Figure 7
VCC = 4.5 V 22 54 - 18 - MHz
VCC =5V; C
L=15pF - 59 - - - MHz
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC 1.5 V [4] -29 - - -pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 CUnit
Min Typ[1] Max Min Max
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 10 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
11. Waveforms
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width and the
maximum frequency (CP)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 11 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. The s e t (nSD) and reset (nRD) input to output (nQ,nQ) propagation delays, set and reset pulse widths and
the nSD, nRD to nCP recovery time
Table 9. Measur ement points
Type Input Output
VMVM
74HC74-Q100 0.5VCC 0.5VCC
74HCT74-Q100 1.3 V 1.3 V
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 12 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 9. Test circuit for measuring switching times
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Type Input Load Test
VItr, tfCLRL
74HC74-Q100 VCC 6ns 15pF, 50 pF 1ktPLH, tPHL
74HCT74-Q100 3 V 6 ns 15 pF, 50 pF 1 ktPLH, tPHL
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 13 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
12. Package outline
Fig 10. Package outline SOT108-1 (SO14)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 14 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
Fig 11. Package outline SOT402-1 (TSSOP14)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 15 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
Fig 12. Package outline SOT762-1 (DHVQFN14)
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© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 16 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
13. Abbreviations
14. Revision history
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
ESD ElectroStatic Discharge
HBM Human Body Model
MIL Military
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT74_Q100 v.3 20151204 Product data sheet - 74HC_HCT74_Q100 v.2
Modifications: Type number 74HC74N-Q100 (SOT27-1) removed.
74HC_HCT74_Q100 v.2 20130906 Product data sheet - 74HC_HCT74_Q100 v.1
Modifications: 74HC74N-Q100 (DIP14) adde d.
74HC_HCT74_Q100 v.1 20120807 Product data sheet - -
© Nexperia B.V. 2017. All rights reserved
74HC_HCT74_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 3 — 4 December 2015 17 of 19
Nexperia 74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict wit h the short data sheet, the
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This Nexperia
product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and t her efo re su ch inclu si on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using Nexperia products, and Nexperia
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Nexperia does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the