MA80C186XL16 - Intel - Datasheet.Directory

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M80C186XL20, 16, 12, 10

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR

YLow Power, Full Static Version of

M80C186

YOperation Modes:

Ð Enhanced Mode

Ð DRAM Refresh Control Unit

Ð Power-Save Mode

Ð Direct Interface to 80C187

Ð Compatible Mode

Ð NMOS 80186 Pin-for-Pin

Replacement for Non-Numerics

Applications

YIntegrated Feature Set

Ð Static, Modular CPU

Ð Clock Generator

Ð 2 Independent DMA Channels

Ð Programmable Interrupt Controller

Ð 3 Programmable 16-Bit Timers

Ð Dynamic RAM Refresh Control Unit

Ð Programmable Memory and

Peripheral Chip Select Logic

Ð Programmable Wait State Generator

Ð Local Bus Controller

Ð Power-Save Mode

Ð System-Level Testing Support (High

Impedance Test Mode)

YCompletely Object Code Compatible

with Existing 8086/8088 Software and

Has 10 Additional Instructions over

8086/8088

YSpeed Versions Available

Ð 20 MHz (M80C186XL20)

Ð 16 MHz (M80C186XL16)

Ð 12.5 MHz (M80C186XL12)

Ð 10 MHz (M80C186XL)

YDirect Addressing Capability to

1 MByte Memory and 64 Kbyte I/O

YComplete System Development

Support

Ð All 8086 and 80C186 Software

Development Tools Can Be Used for

M80C186XL System Development

Ð ASM 86 Assembler, PL/M-86,

Pascal-86, Fortran-86, iC-86 and

System Utilities

Ð In-Circuit-Emulator (ICETM-186)

YAvailable in 68-Pin:

Ð Ceramic Pin Grid Array (PGA)

YMilitary Temperature Range:

Ðb55§Ctoa

125§C(T

)

The Intel M80C186XL is a Modular Core re-implementation of the M80C186 microprocessor. It offers higher

speed and lower power consumption than the standard M80C186 but maintains 100% clock-for-clock func-

tional compatibility. Packaging and pinout are also identical.

271276–1

M80C186XL20, 16, 12, 10

16-BIT HIGH INTEGRATION EMBEDDED PROCESSOR

CONTENTS PAGE

INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 10

M80C186XL BASE ARCHITECTURE ÀÀÀÀÀ 10

M80C186XL Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀ 10

Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11

M80C186XL PERIPHERAL

ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 11

Chip-Select/Ready Generation Logic ÀÀÀÀÀÀ 11

DMA Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12

Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12

Interrupt Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12

Enhanced Mode Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12

Queue-Status Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 12

DRAM Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13

Power-Save Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13

Interface for 80C187 Math

Coprocessor ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13

ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 13

ABSOLUTE MAXIMUM RATINGS ÀÀÀÀÀÀÀÀ 14

DC CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 14

CONTENTS PAGE

AC CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16

Major Cycle Timings (Read Cycle) ÀÀÀÀÀÀÀÀÀ 16

Major Cycle Timings (Write Cycle) ÀÀÀÀÀÀÀÀÀ 18

Major Cycle Timings (Interrupt

Acknowledge Cycle) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 20

Software Halt Cycle Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22

Clock Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23

Ready, Peripheral and Queue Status

Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 25

Reset and Hold/HLDA Timings ÀÀÀÀÀÀÀÀÀÀÀÀ 27

AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 33

EXPLANATION OF THE AC

SYMBOLS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36

DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37

M80C186XL EXECUTION TIMINGS ÀÀÀÀÀÀ 38

INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 39

FOOTNOTES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 44

M80C186XL

Figure 1. M80C186XL Block Diagram

271276–2

M80C186XL

Ceramic Pin Grid Array

Pins Facing Up Pins Facing Down

271276–3

NOTE:

XXXXXXXXA indicates the Intel FPO number.

Figure 2. M80C186XL Pinout Diagrams

M80C186XL

Table 1. M80C186XL Pin Description

Symbol PGA Type Name and Function

Pin No.

VCC 9 I System Power: a5 volt power supply.

43 I

VSS 26 I System Ground.

60 I

RESET 57 O RESET Output indicates that the M80C186XL CPU is being reset, and

can be used as a system reset. It is active HIGH, synchronized with

the processor clock, and lasts an integer number of clock periods

corresponding to the length of the RES signal. Reset goes inactive 2

clockout periods after RES goes inactive. When tied to the TEST/

BUSY pin, RESET forces the M80C186XL into enhanced mode.

RESET is not floated during bus hold.

X1 59 I Crystal Inputs X1 and X2 provide external connections for a

fundamental mode or third overtone parallel resonant crystal for the

X2 58 O

internal oscillator. X1 can connect to an external clock instead of a

crystal. In this case, minimize the capacitance on X2. The input or

oscillator frequency is internally divided by two to generate the clock

signal (CLKOUT).

CLKOUT 56 O Clock Output provides the system with a 50% duty cycle waveform.

All device pin timings are specified relative to CLKOUT. CLKOUT is

active during reset and bus hold.

RES 24 I An active RES causes the M80C186XL to immediately terminate its

present activity, clear the internal logic, and enter a dormant state.

This signal may be asynchronous to the M80C186XL clock. The

M80C186XL begins fetching instructions approximately 6(/2 clock

cycles after RES is returned HIGH. For proper initialization, VCC must

be within specifications and the clock signal must be stable for more

than 4 clocks with RES held LOW. RES is internally synchronized.

This input is provided with a Schmitt-trigger to facilitate power-on RES

generation via an RC network.

TEST/BUSY 47 I/O The TEST pin is sampled during and after reset to determine whether

the M80C186XL is to enter Compatible or Enhanced Mode. Enhanced

Mode requires TEST to be HIGH on the rising edge of RES and LOW

four CLKOUT cycles later. Any other combination will place the

M80C186XL in Compatible Mode. During power-up, active RES is

required to configure TEST/BUSY as an input. A weak internal pullup

ensures a HIGH state when the input is not externally driven.

TESTÐIn Compatible Mode this pin is configured to operate as TEST.

This pin is examined by the WAIT instruction. If the TEST input is

HIGH when WAIT execution begins, instruction execution will

suspend. TEST will be resampled every five clocks until it goes LOW,

at which time execution will resume. If interrupts are enabled while the

M80C186XL is waiting for TEST, interrupts will be serviced.

BUSYÐIn Enhanced Mode, this pin is configured to operate as

BUSY. The BUSY input is used to notify the M80C186XL of Math

Coprocessor activity. Floating point instructions executing in the

M80C186XL sample the BUSY pin to determine when the Math

Coprocessor is ready to accept a new command. BUSY is active

HIGH.

M80C186XL

Table 1. M80C186XL Pin Description (Continued)

Symbol PGA Type Name and Function

Pin No.

TMR IN 0 20 I Timer Inputs are used either as clock or control signals,

depending upon the programmed timer mode. These inputs are

TMR IN 1 21 I

active HIGH (or LOW-to-HIGH transitions are counted) and

internally synchronized. Timer Inputs must be tied HIGH when

not being used as clock or retrigger inputs.

TMR OUT 0 22 O Timer outputs are used to provide single pulse or continous

waveform generation, depending upon the timer mode selected.

TMR OUT 1 23 O

These outputs are not floated during a bus hold.

DRQ0 18 I DMA Request is asserted HIGH by an external device when it is

ready for DMA Channel 0 or 1 to perform a transfer. These

DRQ1 19 I

signals are level-triggered and internally synchronized.

NMI 46 I The Non-Maskable Interrupt input causes a Type 2 interrupt. An

NMI transition from LOW to HIGH is latched and synchronized

internally, and initiates the interrupt at the next instruction

boundary. NMI must be asserted for at least one CLKOUT period.

The Non-Maskable Interrupt cannot be avoided by programming.

INT0 45 I Maskable Interrupt Requests can be requested by activating one

of these pins. When configured as inputs, these pins are active

INT1/SELECT 44 I

HIGH. Interrupt Requests are synchronized internally. INT2 and

INT2/INTA0 42 I/O INT3 may be configured to provide active-LOW interrupt-

INT3/INTA1/IRQ 41 I/O acknowledge output signals. All interrupt inputs may be

configured to be either edge- or level-triggered. To ensure

recognition, all interrupt requests must remain active until the

interrupt is acknowledged. When Slave Mode is selected, the

function of these pins changes (see Interrupt Controller section

of this data sheet).

A19/S6 65 O Address Bus Outputs (16– 19) and Bus Cycle Status (3– 6)

indicate the four most significant address bits during T1. These

A18/S5 66 O

signals are active HIGH.

A17/S4 67 O

A16/S3 68 O During T2,T

Wand T4, the S6 pin is LOW to indicate a CPU-

initiated bus cycle or HIGH to indicate a DMA-initiated or refresh

bus cycle. During the same T-states, S3, S4 and S5 are always

LOW. These outputs are floated during bus hold or reset.

AD15 1 I/O Address/Data Bus (0– 15) signals constitute the time multiplexed

memory or I/O address (T1) and data (T2,T

Wand T4) bus.

AD14 3 I/O

The bus is active HIGH. A0is analogous to BHE for the lower

AD13 5 I/O byte of the data bus, pins D7through D0. It is LOW during T1

AD12 7 I/O when a byte is to be transferred onto the lower portion of the bus

AD11 10 I/O in memory or I/O operations. These pins are floated during a bus

AD10 12 I/O hold or reset.

AD9 14 I/O

AD8 16 I/O

AD7 2 I/O

AD6 4 I/O

AD5 6 I/O

AD4 8 I/O

AD3 11 I/O

AD2 13 I/O

AD1 15 I/O

AD0 17 I/O

M80C186XL

Table 1. M80C186XL Pin Description (Continued)

Symbol PGA Type Name and Function

Pin No.

BHE 64 O The BHE (Bus High Enable) signal is analogous to A0 in that it is used

to enable data on to the most significant half of the data bus, pins D15–

D8. BHE will be LOW during T1when the upper byte is transferred and

will remain LOW through T3AND TW. BHE does not need to be latched.

BHE will float during HOLD or RESET.

In Enhanced Mode, BHE will also be used to signify DRAM refresh

cycles. A refresh cycle is indicated by both BHE and A0 being HIGH.

BHE and A0 Encodings

BHE A0 Function

Value Value

0 0 Word Transfer

0 1 Byte Transfer on upper half of data bus (D15–D8)

1 0 Byte Transfer on lower half of data bus (D7–D0)

1 1 Refresh

ALE/QS0 61 O Address Latch Enable/Queue Status 0 is provided by the M80C186XL

to latch the address. ALE is active HIGH, with addresses guaranteed

valid on the trailing edge.

WR/QS1 63 O Write Strobe/Queue Status 1 indicates that the data on the bus is to be

written into a memory or an I/O device. It is active LOW, and floats

during bus hold or reset. When the M80C186XL is in Queue Status

Mode, the ALE/QS0 and WR/QS1 pins provide information about

processor/instruction queue interaction.

QS1 QS0 Queue Operation

0 0 No queue operation

0 1 First opcode byte fetched from the queue

1 1 Subsequent byte fetched from the queue

1 0 Empty the queue

RD/QSMD 62 O/I Read Strobe is an active LOW signal which indicates that the

M80C186XL is performing a memory or I/O read cycle. It is guaranteed

not to go LOW before the A/D bus is floated. An internal pull-up

ensures that RD/QSMD is HIGH during RESET. Following RESET the

pin is sampled to determine whether the M80C186XL is to provide ALE,

RD, and WR, or queue status information. To enable Queue Status

Mode, RD must be connected to GND. RD will float during bus HOLD.

ARDY 55 I Asynchronous Ready informs the M80C186XL that the addressed

memory space or I/O device will complete a data transfer. The ARDY

pin accepts a rising edge that is asynchronous to CLKOUT and is active

HIGH. The falling edge of ARDY must be synchronized to the

M80C186XL clock. Connecting ARDY HIGH will always assert the

ready condition to the CPU. If this line is unused, it should be tied LOW

to yield control to the SRDY pin.

SRDY 49 I Synchronous Ready informs the M80C186XL that the addressed

memory space or I/O device will complete a data transfer. The SRDY

pin accepts an active-HIGH input synchronized to CLKOUT. The use of

SRDY allows a relaxed system timing over ARDY. This is accomplished

by elimination of the one-half clock cycle required to internally

synchonize the ARDY input signal. Connecting SRDY high will always

assert the ready condition to the CPU. If this line is unused, it should be

tied LOW to yield control to the ARDY pin.

M80C186XL

Table 1. M80C186XL Pin Description (Continued)

Symbol PGA Type Name and Function

Pin No.

LOCK 48 O LOCK output indicates that other system bus masters are not to gain

control of the system bus. LOCK is active LOW. The LOCK signal is

requested by the LOCK prefix instruction and is activated at the beginning

of the first data cycle associated with the instruction immediately following

the LOCK prefix. It remains active until the completion of that instruction.

No instruction prefetching will occur while LOCK is asserted. LOCK floats

during bus hold or reset.

S0 52 O Bus cycle status S0–S2 are encoded to provide bus-transaction

information:

S1 53 O

S2 54 O M80C186XL Bus Cycle Status Information

S2 S1 S0 Bus Cycle Initiated

0 0 0 Interrupt Acknowledge

0 0 1 Read I/O

0 1 0 Write I/O

0 1 1 Halt

1 0 0 Instruction Fetch

1 0 1 Read Data from Memory

1 1 0 Write Data to Memory

1 1 1 Passive (no bus cycle)

The status pins float during HOLD.

S2 may be used as a logical M/IO indicator, and S1 as a DT/R indicator.

HOLD 50 I HOLD indicates that another bus master is requesting the local bus. The

HOLD input is active HIGH. The M80C186XL generates HLDA (HIGH) in

HLDA 51 O

response to a HOLD request. Simultaneous with the issuance of HLDA,

the M80C186XL will float the local bus and control lines. After HOLD is

detected as being LOW, the M80C186XL will lower HLDA. When the

M80C186XL needs to run another bus cycle, it will again drive the local bus

and control lines.

In Enhanced Mode, HLDA will go low when a DRAM refresh cycle is

pending in the M80C186XL and an external bus master has control of the

bus. It will be up to the external master to relinquish the bus by lowering

HOLD so that the M80C186XL may execute the refresh cycle.

UCS 34 O/I Upper Memory Chip Select is an active LOW output whenever a memory

reference is made to the defined upper portion (1K– 256K block) of

memory. UCS does not float during bus hold. The address range activating

UCS is software programmable.

UCS and LCS are sampled upon the rising edge of RES. If both pins are

held low, the M80C186XL will enter ONCE Mode. In ONCE Mode all pins

assume a high impedance state and remain so until a subsequent RESET.

UCS has a weak internal pullup that is active during RESET to ensure that

the M80C186XL does not enter ONCE Mode inadvertently.

LCS 33 O/I Lower Memory Chip Select is active LOW whenever a memory reference is

made to the defined lower portion (1K– 256K) of memory. LCS does not

float during bus HOLD. The address range activating LCS is software

programmable.

M80C186XL

Table 1. M80C186XL Pin Description (Continued)

Symbol PGA Type Name and Function

Pin No.

LCS UCS and LCS are sampled upon the rising edge of RES. If both

pins are held low, the M80C186XL will enter ONCE Mode. In ONCE

(Continued)

Mode all pins assume a high impedance state and remain so until a

subsequent RESET. LCS has a weak internal pullup that is active

only during RESET to ensure that the M80C186XL does not enter

ONCE mode inadvertently.

MCS0/PEREQ 38 O/I Mid-Range Memory Chip Select signals are active LOW when a

memory reference is made to the defined mid-range portion of

MCS1/ERROR 37 O/I

memory (8K– 512K). These lines do not float during bus HOLD. The

MCS2 36 O address ranges activating MCS0– 3 are software programmable.

MCS3/NPS 35 O

In Enhanced Mode, MCS0 becomes a PEREQ input (Processor

Extension Request). When connected to the Math Coprocessor,

this input is used to signal the M80C186XL when to make numeric

data transfers to and from the coprocessor. MCS3 becomes NPS

(Numeric Processor Select) which may only be activated by

communication to the 80C187. MCS1 becomes ERROR in

Enhanced Mode and is used to signal numerics coprocessor errors.

MCS0/PEREQ and MCS1/ERROR have weak internal pullups

which are active during reset.

PCS0 25 O Peripheral Chip Select signals 0–4 are active LOW when a

reference is made to the defined peripheral area (64K byte I/O or 1

PCS1 27 O

MByte memory space). These lines do not float during bus HOLD.

PCS2 28 O The address ranges activating PCS0– 4 are software

PCS3 29 O programmable.

PCS4 30 O

PCS5/A1 31 O Peripheral Chip Select 5 or Latched A1 may be programmed to

provide a sixth peripheral chip select, or to provide an internally

latched A1 signal. The address range activating PCS5 is software-

programmable. PCS5/A1 does not float during bus HOLD. When

programmed to provide latched A1, this pin will retain the previously

latched value during HOLD.

PCS6/A2 32 O Peripheral Chip Select 6 or Latched A2 may be programmed to

provide a seventh peripheral chip select, or to provide an internally

latched A2 signal. The address range activating PCS6 is software-

programmable. PCS6/A2 does not float during bus HOLD. When

programmed to provide latched A2, this pin will retain the previously

latched value during HOLD.

DT/R 40 O Data Transmit/Receive controls the direction of data flow through

an external data bus transceiver. When LOW, data is transferred to

the M80C186XL. When HIGH the M80C186XL places write data on

the data bus. DT/R floats during a bus hold or reset.

DEN 39 O Data Enable is provided as a data bus transceiver output enable.

DEN is active LOW during each memory and I/O access (including

80C187 access). DEN is HIGH whenever DT/R changes state.

During RESET, DEN is driven HIGH for one clock, then floated.

DEN also floats during HOLD.

N.C. Ð Ð Not connected. To maintain compatibility with future products, do

not connect to these pins.

M80C186XL

271276–4

(3a)

271276–5

(3b)

Note 1:

XTAL Frequency L1 Value

20 MHz 12.0 mHg20%

25 MHz 8.2 mHg20%

32 MHz 4.7 mHg20%

40 MHz 3.0 mHg20%

LC network is only required when using a third

overtone crystal.

Figure 3. M80C186XL Oscillator Configurations (see text)

INTRODUCTION

The following Functional Description describes the

base architecture of the M80C186XL. The

M80C186XL is a very high integration 16-bit micro-

processor. It combines 15–20 of the most common

microprocessor system components onto one chip.

The M80C186XL is object code compatible with the

8086/8088 microprocessors and adds 10 new in-

struction types to the 8086/8088 instruction set.

The M80C186XL has two major modes of operation,

Compatible and Enhanced. In Compatible Mode the

M80C186XL is completely compatible with NMOS

80186, with the exception of 8087 support. The En-

hanced mode adds three new features to the system

design. These are Power-Save control, Dynamic

RAM refresh, and an asynchronous Numerics Co-

processor interface.

M80C186XL BASE ARCHITECTURE

M80C186XL Clock Generator

The M80C186XL provides an on-chip clock genera-

tor for both internal and external clock generation.

The clock generator features a crystal oscillator, a

divide-by-two counter, synchronous and asynchro-

nous ready inputs, and reset circuitry.

The M80C186XL oscillator circuit is designed to be

used either with a parallel resonant fundamental or

third-overtone mode crystal, depending upon the

frequency range of the application. This is used as

the time base for the M80C186XL.

The output of the oscillator is not directly available

outside the M80C186XL. The recommended crystal

configuration is shown in Figure 3b. When used in

third-overtone mode, the tank circuit is recommend-

ed for stable operation. Alternately, the oscillator

may be driven from an external source as shown in

Figure 3a.

The crystal or clock frequency chosen must be twice

the required processor operating frequency due to

the internal divide by two counter. This counter is

used to drive all internal phase clocks and the exter-

nal CLKOUT signal. CLKOUT is a 50% duty cycle

processor clock and can be used to drive other sys-

tem components. All AC Timings are referenced to

CLKOUT.

Intel recommends the following values for crystal se-

lection parameters.

Temperature Range: Application Specific

ESR (Equivalent Series Resistance): 60Xmax

C0(Shunt Capacitance of Crystal): 7.0 pF max

C1(Load Capacitance): 20 pF g5pF

Drive Level: 2 mW max

M80C186XL

Bus Interface Unit

The M80C186XL provides a local bus controller to

generate the local bus control signals. In addition, it

employs a HOLD/HLDA protocol for relinquishing

the local bus to other bus masters. It also provides

outputs that can be used to enable external buffers

and to direct the flow of data on and off the local

bus.

The bus controller is responsible for generating 20

bits of address, read and write strobes, bus cycle

status information and data (for write operations) in-

formation. It is also responsible for reading data

from the local bus during a read operation. Synchro-

nous and asynchronous ready input pins are provid-

ed to extend a bus cycle beyond the minimum four

states (clocks).

The M80C186XL bus controller also generates two

control signals (DEN and DT/R) when interfacing to

external transceiver chips. This capability allows the

addition of transceivers for simple buffering of the

multiplexed address/data bus.

During RESET the local bus controller will perform

the following action:

#Drive DEN,RDand WR HIGH for one clock cy-

cle, then float them.

#Drive S0–S2 to the inactive state (all HIGH) and

then float.

#Drive LOCK HIGH and then float.

#Float AD0– 15, A16– 19, BHE, DT/R.

#Drive ALE LOW

#Drive HLDA LOW.

RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/

ERROR and TEST/BUSY pins have internal pullup

devices which are active while RES is applied. Ex-

cessive loading or grounding certain of these pins

causes the M80C186XL to enter an alternative

mode of operation:

#RD/QSMD low results in Queue Status Mode.

#UCS and LCS low results in ONCE Mode.

#TEST/BUSY low (and high later) results in En-

hanced Mode.

M80C186XL PERIPHERAL

ARCHITECTURE

All the M80C186XL integrated peripherals are con-

trolled by 16-bit registers contained within an inter-

nal 256-byte control block. The control block may be

mapped into either memory or I/O space. Internal

logic will recognize control block addresses and re-

spond to bus cycles. An offset map of the 256-byte

control register block is shown in Figure 4.

Chip-Select/Ready Generation Logic

The M80C186XL contains logic which provides pro-

grammable chip-select generation for both memo-

ries and peripherals. In addition, it can be pro-

grammed to provide READY (or WAIT state) genera-

tion. It can also provide latched address bits A1 and

A2. The chip-select lines are active for all memory

and I/O cycles in their programmed areas, whether

they be generated by the CPU or by the integrated

DMA unit.

The M80C186XL provides 6 memory chip select out-

puts for 3 address areas; upper memory, lower

memory, and midrange memory. One each is provid-

ed for upper memory and lower memory, while four

are provided for midrange memory.

OFFSET

Relocation Register FEH

DMA Descriptors Channel 1

DAH

D0H

DMA Descriptors Channel 0

CAH

C0H

Chip-Select Control Registers

A8H

A0H

Time 2 Control Registers

66H

60H

Time 1 Control Registers

5EH

58H

Time 0 Control Registers

56H

50H

Interrupt Controller Registers

3EH

20H

Figure 4. Internal Register Map

The M80C186XL provides a chip select, called UCS,

for the top of memory. The top of memory is usually

used as the system memory because after reset the

M80C186XL begins executing at memory location

FFFF0H.

M80C186XL

The M80C186XL provides a chip select for low

memory called LCS. The bottom of memory con-

tains the interrupt vector table, starting at location

00000H.

The M80C186XL provides four MCS lines which are

active within a user-locatable memory block. This

block can be located within the M80C186XL 1 Mbyte

memory address space exclusive of the areas de-

fined by UCS and LCS. Both the base address and

size of this memory block are programmable.

The M80C186XL can generate chip selects for up to

seven peripheral devices. These chip selects are ac-

tive for seven contiguous blocks of 128 bytes above

a programmable base address. The base address

may be located in either memory or I/O space.

The M80C186XL can generate a READY signal in-

ternally for each of the memory or peripheral CS

lines. The number of WAIT states to be inserted for

each peripheral or memory is programmable to pro-

vide 0– 3 wait states for all accesses to the area for

which the chip select is active. In addition, the

M80C186XL may be programmed to either ignore

external READY for each chip-select range individu-

ally or to factor external READY with the integrated

ready generator.

Upon RESET, the Chip-Select/Ready Logic will per-

form the following actions:

#All chip-select outputs will be driven HIGH.

#Upon leaving RESET, the UCS line will be pro-

grammed to provide chip selects to a 1K block

with the accompanying READY control bits set at

011 to insert 3 wait states in conjunction with ex-

ternal READY (i.e., UMCS resets to FFFBH).

#No other chip select or READY control registers

have any predefined values after RESET. They

will not become active until the CPU accesses

their control registers.

DMA Unit

The M80C186XL DMA controller provides two inde-

pendent high-speed DMA channels. Data transfers

can occur between memory and I/O spaces (e.g.,

Memory to I/O) or within the same space (e.g.,

Memory to Memory or I/O to I/O). Data can be

transferred either in bytes (8 bits) or in words (16

bits) to or from even or odd addresses. Each DMA

channel maintains both a 20-bit source and destina-

tion pointer which can be optionally incremented or

decremented after each data transfer (by one or two

depending on byte or word transfers). Each data

transfer consumes 2 bus cycles (a minimum of 8

clocks), one cycle to fetch data and the other to

store data.

Timer/Counter Unit

The M80C186XL provides three internal 16-bit pro-

grammable timers. Two of these are highly flexible

and are connected to four external pins (2 per timer).

They can be used to count external events, time ex-

ternal events, generate nonrepetitive waveforms,

etc. The third timer is not connected to any external

pins, and is useful for real-time coding and time de-

lay applications. In addition, the third timer can be

used as a prescaler to the other two, or as a DMA

request source.

Interrupt Control Unit

The M80C186XL can receive interrupts from a num-

ber of sources, both internal and external. The

M80C186XL has 5 external and 2 internal interrupt

sources (Timer/Couners and DMA). The internal in-

terrupt controller serves to merge these requests on

a priority basis, for individual service by the CPU.

Enhanced Mode Operation

In Compatible Mode the M80C186XL operates with

all the features of the NMOS 80186, with the excep-

tion of 8087 support (i.e. no math coprocessing is

possible in Compatible Mode). Queue-Status infor-

mation is still available for design purposes other

than 8087 support.

All the Enhanced Mode features are completely

masked when in Compatible Mode. A write to any of

the Enhanced Mode registers will have no effect,

while a read will not return any valid data.

In Enhanced Mode, the M80C186XL will operate

with Power-Save, DRAM refresh, and numerics co-

processor support in addition to all the Compatible

Mode features.

If connected to a math coprocessor, this mode will

be invoked automatically. Without an NPX, this

mode can be entered by tying the RESET output

signal from the M80C186XL to the TEST/BUSY in-

put.

Queue-Status Mode

The queue-status mode is entered by strapping the

RD pin low. RD is sampled at RESET and if LOW,

the M80C186XL will reconfigure the ALE and WR

pins to be QS0 and QS1 respectively. This mode is

available on the M80C186XL in both Compatible

and Enhanced Modes.

M80C186XL

DRAM Refresh Control Unit

The Refresh Control Unit (RCU) automatically gen-

erates DRAM refresh bus cycles. The RCU operates

only in Enhanced Mode. After a programmable peri-

od of time, the RCU generates a memory read re-

quest to the BIU. If the address generated during a

refresh bus cycle is within the range of a properly

programmed chip select, that chip select will be acti-

vated when the BIU executes the refresh bus cycle.

Power-Save Control

The M80C186XL, when in Enhanced Mode, can en-

ter a power saving state by internally dividing the

processor clock frequency by a programmable fac-

tor. This divided frequency is also available at the

CLKOUT pin.

All internal logic, including the Refresh Control Unit

and the timers, have their clocks slowed down by

the division factor. To maintain a real time count or a

fixed DRAM refresh rate, these peripherals must be

re-programmed when entering and leaving the pow-

er-save mode.

Interface for 80C187 Math

Coprocessor

In Enhanced Mode, three of the mid-range memory

chip selects are redefined according to Table 2 for

use with the 80C187. The fourth chip select, MCS2

functions as in compatible mode, and may be pro-

grammed for activity with ready logic and wait states

accordingly. As in Compatible Mode, MCS2 will func-

tion for one-fourth a programmed block size.

Table 2. MCS Assignments

Compatible Enhanced Mode

Mode

MCS0 PEREQ Processor Extension Request

MCS1 ERROR NPX Error

MCS2 MCS2 Mid-Range Chip Select

MCS3 NPS Numeric Processor Select

ONCE Test Mode

To facilitate testing and inspection of devices when

fixed into a target system, the M80C186XL has a

test mode available which allows all pins to be

placed in a high-impedance state. ONCE stands for

‘‘ON Circuit Emulation’’. When placed in this mode,

the M80C186XL will put all pins in the high-imped-

ance state until RESET.

The ONCE mode is selected by tying the UCS and

the LCS LOW during RESET. These pins are sam-

pled on the low-to-high transition of the RES pin.

The UCS and the LCS pins have weak internal pull-

up resistors similar to the RD and TEST/BUSY pins

to guarantee ONCE Mode is not entered inadver-

tently during normal operation. LCS and UCS must

be held low at least one clock after RES goes high

to guarantee entrance into ONCE Mode.

M80C186XL

ABSOLUTE MAXIMUM RATINGS*

Case Temperature under Bias ÀÀÀb55§Ctoa

125§C

Storage Temperature ÀÀÀÀÀÀÀÀÀÀb65§Ctoa

150§C

Voltage on Any Pin with

Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀb1.0V to a7.0V

/Package Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1W

Not to exceed the maximum allowable die tempera-

ture based on thermal resistance of the package.

NOTICE: This data sheet contains information on

products in the sampling and initial production phases

of development. It is valid for the devices indicated in

the revision history. The specifications are subject to

change without notice.

WARNING: Stressing the device beyond the ‘‘Absolute

Maximum Ratings’’ may cause permanent damage.

These are stress ratings only. Operation beyond the

‘‘Operating Conditions’’ is not recommended and ex-

tended exposure beyond the ‘‘Operating Conditions’’

may affect device reliability.

NOTICE: The specifications are subject to change

without notice.

DC CHARACTERISTICS TCeb

55§Ctoa

125§C, VCC e5V g10%

Symbol Parameter Min Max Units Test Conditions

VIL Input Low Voltage (Except X1) b0.5 0.2 VCC b0.3 V

VIL1 Clock Input Low Voltage (X1) b0.5 0.6 V

VIH Input High Voltage 0.2 VCC a0.9 VCC a0.5 V

(All except X1 and RES)

VIH1 Input High Voltage (RES) 3.0 VCC a0.5 V

VIH2 Clock Input High Voltage (X1) 3.9 VCC a0.5 V

VOL Output Low Voltage 0.45 V IOL e2.5 mA (S0, 1, 2)

IOL e2.0 mA (others)

VOH Output High Voltage 2.4 VCC VI

OH eb

2.4 mA @2.4V (4)

VCC b0.5 VCC VI

OH eb

200 mA@VCC b0.5(4)

ICC Power Supply Current 100 mA @20 MHz, b55§C

VCC e5.5V(3)

90 mA @16 MHz, b55§C

VCC e5.5V(3)

80 mA @12.5 MHz, b55§C

VCC e5.5V (3)

70 mA @10 MHz, b55§C

VCC e5.5V (3)

ILI Input Leakage Current g10 mA@0.5 MHz,

0.45V sVIN sVCC

ILO Output Leakage Current g10 mA@0.5 MHz,

0.45V sVOUT sVCC(1)

VCLO Clock Output Low 0.45 V ICLO e4.0 mA

M80C186XL

DC CHARACTERISTICS (Continued) TCeb

55§Ctoa

125§C, VCC e5V g10%

Symbol Parameter Min Max Units Test Conditions

VCHO Clock Output High VCC b0.5 V ICHO eb

500 mA

CIN Input Capacitance 10 pF @1 MHz(2)

CIO Output or I/O Capacitance 20 pF @1 MHz(2)

NOTES:

1. Pins being floated during HOLD or by invoking the ONCE Mode.

2. Characterization conditions are a) Frequency e1 MHz; b) Unmeasured pins at GND; c) VIN at a5.0V or 0.45V. This

parameter is not tested.

3. Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open.

4. RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/ERROR and TEST/BUSY pins have internal pullup devices. Loading some

of these pins above IOH eb

200 mA can cause the M80C186XL to go into alternative modes of operation. See the section

on Local Bus Controller and Reset for details.

M80C186XL

AC CHARACTERISTICS

MAJOR CYCLE TIMINGS (READ CYCLE)

TCeb

55§Ctoa

125§C, VCC e5V g10%

All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.

All output test conditions are with CLe50 pF.

For AC tests, input VIL e0.45V and VIH e2.4V except at X1 where VIH eVCC b0.5V.

Values

Conditions

Test

Symbol Parameter M80C186XL M80C186XL12 Unit

Min Max Min Max

M80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once)

TDVCL Data in Setup (A/D) 15 15 ns

TCLDX Data in Hold (A/D) 3 3 ns

M80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

TCHSV Status Active Delay 3 45 3 35 ns

TCLSH Status Inactive Delay 3 46 3 35 ns

TCLAV Address Valid Delay 3 44 3 36 ns

TCLAX Address Hold 0 0 ns

TCLDV Data Valid Delay 3 40 3 36 ns

TCHDX Status Hold Time 10 10 ns

TCHLH ALE Active Delay 30 25 ns

TLHLL ALE Width TCLCL b15 TCLCL b15 ns

TCHLL ALE Inactive Delay 30 25 ns

TAVLL Address Valid to ALE Low TCLCH b18 TCLCH b15 ns Equal

TLLAX Address Hold from ALE TCHCL b15 TCHCL b15 ns Equal

Inactive Loading

TAVCH Address Valid to Clock High 0 0 ns

TCLAZ Address Float Delay TCLAX 30 TCLAX 25 ns

TCLCSV Chip-Select Active Delay 3 42 3 33 ns

TCXCSX Chip-Select Hold from TCLCH b10 TCLCH b10 ns Equal

Command Inactive Loading

TCHCSX Chip-Select Inactive Delay 3 35 3 30 ns

TDXDL DEN Inactive to DT/R Low 0 0 ns Equal

TCVCTV Control Active Delay 1 3 44 3 37 ns

TCVDEX DEN Inactive Delay 3 44 3 37 ns

TCHCTV Control Active Delay 2 3 44 3 37 ns

TCLLV LOCK Valid/Invalid Delay 3 40 3 37 ns

M80C186XL TIMING RESPONSES (Read Cycle)

TAZRL Address Float to RD Active 0 0 ns

TCLRL RD Active Delay 3 44 3 37 ns

TRLRH RD Pulse Width 2TCLCL b30 2TCLCL b25 ns

TCLRH RD Inactive Delay 3 44 3 37 ns

TRHLH RD Inactive to ALE High TCLCH b14 TCLCH b14 ns Equal

TRHAV RD Inactive to Address TCLCL b15 TCLCL b15 ns Equal

Active Loading

M80C186XL

AC CHARACTERISTICS

MAJOR CYCLE TIMINGS (READ CYCLE)

TCeb

55§Ctoa

125§C, VCC e5V g10%

All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.

All output test conditions are with CLe50 pF.

For AC tests, input VIL e0.45V and VIH e2.4V except at X1 where VIH eVCC b0.5V.

Values

Conditions

Test

Symbol Parameter M80C186XL16 M80C186XL20 Unit

Min Max Min Max

M80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once)

TDVCL Data in Setup (A/D) 15 10 ns

TCLDX Data in Hold (A/D) 3 3 ns

M80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

TCHSV Status Active Delay 1 31 1 25 ns

TCLSH Status Inactive Delay 1 30 1 25 ns

TCLAV Address Valid Delay 1 33 1 27 ns

TCLAX Address Hold 0 0 ns

TCLDV Data Valid Delay 1 33 1 27 ns

TCHDX Status Hold Time 10 10 ns

TCHLH ALE Active Delay 20 20 ns

TLHLL ALE Width TCLCL b15 TCLCL b15 ns

TCHLL ALE Inactive Delay 20 20 ns

TAVLL Address Valid to ALE Low TCLCH b15 TCLCH b10 ns Equal

TLLAX Address Hold from ALE TCHCL b15 TCHCL b10 ns Equal

Inactive Loading

TAVCH Address Valid to Clock High 0 0 ns

TCLAZ Address Float Delay TCLAX 20 TCLAX 20 ns

TCLCSV Chip-Select Active Delay 1 30 1 25 ns

TCXCSX Chip-Select Hold from tCLCH b10 TCLCH b10 ns Equal

Command Inactive Loading

TCHCSX Chip-Select Inactive Delay 1 25 1 20 ns

TDXDL DEN Inactive to DT/R Low 0 0 ns Equal

TCVCTV Control Active Delay 1 1 31 1 22 ns

TCVDEX DEN Inactive Delay 1 31 1 22 ns

TCHCTV Control Active Delay 2 1 31 1 22 ns

TCLLV LOCK Valid/Invalid Delay 1 35 1 22 ns

M80C186XL TIMING RESPONSES (Read Cycle)

TAZRL Address Float to RD Active 0 0 ns

TCLRL RD Active Delay 1 31 1 27 ns

TRLRH RD Pulse Width 2TCLCL b25 2TCLCL b20 ns

TCLRH RD Inactive Delay 1 31 1 27 ns

TRHLH RD Inactive to ALE High TCLCH b14 TCLCH b14 ns Equal

TRHAV RD Inactive to Address TCLCL b15 TCLCL b15 ns Equal

Active Loading

M80C186XL

AC CHARACTERISTICS

MAJOR CYCLE TIMINGS (WRITE CYCLE)

TCeb

55§Ctoa

125§C, VCC e5V g10%

All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.

All output test conditions are with CLe50 pF.

For AC tests, input VIL e0.45V and VIH e2.4V except at X1 where VIH eVCC b0.5V.

Values

Conditions

Test

Symbol Parameter M80C186XL M80C186XL12 Unit

Min Max Min Max

M80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

TCHSV Status Active Delay 3 45 3 35 ns

TCLSH Status Inactive Delay 3 46 3 35 ns

TCLAV Address Valid Delay 3 44 3 36 ns

TCLAX Address Hold 0 0 ns

TCLDV Data Valid Delay 3 40 3 36 ns

TCHDX Status Hold Time 10 10 ns

TCHLH ALE Active Delay 30 25 ns

TLHLL ALE Width TCLCL b15 TCLCL b15 ns

TCHLL ALE Inactive Delay 30 25 ns

TAVLL Address Valid to ALE Low TCLCH b18 TCLCH b15 ns Equal

TLLAX Address Hold from ALE TCHCL b15 TCHCL b15 ns Equal

Inactive Loading

TAVCH Address Valid to Clock High 0 0 ns

TCLDOX Data Hold Time 3 3 ns

TCVCTV Control Active Delay 1 3 44 3 37 ns

TCVCTX Control Inactive Delay 3 44 3 37 ns

TCLCSV Chip-Select Active Delay 3 42 3 33 ns

TCXCSX Chip-Select Hold from TCLCH b10 TCLCH b10 ns Equal

Command Inactive Loading

TCHCSX Chip-Select Inactive Delay 3 35 3 30 ns

TDXDL DEN Inactive to DT/R Low 0 0 ns Equal

TCLLV LOCK Valid/Invalid Delay 3 40 3 37 ns

M80C186XL TIMING RESPONSES (Write Cycle)

TWLWH WR Pulse Width 2TCLCL b30 2TCLCL b25 ns

TWHLH WR Inactive to ALE High TCLCH b14 TCLCH b14 ns Equal

TWHDX Data Hold after WR TCLCL b34 TCLCL b20 ns Equal

TWHDEX WR Inactive to DEN Inactive TCLCH b10 TCLCH b10 ns Equal

M80C186XL

AC CHARACTERISTICS

MAJOR CYCLE TIMINGS (WRITE CYCLE)

TCeb

55§Ctoa

125§C, VCC e5V g10%

All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.

All output test conditions are with CLe50 pF.

For AC tests, input VIL e0.45V and VIH e2.4V except at X1 where VIH eVCC b0.5V.

Values

Conditions

Test

Symbol Parameter M80C186XL16 M80C186XL20 Unit

Min Max Min Max

M80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

TCHSV Status Active Delay 1 31 1 25 ns

TCLSH Status Inactive Delay 1 30 1 25 ns

TCLAV Address Valid Delay 1 33 1 27 ns

TCLAX Address Hold 0 0 ns

TCLDV Data Valid Delay 1 33 1 27 ns

TCHDX Status Hold Time 10 10 ns

TCHLH ALE Active Delay 20 20 ns

TLHLL ALE Width TCLCL b15 TCLCL b15 ns

TCHLL ALE Inactive Delay 20 20 ns

TAVLL Address Valid to ALE Low TCLCH b15 TCLCH b10 ns Equal

TLLAX Address Hold from ALE TCHCL b15 TCHCL b10 ns Equal

Inactive Loading

TAVCH Address Valid to Clock High 0 0 ns

TCLDOX Data Hold Time 1 1 ns

TCVCTV Control Active Delay 1 1 31 1 25 ns

TCVCTX Control Inactive Delay 1 31 1 25 ns

TCLCSV Chip-Select Active Delay 1 30 1 25 ns

TCXCSX Chip-Select Hold from TCLCH b10 TCLCH b10 ns Equal

Command Inactive Loading

TCHCSX Chip-Select Inactive Delay 1 25 1 20 ns

TDXDL DEN Inactive to DT/R Low 0 0 ns Equal

TCLLV LOCK Valid/Invalid Delay 1 35 1 22 ns

M80C186XL TIMING RESPONSES (Write Cycle)

TWLWH WR Pulse Width 2TCLCL b25 2TCLCL b20 ns

TWHLH WR Inactive to ALE High TCLCH b14 TCLCH b14 ns Equal

TWHDX Data Hold after WR TCLCL b20 TCLCL b15 ns Equal

TWHDEX WR Inactive to DEN Inactive TCLCH b10 TCLCH b10 ns Equal

M80C186XL

AC CHARACTERISTICS

MAJOR CYCLE TIMINGS (INTERRUPT ACKNOWLEDGE CYCLE)

TCeb

55§Ctoa

125§C, VCC e5V g10%

All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.

All output test conditions are with CLe50 pF.

For AC tests, input VIL e0.45V and VIH e2.4V except at X1 where VIH eVCC b0.5V.

Values

Conditions

Test

Symbol Parameter M80C186XL M80C186XL12 Unit

Min Max Min Max

M80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once)

TDVCL Data in Setup (A/D) 15 15 ns

TCLDX Data in Hold (A/D) 3 3 ns

M80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

TCHSV Status Active Delay 3 45 3 35 ns

TCLSH Status Inactive Delay 3 46 3 35 ns

TCLAV Address Valid Delay 3 44 3 36 ns

TAVCH Address Valid to Clock High 0 0 ns

TCLAX Address Hold 0 0 ns

TCLDV Data Valid Delay 3 40 3 36 ns

TCHDX Status Hold Time 10 10 ns

TCHLH ALE Active Delay 30 25 ns

TLHLL ALE Width TCLCL b15 TCLCL b15 ns

TCHLL ALE Inactive Delay 30 25 ns

TAVLL Address Valid to ALE Low TCLCH b18 TCLCH b15 ns Equal

TLLAX Address Hold to ALE TCHCL b15 TCHCL b15 ns Equal

Inactive Loading

TCLAZ Address Float Delay TCLAX 30 TCLAX 25 ns

TCVCTV Control Active Delay 1 3 44 3 37 ns

TCVCTX Control Inactive Delay 3 44 3 37 ns

TDXDL DEN Inactive to DT/R Low 0 0 ns Equal

TCHCTV Control Active Delay 2 3 44 3 37 ns

TCVDEX DEN Inactive Delay 3 44 3 37 ns

(Non-Write Cycles)

TCLLV LOCK Valid/Invalid Delay 3 40 3 37 ns

M80C186XL

AC CHARACTERISTICS

MAJOR CYCLE TIMINGS (INTERRUPT ACKNOWLEDGE CYCLE)

TCeb

55§Ctoa

125§C, VCC e5V g10%

All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.

All output test conditions are with CLe50 pF.

For AC tests, input VIL e0.45V and VIH e2.4V except at X1 where VIH eVCC b0.5V.

Values

Conditions

Test

Symbol Parameter M80C186XL16 M80C186XL20 Unit

Min Max Min Max

M80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once)

TDVCL Data in Setup (A/D) 15 10 ns

TCLDX Data in Hold (A/D) 1 1 ns

M80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

TCHSV Status Active Delay 1 31 1 25 ns

TCLSH Status Inactive Delay 1 30 1 25 ns

TCLAV Address Valid Delay 1 33 1 27 ns

TAVCH Address Valid to Clock High 0 0 ns

TCLAX Address Hold 0 0 ns

TCLDV Data Valid Delay 1 33 1 27 ns

TCHDX Status Hold Time 10 10 ns

TCHLH ALE Active Delay 20 20 ns

TLHLL ALE Width TCLCL b15 TCLCL b15 ns

TCHLL ALE Inactive Delay 20 20 ns

TAVLL Address Valid to ALE Low TCLCH b15 TCLCH b10 ns Equal

TLLAX Address Hold to ALE TCHCL b15 TCHCL b10 ns Equal

Inactive Loading

TCLAZ Address Float Delay TCLAX 20 TCLAX 20 ns

TCVCTV Control Active Delay 1 1 31 1 25 ns

TCVCTX Control Inactive Delay 1 31 1 25 ns

TDXDL DEN Inactive to DT/R Low 0 0 ns Equal

TCHCTV Control Active Delay 2 1 31 1 22 ns

TCVDEX DEN Inactive Delay 1 31 1 22 ns

(Non-Write Cycles)

TCLLV LOCK Valid/Invalid Delay 1 35 1 22 ns

M80C186XL

AC CHARACTERISTICS

SOFTWARE HALT CYCLE TIMINGS

TCeb

55§Ctoa

125§C, VCC e5V g10%

All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.

All output test conditions are with CLe50 pF.

For AC tests, input VIL e0.45V and VIH e2.4V except at X1 where VIH eVCC b0.5V.

Values

Conditions

Test

Symbol Parameter M80C186XL M80C186XL12 Unit

Min Max Min Max

M80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once)

TCHSV Status Active Delay 3 45 3 35 ns

TCLSH Status Inactive Delay 3 46 3 35 ns

TCLAV Address Valid Delay 3 44 3 36 ns

TCHLH ALE Active Delay 30 25 ns

TLHLL ALE Width TCLCL b15 TCLCL b15 ns

TCHLL ALE Inactive Delay 30 25 ns

TDXDL DEN Inactive to DT/R Low 0 0 ns Equal

TCHCTV Control Active Delay 2 3 44 3 37 ns

Values

Conditions

Test

Symbol ParameterTarget M80C186XL16 M80C186XL20 Unit

Min Max Min Max

M80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

TCHSV Status Active Delay 3 31 3 25 ns

TCLSH Status Inactive Delay 3 30 3 25 ns

TCLAV Address Valid Delay 3 33 3 27 ns

TCHLH ALE Active Delay 20 20 ns

TLHLL ALE Width TCLCL b15 TCLCL b15 ns

TCHLL ALE Inactive Delay 20 20 ns

TDXDL DEN Inactive to DT/R Low 0 0 ns Equal

TCHCTV Control Active Delay 2 3 31 3 22 ns

M80C186XL

AC CHARACTERISTICS

CLOCK TIMINGS

TCeb

55§Ctoa

125§C, VCC e5V g10%

All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.

All output test conditions are with CLe50 pF.

For AC tests, input VIL e0.45V and VIH e2.4V except at X1 where VIH eVCC b0.5V.

Values

Conditions

Test

Symbol Parameter M80C186XL M80C186XL12 Unit

Min Max Min Max

M80C186XL CLKIN REQUIREMENTS(1)

TCKIN CLKIN Period 50 %40 %ns

TCLCK CLKIN Low Time 20 %16 %ns 1.5V(2)

TCHCK CLKIN High Time 20 %16 %ns 1.5V(2)

TCKHL CLKIN Fall Time 5 5 ns 3.5 to 1.0V

TCKLH CLKIN Rise Time 5 5 ns 1.0 to 3.5V

M80C186XL CLKOUT TIMING

TCICO CLKIN to CLKOUT Skew 25 21 ns

TCLCL CLKOUT Period 100 %80 %ns

TCLCH CLKOUT Low Time 0.5 TCLCL b6 0.5 TCLCL b5nsC

100 pF(3)

TCHCL CLKOUT High Time 0.5 TCLCL b6 0.5 TCLCL b5nsC

100 pF(4)

TCH1CH2 CLKOUT Rise Time 10 10 ns 1.0 to 3.5V

TCL2CL1 CLKOUT Fall Time 10 10 ns 3.5 to 1.0V

NOTES:

1. External clock applied to X1 and X2 not connected.

2. TCLCK and TCHCK (CLKIN Low and High times) should not have a duration less than 40% of TCKIN.

3. Tested under worst case conditions: VCC e5.5V TCea

125§C.

4. Tested under worst case conditions: VCC e4.5V TCeb

55§C.

M80C186XL

AC CHARACTERISTICS

CLOCK TIMINGS

TCeb

55§Ctoa

125§C, VCC e5V g10%

All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.

All output test conditions are with CLe50 pF.

For AC tests, input VIL e0.45V and VIH e2.4V except at X1 where VIH eVCC b0.5V.

Values

Conditions

Test

Symbol Parameter M80C186XL16 M80C186XL20 Unit

Min Max Min Max

M80C186XL CLKIN REQUIREMENTS(1)

TCKIN CLKIN Period 31.25 %25 %ns

TCLCK CLKIN Low Time 13 %10 %ns 1.5V(2)

TCHCK CLKIN High Time 13 %10 %ns 1.5V(2)

TCKHL CLKIN Fall Time 5 5 ns 3.5 to 1.0V

TCKLH CLKIN Rise Time 5 5 ns 1.0 to 3.5V

M80C186XL CLKOUT TIMING

TCICO CLKIN to CLKOUT Skew 17 17 ns

TCLCL CLKOUT Period 62.5 50 ns

TCLCH CLKOUT Low Time 0.5 TCLCL b5 0.5 TCLCL b5nsC

100 pF(3)

TCHCL CLKOUT High Time 0.5 TCLCL b5 0.5 TCLCL b5nsC

100 pF(4)

TCH1CH2 CLKOUT Rise Time 10 8 ns 1.0 to 3.5V

TCL2CL1 CLKOUT Fall Time 10 8 ns 3.5 to 1.0V

NOTES:

1. External clock applied to X1 and X2 not connected.

2. TCLCK and TCHCK (CLKIN Low and High times) should not have a duration less than 40% of TCKIN.

3. Tested under worst case conditions: VCC e5.5V. TCea

125§C.

4. Tested under worst case conditions: VCC e4.5V. TCeb

55§C.

M80C186XL

AC CHARACTERISTICS

READY, PERIPHERAL AND QUEUE STATUS TIMINGS

TCeb

55§Ctoa

125§C, VCC e5V g10%

All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.

All output test conditions are with CLe50 pF.

For AC tests, input VIL e0.45V and VIH e2.4V except at X1 where VIH eVCC b0.5V.

Values

Conditions

Test

Symbol Parameter M80C186XL M80C186XL12 Unit

Min Max Min Max

M80C186XL READY AND PERIPHERAL TIMING REQUIREMENTS (Listed More Than Once)

TSRYCL Synchronous Ready (SRDY) 15 15 ns

Transition Setup Time(1)

TCLSRY SRDY Transition Hold Time(1) 15 15 ns

TARYCH ARDY Resolution Transition 15 15 ns

Setup Time(2)

TCLARX ARDY Active Hold Time(1) 15 15 ns

TARYCHL ARDY Inactive Holding Time 15 15 ns

TARYLCL Asynchronous Ready 25 25 ns

(ARDY) Setup Time(1)

TINVCH INTx, NMI, TEST/BUSY, 15 15 ns

TMR IN Setup Time(2)

TINVCL DRQ0, DRQ1 Setup Time(2) 15 15 ns

M80C186XL PERIPHERAL AND QUEUE STATUS TIMING RESPONSES

TCLTMV Timer Output Delay 40 33 ns

TCHQSV Queue Status Delay 37 32 ns

NOTES:

1. To guarantee proper operation.

2. To guarantee recognition at clock edge.

M80C186XL

AC CHARACTERISTICS

READY, PERIPHERAL, AND QUEUE STATUS TIMINGS

TCeb

55§Ctoa

125§C, VCC e5V g10%

All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.

All output test conditions are with CLe50 pF.

For AC tests, input VIL e0.45V and VIH e2.4V except at X1 where VIH eVCC b0.5V.

Values

Conditions

Test

Symbol Parameter M80C186XL16 M80C186XL20 Unit

Min Max Min Max

M80C186XL READY AND PERIPHERAL TIMING REQUIREMENTS

TSRYCL Synchronous Ready (SRDY) 15 10 ns

Transition Setup Time(1)

TCLSRY SRDY Transition Hold Time(1) 15 10 ns

TARYCH ARDY Resolution Transition 15 10 ns

Setup Time(2)

TCLARX ARDY Active Hold Time(1) 15 10 ns

TARYCHL ARDY Inactive Holding Time 15 10 ns

TARYLCL Asynchronous Ready 25 15 ns

(ARDY) Setup Time(1)

TINVCH INTx, NMI, TEST/BUSY, 15 10 ns

TMR IN Setup Time(2)

TINVCL DRQ0, DRQ1 Setup Time(2) 15 10 ns

M80C186XL PERIPHERAL AND QUEUE STATUS TIMING RESPONSES

TCLTMV Timer Output Delay 27 22 ns

TCHQSV Queue Status Delay 30 27 ns

NOTES:

1. To guarantee proper operation.

2. To guarantee recognition at clock edge.

M80C186XL

AC CHARACTERISTICS

RESET AND HOLD/HLDA TIMINGS

TCeb

55§Ctoa

125§C, VCC e5V g10%

All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.

All output test conditions are with CLe50 pF.

For AC tests, input VIL e0.45V and VIH e2.4V except at X1 where VIH eVCC b0.5V.

Values

Conditions

Test

Symbol Parameter M80C186XL M80C186XL12 Unit

Min Max Min Max

M80C186XL RESET AND HOLD/HLDA TIMING REQUIREMENTS

TRESIN RES Setup 15 15 ns

THVCL HOLD Setup(1) 15 15 ns

M80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

TCLAZ Address Float Delay TCLAX 30 TCLAX 25 ns

TCLAV Address Valid Delay 3 44 3 36 ns

M80C186XL RESET AND HOLD/HLDA TIMING RESPONSES

TCLRO Reset Delay 40 33 ns

TCLHAV HLDA Valid Delay 3 40 3 33 ns

TCHCZ Command Lines Float Delay 40 33 ns

TCHCV Command Lines Valid Delay 44 36 ns

(after Float)

NOTE:

1. To guarantee recognition at next clock.

M80C186XL

AC CHARACTERISTICS

RESET AND HOLD/HLDA TIMINGS

TCeb

55§Ctoa

125§C, VCC e5V g10%

All timings are measured at 1.5V and 100 pF loading on CLKOUT unless otherwise noted.

All output test conditions are with CLe50 pF.

For AC tests, input VIL e0.45V and VIH e2.4V except at X1 where VIH eVCC b0.5V.

Values

Conditions

Test

Symbol Parameter M80C186XL16 M80C186XL20 Unit

Min Max Min Max

M80C186XL RESET AND HOLD/HLDA TIMING REQUIREMENTS

TRESIN RES Setup 15 15 ns

THVCL HOLD Setup(1) 15 10 ns

M80C186XL GENERAL TIMING RESPONSES (Listed More Than Once)

TCLAZ Address Float Delay TCLAX 20 TCLAX 20 ns

TCLAV Address Valid Delay 1 33 1 22 ns

M80C186XL RESET AND HOLD/HLDA TIMING RESPONSES

TCLRO Reset Delay 27 22 ns

TCLHAV HLDA Valid Delay 1 25 1 22 ns

TCHCZ Command Lines Float Delay 28 25 ns

TCHCV Command Lines Valid Delay 32 26 ns

(after Float)

NOTE:

1. To guarantee recognition at next clock.

M80C186XL

AC CHARACTERISTICS

271276–7

NOTES:

1. Status inactive in state preceding T4.

2. If latched A1and A2are selected instead of PCS5 and PCS6, only TCLCSV is applicable.

3. For write cycle followed by read cycle.

4. T1of next bus cycle.

5. Changes in T-state preceding next bus cycle if followed by write.

Figure 5. Read Cycle Waveforms

M80C186XL

AC CHARACTERISTICS

271276–8

NOTES:

1. Status inactive in state preceding T4.

2. If latched A1and A2are selected instead of PCS5 and PCS6, only TCLCSV is applicable.

3. For write cycle followed by read cycle.

4. T1of next bus cycle.

5. Changes in T-state preceding next bus cycle if followed by read, INTA, or halt.

Figure 6. Write Cycle Waveforms

M80C186XL

AC CHARACTERISTICS

271276–9

NOTES:

1. Status inactive in state preceding T4.

2. The data hold time lasts only until INTA goes inactive, even if the INTA transition occurs prior to TCLDX (min).

3. INTA occurs one clock later in Slave Mode.

4. For write cycle followed by interrupt acknowledge cycle.

5. LOCK is active upon T1of the first interrupt acknowledge cycle and inactive upon T2of the second interrupt acknowl-

edge cycle.

6. Changes in T-state preceding next bus cycle if followed by write.

Figure 7. Interrupt Acknowledge Cycle Waveforms

M80C186XL

AC CHARACTERISTICS

271276–10

NOTE:

1. For write cycle followed by halt cycle.

Figure 8. Software Halt Cycle Waveforms

M80C186XL

WAVEFORMS

271276–11

Figure 9. Clock Waveforms

271276–12

Figure 10. Reset Waveforms

271276–13

Figure 11. Synchronous Ready (SRDY) Waveforms

M80C186XL

AC CHARACTERISTICS

271276–19

Figure 12. Asynchronous Ready (ARDY) Waveforms

271276–14

Figure 13. Peripheral and Queue Status Waveforms

M80C186XL

AC CHARACTERISTICS

271276–20

Figure 14. HOLD/HLDA Waveforms (Entering Hold)

271276–15

Figure 15. HOLD/HLDA Waveforms (Leaving Hold)

M80C186XL

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has from 5 to 7 characters. The first character is always a ‘T’ (stands for time). The other

characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The

following is a list of all the characters and what they stand for.

A: Address

ARY: Asynchronous Ready Input

C: Clock Output

CK: Clock Input

CS: Chip Select

CT: Control (DT/R, DEN,...)

D: Data Input

DE: DEN

H: Logic Level High

OUT: Input (DRQ0, TIM0, . . . )

L: Logic Level Low or ALE

O: Output

QS: Queue Status (QS1, QS2)

R: RD Signal, RESET Signal

S: Status (S0,S1,S2)

SRY: Synchronous Ready Input

V: Valid

W: WR Signal

X: No Longer a Valid Logic Level

Z: Float

Examples:

TCLAV Ð Time from Clock low to Address valid

TCHLH Ð Time from Clock high to ALE high

TCLCSV Ð Time from Clock low to Chip Select valid

M80C186XL

DERATING CURVES

Typical Output Delay Capacitive Derating

271276–16

Figure 16. Capacitive Derating Curve

Typical Rise and Fall Times for TTL Voltage Levels

271276–17

Figure 17. TTL Level Rise and Fall Times for Output Buffers

Typical Rise and Fall Times for CMOS Voltage Levels

271276–18

Figure 18. CMOS Level Rise and Fall Times for Output Buffers

M80C186XL

M80C186XL EXECUTION TIMINGS

A determination of M80C186XL program execution

timing must consider the bus cycles necessary to

prefetch instructions as well as the number of exe-

cution unit cycles necessary to execute instructions.

The following instruction timings represent the mini-

mum execution time in clock cycles for each instruc-

tion. The timings given are based on the following

assumptions:

#The opcode, along with any data or displacement

required for execution of a particular instruction,

has been prefetched and resides in the queue at

the time it is needed.

#No wait states or bus HOLDs occur.

#All word-data is located on even-address bound-

aries.

All jumps and calls include the time required to fetch

the opcode of the next instruction at the destination

address.

All instructions which involve memory accesses can

require one or two additional clocks above the mini-

mum timings shown due to the asynchronous hand-

shake between the bus interface unit (BIU) and exe-

cution unit.

With a 16-bit BIU, the M80C186XL has sufficient bus

performance to ensure that an adequate number of

prefetched bytes will reside in the queue most of the

time. Therefore, actual program execution time will

not be substantially greater than that derived from

adding the instruction timings shown.

M80C186XL

INSTRUCTION SET SUMMARY

Function Format Clock Comments

Cycles

DATA TRANSFER

MOV eMove:

Immediate to register/memory 1100011w mod000 r/m data data if we1 12 – 13 8/16-bit

Immediate to register 1011w reg data data if we1 3–4 8/16-bit

Memory to accumulator 1010000w addr-low addr-high 8

Accumulator to memory 1010001w addr-low addr-high 9

Segment register to register/memory 10001100 mod0reg r/m 2/11

PUSH ePush:

Memory 11111111 mod110 r/m 16

Segment register 000reg110 9

Immediate 011010s0 data data if se010

PUSHA ePush All 01100000 36

POP ePop:

Memory 10001111 mod000 r/m 20

Segment register 000reg111 (regi01) 8

POPA ePopAll 01100001 51

XCHG eExchange:

IN eInput from:

Fixed port 1110010w port 10

Variable port 1110110w 8

OUT eOutput to:

Fixed port 1110011w port 9

Variable port 1110111w 7

XLAT eTranslate byte to AL 11010111 11

LEA eLoad EA to register 10001101 modreg r/m 6

LDS eLoad pointer to DS 11000101 modreg r/m (mod i11) 18

LES eLoad pointer to ES 11000100 modreg r/m (modi11) 18

LAHF eLoad AH with flags 10011111 2

SAHF eStore AH into flags 10011110 3

PUSHF ePush flags 10011100 9

POPF ePop flags 10011101 8

Shaded areas indicate instructions not available in 8086/8088 microsystems.

M80C186XL

INSTRUCTION SET SUMMARY (Continued)

Function Format Clock Comments

Cycles

DATA TRANSFER (Continued)

SEGMENT eSegment Override:

CS 00101110 2

SS 00110110 2

DS 00111110 2

ES 00100110 2

ARITHMETIC

ADD eAdd:

Reg/memory with register to either 000000dw modreg r/m 3/10

Immediate to register/memory 100000sw mod000 r/m data data if s we01 4/16

Immediate to accumulator 0000010w data data if we1 3/4 8/16-bit

ADC eAdd with carry:

Reg/memory with register to either 000100dw modreg r/m 3/10

Immediate to register/memory 100000sw mod010 r/m data data if s we01 4/16

Immediate to accumulator 0001010w data data if we1 3/4 8/16-bit

INC eIncrement:

SUB eSubtract:

Reg/memory and register to either 001010dw modreg r/m 3/10

Immediate from register/memory 100000sw mod101 r/m data data if s we01 4/16

Immediate from accumulator 0010110w data data if we1 3/4 8/16-bit

SBB eSubtract with borrow:

Reg/memory and register to either 000110dw modreg r/m 3/10

Immediate from register/memory 100000sw mod011 r/m data data if s we01 4/16

Immediate from accumulator 0001110w data data if we1 3/4 8/16-bit

DEC eDecrement

CMP eCompare:

Immediate with register/memory 100000sw mod111 r/m data data if s we01 3/10

Immediate with accumulator 0011110w data data if we1 3/4 8/16-bit

NEG eChange sign register/memory 1111011w mod011 r/m 3/10

AAA eASCII adjust for add 00110111 8

DAA eDecimal adjust for add 00100111 4

AAS eASCII adjust for subtract 00111111 7

DAS eDecimal adjust for subtract 00101111 4

MUL eMultiply (unsigned): 1111011w mod100 r/m

Memory-Byte 32–34

Memory-Word 41–43

Shaded areas indicate instructions not available in 8086/8088 microsystems.

M80C186XL

INSTRUCTION SET SUMMARY (Continued)

Function Format Clock Comments

Cycles

ARITHMETIC (Continued)

IMUL eInteger multiply (signed): 1111011w mod101 r/m

Memory-Byte 31–34

Memory-Word 40–43

IMUL eInteger Immediate multiply 011010s1 modreg r/m data data if se0 22–25/

(signed) 29–32

DIV eDivide (unsigned): 1111011w mod110 r/m

Memory-Byte 35

Memory-Word 44

IDIV eInteger divide (signed): 1111011w mod111 r/m

Memory-Byte 50–58

Memory-Word 59–67

AAM eASCII adjust for multiply 11010100 00001010 19

AAD eASCII adjust for divide 11010101 00001010 15

CBW eConvert byte to word 10011000 2

CWD eConvert word to double word 10011001 4

LOGIC

Shift/Rotate Instructions:

n/17an

TTT Instruction

000 ROL

001 ROR

010 RCL

011 RCR

1 0 0 SHL/SAL

101 SHR

111 SAR

AND eAnd:

Reg/memory and register to either 001000dw modreg r/m 3/10

Immediate to register/memory 1000000w mod100 r/m data data if we1 4/16

Immediate to accumulator 0010010w data data if we1 3/4 8/16-bit

TESTeAnd function to flags, no result:

Immediate data and register/memory 1111011w mod000 r/m data data if we1 4/10

Immediate data and accumulator 1010100w data data if we1 3/4 8/16-bit

OReOr:

Reg/memory and register to either 000010dw modreg r/m 3/10

Immediate to register/memory 1000000w mod001 r/m data data if we1 4/16

Immediate to accumulator 0000110w data data if we1 3/4 8/16-bit

Shaded areas indicate instructions not available in 8086/8088 microsystems.

M80C186XL

INSTRUCTION SET SUMMARY (Continued)

Function Format Clock Comments

Cycles

LOGIC (Continued)

XOR eExclusive or:

Reg/memory and register to either 001100dw modreg r/m 3/10

Immediate to register/memory 1000000w mod110 r/m data data if we1 4/16

Immediate to accumulator 0011010w data data if we1 3/4 8/16-bit

NOT eInvert register/memory 1111011w mod010 r/m 3/10

STRING MANIPULATION

MOVS eMove byte/word 1010010w 14

CMPS eCompare byte/word 1010011w 22

SCAS eScan byte/word 1010111w 15

LODS eLoad byte/wd to AL/AX 1010110w 12

STOS eStore byte/wd from AL/AX 1010101w 10

INS eInput byte/wd from DX port 0110110w 14

OUTS eOutput byte/wd to DX port 0110111w 14

Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ)

MOVS eMove string 11110010 1010010w 8

CMPS eCompare string 1111001z 1010011w 5

22n

SCAS eScan string 1111001z 1010111w 5

15n

LODS eLoad string 11110010 1010110w 6

11n

STOS eStore string 11110010 1010101w 6

INS eInput string 11110010 0110110w 8

OUTS eOutput string 11110010 0110111w 8

CONTROL TRANSFER

CALL eCall:

Direct within segment 11101000 disp-low disp-high 15

indirect within segment

Direct intersegment 10011010 segment offset 23

segment selector

Indirect intersegment 11111111 mod011 r/m (mod i11) 38

JMP eUnconditional jump:

Short/long 11101011 disp-low 14

Direct within segment 11101001 disp-low disp-high 14

indirect within segment

Direct intersegment 11101010 segment offset 14

segment selector

Indirect intersegment 11111111 mod101 r/m (mod i11) 26

Shaded areas indicate instructions not available in 8086/8088 microsystems.

M80C186XL

INSTRUCTION SET SUMMARY (Continued)

Function Format Clock Comments

Cycles

CONTROL TRANSFER (Continued)

RET eReturn from CALL:

Within segment 11000011 16

Within seg adding immed to SP 11000010 data-low data-high 18

Intersegment 11001011 22

Intersegment adding immediate to SP 11001010 data-low data-high 25

JE/JZ eJump on equal/zero 01110100 disp 4/13 JMP not

JL/JNGE eJump on less/not greater or equal 01111100 disp 4/13 taken/JMP

JLE/JNG eJump on less or equal/not greater 01111110 disp 4/13

taken

JB/JNAE eJump on below/not above or equal 01110010 disp 4/13

JBE/JNA eJump on below or equal/not above 01110110 disp 4/13

JP/JPE eJump on parity/parity even 01111010 disp 4/13

JO eJump on overflow 01110 000 disp 4/13

JS eJump on sign 01111000 disp 4/13

JNE/JNZ eJump on not equal/not zero 01110101 disp 4/13

JNL/JGE eJump on not less/greater or equal 01111101 disp 4/13

JNLE/JG eJump on not less or equal/greater 01111111 disp 4/13

JNB/JAE eJump on not below/above or equal 01110011 disp 4/13

JNBE/JA eJump on not below or equal/above 01110111 disp 4/13

JNP/JPO eJump on not par/par odd 01111011 disp 4/13

JNO eJump on not overflow 01110001 disp 4/13

JNS eJump on not sign 01111001 disp 4/13

JCXZ eJump on CX zero 11100011 disp 5/15

LOOP eLoop CX times 11100010 disp 6/16 LOOP not

LOOPZ/LOOPE eLoop while zero/equal 11100001 disp 6/16 taken/LOOP

LOOPNZ/LOOPNE eLoop while not zero/equal 11100000 disp 6/16

taken

ENTER eEnter Procedure 11001000 data-low data-high L

Le0 15

Le1 25

Ll1 22a16(nb1)

LEAVE eLeave Procedure 11001001 8

INT eInterrupt:

Type specified 11001101 type 47

Type 3 11001100 45 ifINT. taken/

INTO eInterrupt on overflow 11001110 48/4 if INT. not

taken

IRET eInterrupt return 11001111 28

BOUND eDetect value out of range 01100010 modreg r/m 33–35

Shaded areas indicate instructions not available in 8086/8088 microsystems.

M80C186XL

INSTRUCTION SET SUMMARY (Continued)

Function Format Clock Comments

Cycles

PROCESSOR CONTROL

CLC eClear carry 11111000 2

CMC eComplement carry 11110101 2

STC eSet carry 11111001 2

CLD eClear direction 11111100 2

STD eSet direction 11111101 2

CLI eClear interrupt 11111010 2

STI eSet interrupt 11111011 2

HLT eHalt 11110100 2

WAIT eWait 10011011 6 ifTEST e0

LOCK eBus lock prefix 11110000 2

NOP eNo Operation 10010000 3

(TTT LLL are opcode to processor extension)

Shaded areas indicate instructions not available in 8086/8088 microsystems.

FOOTNOTES

The Effective Address (EA) of the memory operand

is computed according to the mod and r/m fields:

if mod e11 then r/m is treated as a REG field

if mod e00 then DISP e0*, disp-low and disp-

high are absent

if mod e01 then DISP edisp-low sign-ex-

tended to 16-bits, disp-high is absent

if mod e10 then DISP edisp-high: disp-low

if r/m e000 then EA e(BX) a(SI) aDISP

if r/m e001 then EA e(BX) a(DI) aDISP

if r/m e010 then EA e(BP) a(SI) aDISP

if r/m e011 then EA e(BP) a(DI) aDISP

if r/m e100 then EA e(SI) aDISP

if r/m e101 then EA e(DI) aDISP

if r/m e110 then EA e(BP) aDISP*

if r/m e111 then EA e(BX) aDISP

DISP follows 2nd byte of instruction (before data if

required)

*except if mod e00 and r/m e110 then EA e

disp-high: disp-low.

EA calculation time is 4 clock cycles for all modes,

and is included in the execution times given whenev-

er appropriate.

Segment Override Prefix

0 0 1 reg 1 1 0

reg is assigned according to the following:

Segment

reg Register

00 ES

01 CS

10 SS

11 DS

REG is assigned according to the following table:

16-Bit (w e1) 8-Bit (w e0)

000 AX 000 AL

001 CX 001 CL

010 DX 010 DL

011 BX 011 BL

100 SP 100 AH

101 BP 101 CH

110 SI 110 DH

111 DI 111 BH

The physical addresses of all operands addressed

by the BP register are computed using the SS seg-

ment register. The physical addresses of the desti-

nation operands of the string primitive operations

(those addressed by the DI register) are computed

using the ES segment, which may not be overridden.

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