PRELIMINARY TECHNICAL DATA a 16-Bit, 1 LSB INL, 3 MSPS PulSARTM ADC Preliminary Technical Data AD7621 FEATURES 16 Bits Resolution with No Missing Codes No Pipeline Delay ( SAR architecture ) Differential Input Range: VREF (VREF up to 2.5V) Throughput: 3 MSPS (Wideband Warp and Warp Mode) 2 MSPS (Normal Mode) 1.25 MSPS (Impulse Mode) INL: 1 LSB Max (0.0015% of Full-Scale) S/(N+D): 90 dB Typ @ 100 kHz ( VREF = 2.5V ) THD: -100 dB Typ @ 100 kHz Parallel (16 or 8bits bus) and Serial 5V/3.3V/2.5V Interface SPI/QSPI/MICROWIRE/DSP Compatible On-board Low Drift Reference with Buffer and Temperature sensor Single 2.5 V Supply Operation Power Dissipation: 100 mW Typ @ 3 MSPS Power-Down Mode Package: 48-Lead Quad Flat Pack (LQFP) 48-Lead Frame Chip Scale Package (LFCSP) Speed Upgrade of the AD7677 APPLICATIONS Medical Instruments High Speed Data Acquisition Communications Instrumentation Spectrum Analysis ATE FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND DVDD DGND AGND OVDD AD7621 AVDD REF IN+ IN- OGND SERIAL PORT SER/PAR 16 SWITCHED CAP DAC D[15:0] BUSY PARALLEL INTERFACE PDREF CLOCK CS PDBUF PD RESET RD CONTROL LOGIC AND CALIBRATION CIRCUITRY OB/2C BYTESWAP WARP IMPULSE CNVST PulSAR Selection Type / kSPS 100 - 250 500 - 570 Pseudo AD7651 AD7650/52 Differential AD7660/61 AD7664/66 800 - 1000 AD7653 AD7667 True Bipolar AD7663 AD7665 AD7671 True Differential AD7675 AD7676 AD7677 18 Bit AD7678 Multichannel/ Simultaneous AD7679 AD7674 AD7654 AD7655 >1000 AD7621 GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7621 is a 16-bit, 3 MSPS, charge redistribution SAR, fully differential analog-to-digital converter that operates from a single 2.5 V power supply. The part contains a high-speed 16-bit sampling ADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports. 1. High resolution and Fast Throughput The AD7621 is a 3 MSPS, charge redistribution, 16-bit SAR ADC ( no latency ). It features a very high sampling rate mode (Wideband Warp) for undersampling applications and, for asynchronous conversion rate applications, a fast mode (Normal) and, for low power applications, a reduced power mode (Impulse) where the power is scaled with the throughput. It is available in a 48-lead LQFP or a 48-lead LFCSP with operation specified from -40C to +85C. 2. Excellent accuracy The AD7621 has a maximum integral nonlinearity of 1 LSB with no missing 16-bit code. 3. Single-Supply Operation The AD7621 operates from a single 2.5 V supply and typically dissipates only 100 mW. In impulse mode, its power dissipation decreases with the throughput and it features a power-down mode. 5. Serial or Parallel Interface Versatile parallel (16 or 8 bits bus) or 2-wire serial interface arrangement compatible with either 2.5V, 3.3V or 5 V logic. REV. Pr D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2003 PRELIMINARY TECHNICAL DATA AD7621-SPECIFICATIONS Parameter (-40C to +85C, VREF = AVDD, AVDD = DVDD = OVDD = 2.5 V, unless otherwise noted.)) Conditions Min RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Throughput Rate Time Between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise Gain Error, TMIN to TMAX2 Gain Error Temperature Drift Zero Error, TMIN to TMAX2 Zero Error Temperature Drift Power Supply Sensitivity AC ACCURACY Signal-to-Noise Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise+Distortion) REFERENCE External Reference Voltage Range REF Current Drain REF Voltage with reference buffer Reference Buffer Input Voltage REFBUFIN Input Current INTERNAL REFERENCE Internal Reference Voltage Internal Reference Temp Drift Internal Reference Temp Drift REFBUFIN Line Regulation REFBUFIN Output Resistance Power Supply Rejection Turn-on Settling Time Long-term Stability Hysterisis REFBUFIN Output Resistance Temperature Pin Voltage Output Temperature Sensitivity TEMP pin Output Resistance REV. Pr D Max 16 VIN+ - VIN-V REF VIN+, VIN- to AGND -0.1 fIN = TBD kHz TBD MSPS Throughput In WideBand Warp Mode In Wideband Warp Mode In Warp Mode In Warp Mode In Normal Mode In Normal Mode In Impulse Mode In Impulse Mode +VREF AVDD TBD TBD See Analog Input Section 0 0 -1 -1 16 1 V REF = AVDD 0.7 AVDD = 2.5V 5% TBD TBD TBD TBD ns MSPS MSPS ms ns MSPS ns MSPS +1 +1 LSB1 LSB Bits LSB % of FSR ppm/C LSB ppm/C LSB TBD 90 88.3 100 -100 90 30 50 dB 3 dB dB dB dB dB MHz 1 TBD ns ps rms ns ns Full-Scale Step 50 50 REF 3 MSPS Throughput REFBUFIN=1.2V REFBUFIN @ 25C -40C to +85C 0C to +70C AVDD = 2.5V 5% @ TBD kHz 1,000 Hours @ 25C -2- TBD 2 TBD -1 TBD V V dB A 333 3 3 1 500 2 800 1.25 TBD f IN = 100 kHz, V REF= A V D D 88 V R E F =2.048V f IN = 100 kHz f IN = 100 kHz f IN = 100 kHz, fIN = 100 kHz,-60 dB Input Unit Bits 0.1 0.001 -3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response Overvoltage recovery Typ 2.048 TBD 2.048 1.2 1.2 TBD TBD TBD 16 TBD TBD TBD TBD TBD 313 1 4.3 AVDD 2.1 TBD +1 TBD V A V V A V ppm/C ppm/C ppm/V k dB s ppm ppm k mV mV/C k PRELIMINARY TECHNICAL DATA AD7621 Parameter Conditions Min DIGITAL INPUTS Logic Levels V IL V IH I IL I IH -0.3 +1.7 -1 -1 DIGITAL OUTPUTS Data Format Pipeline Delay VOL V OH POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current4 AVDD DVDD5 OVDD5 Power Dissipation5 TEMPERATURE RANGE8 Specified Performance Typ ISINK = 500 A ISOURCE = -500 A Max Unit +0.6 5.25 +1 +1 V V A A Parallel or Serial 16-Bits Conversion Results Available Immediately After Completed Conversion 0.4 OVDD - 0.3 V V 2.37 2.37 2.3 V V V 2.5 2.5 2.63 2.63 3.6 3 MSPS Throughput 15 4.5 130 PDBUF high @ 3 MSPS4 PDBUF low @ 3 MSPS4 PDBUF high @ 1.25 MSPS6 PDBUF low @ 1.25 MSPS6 In Power-Down Mode7 TMIN to TMAX 100 108 TBD TBD TBD -40 mA mA A TBD TBD TBD TBD TBD mW mW mW mW W +85 C NOTES 1 LSB means Least Significant Bit. With the 2.5 V input range, one LSB is 76.294 V. 2 See Definition of Specifications section. These specifications do not include the error contribution from the external reference. 3 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified. 4 In warp mode. 5 Tested in parallel reading mode. 6 In impulse mode. 7 With all digital inputs forced to DVDD or DGND respectively. 8 Contact factory for extended temperature range. Specifications subject to change without notice. TIMING SPECIFICATIONS (-40C to +85C, AVDD = DVDD = 2.5 V, OVDD = 2.3 V to 3.6 V, unless otherwise noted.) REFER TO FIGURES 12 AND 13 Convert Pulsewidth Time Between Conversions (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except in Master Serial Read After Convert (Warp Mode/Normal Mode/Impulse Mode) Aperture Delay End of Conversion to BUSY LOW Delay Conversion Time (Warp Mode/Normal Mode/Impulse Mode) Acquisition Time (Warp Mode/Normal Mode/Impulse Mode) RESET Pulsewidth REFER TO FIGURES 14, 15, AND 16 (Parallel Interface Modes) CNVST LOW to Data Valid Delay (Warp Mode/Normal Mode/Impulse Mode) Data Valid to BUSY LOW Delay Bus Access Request to Data Valid Bus Relinquish Time REV. Pr D Symbol Min t1 t2 5 333/500/800 Typ t3 t4 t5 t6 t7 t8 t9 -3- Unit Note 1 ns ns 30 263/400/750 ns ns 263/400/750 ns ns ns ns ns 263/400/750 ns 40 15 ns ns ns 1 10 70/100/50 10 t 10 t 11 t 12 t 13 Max 20 2 PRELIMINARY TECHNICAL DATA AD7621 TIMING SPECIFICATIONS (continued) Symbol REFER TO FIGURES 18 AND 19 (Master Serial Interface Modes)2 CS LOW to SYNC Valid Delay CS LOW to Internal SCLK Valid Delay CS LOW to SDOUT Delay CNVST LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay3 Internal SCLK Period 3 Internal SCLK HIGH 3 Internal SCLK LOW 3 SDOUT Valid Setup Time 3 SDOUT Valid Hold Time 3 SCLK Last Edge to SYNC Delay3 CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read after Convert3 CNVST LOW to SYNC Asserted Delay (Warp Mode/Normal Mode/Impulse Mode) SYNC Deasserted to BUSY LOW Delay REFER TO FIGURES 20 AND 22 (Slave Serial Interface Modes) External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK HIGH External SCLK LOW Min Typ t 14 t 15 t 16 t 17 Max Unit TBD TBD TBD ns ns ns ns TBD t 18 t 19 t 20 t 21 t 22 t 23 t 24 t 25 t 26 t 27 t 28 t 29 TBD TBD TBD TBD TBD TBD TBD ns ns ns ns ns ns TBD TBD TBD TBD t 30 t 31 t 32 t 33 t 34 t 35 t 36 t 37 See Table I TBD ns ns ns ns ns TBD ns 5 2 TBD TBD 12.5 5 5 ns ns ns ns ns ns ns 7 NOTES 1 In warp mode only, the maximum time between conversions is 1ms; otherwise, there is no required maximum time. 2 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 3 In serial master read during convert mode. See Table I for serial master read after convert mode. Specifications subject to change without notice. Table I. Serial clock timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum Busy High Width Maximum (Warp) Busy High Width Maximum (Normal) Busy High Width Maximum (Impulse) t18 t19 t19 t20 t21 t22 t23 t24 t28 t28 t28 -4- 0 0 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 0 1 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 1 0 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 1 1 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD unit ns ns ns ns ns ns ns ns ns ns ns REV. Pr D PRELIMINARY TECHNICAL DATA AD7621 ABSOLUTE MAXIMUM RATINGS1 Analog Inputs IN+ 2, IN-2 , REF, REFBUFIN, TEMP, REFGND to AGND . . . . . . . . . . AVDD + 0.3 V to AGND - 0.3 V Ground Voltage Differences AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . 0.3 V Supply Voltages AVDD, DVDD . . . . . . . . . . . . . . . . . . . -0.3V to +2.7 V O V D D . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +3.8 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 5.5V Internal Power Dissipation 3 . . . . . . . . . . . . . . . . 700 mW Internal Power Dissipation 4 . . . . . . . . . . . . . . . . . . . 2.5W Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage Temperature Range . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 300C 500A TO OUTPUT PIN IOL 1.4V CL 50pF* 500A IOH *IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 50pF MAXIMUM. Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, CL = 10 pF 2V 0.8V NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Input section. 3 Specification is for device in free air: 48-Lead LQFP: JA = 91C/W, JC = 30C/W. 4 Specification is for device in free air: 48-Lead LFCSP: JA = 26C/W. tDELAY tDELAY 2V 0.8V 2V 0.8V Figure 2. Voltage Reference Levels for Timing ORDERING GUIDE Model Temperature Range Package Description Package Option AD7621AST AD7621ASTRL AD7621ACP AD7621ACPRL EVAL-AD7621CB 1 EVAL-CONTROL BRD3 2 -40C -40C -40C -40C Quad Flatpack (LQFP) Quad Flatpack (LQFP) Chip Scale (LFCSP) Chip Scale (LFCSP) Evaluation Board Controller Board ST-48 ST-48 CP-48 CP-48 to to to to +85C +85C +85C +85C NOTES 1 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. 2 This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7621 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. Pr D -5- WARNING ING! ESD SENSITIVE DEVICE PRELIMINARY TECHNICAL DATA AD7621 REFGND REF IN- AGND NC IN+ AGND AVDD PDBUF PDREF REFBUFIN TEMP PIN CONFIGURATION 48-Lead LQFP and 48-Lead LFCSP (ST-48 and CP-48) 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 AVDD 2 36 AGND PIN 1 IDENTIFIER 35 CNVST NC 3 BYTESWAP 4 34 PD 33 RESET OB/2C 5 32 CS AD7621 WARP 6 IMPULSE 7 31 RD TOP VIEW (Not to Scale) SER/PAR 8 30 DGND 29 BUSY D0 9 D1 10 28 D15 D2/DIVSCLK[0] 11 D3/DIVSCLK[1] 12 26 D13 25 D12 -6- D11/RDERROR D9/SCLK D10/SYNC DVDD DGND D8/SDOUT OVDD D7/RDC/SDIN OGND 13 14 15 16 17 18 19 20 21 22 23 24 D4/EXT/INT D5/INVSYNC D6/INVSCLK NC = NO CONNECT 27 D14 REV. Pr D PRELIMINARY TECHNICAL DATA AD7621 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type 1, 41, 42 AGND P 2, 44 AVDD P 3, 40 NC 4 BYTESWAP D I 5 OB/2C DI 6 WARP DI 7 IMPULSE DI 8 S E R / PAR DI 9, 10 D[0:1] DO 11,12 D[2:3]or DI/O DIVSCLK[0:1] 13 D4 DI/O or EXT/INT 14 D5 DI/O or INVSYNC 15 D6 DI/O or INVSCLK 16 D7 DI/O or RDC/SDIN 17 18 REV. Pr D OGND OVDD P P Description Analog Power Ground Pin. Input Analog Power Pins. Nominally 2.5 V. No Connect. Parallel Mode Selection (8-bit/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. Straight Binary/Binary Two's Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted resulting in a two's complement output from its internal shift register. Conversion mode selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. Conversion mode selection. When HIGH and WARP LOW, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface is selected and some bits of the data bus are used as a serial port. Bit 0 and Bit 1 of the parallel port data output bus. When SER/PAR is HIGH, these outputs are in high impedance. When SER/PAR is LOW, these pins are Bit 2 and Bit 3 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW, which is serial master read after convert, these inputs, part of the serial port, are used to slow down if desired the internal serial clock which clocks the data output. In other serial modes, these pins are high impedance outputs. When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave mode. When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of E X T /INT . When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. Input/Output Interface Digital Power Ground. Input/Output Interface Digital Power. Nominally at the same supply than the supply -7- PRELIMINARY TECHNICAL DATA AD7621 Pin No. Mnemonic Type 19 20 21 DVDD DGND D8 P P DO or SDOUT 22 D9 DI/O or SCLK 23 D10 DO or SYNC 24 D11 DO or RDERROR 25-28 D[12:15] DO 29 BUSY DO 30 31 DGND RD P DI 32 CS DI 33 RESET DI 34 PD DI 35 CNVST DI 36 37 AGND REF P AI 38 REFGND AI Description of the host interface (2.5 V or 3 V). Digital Power. Nominally at 2.5 V. Digital Power Ground. When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7621 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode, when EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge. When SER/PAR is LOW, this output is used as the Bit 9 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. When SER/PAR is LOW, this output is used as the Bit 10 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. When SER/PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus. When SER/PAR is HIGH and when EXT/INT is HIGH, this output, part of the serial port, is used as a incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high. Bit 12 to Bit 15 of the Parallel Port Data output bus. These pins are always outputs regard less of the interface mode. Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. Must be tied to digital ground. Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock. Reset Input. When set to a logic HIGH, reset the AD7621. Current conversion if any is aborted. If not used, this pin could be tied to DGND. Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW), if CNVST is held LOW when the acquisition phase (t8) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. Must be tied to analog ground. Reference Input Voltage and Internal Reference Buffer Output. Apply an external reference on this pin if the internal reference buffer is not used. Should be decoupled effectively with or without the internal buffer. Reference Input Analog Ground. -8- REV. Pr D PRELIMINARY TECHNICAL DATA AD7621 Pin No. Mnemonic Type Description 39 43 45 46 ININ+ TEMP REFBUFIN AI AI AO AI 47 PDREF DI 48 PDBUF DI Differential Negative Analog Input. Differential Negative Analog Input. Temperature sensor analog output typically 1mV/C. Internal Reference Output and Reference Buffer Input Voltage. The internal reference buffer has a fixed gain. It outputs 2.048V typically when 1.2V is applied on this pin. Allows choice of Internal or External voltage reference. When HIGH, the internal reference is switched off and an external reference must been used. When LOW, the on-chip reference is turned on. Allows choice of buffering reference. When LOW, the buffer is selected. When HIGH, the buffer is switched off. NOTES AI = Analog Input AI/O = Bidirectional Analog AO = Analog Output DI = Digital Input DI/O = Bidirectional Digital DO = Digital Output P = Power REV. Pr D -9- PRELIMINARY TECHNICAL DATA AD7621 DEFINITION OF SPECIFICATIONS Integral nonlinearity error (INL) Linearity error refers to the deviation of each individual code from a line drawn from "negative full scale" through "positive full scale". The point used as "negative full scale" occurs 1/2 LSB before the first code transition. "Positive full scale" is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Differential nonlinearity error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Gain error The first transition (from 000 . . . 00 to 000 . . . 01) should occur for an analog voltage 1/2 LSB above the nominal - full scale (-2.047962 V for the 2.048V range). The last transition (from 111 . . . 10 to 111 . . . 11) should occur for an analog voltage 1 1/2 LSB below the nominal full scale (2.047886 V for the 2.048V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Zero error The zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Signal to (noise + distortion) ratio (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels. Aperture delay Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient response The time required for the AD7621 to achieve its rated accuracy after a full-scale step function is applied to its input. Reference Voltage Temperature Coefficient The change of the internal reference output voltage V over the operating temperature range and normalized by the output voltage at 25C, expressed in ppm/C. The equation follows: TCV (ppm / C ) = V (T2 ) - V (T1) x 106 V (25C ) x (T2 - T1) where V(25C) = V at 25C V(T2) = V at Temperature 2 V(T1) = V at Temperature 1 Reference Voltage Long-Term Stability Typical shift of output voltage at 25C on a sample of parts subjected to operation life test of 1000 hours at 125C: Spurious free dynamic range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective number of bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula: V (ppm ) = V (t1) - V (t 0 ) x 106 V (t 0 ) where V(t0) = V at 25C at Time 0 V(t1) = V at 25C after 1,000 hours operation at 125C ENOB = (S/[N+D] dB - 1.76)/6.02) and is expressed in bits. Total harmonic distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Reference Voltage Thermal Hysteresis Thermal hysteresis is defined as the change of output voltage after the device is cycled through temperature from +25C to -40C to +125C and back to +25C. This is a typical value from a sample of parts put through such a cycle Dynamic range Dynamic range is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. VHYS (ppm ) = Signal-to-noise ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. VTC - V (25C ) x 106 V (25C ) where V(25C) = V at 25C VTC = V at 25C after temperature cycle at +25C to -40C to +125C and back to +25C -10- REV. Pr D PRELIMINARY TECHNICAL DATA Typical Performance Characteristics- AD7621 To Be Supplied To Be Supplied TPC 1. Integral Nonlinearity vs. Code TPC 4. Differential Nonlinearity vs. Code To Be Supplied To Be Supplied TPC 2. Histogram of 131,072 Conversions of a DC Input at the Code Transition TPC 5. Histogram of 131,072 Conversions of a DC Input at the Code Center To Be Supplied To Be Supplied TPC 3. Typical Positive INL Distribution (TBD Units) TPC 6. Typical Negative INL Distribution (TBD Units) REV. Pr D -11- PRELIMINARY TECHNICAL DATA AD7621 To Be Supplied To Be Supplied TPC 7. Typical INL and DNL vs Temperature TPC 10. Typical INL and DNL vs Sampling rate To Be Supplied To Be Supplied TPC 8. FFT TPC 11. SNR, S/(N+D) and ENOB vs. Frequency To Be Supplied To Be Supplied TPC 9. FFT TPC 12. THD, SFDR and Harmonics vs. Frequency -12- REV. Pr D PRELIMINARY TECHNICAL DATA AD7621 To Be Supplied To Be Supplied TPC 13. SNR, S/(N+D) and THD vs. Input Level TPC 16.Operating Current vs. Sampling Rate To Be Supplied To Be Supplied TPC 14. SNR, S/(N+D) and ENOB vs Temperature TPC 17. Power-Down Operating Currents vs. Temperature To Be Supplied To Be Supplied TPC 15. THD, SFDR and Harmonics vs Temperature TPC 18. Positive and Negative Full Scale, Offset and Reference Buffer Gain vs. Temperature REV. Pr D -13- PRELIMINARY TECHNICAL DATA AD7621 To Be Supplied To Be Supplied TPC 19.Positive and Negative Full Scale, Offset and Reference Buffer Gain vs. Supply . To Be Supplied TPC 22. Typical Internal Reference Temperature Drift Distribution (TBD Units) To Be Supplied TPC 20.Typical Delay vs. Load Capacitance CL TPC 23. Typical Internal Reference Hysterisis Distribution (TBD Units) To Be Supplied TPC 21.Typical Internal Reference voltage vs. Temperature -14- REV. Pr D PRELIMINARY TECHNICAL DATA AD7621 IN+ LSB MSB 32,768C 16,384C 4C 2C C SW + SWITCHES CONTROL C BUSY REF COMP CONTROL LOGIC OUTPUT CODE REFGND 32,768C 16,384C 4C 2C MSB C C SW LSB CNVST IN - Figure 3. ADC Simplified Schematic CIRCUIT INFORMATION The AD7621 is a very fast, low-power, single-supply, precise 16-bit analog-to-digital converter (ADC) using successive approximation architecture. The AD7621 features different modes to optimize performances according to the applications. In Warp mode, the AD7621 is capable of converting 3,000,000 samples per second (3 MSPS). The AD7621 provides the user with an on-chip track/hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7621 can be operated from a single 2.5 V supply and be interfaced to either 5 V or 3.3 V or 2.5 V digital logic. It is housed in a 48-lead LQFP or a tiny LFCSP packages that combines space savings and allows flexible configurations as either serial or parallel interface. The AD7621 is pin-to-pin-compatible with the AD7674. CONVERTER OPERATION The AD7621 is a successive approximation analog-todigital converter based on a charge redistribution DAC. Figure 3 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator's input are connected to AGND via SW+ and SW-. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on IN+ and IN- inputs. When the acquisition phase is complete and the CNVST input goes low, a conversion phase is initiated. When the conversion phase begins, SW+ and SW- are opened first. The two capacitor arrays are then disconREV. Pr D nected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the inputs IN+ and IN- captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND or REF, the comparator input varies by binary weighted voltage steps (VREF/2, V REF/4 . . . V REF/65536). The control logic toggles these switches, starting with the MSB first, in order to bring the comparator back into a balanced condition. After the completion of this process, the control logic generates the ADC output code and brings BUSY output low. Modes of Operation The AD7621 features three modes of operations, Warp, Normal, and Impulse. Each of these modes is more suitable for specific applications. The Warp mode allows the fastest conversion rate up to 3 MSPS. However, in this mode, and this mode only, the full specified accuracy is guaranteed only when the time between conversion does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms, for instance, after power-up, the first conversion result should be ignored. This mode makes the AD7621 ideal for applications where fast sample rate are required. The normal mode is the fastest mode (2 MSPS) without any limitation about the time between conversions. This mode makes the AD7621 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. The impulse mode, the lowest power dissipation mode, allows power saving between conversions. The maximum throughput in this mode is 1.25 MSPS. This feature makes the AD7621 ideal for battery-powered applications. -15- PRELIMINARY TECHNICAL DATA AD7621 Transfer Functions Table III. Output Codes and Ideal Input Voltages ADC CODE - Straight Binary Using the OB/2C digital input, the AD7621 offers two output codings: straight binary and two's complement. The ideal transfer characteristic for the AD7621 is shown in Figure 4 and Table III. Digital Output Code Hexa Analog Straight Two's Input Binary CompleVREF = 2.048V ment D escription FSR -1 LSB FSR - 2 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR 111...111 111...110 111...101 2.047924 V 2.047849 V 75.684V 0 V -75.684V -2.047924 V -2.048 V 3FFFF1 3FFFE 20001 20000 1FFFF 00001 00000 2 1FFFF1 1FFE 00001 00000 3FFFF 20001 20000 2 NOTES 1 This is also the code for overrange analog input (V IN+ - V IN- above V REF - V REFGND ). 2 This is also the code for underrange analog input (V IN+ - V IN- below -V REF + V REFGND ). 000...010 000...001 000...000 -FS -FS+1 LSB +FS-1 LSB -FS+0.5 LSB +FS-1.5 LSB ANALOG INPUT Figure 4. ADC Ideal Transfer Function DVDD ANALOG SUPPLY (2.5V) 10 DIGITAL SUPPLY (2.5V OR 3.3V) note 5 100nF 10F 10F AVDD AGND 100nF DGND DVDD 100nF OVDD 10F OGND SERIAL PORT REFBUFIN SCLK CREF note 1 100nF SDOUT note 1 REF BUSY CREF AD7621 10F note 2 REFGND MODE0 15 U1 ANALOG INPUT+ D note 6 MODE1 IN+ note 3 C/P/DSP 50 CNVST OB/2C DVDD 1.2nF AD8021 CC note 4 PDREF PDBUF CLOCK CS RD 15 U2 ANALOG INPUT- IN- note 3 RESET PD 1.2nF AD8021 CC note 4 NOTES : Note 1 : See Voltage Reference Input Section. Note 2 : CREF is 10F ceramic capacitor or low esr tantalum. Ceramic size 1206 Panasonic ECJ-3xB0J106 is recommended. See Voltage Reference Input Section. Note 3 : The AD8021 is recommended. See Driver Amplifier Choice Section. Note 4 : See Analog Inputs Section. Note 5 : Option. See Power Supply Section. Note 6 : Optional Low jitter CNVST. See Conversion Control Section. -16- REV. Pr D PRELIMINARY TECHNICAL DATA AD7621 TYPICAL CONNECTION DIAGRAM Figure 5 shows a typical connection diagram for the AD7621. Different circuitry shown on this diagram are optional and are discussed below. Analog Inputs Figure 6 shows a simplified analog input section of the AD7621. To Be Supplied To Be Supplied Figure 7. Analog Input CMRR vs. Frequency Figure 6. AD7621 simplified Analog Input. The diodes shown in Figure 6 provide ESD protection for the inputs. Care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs. This will cause these diodes to become forwardbiased and start conducting current. These diodes can handle a forward-biased current of 150 mA maximum. This condition could eventually occur when the input buffer's (U1) or (U2) supplies are different from AVDD. In such case, an input buffer with a short-circuit current limitation can be used to protect the part. This analog input structure is a true differential structure. By using these differential inputs, signals common to both inputs are rejected as shown in Figure 7 which represents the typical CMRR over frequency. During the acquisition phase, for AC signals, the AD7621 behaves like a one pole RC filter consisted of the equivalent resistance R+ , R- and CS. The resistors R+ and Rare typically TBD and are lumped component made up of some serial resistor and the on resistance of the switches. The capacitor CS is typically TBD pF and is mainly the ADC sampling capacitor. This one pole filter with a typical -3dB cutoff frequency of 50 MHz reduces undesirable aliasing effect and limits the noise coming from the inputs. Because the input impedance of the AD7621 is very high, the AD7621 can be driven directly by a low impedance source without gain error. That allows to put, as shown in Figure 5, an external one-pole RC filter between the output of the amplifier output and the ADC analog inputs to even further improve the noise filtering done by the AD7621 analog input circuit. However, the source impedance has to be kept low because it affects the ac performances, especially the total harmonic distortion. The maximum source impedance depends on the amount of total harmonic distortion (THD) that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. Driver Amplifier Choice Although the AD7621 is easy to drive, the driver amplifier needs to meet at least the following requirements: * The driver amplifier and the AD7621 analog input circuit have to be able together to settle for a full-scale step the capacitor array at a 16-bit level (0.0015%). In the amplifier's datasheet, the settling at 0.1% or 0.01% is more commonly specified. It could significantly differ from the settling time at 16 bit level and, therefore, it should be verified prior to the driver selection. The tiny op-amp AD8021 which combines ultra low noise and a high gain bandwidth meets this settling time requirement. REV. Pr D -17- PRELIMINARY TECHNICAL DATA AD7621 * The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7621. The noise coming from the driver is filtered by the AD7621 analog input circuit one-pole low-pass filter made by R+, R- and CS. The SNR degradation due to the amplifier is : SNRLOSS ANALOG INPUT (UNIPOLAR 0 to 2.048V) U1 AD8021 10pF 15 590 1.2nF 590 56 = 20LOG 3136 + f -3dB NeN 2 , ( ) IN- U2 1k AD8021 1k 100nF IN+ AD7621 15 1.2nF REF 10pF 10F where : f-3dB is the -3dB input bandwidth in MHz of the AD7621 (50 MHz) or the cutoff frequency of the input filter if any used Figure 8. Single Ended to Differential Driver Circuit ( internal reference buffer used ) N is the noise factor of the amplifiers ( 1 if in buffer configuration ) Voltage Reference The AD7621 allows the choice of either a very low temperature drift internal voltage reference or an external reference. eN is the equivalent input noise voltage of each op-amp in nV/(Hz) 1/2 For instance, a driver with an equivalent input noise of 2nV/Hz like the AD8021 and configured as a buffer, thus with a noise gain of +1, the SNR degrades by only 0.17 dB with the filter in figure 5, and 0.8 dB without. * The driver needs to have a THD performance suitable to that of the AD7621. The AD8021 meets these requirements and is usually appropriate for almost all applications. The AD8021 needs an external compensation capacitor of 10 pF. This capacitor should have good linearity as an NPO ceramic or mica type. Unlike many ADC with internal reference, the internal reference of the AD7621 provides excellent performances and can be used in almost all applications. It is temperature compensated to 1.2V TBD mV with a typical drift of TBD ppm/C, a typical long-term stability of TBD ppm and a typical hysterisis of TBD ppm. However, the advantages to use the external reference voltage directly are : - The power saving of about 8mW typical when the internal reference and its buffer are powered down ( PDREF and PDBUF High ) The AD8022 could also be used where dual version is needed and gain of 1 is used. - The SNR and dynamic range improvement of about 1.7 dB resulting of the use of a reference voltage very close to the supply (2.5V) instead of a typical 2.048V reference when the internal buffer is used. Single to Differential Driver For applications using unipolar analog signals, a singleended to differential driver will allow for a differential input into the part. The schematic is shown in Figure 8. This configuration, when provided an input signal of 0 to VREF , will produce a differential VREF with midscale at V REF /2. To use the internal reference along with the internal buffer, PDREF and PDBUF should both be LOW. This will produce a voltage on REFBUFIN of 1.2 V and the buffer will gain it up, resulting in a 2.048 V reference on REF pin. If the application can tolerate more noise, the AD8138, differential driver, can be used. It is useful to decouple the REFBUFIN pin with a 100 nF ceramic capacitor. The output impedance of the REFBUFIN pin is 16 k. Thus, the 100 nF capacitor provides an RC filter for noise reduction. To use an external reference along with the internal buffer, PDREF should be HIGH and PDBUF should be low. This powers down the internal reference and allows for the 1.2 V reference to be applied to REFBUFIN. To use an external reference directly on REF pin, PDREF and PDBUF should both be HIGH. It should be noted that the internal reference and internal buffer are independent of the power down (PD) pin of the part. Furthermore, powering up the internal reference and internal buffer requires time due to the charge of the REF decoupling. -18- REV. Pr D PRELIMINARY TECHNICAL DATA AD7621 In both cases, the voltage reference input REF has a dynamic input impedance and requires, therefore, an efficient decoupling between REF and REFGND inputs. When the internal reference buffer is used, this decoupling consists of a 10 F ceramic capacitor ( e.g. : Panasonic ECJ-3xB0J106 1206 size ). When external reference is used, the decoupling consists of a low ESR 47 F tantalum capacitor connected to the REF and REFGND inputs with minimum parasitic inductance. To Be Supplied Temperature Sensor The TEMP pin, which measures the temperature of the AD7621, can be used as shown in figure 9. The output of the TEMP pin is applied to one of the inputs of the analog switch (e.g. : ADG779) and the ADC itself is used to measure its own temperature. This configuration could be very useful to improve the calibration accuracy over the temperature range. Figure 10. PSRR vs. Frequency To Be Supplied POWER DISSIPATION Vs. THROUGHPUT In Impulse mode, the AD7621 automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are very low which allows a significant power saving when the conversion rate is reduced as shown in Figure 11. This feature makes the AD7621 ideal for very low-power battery applications. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (i.e., DVDD and DGND). Figure 9. Use of the Temperature Sensor Power Supply The AD7621 uses three sets of power supply pins: an analog 2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.3 V and 5.25 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply as shown in Figure 5. The AD7621 is independent of power supply sequencing and thus free from supply voltage induced latchup. Additionally, it is very insensitive to power supply variations over a wide frequency range as shown in Figure 10. To Be Supplied Figure 11. Power Dissipation vs. Sample Rate REV. Pr D -19- PRELIMINARY TECHNICAL DATA AD7621 CONVERSION CONTROL Figure 12 shows the detailed timing diagrams of the conversion process. The AD7621 is controlled by the signal CNVST which initiates conversion. Once initiated, it cannot be restarted or aborted, even by the power-down input PD, until the conversion is complete. The CNVST signal operates independently of CS and RD signals. t9 RESET BUSY t2 t1 DATA BUS CNVST t8 CNVST BUSY t4 t3 Figure 13. t6 t5 MODE ACQUIRE CONVERT t7 ACQUIRE RESET Timing DIGITAL INTERFACE CONVERT The AD7621 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The AD7621 digital interface also accommodates both 2.5V, 3.3V or 5V logic with either OVDD at 2.5V or 3.3V. OVDD defines the logic high output voltage. In most applications, the OVDD supply pin of the AD7621 is connected to the host system interface 2.5V or 3.3V digital supply. Finally, by using the OB/2C input pin, both two's complement or straight binary coding can be used. t8 Figure 12. Basic Conversion Timing Although CNVST is a digital signal, it should be designed with this special care with fast, clean edges and levels, with minimum overshoot and undershoot or ringing. For applications where the SNR is critical, the CNVST signal should have a very low jitter. Some solutions to achieve that are to use a dedicated oscillator for CNVST generation or, at least, to clock it with a high frequency low jitter clock as shown in Figure 5. In impulse mode, conversions can be automatically initiated. If CNVST is held low when BUSY is low, the AD7621 controls the acquisition phase and then automatically initiates a new conversion. By keeping CNVST low, the AD7621 keeps the conversion process running by itself. It should be noted that the analog input has to be settled when BUSY goes low. Also, at power-up, CNVST should be brought low once to initiate the conversion process. In this mode, the AD7621 could sometimes run slightly faster then the guaranteed limits in the impulse mode. This feature does not exist in warp or normal modes. The two signals CS and RD control the interface. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7621 in multi-circuits applications and is held low in a single AD7621 design. RD is generally used to enable the conversion result on the data bus. CS = RD = 0 t1 CNVST t 10 BUSY t4 t3 DATA BUS t 11 PREVIOUS CONVERSION DATA NEW DATA Figure 14. Master Parallel Data Timing for Reading (Continuous Read) -20- REV. Pr D PRELIMINARY TECHNICAL DATA AD7621 PARALLEL INTERFACE CS = 0 The AD7621 is configured to use the parallel interface with either a 16-bit or 8-bit bus width. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in Figure 15 and Figure 16. When the data is read during the conversion, however, it is recommended that it is read only during the first half of the conversion phase. That avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. t1 CNVST, RD BUSY t4 t3 DATA BUS PREVIOUS CONVERSION t 12 CS t 13 Figure 16. Slave Parallel Data Timing for Reading (Read During Convert) RD CS RD BUSY A0, A1 DATA BUS CURRENT CONVERSION t 12 Pins D[15:8] t 13 HI-Z HI-Z HIGH BYTE t12 Figure 15. Slave Parallel Data Timing for Reading (Read After Convert) Pins D[7:0] HI-Z LOW BYTE t12 LOW BYTE HIGH BYTE Figure 17. 8-Bit and 16-Bit Parallel Interface EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 CS, RD t3 CNVST t 28 BUSY t 30 t 29 t 25 SYNC t 14 t 18 t 19 t 20 SCLK t 24 t 21 1 2 3 D15 D14 14 15 D2 D1 t 26 16 t 15 t 27 SDOUT X t 16 t 22 D0 t 23 Figure 18. Master Serial Data Timing for Reading (Read After Convert) REV. Pr D -21- t13 HI-Z PRELIMINARY TECHNICAL DATA AD7621 SERIAL INTERFACE The AD7621 is configured to use the serial interface when SER/PAR is held high. The AD7621 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on SCLK pin. The output data is valid on both the rising and falling edge of the data clock. That allows a fast serial interface speed by using the same clock edge to output the data from the ADC and to sample the previous bit by the digital host. To accomodate slow digital hosts, the serial clock can be slowed down by using DIVSCLK. SLAVE SERIAL INTERFACE External Clock The AD7621 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When CS and RD are both low, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figure 20 and Figure 22 show the detailed timing diagrams of these methods. MASTER SERIAL INTERFACE Internal Clock The AD7621 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. The AD7621 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired. Depending on RDC/SDIN input, the data can be read after each conversion or during the following conversion. Figure 18 and Figure 19 show the detailed timing diagrams of these two modes. While the AD7621 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the AD7621 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that is toggling only when BUSY is low or, more importantly, that it does not transition during the latter half of BUSY high. Usually, because the AD7621 is used with a fast throughput, the mode master, read during conversion is the most recommended serial mode when it can be used. In read-during-conversion mode, the serial clock and data toggle at appropriate instants which minimize potential feedthrough between digital activity and the critical conversion decisions. In read-after-conversion mode, it should be noted that, unlike in other modes, the signal BUSY returns low after the 16 data bits are pulsed out and not at the end of the conversion phase which results in a longer BUSY width. EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t1 CNVST t3 BUSY t 17 t 25 SYNC t 14 t 19 t 20 t 21 t 15 SCLK 1 t 24 2 3 14 15 t 26 16 t 18 t 27 SDOUT X t 16 t 22 D15 D14 D2 D1 D0 t 23 Figure 19. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) -22- REV. Pr D PRELIMINARY TECHNICAL DATA AD7621 Another advantage is to be able to read the data at any speed up to 80 MHz which accommodates both slow digital host interface and the fastest serial reading. External Discontinuous Clock Data Read After Conversion Though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 20 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning low, the result of this conversion can be read while both CS and RD are low. The data is shifted out, MSB first, with 16 clock pulses and is valid on both rising and falling edge of the clock. Finally, in this mode only, the AD7621 provides a "daisy-chain" feature using the RDC/SDIN input pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when desired as, for instance, in isolated multiconverter applications. An example of the concatenation of two devices is shown in Figure 21. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the edge of SCLK opposite to the one used to shift out the data on SDOUT. Hence, the MSB of the "upstream" converter just follows the LSB of the "downstream" converter on the next SCLK cycle. Among the advantages of this method, the conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. EXT/INT = 1 INVSCLK = 0 RD = 0 CS BUSY t 35 t 36 t 37 SCLK 1 2 3 t 31 15 16 17 18 t 32 X SDOUT D15 t 16 D14 D13 X14 X13 D1 D0 X15 X14 1 X0 Y15 Y14 t 34 SDIN X15 X t 33 Figure 20. Slave Serial Data Timing for Reading (Read After Convert) EXT/INT = 1 RD =0 INVSCLK = 0 CS CNVST BUSY t3 t 36 SCLK t 35 t 37 1 4 15 16 t 32 X SDOUT 3 2 t 31 D15 D14 D15 D1 D0 t 16 Figure 22. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert) REV. Pr D -23- PRELIMINARY TECHNICAL DATA AD7621 MICROPROCESSOR INTERFACING The AD7621 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. The AD7621 is designed to interface either with a parallel 8-bit or 16-bit wide interface or with a general purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7621 to prevent digital noise from coupling into the ADC. The following section illustrates the use of the AD7621 with an SPI equipped DSP, the ADSP-219x. BUSY OUT BUSY BUSY AD7621 AD7621 #2 (UPSTREAM) #1 (DOWNSTREAM) RDC/SDIN SDOUT CNVST RDC/SDIN SDOUT DATA OUT CNVST CS CS SCLK SCLK SCLK IN CS IN CNVST IN Figure 21. Two AD7621s in a "Daisy-Chain" Configuration External Clock Data Read During Conversion Figure 22 shows the detailed timing diagrams of this method. During a conversion, while both CS and RD are both low, the result of the previous conversion can be read. The data is shifted out, MSB first, with 16 clock pulses and is valid on both rising and falling edge of the clock. The 16 bits have to be read before the current conversion is complete. If that is not done, RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. There is no "daisy chain" feature in this mode and RDC/SDIN input should always be tied either high or low. SPI Interface (ADSP-219x) Figure 22 shows an interface diagram between the AD7621 and an SPI-equipped DSP, ADSP219x. To accommodate the slower speed of the DSP, the AD7621 acts as a slave device and data must be read after conversion. This mode also allows the "daisy chain" feature. The convert command could be initiated in response to an internal timer interrupt. The reading process could be initiated in response to the end-of-conversion signal (BUSY going low) using an interrupt line of the DSP. The Serial Peripheral Interface (SPI) on the ADSP-219x is configured for master mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and SPI interrupt enable (TIMOD) =00 by writing to the SPI Control Register (SPICLTx). It should be noted that to meet all timing requirements, the SPI clock should be limited to 17Mbits/s which allow to read an ADC result in about 1.1 s. When higher sampling rate is desired, it is recomended to use one of the parallel interface mode with the ADSP-219x. To reduce performance degradation due to digital activity, a fast discontinuous clock of is recommended to ensure that all the bits are read during the first half of the conversion phase. It is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated. DVDD AD7621* ADSP-219x* SER/PAR EXT/INT BUSY CS SDOUT SCLK RD INVSCLK CNVST PFx SPIxSEL (PFx) MISOx SCKx PFx or TFSx *ADDITIONAL PINS OMITTED FOR CLARITY Figure 23. Interfacing the AD7621 to SPI Interface -24- REV. Pr D PRELIMINARY TECHNICAL DATA AD7621 APPLICATION HINTS Layout The AD7621 has very good immunity to noise on the power supplies. However, care should still be taken with regard to grounding layout. The printed circuit board that houses the AD7621 should be designed so the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7621, or, at least, as close as possible to the AD7621. If the AD7621 is in a system where multiple devices require analog to digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the AD7621. ing on the configuration. OGND is connected to the digital system ground. The layout of the decoupling of the reference voltage is important. The decoupling capacitor should be close to the ADC and connected with short and large traces to minimize parasitic inductances. Evaluating the AD7621 Performance A recommended layout for the AD7621 is outlined in the documentation of the EVAL-AD7621-CB, evaluation board for the AD7621. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the Eval Control Brd3. It is recommended to avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7621 to avoid noise coupling. Fast switching signals like CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other. This will reduce the effect of feedthrough through the board. The power supply lines to the AD7621 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supplies impedance presented to the AD7621 and reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each power supplies pins AVDD, DVDD and OVDD close to, and ideally right up against these pins and their corresponding ground pins. Additionally, low ESR 10 F capacitors should be located in the vicinity of the ADC to further reduce low frequency ripple. The DVDD supply of the AD7621 can be either a separate supply or come from the analog supply, AVDD, or from the digital interface supply, OVDD. When the system digital supply is noisy, or fast switching digital signals are present, it is recommended if no separate supply available, to connect the DVDD digital supply to the analog supply AVDD through an RC filter as shown in Figure 5, and connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high-frequency spikes. The AD7621 has four different ground pins; REFGND, AGND, DGND, and OGND. REFGND senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. AGND is the ground to which most internal ADC analog signals are referenced. This ground must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane dependREV. Pr D -25- PRELIMINARY TECHNICAL DATA AD7621 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead Quad Flatpack (LQFP) (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC SQ 0.030 (0.75) 0.018 (0.45) 37 48 36 1 0.276 (7.00) BSC SQ TOP VIEW (PINS DOWN) COPLANARITY 0.003 (0.08) 0 MIN 25 12 13 24 0.019 (0.5) 0.011 (0.27) BSC 0.006 (0.17) 0.008 (0.2) 0.004 (0.09) 0.057 (1.45) 0.053 (1.35) 7 0 0.006 (0.15) SEATING 0.002 (0.05) PLANE 48-Lead Frame Chip Scale Package (LFCSP) (CP-48) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 37 0.009 (0.24) 36 0.276 (7.0) BSC SQ PIN 1 INDICATOR 0.266 (6.75) BSC SQ TOP VIEW 0.039 (1.00) MAX 0.033 (0.85) NOM 0.008 (0.20) REF 0.215 (5.45) 0.209 (5.30) SQ 0.203 (5.15) 12 25 24 13 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.031 (0.80) MAX 0.026 (0.65) NOM 0.020 (0.50) BSC 1 BOTTOM VIEW 0.020 (0.50) 0.016 (0.40) 0.012 (0.30) 12MAX 48 0.002 (0.05) 0.0004 (0.01) 0.0 (0.0) Paddle connected to AGND ( This connection is not required to meet electrical performances ) CONTROLLING DIMENSIONS ARE IN MILLIMETERS -26- REV. Pr D