SEMICONDUCTOR
TECHNICAL DATA
HIGH SPEED
DUAL MOSFET DRIVERS
PIN CONNECTIONS
Order this document by MC34151/D
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
P SUFFIX
PLASTIC PACKAGE
CASE 626
8
1
1
8
1
2
3
45
6
7
8N.C.
Logic Input A
Gnd
Logic Input B
N.C.
Drive Output A
VCC
Drive Output B
(Top View)
Device Operating
Temperature Range Package
ORDERING INFORMATION
MC34151D
MC34151P TA = 0° to +70°CSO–8
Plastic DIP
MC33151D
MC33151P
SO–8
Plastic DIP
TA = –40° to +85°C
1
MOTOROLA ANALOG IC DEVICE DATA
The MC34151/MC33151 are dual inverting high speed drivers specifically
designed for applications that require low current digital circuitry to drive
large capacitive loads with high slew rates. These devices feature low input
current making them CMOS and LSTTL logic compatible, input hysteresis for
fast output switching that is independent of input transition time, and two high
current totem pole outputs ideally suited for driving power MOSFETs. Also
included is an undervoltage lockout with hysteresis to prevent erratic system
operation at low supply voltages.
Typical applications include switching power supplies, dc to dc
converters, capacitor charge pump voltage doublers/inverters, and motor
controllers.
These devices are available in dual–in–line and surface mount packages.
•Two Independent Channels with 1.5 A Totem Pole Output
•Output Rise and Fall Times of 15 ns with 1000 pF Load
•CMOS/LSTTL Compatible Inputs with Hysteresis
•Undervoltage Lockout with Hysteresis
•Low Standby Current
•Efficient High Frequency Operation
•Enhanced System Performance with Common Switching Regulator
Control ICs
•Pin Out Equivalent to DS0026 and MMH0026
Representative Block Diagram
+
+
+
–
VCC 6
5.7V
Logic Input A
2
Logic Input B
4
Gnd 3
100k
Drive Output A
7
Drive Output B
5
+
+
+
+
100k
Motorola, Inc. 1996 Rev 0
MC34151 MC33151
2MOTOROLA ANALOG IC DEVICE DATA
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage VCC 20 V
Logic Inputs (Note 1) Vin –0.3 to VCC V
Drive Outputs (Note 2)
Totem Pole Sink or Source Current
Diode Clamp Current (Drive Output to VCC)IO
IO(clamp) 1.5
1.0
A
Power Dissipation and Thermal Characteristics
D Suffix SO–8 Package Case 751
Maximum Power Dissipation @ TA = 50°C
Thermal Resistance, Junction–to–Air
P Suffix 8–Pin Package Case 626
Maximum Power Dissipation @ TA = 50°C
Thermal Resistance, Junction–to–Air
PD
RθJA
PD
RθJA
0.56
180
1.0
100
W
°C/W
W
°C/W
Operating Junction Temperature TJ+150 °C
Operating Ambient Temperature
MC34151
MC33151
TA0 to +70
–40 to +85
°C
Storage Temperature Range Tstg –65 to +150 °C
ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = 25°C, for min/max values TA is the only operating ambient
temperature range that applies [Note 3], unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
LOGIC INPUTS
Input Threshold Voltage – High State Logic 1
Input Threshold Voltage – Low State Logic 0 VIH
VIL 2.6
–1.75
1.58 –
0.8 V
Input Current – High State (VIH = 2.6 V)
Input Current – Low State (VIL = 0.8 V) IIH
IIL –
–200
20 500
100 µA
DRIVE OUTPUT
Output Voltage – Low State (ISink = 10 mA)
Output Voltage – Low State (ISink = 50 mA)
Output Voltage – Low State (ISink = 400 mA)
Output Voltage – High State (ISource = 10 mA)
Output Voltage – High State (ISource = 50 mA)
Output Voltage – High State (ISource = 400 mA)
VOL
VOH
–
–
–
10.5
10.4
9.5
0.8
1.1
1.7
11.2
11.1
10.9
1.2
1.5
2.5
–
–
–
V
Output Pull–Down Resistor RPD –100 – kΩ
SWITCHING CHARACTERISTICS (TA = 25°C)
Propagation Delay (10% Input to 10% Output, CL = 1.0 nF)
Logic Input to Drive Output Rise
Logic Input to Drive Output Fall tPLH(in/out)
tPHL(in/out) –
–35
36 100
100
ns
Drive Output Rise T ime (10% to 90%) CL = 1.0 nF
Drive Output Rise T ime (10% to 90%) CL = 2.5 nF tr–
–14
31 30
–ns
Drive Output Fall T ime (90% to 10%) CL = 1.0 nF
Drive Output Fall T ime (90% to 10%) CL = 2.5 nF tf–
–16
32 30
–ns
TOTAL DEVICE
Power Supply Current
Standby (Logic Inputs Grounded)
Operating (CL = 1.0 nF Drive Outputs 1 and 2, f = 100 kHz)
ICC –
–6.0
10.5 10
15
mA
Operating Voltage VCC 6.5 – 18 V
NOTES: 1.For optimum switching speed, the maximum input voltage should be limited to 10 V or VCC, whichever is less.
2.Maximum package power dissipation limits must be observed.
3.Tlow =0°C for MC34151 Thigh = +70°C for MC34151
–40°C for MC33151 +85°C for MC33151
MC34151 MC33151
3
MOTOROLA ANALOG IC DEVICE DATA
Figure 1. Switching Characteristics Test Circuit Figure 2. Switching W aveform Definitions
Figure 3. Logic Input Current versus
Input Voltage Figure 4. Logic Input Threshold Voltage
versus Temperature
Figure 5. Drive Output Low–to–High Propagation
Delay versus Logic Overdrive Voltage Figure 6. Drive Output High–to–Low Propagation
Delay versus Logic Input Overdrive Voltage
Vin, INPUT VOLTAGE (V)
, INPUT CURRENT (mA)
in
I
VCC = 12 V
TA = 25
°
C
TA, AMBIENT TEMPERATURE (
°
C)
Vth, INPUT THRESHOLD VOLTAGE (V)
VCC = 12 V
Upper Threshold
Low State Output
Lower Threshold
High State Output
Vin, INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V)
tPLH(IN/OUT), DRIVE OUTPUT PROPAGATION DELAY (ns)
Overdrive Voltage is with Respect
to the Logic Input Lower Threshold
Vth(lower)
VCC = 12 V
CL = 1.0 nF
TA = 25
°
C
Vin, INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V)
tPHL(IN/OUT), DRIVE OUTPUT PROPAGATION DELAY (ns)
VCC = 12 V
CL = 1.0 nF
TA = 25
°
C
Vth(upper)
Overdrive Voltage is with Respect
to the Logic Input Lower Threshold
+
+
+
–
6
5.7V
Logic Input 2
4
3
100k
Drive Output
7
5
+
+
+
+
100k
12V
4.7 0.1
50 CL
+
5.0 V
0 V 10%
90%
tPHL tPLH
90%
10%
tftr
Logic Input
tr, tf
≤
10 ns
Drive Output
2.4
2.0
1.6
1.2
0.8
0.4
0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
200
160
120
80
40
0
200
160
120
80
40
0
0 2.0 4.0 6.0 8.0 10 12 –55 –25 0 25 50 75 100 125
–1.6 –1.2 –0.8 –0.4 0 0 1.0 2.0 3.0 4.0
MC34151 MC33151
4MOTOROLA ANALOG IC DEVICE DATA
VCC = 12 V
Vin = 5 V to 0 V
CL = 1.0 nF
TA = 25
°
C
Figure 7. Propagation Delay Figure 8. Drive Output Clamp Voltage
versus Clamp Current
Figure 9. Drive Output Saturation Voltage
versus Load Current Figure 10. Drive Output Saturation Voltage
versus Temperature
Figure 11. Drive Output Rise Time Figure 12. Drive Output Fall Time
90%
10%
50 ns/DIV
90%
10%
10 ns/DIV
90%
10%
10 ns/DIV
IO, OUTPUT LOAD CURRENT (A)
Vclamp, OUTPUT CLAMP VOLTAGE (V)
High State Clamp
(Drive Output Driven Above VCC)
VCC
Gnd Low State Clamp
(Drive Output Driven Below Ground)
VCC = 12 V
80
µ
s Pulsed Load
120 Hz Rate
TA = 25
°
C
IO, OUTPUT LOAD CURRENT (A)
Vsat , OUTPUT SATURATION VOLTAGE(V)
Source Saturation
(Load to Ground) VCC = 12 V
80
µ
s Pulsed Load
120 Hz Rate
TA = 25
°
C
VCC
Sink Saturation
(Load to VCC)Gnd
TA, AMBIENT TEMPERATURE (
°
C)
Vsat , OUTPUT SATURATION VOLTAGE(V)
Source Saturation
(Load to Ground)
Sink Saturation
(Load to VCC)
VCC = 12 V
Isource = 400 mA
Isink = 400 mA
VCC Isource = 10 mA
Isink = 10 mA
Gnd
Drive Output
Logic Input VCC = 12 V
Vin = 5 V to 0 V
CL = 1.0 nF
TA = 25
°
C
VCC = 12 V
Vin = 5 V to 0 V
CL = 1.0 nF
TA = 25
°
C
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 –55 –25 0 25 50 75 100 125
3.0
2.0
1.0
0
0
–1.0
0
–1.0
–2.0
–3.0
3.0
2.0
1.0
0
0
–0.5
–0.7
–0.9
–1.1
1.9
1.7
1.5
1.0
0.8
0.6
0
MC34151 MC33151
5
MOTOROLA ANALOG IC DEVICE DATA
Figure 13. Drive Output Rise and Fall Time
versus Load Capacitance Figure 14. Supply Current versus Drive Output
Load Capacitance
Figure 15. Supply Current versus Input Frequency Figure 16. Supply Current versus Supply Voltage
CL, OUTPUT LOAD CAPACITANCE (nF)
–t , OUTPUT RISE-FALL TIME(ns)
tf
tr
tr
VCC = 12 V
VIN = 0 V to 5.0 V
TA = 25
°
C
CL, OUTPUT LOAD CAPACITANCE (nF)
ICC, SUPPLY CURRENT (mA)
VCC = 12 V
Both Logic Inputs Driven
0 V to 5.0 V
50% Duty Cycle
Both Drive Outputs Loaded
TA = 25
°
C
f = 500 kHz
f = 200 kHz
f = 50 kHz
ICC, SUPPL Y CURRENT (mA)
1
23
4
Both Logic Inputs Driven
0 V to 5.0 V,
50% Duty Cycle
Both Drive Outputs Loaded
TA = 25
°
C
1 – VCC = 18 V, CL = 2.5 nF
2 – VCC = 12 V, CL = 2.5 nF
3 – VCC = 18 V, CL = 1.0 nF
4 – VCC = 12 V, CL = 1.0 nF
f, INPUT FREQUENCY (Hz)
ICC, SUPPLY CURRENT (mA)
VCC, SUPPLY VOLTAGE (V)
TA = 25
°
C
Logic Inputs at VCC
Low State Drive Outputs
Logic Inputs Grounded
High State Drive Outputs
f
80
60
40
20
0
80
60
40
20
0
80
60
40
20
0
8.0
6.0
4.0
2.0
0
0.1 1.0 10 0.1 1.0 10
100 1.0 M 0 4.0 8.0 12 16
10 k
APPLICATIONS INFORMATION
Description
The MC34151 is a dual inverting high speed driver
specifically designed to interface low current digital circuitry
with power MOSFETs. This device is constructed with
Schottky clamped Bipolar Analog technology which offers a
high degree of performance and ruggedness in hostile
industrial environments.
Input Stage
The Logic Inputs have 170 mV of hysteresis with the input
threshold centered at 1.67 V. The input thresholds are
insensitive to VCC making this device directly compatible with
CMOS and LSTTL logic families over its entire operating
voltage range. Input hysteresis provides fast output switching
that is independent of the input signal transition time,
preventing output oscillations as the input thresholds are
crossed. The inputs are designed to accept a signal
amplitude ranging from ground to VCC. This allows the output
of one channel to directly drive the input of a second channel
for master–slave operation. Each input has a 30 kΩ
pull–down resistor so that an unconnected open input will
cause the associated Drive Output to be in a known high
state.
Output Stage
Each totem pole Drive Output is capable of sourcing and
sinking up to 1.5 A with a typical ‘on’ resistance of 2.4 Ω at
1.0 A. The low ‘on’ resistance allows high output currents to
be attained at a lower VCC than with comparative CMOS
drivers. Each output has a 100 kΩ pull–down resistor to keep
the MOSFET gate low when VCC is less than 1.4 V. No over
current or thermal protection has been designed into the
device, so output shorting to VCC or ground must be avoided.
Parasitic inductance in series with the load will cause the
driver outputs to ring above VCC during the turn–on transition,
and below ground during the turn–off transition. With CMOS
drivers, this mode of operation can cause a destructive
output latch–up condition. The MC34151 is immune to output
latch–up. The Drive Outputs contain an internal diode to VCC
for clamping positive voltage transients. When operating with
VCC at 18 V, proper power supply bypassing must be
observed to prevent the output ringing from exceeding the
maximum 20 V device rating. Negative output transients are
clamped by the internal NPN pull–up transistor. Since full
supply voltage is applied across the NPN pull–up during the
negative output transient, power dissipation at high
frequencies can become excessive. Figures 19, 20, and 21
show a method of using external Schottky diode clamps to
reduce driver power dissipation.
Undervoltage Lockout
An undervoltage lockout with hysteresis prevents erratic
system operation at low supply voltages. The UVLO forces
the Drive Outputs into a low state as VCC rises from 1.4 V to
MC34151 MC33151
6MOTOROLA ANALOG IC DEVICE DATA
the 5.8 V upper threshold. The lower UVLO threshold is 5.3 V ,
yielding about 500 mV of hysteresis.
Power Dissipation
Circuit performance and long term reliability are enhanced
with reduced die temperature. Die temperature increase is
directly related to the power that the integrated circuit must
dissipate and the total thermal resistance from the junction to
ambient. The formula for calculating the junction temperature
with the package in free air is:
TJ =T
A
+ PD (RθJA)
where: TJ = Junction Temperature
TA = Ambient Temperature
PD = Power Dissipation
RθJA =Thermal Resistance Junction to Ambient
There are three basic components that make up total
power to be dissipated when driving a capacitive load with
respect to ground. They are:
PD =PQ + PC + PT
where: PQ = Quiescent Power Dissipation
PC = Capacitive Load Power Dissipation
PT = Transition Power Dissipation
The quiescent power supply current depends on the
supply voltage and duty cycle as shown in Figure 16. The
device’s quiescent power dissipation is:
PQ = VCC I
CCL (1–D) + ICCH (D)
where: ICCL = Supply Current with Low State Drive
Outputs
ICCH = Supply Current with High State Drive
Outputs
D = Output Duty Cycle
The capacitive load power dissipation is directly related to
the load capacitance value, frequency, and Drive Output
voltage swing. The capacitive load power dissipation per
driver is:
PC =V
CC (VOH – VOL) CL f
where: VOH = High State Drive Output Voltage
VOL = Low State Drive Output Voltage
CL = Load Capacitance
f = frequency
When driving a MOSFET, the calculation of capacitive load
power PC is somewhat complicated by the changing gate to
source capacitance CGS as the device switches. T o aid in this
calculation, power MOSFET manufacturers provide gate
charge information on their data sheets. Figure 17 shows a
curve of gate voltage versus gate charge for the Motorola
MTM15N50. Note that there are three distinct slopes to the
curve representing different input capacitance values. To
completely switch the MOSFET ‘on’, the gate must be
brought to 10 V with respect to the source. The graph shows
that a gate charge Qg of 110 nC is required when operating
the MOSFET with a drain to source voltage VDS of 400 V.
VGS, GATE–TO–SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
CGS =
∆
Qg
16
12
8.0
4.0
00 40 80 120 160
VDS = 100 V VDS = 400 V
8.9 nF
2.0 nF
MTM15N50
ID = 15 A
TA = 25
°
C
Figure 17. Gate–To–Source Voltage
versus Gate Charge
∆
VGS
The capacitive load power dissipation is directly related to the
required gate charge, and operating frequency. The
capacitive load power dissipation per driver is:
PC(MOSFET) = VC Qg f
The flat region from 10 nC to 55 nC is caused by the
drain–to–gate Miller capacitance, occuring while the
MOSFET is in the linear region dissipating substantial
amounts of power. The high output current capability of the
MC34151 is able to quickly deliver the required gate charge
for fast power efficient MOSFET switching. By operating the
MC34151 at a higher VCC, additional charge can be provided
to bring the gate above 10 V. This will reduce the ‘on’
resistance of the MOSFET at the expense of higher driver
dissipation at a given operating frequency.
The transition power dissipation is due to extremely short
simultaneous conduction of internal circuit nodes when the
Drive Outputs change state. The transition power dissipation
per driver is approximately:
PT ≈ VCC (1.08 VCC CL f – 8 × 10–4)
PT must be greater than zero.
Switching time characterization of the MC34151 is
performed with fixed capacitive loads. Figure 13 shows that
for small capacitance loads, the switching speed is limited by
transistor turn–on/off time and the slew rate of the internal
nodes. For large capacitance loads, the switching speed is
limited by the maximum output current capability of the
integrated circuit.
MC34151 MC33151
7
MOTOROLA ANALOG IC DEVICE DATA
LAYOUT CONSIDERATIONS
High frequency printed circuit layout techniques are
imperative to prevent excessive output ringing and
overshoot. Do not attempt to construct the driver circuit
on wire–wrap or plug–in prototype boards. When driving
large capacitive loads, the printed circuit board must contain
a low inductance ground plane to minimize the voltage spikes
induced by the high ground ripple currents. All high current
loops should be kept as short as possible using heavy copper
runs to provide a low impedance high frequency path. For
optimum drive performance, it is recommended that the initial
circuit design contains dual power supply bypass capacitors
connected with short leads as close to the VCC pin and
ground as the layout will permit. Suggested capacitors are a
low inductance 0.1 µF ceramic in parallel with a 4.7 µF
tantalum. Additional bypass capacitors may be required
depending upon Drive Output loading and circuit layout.
Proper printed circuit board layout is extremely critical
and cannot be over emphasized.
The MC34151 greatly enhances the drive capabilities of common switching
regulators and CMOS/TTL logic devices.
Figure 18. Enhanced System Performance with
Common Switching Regulators Figure 19. MOSFET Parasitic Oscillations
Figure 20. Direct T ransformer Drive Figure 21. Isolated MOSFET Drive
Series gate resistor Rg may be needed to damp high frequency parasitic
oscillations caused by the MOSFET input capacitance and any series
wiring inductance in the gate–source circuit. Rg will decrease the
MOSFET switching speed. Schottky diode D1 can reduce the driver’s
power dissipation due to excessive ringing, by preventing the output pin
from being driven below ground.
Output Schottky diodes are recommended when driving inductive loads at
high frequencies. The diodes reduce the driver’s power dissipation by
preventing the output pins from being driven above VCC and below ground.
+
–
VCC
47 0.1
6
5.7V
TL494
or
TL594
2
4
3
100k100k
7
5
Vin
++
++
+
+
100k
1N5819
D1
Rg
Vin
+
+
100k100k
3
7
5
4 X
1N5819
+
+
+
+
3
100k
1N
5819
Isolation
Boundary
MC34151 MC33151
8MOTOROLA ANALOG IC DEVICE DATA
Output Load Regulation
IO (mA) +VO (V) –VO (V)
027.7 –13.3
1.0 27.4 –12.9
10 26.4 –11.9
20 25.5 –11.2
30 24.6 –10.5
50 22.6 –9.4
Figure 22. Controlled MOSFET Drive Figure 23. Bipolar T ransistor Drive
Figure 24. Dual Charge Pump Converter
The totem–pole outputs can furnish negative base current for enhanced
transistor turn–off, with the addition of capacitor C1.
The capacitor’s equivalent series resistance limits the Drive Output Current
to 1.5 A. An additional series resistor may be required when using tantalum
or other low ESR capacitors.
In noise sensitive applications, both conducted and radiated EMI can
be reduced significantly by controlling the MOSFET’s turn–on and
turn–of f times.
+
100k
Vin
Rg(on)
Rg(off)
+
IB
+
0
–Base Charge
Removal
100k
C1
Vin
+
–
VCC = 15 V
4.7 0.1
6
5.7V
6.8 10
7
1N5819
2+ VO
≈
2.0 VCC
47
100k
100k
5
6.8 10 1N5819
4– VO
≈
– VCC
330pF
47
3
10k
+
+
+
+
+
+
+
+
+
+
+
MC34151 MC33151
9
MOTOROLA ANALOG IC DEVICE DATA
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE N
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 –A–
–B–
–T–
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M––– 10 ––– 10
N0.76 1.01 0.030 0.040
__
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
SEATING
PLANE
14
58
C
K
4X P
A0.25 (0.010) MTBSS
0.25 (0.010) MBM
8X D
R
MJ
X 45
_
_
F
–A–
–B–
–T–
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.80 5.00 0.189 0.196
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.18 0.25 0.007 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
G
MC34151 MC33151
10 MOTOROLA ANALOG IC DEVICE DATA
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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MC34151/D
*MC34151/D*
◊
