LTC3870EUF-1#PBF - LINEAR TECHNOLOGY

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

Typical applicaTion

FeaTures DescripTion

PolyPhase Step-Down

Slave Controller for Digital

Power System Management

The LT C

3870-1 is a PolyPhase

step-down slave control-

ler specially designed for multiphase operation with LTC's

digital power system management DC/DC controllers. It

provides a small and cost effective solution for supply-

ing very large currents by cascading it with a LTC3887-1

controller. A peak current mode architecture provides the

LTC3870-1 with excellent current sharing from phase to

phase and from chip to chip.

Coherently working with the LTC3887-1, the LTC3870-1

does not require additional I2C addresses, and it supports

all programmable features as well as fault protection.

The constant switching frequency can be synchronized

to an external clock from the LTC3887-1 over a range of

100kHz to 1MHz.

Load Transient Response of a

2-Phase Master (3887-1)/Slave

(3870-1) Converter

applicaTions

n LTC3887-1 Phase Extender

n Operates with Power Blocks, DrMOS or External

Gate Drivers and MOSFETs

n Cascade with Multiple Chips for Very Large Current

Applications

n Accurate PolyPhase Current Sharing

n EXTVCC Capable of 5V to 14V Input

n Wide VIN Range: 4.5V to 60V

n Wide Output Voltage Range : 0.5V to 14V

n Wide SYNC Frequency Range: 100kHz to 1MHz

n Pin Programmable CCM/DCM Operation

n Pin Programmable Phase-Shift Control

n Available in a 24-Pin (4mm × 4mm) QFN Package

n High Power Distributed Power Systems

n Telecom Systems

n Industrial Applications

L, LT , LT C , LT M , PolyPhase, Linear Technology and the Linear logo are registered trademarks

of Linear Technology Corporation. All other trademarks are the property of their respective

owners. Protected by U.S. Patents including 5481178, 5705919, 5929620, 6144194, 6177787,

6580258, 5408150

1.0µH

2.15k

0.2µF

0.56µH

1.74k

4.7µF

530µF

82.5k

DrMOS

RUN0

RUN1

FAULT0

FAULT1

TH0

SYNC

TH1

FREQ

PHASMD

MODE1

MODE0

GND

LTC3870-1

LIM

SENSE1

SENSE0

SENSE1

CC1

CC0

PWM0

PWM1

INTV

EXTV

VOUT0

3.3V, 30A

VIN

7V TO 14V

RUN0

RUN1

GPIO0

GPIO1

TH0

SYNC

TH1

LTC3887-1

SENSE0

SENSE1

VOUT1

1.8V, 40A

3.3V

1.8V

* REFER TO LTC3887-1 DATA SHEET

FOR MASTER SETUP

38701 TA01a

0.2µF

22µF

= 12V

OUT

= 1.8V

100µs/DIV

LOAD

20A/DIV

10A TO 20A TO 10A

LTC3887–1

(CH0)

10A/DIV

LTC3870–1

(CH0)

10A/DIV

OUT

200mV/DIV

AC–COUPLED

38701 TA01b

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

pin conFiguraTionabsoluTe MaxiMuM raTings

VIN ............................................................. –0.3V to 65V

VCC0, VCC1 .................................................... –0.3V to 6V

ISENSE0+, ISENSE0−, ISENSE1+, ISENSE1− ....... –0.3V to 15V

INTVCC, RUN0/RUN1 .................................. –0.3V to 6V

EXTVCC .................................................... –0.3V to 14V

MODE0/MODE1,

FREQ, PHASMD, ILIM ........................ –0.3V to INTVCC

FA U LT0 /FA U LT1 , ITH0/ITH1, SYNC .............. –0.3V to 3.6V

INTVCC, EXTVCC Peak Current (Note 7) ...............100mA

Operating Junction

Temperature Range ............................ –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

24 23 22 21 20 19

7 8 9

TOP VIEW

UF PACKAGE

24-LEAD (4mm × 4mm) PLASTIC QFN

GND

10 11 12

ISENSE0+

ISENSE0–

RUN0

RUN1

ISENSE1–

ISENSE1+

VCC0

VIN

GND

EXTVCC

INTVCC

VCC1

MODE0

ITH0

FREQ

FAULT0

FAULT1

PWM0

MODE1

ITH1

ILIM

SYNC

PHASMD

PWM1

TJMAX = 125°C, θJA = 46.9°C/W, θJC_BOT = 4.5°C/W

EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

elecTrical characTerisTics

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 15V, VRUN0,VRUN1 = 3.3V, fSYNC = 350kHz

(externally driven) unless otherwise specified.

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3870EUF-1#PBF LTC3870EUF-1#TRPBF 38701 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C

LTC3870IUF-1#PBF LTC3870IUF-1#TRPBF 38701 24-Lead (4mm × 4mm) Plastic QFN –40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN Input Voltage Range (Note 3) 4.5 60 V

VOUT Output Voltage Range (Note 4) 0.5 14 V

IQInput Voltage Supply Current

Normal Operation

VRUN0, VRUN1=0V

VRUN0, VRUN1=3.3V

1.1

2.6

VUVLO Undervoltage Lockout Threshold

when VIN > 4.2V

VINTVCC Falling

VINTVCC Rising

3.7

4.0

CONTROL LOOP

IISENSE0+,

IISENSE1+

Current Sense + Pin Current VISENSE0,1+=3.3V l±0.1 ±1 µA

IISENSE0–,

IISENSE1–

Current Sense – Pin Current VISENSE0,1–=3.3V l±0.1 ±1 µA

(Note 1)

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

The l denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at TA = 25°C. (Note 2) VIN = 15V, VRUN0,VRUN1 = 3.3V, fSYNC = 350kHz

(externally driven) unless otherwise specified.

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIILIMIT Maximum Current Sense Threshold (High Range) VITH=2.22V, ILIM=INTVCC l70 75 80 mV

Maximum Current Sense Threshold (Low Range) VITH=2.22V, ILIM=GND l45 50 55 mV

PWM Outputs

PWM PWM Output High Voltage

PWM Output Low Voltage

PWM Output Current in Hi-Z State

ILOAD=500µA

ILOAD=–500µA

VCC – 0.2

–5

0.2

µA

tON(MIN) Minimum On-Time (Note 5) 90 ns

INTVCC Regulator

VINTVCC_VIN Internal VCC Voltage No Load 6.0V<VIN<60V, VEXTVCC=0V 4.85 5.1 5.35 V

VLDO INT INTVCC Load Regulation ICC=0mA to 50mA, VEXTVCC=0V 0.8 ±2 %

VINTVCC_EXT Internal VCC Voltage No Load VEXTVCC=8.5V (Note 6) 4.85 5.1 5.35 V

VLDO EXT EXTVCC Load Regulation ICC=0mA to 20mA, VEXTVCC=8.5V 0.5 ±2 %

VEXTVCC EXTVCC Switchover Voltage VEXTVCC Ramping Positive (Note 6) 4.65 4.8 4.95 V

VHYS_EXTVCC EXTVCC Hysteresis 200 mV

Oscillator and Phase-Locked Loop

fSYNC Oscillator SYNC Range l100 1000 kHz

VTH,SYNC SYNC Input Threshold VTH,SYNC Falling (Note 7)

VTH,SYNC Rising

0.4

2.0

fNOM Nominal Frequency VFREQ=1.0V 500 kHz

IFREQ FREQ Setting Current 9 10 11 µA

θSYNC-θ0SYNC to Ch0 Phase Relationship Based on the

Falling Edge of SYNC and Rising Edge of PWM0

PHASMD =0

PHASMD=1/3 INTVCC

PHASMD=2/3 INTVCC

PHASMD=INTVCC

180

120

Deg

θSYNC-θ1SYNC to Ch1 Phase Relationship Based on the

Falling Edge of SYNC and Rising Edge of PWM1

PHASMD=0

PHASMD=1/3 INTVCC

PHASMD=2/3 INTVCC

PHASMD=INTVCC

300

240

270

Deg

Digital Inputs RUN0/RUN1, MODE0/MODE1, FAULT0/FAULT1

VIH Input High Threshold Voltage l2.0 V

VIL Input Low Threshold Voltage l1.4 V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3870-1 is tested under pulsed load conditions such that

TJ ≈ TA. The LTC3870E-1 is guaranteed to meet specifications from

0°C to 85°C junction temperature. Specifications over the –40°C to

125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3870I-1 is guaranteed over the full –40°C to 125°C operating

junction temperature range. Note that the maximum ambient temperature

consistent with these specifications is determined by specific operating

conditions in conjunction with board layout, the related package thermal

impedance and other environmental factors. The junction temperature TJ

is calculated from the ambient temperature TA and power dissipation PD

according to the following formula:

TJ = TA + (PD • 46.9°C/W)

Note 3: When VIN >15V, EXTVCC is recommended to reduce IC Temperature.

Note 4: Output voltage is set and controlled by the master controller in

multiphase operations.

Note 5: The minimum on-time condition corresponds to an inductor

peak-to-peak ripple current ≥40% of IMAX (see Minimum On-Time

Considerations in the Applications Information section).

Note 6: EXTVCC is enabled only if VIN is higher than 6.5V.

Note 7: Guaranteed by design.

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

Typical perForMance characTerisTics

Load Step (Discontinuous Conduction

Mode) 4-Phase Operation

LTC3887-1 and LTC3870-1

Load Step (Forced Continuous

Mode) 4-Phase Operation

LTC3887-1 and LTC3870-1 Inductor Current at Light Load

Efficiency vs Load Current Efficiency vs Load Current

Full Load (ILOAD = 20A/Phase)

Efficiency and Power Loss vs

Input Voltage

= 12V

OUT

= 1.8V

L = 0.56µH

DCR = 1.61mΩ

= 350kHz

CCM

DCM

LOAD CURRENT (A)

0.1

100

EFFICIENCY (%)

3874 G01

= 12V

OUT

= 3.3V

= 350kHz

L = 1µH

DCR = 2.4mΩ

CCM

DCM

LOAD CURRENT (A)

0.1

100

EFFICIENCY (%)

38701 G02

OUT

= 1.8V

L = 0.56µH

DCR = 1.61mΩ

EFFICIENCY

POWER LOSS

INPUT VOLTAGE (V)

91.0

91.5

92.0

92.5

93.0

93.5

2.5

2.6

2.7

2.8

2.9

3.0

EFFICIENCY (%)

POWER LOSS (W)

38701 G03

= 12V

OUT

= 1.0V

50µs/DIV

LOAD

50A/DIV

0A TO 20A TO 0A

OUT

50mV/DIV

AC–COUPLED

INDUCTOR CURRENT

LTC3887–1 (CH0)

10A/DIV

INDUCTOR CURRENT

LTC3870–1 (CH0)

10A/DIV

38701 G04

= 12V

OUT

= 1.0V

50µs/DIV

LOAD

50A/DIV

0A TO 20A TO 0A

OUT

50mV/DIV

AC–COUPLED

INDUCTOR CURRENT

LTC3887–1 (CH0)

10A/DIV

INDUCTOR CURRENT

LTC3870–1 (CH0)

10A/DIV

38701 G05

1µs/DIV

LTC3870–1 (CH1)

FORCED

CONTINUOUS

MODE

5A/DIV

LTC3870–1 (CH1)

DISCONTINUOUS

MODE

5A/DIV

38701 G06

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

Typical perForMance characTerisTics

Start-Up into a Pre-Biased Load

2-Phase Operation LTC3887-1

and LTC3870-1

Current Sense Threshold

vs ITH Voltage

INTVCC Line Regulation

DC Output Current Matching in

a 4-Phase Operation

LTC3887-1 and LTC3870-1

Dynamic Current Sharing During a

Load Transient in a 4-Phase System

LTC3887-1 and LTC3870-1

Quiescent Current vs Input

Voltage without EXTVCC

2ms/DIV

RUN

ALL RUN PINS

TIED TOGETHER

2V/DIV

VOUT

LTC3870–1

IN DCM

500mV/DIV

38701 G07

VIN = 12V

VOUT = 1.8V

INPUT VOLTAGE (V)

1.0

2.0

3.0

4.0

5.0

6.0

INTV

VOLTAGE (V)

38701 G09

LTC3887–1 CH0

LTC3887–1 CH1

LTC3870–1 CH0

LTC3870–1 CH1

TOTAL OUTPUT CURRENT (A)

100

CHANNEL CURRENT (A)

38701 G10

50µs/DIV

LTC3887–1 CH0

10A/DIV

LTC3887–1 CH1

10A/DIV

LTC3870–1 CH0

10A/DIV

LTC3870–1 CH1

10A/DIV

38701 G11

VIN = 12V

VOUT = 1.0V

ILOAD = 0A TO 32A TO 0A

INPUT VOLTAGE (V)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SUPPLY CURRENT (mA)

38701 G12

VITH (V)

–40

VISENSE (mV)

–20

0.5 1 1.5 2 2.5

38701 G08

RANGE LOW

RANGE HIGH

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

ISENSE0+/ISENSE1+ (Pin 1/Pin 6): Current Sense Comparator

positive inputs, normally connected to the positive node

of the DCR sensing networks or current sensing resistors.

ISENSE0−/ISENSE1− (Pin 2/Pin 5): Current Sense Comparator

negative inputs, normally connected to the negative node

of the DCR sensing network or current sensing resistors.

RUN0/RUN1 (Pin 3/Pin 4): Enable Run Input Pins. A logic

high on these pins enables the corresponding channel.

In multiphase operation, these pins are connected to

LTC3887-1's RUN pins.

MODE0/MODE1 (Pin 24/Pin 7): DCM/CCM Mode Control

Pins. Channel0/Channel1 operate in forced continuous

mode if MODE0/MODE1 pin is logic high. There is a 500kΩ

pull-down resistor on MODE0/MODE1 internally. The

default operation mode in each channel is discontinuous

mode operation unless these pins are actively driven high.

ITH0/ITH1 (Pin 23/Pin 8): Current Control Threshold.

Each associated channel’s current comparator tripping

threshold increases with its ITH voltage. In multiphase

operation, these pins are connected to the master con-

troller's ITH pins for current sharing.

ILIM (Pin 9): Programs Current Comparators' Sense

Voltage Range. This pin can be tied to GND or INTVCC

to select the maximum current sense threshold for each

current comparator. GND sets both channels' current low

range with maximum 50mV sensing voltage. INTVCC sets

both channels' current high range with maximum 75mV

sensing voltage. For equal current sharing, the setup on

the ILIM pin has to be same as the setup on the bit 7 of

MFR_PWM_MODE_3887-1 register in the master control-

ler. See Table 2 in the Operation Section for details.

SYNC (Pin 10): External Clock Synchronization Input. If an

external clock is present at this pin, the switching frequency

will be synchronized to the falling edge of the external

clock. In multiphase operation, this pin is connected to

LTC3887-1 SYNC pin for frequency synchronization. Do

not float the SYNC Pin.

PHASMD (Pin 11): Phase Set Pin. This pin can be tied to

GND, INTVCC or a resistor divider from INTVCC to GND. This

pin determines the relative phases between the external

clock on the SYNC pin and the internal controllers. See

Table 1 in the Operation Section for details.

PWM0/PWM1 (Pin 19/Pin 12): (Top) Gate Signal Outputs.

This signal goes to the PWM or top gate input of the external

driver, integrated driver MOSFET or Power Block. This is

a three-state compatible output. To support three-state

mode, an external resistive divider is typically used from

VCC0/VCC1 to ground.

VCC0/VCC1 (Pin 18/Pin 13): PWM Pin Driver Supplies.

Decouple these pins to GND with a capacitor (0.1µF) or tie

these pins to the INTVCC pin. PWM0/PWM1 signal swing

is from ground to VCC0/VCC1.

INTVCC (Pin 14): Internal Regulator 5V Output. The internal

control circuits are powered from this voltage. Bypass this

pin to GND with a minimum of 4.7µF low ESR tantalum

or ceramic capacitor. INTVCC is enabled as soon as VIN

is powered. The INTVCC pin is not short circuit proof. If

overloaded, this will disrupt internal operation that can

damage the part.

EXTVCC (Pin 15): External power input to an internal LDO

connected to INTVCC. This LDO supplies INTVCC power

bypassing the internal LDO powered from VIN whenever

EXTVCC is higher than 4.8V. See EXTVCC connection in the

Applications Information Section. Do not exceed 14V on

this pin. Bypass this pin to GND with a minimum of 4.7µF

low ESR tantalum or ceramic capacitor. If the EXTVCC pin

is not used, leave it open or tie it to ground. EXTVCC can

be present before VIN. However, EXTVCC is enabled only

if VIN is higher than 6.5V.

GND (Pin 16/Exposed Pad Pin 25): Signal ground. All

small-signal and compensation components should con-

nect to this ground. The exposed pad must be soldered

pin FuncTions

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

pin FuncTions

to the PCB ground for electrical connection and rated

thermal performance.

VIN (Pin 17): Main Input Supply. Bypass this pin to GND

with a capacitor (0.1µF to 1µF).

FAULT0 /FAULT1 (Pin 21/Pin 20): Fault Input Pins. Connect

these pins to the master chip GPIO pins to respond to

fault signals from the master controller. If this pin is low,

the PWM pin is in three-state. There is a 500kΩ pull-down

resistor on FAULT0/FAULT1 internally. These pins have to

be driven high externally for normal operation.

FREQ (Pin 22): Frequency Set Pin. There is a precision

10µA current flowing out of this pin. A resistor to ground

sets a voltage which in turn programs the frequency. This

pin sets the default switching frequency when there is no

external clock on the SYNC pin. Setting the frequency close

to the external clock helps the internal PLL sync to the

SYNC pin clock quickly and smoothly. See the Application

Section for the detailed information.

block DiagraM

10 11 15

24 3 2123

10µA

SYNC PHASMD EXTVCC

INTVCC

IREV

ICMP

INTVCC

ITH0

ILIM

ISENSE0+

ISENSE0–

VCC0

REV

UVLO

FCNT

RUN

FAULT

GND

1.7V

RUN0MODE0 FAULT0

PWM0

VIN VIN

VOUT0

COUT0

CIN

4.8V

FREQ

27 17

SYNC

DET PHASE

PROGRAM

OSC

PFD

VCO

UVLO

SLOPE

COMPENSATION

ILIM RANGE SELECT

HI: 1:1

LO: 1:1.5

SWITCH

LOGIC

R Q

5.0V

REF

LDOLDO

–

+–

38701 BD

71.1k

500k 500k

DrMOS

(CH0 Shown)

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

operaTion

Main Control Loop

The LTC3870-1 is a constant frequency, current mode

step-down slave controller for parallel operation with the

LTC3887-1. During normal operation, each top MOSFET

is turned on when the clock for that channel sets the RS

latch, and turned off when the main current comparator,

ICMP, resets the RS latch. The peak inductor current at

which ICMP resets the RS latch is controlled by the voltage

on the ITH pin, which is tied directly to the corresponding

ITH pin of the master controllers (LTC3887-1). When the

load current increases, LTC3887-1 master controllers

drive and increase the ITH voltage, which in turn causes

the peak current in the corresponding slave channels to

increase, until the average inductor current matches the

new load current. After the top MOSFET has been turned

off, the bottom MOSFET is turned on until the beginning

of the next cycle in Continuous Conduction Mode (CCM)

or until the inductor current starts to reverse, as indicated

by the reverse current comparator IREV, in Discontinuous

Conduction Mode (DCM). LTC3870-1 slave controllers DO

NOT regulate the output voltage but regulate the current in

each channel for current sharing with master controllers.

Output voltage regulation is achieved through the voltage

feedback loops in the master controller.

INTVCC/EXTVCC Power

Power for most internal circuitry is derived from the INTVCC

pin. Normally an internal 5.0V linear regulator supplies

INTVCC power from VIN. In high VIN applications, if a high

efficiency external voltage source is available for the EXTVCC

pin, another internal 5.0V linear regulator is enabled and

supplies INTVCC power from EXTVCC. To enable the linear

regulator driven by the EXTVCC pin, VIN needs to be higher

than 6.5V and EXTVCC pin voltage has to be higher than

4.8V. Do not exceed 14V on the EXTVCC pin.

Start-Up and Shutdown (RUN0, RUN1)

The two channels of the LTC3870-1 can independently start

up and shut down using the RUN0 and RUN1 pins. Pulling

either of these pins below 1.4V shuts down the control

circuits for that channel. During shutdown, the PWM pin is

in three-state mode. Pulling either of these pins above 2V

enables the corresponding channel and internal circuits.

During startup, the RUN0/RUN1 pins are actively pulled

down until the INTVCC voltage passes the undervoltage

lockout threshold of 4V. For multiphase parallel operation,

the RUN0/RUN1 pins have to be connected and driven by

the RUN pins of the master controller. Do not exceed the

Absolute Maximum Rating of 6V on these pins.

The start-up of each channel’s output voltage VOUT is

controlled and programmed by the master controller.

After the RUN pins are released, the master controller

drives the output based on the programmed delay time

and rise time, and the slave controller LTC3870-1 just

follows the master to supply equivalent current to the

output during start-up.

Light Load Current Operation (Discontinuous

Conduction Mode, Continuous Conduction Mode)

The LTC3870-1 can be set to operate either in Discontinu-

ous Conduction Mode (DCM) or forced Continuous Con-

duction Mode (CCM). To select forced Continuous Mode

of operation, tie the MODE pin to a DC voltage above 2V

(e.g., INTVCC). To select Discontinuous Conduction Mode

of operation, tie the MODE pin to a DC voltage below 1.4V

(e.g., SGND). In forced continuous operation, the induc-

tor current is allowed to reverse at light loads or under

large transient conditions. The peak inductor current is

determined by the voltage on the ITH pin. In this mode,

the efficiency at light loads is lower than in discontinu-

ous mode operation. However, continuous mode has the

advantages of lower output ripple and less interference

with audio circuitry. When the MODE pin is connected to

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

GND, the LTC3870-1 operates in discontinuous mode at

light loads. At very light loads, the current comparator

ICMP may remain tripped for several cycles and force the

external top MOSFET to stay off for the same number of

cycles (i.e., skipping pulses). This mode provides higher

light load efficiency than forced continuous mode and

the inductor current is not allowed to reverse. There are

500kΩ pull-down resistors internally connected to the

MODE0/MODE1 pins. If MODE0/MODE1 pins are floating,

both channels default to Discontinuous Conduction Mode.

Multichip Operation (PHASMD and SYNC Pins)

The PHASMD pin determines the relative phases between

the internal channels as well as the external clock signal on

the SYNC pin, as shown in Table 1. The phases tabulated

are relative to zero degree phase being defined as the

falling edge of the clock on SYNC.

Table 1.

PHASMD Channel 0 Phase Channel 1 Phase

GND 180° 0°

1/3 INTVCC 60° 300°

2/3 INTVCC or Float 120° 240°

INTVCC 90° 270°

The SYNC pin is used to synchronize switching frequency

between master and slave controllers. Input capacitance

ESR requirements and efficiency losses are substantially

reduced because the peak current drawn from the input

capacitor is effectively divided by the number of phases

used and power loss is proportional to the RMS current

squared. A two-phase, single output voltage implementa-

tion can reduce input path power loss by 75% and radi-

cally reduce the required RMS current rating of the input

capacitor(s).

operaTion

Single Output Multiphase Operation

The LTC3870-1 is designed for multiphase converters with

the LTC3887-1 by making these connections:

• Tie all the ITH pins of paralleled channels together for

current sharing between masters and slaves. Note that

ILIM setup on slaves has to match MFR_PWM_MODE

current range setup in masters.

• Tie all SYNC pins together between master and slaves

for same switching frequency synchronization; one

and only one of the LTC3887-1 controllers has to be

programmed as master to generate clock signal on

the SYNC pin.

• Tie all the RUN pins of paralleled channels together

between master and slaves for startup and shutdown

sequences.

• Tie the GPIO pin of the master controller to the FAULT

pin of slave controller and program the master GPIO

as fault sharing for fault protection.

Examples of single output multiphase converters are

shown in Figure 1.

Inductor Current Sensing

Like the LTC3887-1, the LTC3870-1 can use either induc-

tor DCR or RSENSE to sense the inductor current. Inductor

DCR current sensing provides a lossless method of sens-

ing the instantaneous current. Therefore, it can provide

higher efficiency for applications with high output currents.

However, the DCR of a copper inductor typically has 10%

tolerance. For precise current sensing, a precision sensing

resistor RSENSE can be used to sense the inductor current.

It is important to match the current sensing circuit between

master controllers and slave controllers to guarantee bal-

anced load sharing and overcurrent protection.

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

operaTion

LTC3887-1

0° 180°

LTC3887-1

0° 180°

LTC3870-1

180° 0°

LTC3870-1

120° 240°

PHASMD = GND

2 + 2 OPERATION 1 + 3 OPERATION

6 PHASE OPERATION4 PHASE OPERATION

PHASMD = 2/3 INTVCC OR FLOAT

CH0 CH1

CH0 CH1 CH0 CH1

CH0 CH1

LTC3887-1

0° 180°

LTC3870-1

90° 270°

PHASMD = INTVCC

CH0 CH1 CH0 CH1

LTC3870-1

60° 300°

LTC3887-1

0° 180°

PHASMD = 1/3 INTVCC PHASMD = 2/3 INTVCC

CH0 CH1 CH0 CH1

LTC3870-1

120° 240°

CH0 CH1

38701 F01

Frequency Selection and Phase-Locked Loop (FREQ

and SYNC Pins)

The selection of switching frequency is a trade-off between

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage. The switching fre-

quency of the LTC3870-1 controllers can be synchronized

to the falling edge of the external clock on the SYNC pin

or selected using the FREQ pin. A phase-locked loop

(PLL) is integrated in the LTC3870-1 to synchronize the

internal oscillator to an external clock source that is con-

nected to the SYNC pin; this source is normally provided

by the master controllers. The PLL loop filter network is

Figure 1. Examples of Single/Dual Output Multiphase Converters

integrated inside the LTC3870-1. The phase-locked loop

is capable of locking to any frequency within the range of

100kHz to 1MHz.

If the SYNC pin is not being driven by an external clock

source, the FREQ pin can be used to program the

LTC3870-1’s operating frequency from 100kHz to 1MHz.

There is a precision 10µA current flowing out of the FREQ

pin, so the user can program the controller’s switching

frequency with a single resistor to SGND. A curve is pro-

vided later in the application section showing the relation-

ship between the voltage on the FREQ pin and switching

frequency. The frequency setting resistor should always be

present to set the controller’s initial switching frequency

before locking to the external clock.

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

The Typical Application on the first page of this data sheet

is a basic LTC3870-1 application circuit featuring the

LTC3887-1 as a slave controller. In paralleled operation,

the current sensing scheme as well as the power stage

parameters in LTC3870-1 must be the same as the master

controller to achieve balanced current sharing between

masters and slaves. Finally, input and output capacitors

are selected based on RMS current rating, ripple, and

transient specs.

Current Limit Programming

To match the master controller current limit, each channel

of the LTC3870-1 can be programmed separately with two

current ranges. The ILIM pin of LTC3870-1 is a 4-level logic

input which sets the current limit of LTC3870-1. When ILIM

is grounded, both channel0 and channel1 are set to be low

current range. When ILIM is tied to INTVCC, both channel0

and channel1 are set to be high current range. Here, low

current range means the current sense threshold linearly

increases from 0mV to 50mV as ITH voltage is increased

from 0.5V to 2.22V without slope compensation. High cur-

rent range means the current sense threshold increases to

75mV as ITH voltage is increased to 2.22V without slope

compensation. Set ILIM to one-third INTVCC for channel0

high current range and channel1 low current range. Set

ILIM to two-thirds INTVCC or float for channel0 low current

range and channel1 high current range. The summary of

ILIM pin setups is shown in Table 2. For balanced load

current sharing, use the same current range setting as in

the master controller. Note that the LTC3870-1 does not

have active clamping circuit on the ITH pin for peak current

limit and over current protection. Over current protection

relies on the master controller to drive and clamp the ITH

pin voltage not to exceed the programmed voltage through

the PMBus command.

Table 2. Current Limit Programming

ILIM

Channel 0

Current limit

Channel 1

Current limit

GND Range Low Range Low

1/3 INTVCC Range High Range Low

2/3 INTVCC or Float Range Low Range High

INTVCC Range High Range High

applicaTions inForMaTion

INTVCC Regulators and EXTVCC

The LTC3870-1 includes a PMOS LDO that supplies power

to INTVCC from the VIN supply. INTVCC powers most of the

LTC3870-1’s internal circuitry. The linear regulator regulates

the voltage at the INTVCC pin to 5.0V when VIN is greater

than 6V. EXTVCC connects to INTVCC through another PMOS

LDO and can supply the needed power when its voltage

is higher than 4.8V and VIN is higher than 6.5V. Each of

these LDOs can supply a peak current of 100mA and must

be bypassed to ground with a minimum of 4.7µF ceramic

capacitor or low ESR electrolytic capacitor. No matter what

type of bulk capacitor is used, an additional 0.1µF ceramic

capacitor placed directly adjacent to the INTVCC and PGND

pins is highly recommended. Good bypassing is needed

to prevent interaction between the channels.

The INTVCC pin is not short-circuit proof. If overloaded, this

will disrupt internal operation that can damage the part.

When the voltage applied to EXTVCC rises above 4.8V and

VIN above 6.5V, the INTVCC linear regulator is turned off

and the EXTVCC linear regulator is turned on. Using the

EXTVCC allows the control power to be derived from other

high efficiency sources such as +5V or +12V rails in the

system. Do not apply more than 14V to the EXTVCC pin.

For applications where the main input power is 5V, tie the

VIN and INTVCC pins together and tie the combined pins

to the 5V input with a 1Ω or 2.2Ω resistor as shown in

Figure 2 to minimize the voltage drop. This will override

the INTVCC linear regulator and will prevent INTVCC from

dropping too low due to the dropout voltage. Make sure

the INTVCC voltage is at or exceeds the RDS(ON) test voltage

for the external power MOSFETs which is typically 4.5V

for logic-level devices.

38701 F04

VIN

CIN

CINTVCC

4.7µF

RVIN

1Ω

INTVCC

LTC3870-1

GND

Figure 2. Setup for a 5V Input

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

applicaTions inForMaTion

within the range of the LTC3870-1’s internal VCO. This is

guaranteed to be between 100kHz and 1MHz. A simplified

block diagram is shown in Figure 4.

If the external clock frequency is greater than the inter-

nal oscillator’s frequency, fOSC, then current is sourced

continuously from the phase detector output, pulling up

the filter network. When the external clock frequency is

less than fOSC, current is sunk continuously, pulling down

the filter network. If the external and internal frequencies

are the same but exhibit a phase difference, the current

sources turn on for an amount of time corresponding to

Undervoltage Lockout

The LTC3870-1 has a precision UVLO comparator con-

stantly monitoring the INTVCC voltage. It locks out the

switching action and pulls down the RUN pins when

INTVCC is below 3.7V. To prevent oscillation when there

is a disturbance on the INTVCC, the UVLO comparator has

300mV of precision hysteresis. In multiphase operation,

when LTC3870-1 is in undervoltage lockout, the RUN0

and RUN1 pins are pulled down to disable the master’s

switching action.

Phase-Locked Loop and Frequency Synchronization

The LTC3870-1 has a phase-locked loop (PLL) comprised

of an internal voltage-controlled oscillator (VCO) and a

phase detector. This allows the internal clock to be locked

to the falling edge of an external clock signal applied to

the SYNC pin. The turn-on of channel 0/channel 1’s top

MOSFET is synchronized or out-of-phase with the falling

edge of the external clock. The phase detector is an edge

sensitive digital type that provides zero degree phase shift

between the external and internal oscillators. This type of

phase detector does not exhibit false lock to harmonics

of the external clock.

The output of the phase detector is a pair of complementary

current sources that charge or discharge the internal filter

network. There is a precision 10µA of current flowing out of

the FREQ pin. This allows the user to use a single resistor

to GND to set the switching frequency when no external

clock is applied to the SYNC pin. The voltage on the FREQ

pin is equal to the resistance multiplied by 10µA current

(e.g. the voltage is 1V with a 100k resistor from the FREQ

pin to SGND). The internal switch between FREQ pin and

the integrated PLL filter network is ON, allowing the filter

network to be pre-charged to the same voltage potential

as the FREQ pin. The relationship between the voltage

on the FREQ pin and the operating frequency is shown

in Figure 3 and specified in the Electrical Characteristics

table. If an external clock is detected on the SYNC pin, the

internal switch mentioned above will turn off and isolate the

influence of FREQ pin. Note that the LTC3870-1 can only

be synchronized to an external clock whose frequency is

Figure 3. Relationship Between Oscillator

Frequency and Voltage at the FREQ Pin

Figure 4. Phase-Locked Loop Block Diagram

FREQ PIN VOLTAGE (V)

SWITCHING FREQUENCY (kHz)

0.5 1 1.5 2

38701 F02

2.5

400

600

800

1400

1200

200

1000

DIGITAL

PHASE/

FREQUENCY

DETECTOR

SYNC

VCO

2.4V 5V

10µA

RSET

38701 F03

FREQ

EXTERNAL

OSCILLATOR

SYNC

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

applicaTions inForMaTion

the phase difference. The voltage on the filter network is

adjusted until the phase and frequency of the internal and

external oscillators are identical. At the stable operating

point, the phase detector output is high impedance and

the filter capacitor holds the voltage.

Typically, the external clock (on the SYNC pin) input high

threshold is 2V, while the input low threshold is 0.4V.

Fault Protection and Responses

LTC3887-1 master controllers monitor system voltage,

current, and temperature and provide many protection

features during fault conditions. LTC3870-1 slave con-

trollers do not provide as many fault monitors as master

controllers and have to respond to fault signals from the

master controller. FAULT0 and FAULT1 pins are designed

to share fault signals between masters and slaves. In a

typical parallel application, connect the FAULT pins on

LTC3870-1 to the master GPIO pins of the correspond-

ing paralleled channels and program the master GPIO as

fault sharing, so that the slave controller can respond to

all fault protections from the master. When the FAULT pin

is pulled below 1.4V, the PWM pin in the corresponding

channel is in three-state. When the FAULT pin voltage is

above 2V, the corresponding channel returns to normal

operation. During fault conditions, all internal circuits in

LTC3870-1 are still running so the slave controllers can

immediately go back to normal operation when the FAULT

pin is released.

LTC3870-1 has internal thermal shutdown protection

which forces the PWM pin three-state when the junction

temperature is higher than 160°C. In thermal shutdown,

FAULT0 and FAULT1 pins are also pulled low. There is a

500kΩ pull-down resistor on each FAULT pin which sets

the default voltage on FAULT pins low if FAULT pins are

left floating.

Transient Response and Loop Stability

In a typical parallel operation, LTC3870-1 cooperates with

master controllers to supply more current. To achieve

balanced current sharing between master and slave, it is

recommended that each slave channel copy the design

from the master channel. Select same inductors, same

MOSFET driver, same current sensing circuit and same

output capacitors between the master channel and slave

channels. Control loop and compensation design on the

ITH pin should start with the single phase operation of the

master controller. If the master and slave channels are

exactly the same, then the transient response and loop

stability of the multiphase design is almost the same as

the single phase operation of the master by tying the ITH

pins together between the master and slaves. For example,

design the compensation for a single phase 1.8V/20A output

using LTC3887-1 with a 0.56µH inductor and 530µF output

capacitors. To extend the output to 1.8V/40A, simply paral-

lel one channel of LTC3870-1 with the same inductor and

output capacitors (total output capacitors are 1060µF) and

tie the ITH pin of LTC3870-1 to the master ITH. The loop

stability and transient responses of the two phase converter

are very similar to the single phase design without any extra

compensator on the ITH pin of LTC3870-1 slave controller.

Furthermore, LTpowerCAD is provided on the LTC website

as a free download for transient and stability analysis.

To minimize the high frequency noise on the ITH trace

between master and slave ITH pins, a small filter capacitor

in the range of tens of pF can be placed closely at each ITH

pin of the slave controller. This small capacitor normally

does not significantly affect the closed loop bandwidth but

increases the gain margin at high frequency.

Mode Selection and Pre-Biased Startup

There may be situations that require the power supply to

start up with a pre-bias on the output capacitors. In this

case, it is desirable to start up without discharging the

output capacitors. The LTC3870-1 can be configured to

DCM mode for pre-biased start-up. If a PGOOD signal is

available on the master controller, the PGOOD pin can be

connected to MODE pins of LTC3870-1 to ensure DCM

operation at startup and CCM operation at steady state.

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

Minimum On-Time Considerations

Minimum on-time tON(MIN) is the smallest time duration that

the LTC3870-1 is capable of turning on the top MOSFET.

It is determined by internal timing delays and the gate

charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

tON(MIN) < TSW VOUT/VIN

where TSW is the switching period.

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase. The

minimum on-time for the LTC3870-1 is approximately

90ns, with reasonably good PCB layout, minimum 30%

inductor current ripple and at least 10mV ripple on the

current sense signal. The minimum on-time can be af-

fected by PCB switching noise in the current loop. As

the peak sense voltage decreases, the minimum on-time

gradually increases to 130ns. This is of particular concern

in forced continuous applications with low ripple current

at light loads. If the duty cycle drops below the minimum

on-time limit in this situation, a significant amount of cycle

skipping can occur with correspondingly larger current

and voltage ripple.

PWM Pins

The PWM output pins are three-state compatible outputs,

designed to drive MOSFET drivers, DrMOSs, etc. which do

not represent a heavy capacitive load. An external resistor

divider may be used to set the voltage to mid-rail while in

the high impedance state.

The VCC pin is the corresponding PWM pin driver supply.

Decouple this pin to GND with a capacitor (0.1µF) or tie

this pin to the INTVCC pin.

MOSFET Driver Selection

Gate driver ICs, DrMOSs and power blocks with an interface

compatible with the LTC3870-1’s three-state PWM outputs

can be used.

applicaTions inForMaTion

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. Figure 5 illustrates the current waveforms pres-

ent in the various branches of the 2-phase synchronous

regulators operating in the continuous mode. Check the

following in the PC layout:

1. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return of

CINTVCC must return to the combined COUT (–) terminals.

The ITH traces should be as short as possible. The CIN

capacitor should have short leads and PC trace lengths.

The output capacitor (–) terminals should be connected

as close as possible to the (–) terminals of the input

capacitor by placing the capacitors next to each other.

2. Are the ISENSE+ and ISENSE– leads routed together with

minimum PC trace spacing? The filter capacitor between

ISENSE+ and ISENSE– should be as close as possible to

the IC. Ensure accurate current sensing with Kelvin

connections at the sense resistor or inductor, whichever

is used for current sensing.

3. Is the INTVCC bypassing capacitor connected close to

the IC, between the INTVCC and the ground pins? An

additional 1µF ceramic capacitor placed immediately

next to the INTVCC and PGND pins can help improve

noise performance substantially.

4. Keep the switching nodes (SW1, SW0), away from

sensitive small-signal nodes, especially from the op-

posite channel’s current sensing feedback pins. All of

these nodes have very large and fast moving signals

and therefore should be kept on the “output side” of

the LTC3870-1 and occupy minimum PC trace area.

If DCR sensing is used, place the right resistor (Block

Diagram, “RC”) close to the switching node.

5. Use a modified “star ground” technique: a low imped-

ance, large copper area central grounding point on

the same side of the PC board as the input and output

capacitors with tie-ins for the bottom of the INTVCC

bypassing capacitor, the bottom of the voltage feedback

resistive divider and the GND pin of the IC.

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

applicaTions inForMaTion

PC Board Layout Debugging

Start with one controller at a time. It is helpful to use a

DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switching node (SW pin) to synchronize the oscilloscope to

the internal oscillator and probe the actual output voltage

as well. Check for proper performance over the operating

voltage and current range expected in the application. The

frequency of operation should be maintained over the

input voltage range down to dropout and until the output

load drops below the low current operation threshold—

typically 10% of the maximum designed current level in

Burst Mode operation.

The duty cycle percentage should be maintained from cycle

to cycle in a well-designed, low noise PCB implementation.

Variation in the duty cycle at a sub-harmonic rate can sug-

gest noise pickup at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regulator

bandwidth optimization is not required. Only after each

controller is checked for its individual performance should

both controllers be turned on at the same time. A particularly

difficult region of operation is when one controller channel

is nearing its current comparator trip point when the other

channel is turning on its top MOSFET. This occurs around

50% duty cycle on either channel due to the phasing of

the internal clocks and may cause minor duty cycle jitter.

Reduce VIN from its nominal level to verify operation of

the regulator in dropout. Check the operation of the un-

dervoltage lockout circuit by further lowering VIN while

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher output

currents or only at higher input voltages. If problems coincide

with high input voltages and low output currents, look for

capacitive coupling between the BOOST, SW, TG, and pos-

sibly BG connections and the sensitive voltage and current

pins. The capacitor placed across the current sensing pins

needs to be placed immediately adjacent to the pins of the

IC. This capacitor helps to minimize the effects of differential

noise injection due to high frequency capacitive coupling. If

problems are encountered with high current output loading

at lower input voltages, look for inductive coupling between

CIN, Schottky and the top MOSFET components to the

sensitive current and voltage sensing traces. In addition,

investigate common ground path voltage pickup between

these components and the SGND pin of the IC.

Design Example

As a design example using master chip LTC3887-1 and

slave chip LTC3870-1 for a 4-phase high current regula-

tor, assume VIN = 12V (nominal), VIN = 14V (maximum),

VOUT = 1.0V, IMAX = 120A, and f = 425kHz (see Typical

Applications).

The master chip LTC3887-1 design can be found in the

LTC3887-1 data sheet Design Example section.

LTC3887-1's SYNC pin is connected to LTC3870-1's

SYNC pin and LTC3870-1's PHASMD is connected to

LTC3870-1’s GND.

Slave chip LTC3870-1 should use the same inductor,

DrMOS, CIN, and COUT as the master chip. DCR sensing

is also used for the slave chip.

LTC3870-1's ILIM pin is forced to 0V to match the master

chip's 50mV current limit. Both chips' VIN, VOUT, RUN,

ITH pins are connected together. LTC3887-1's GPIO pins

are connected to LTC3870-1's FAULT pins so the slave

controller will be disabled during fault conditions.

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

applicaTions inForMaTion

Figure 5. Branch Current Waveforms

RL1

SW1 VOUT1

COUT1

CIN

VIN

RIN

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

RL0

SW0 VOUT0

COUT0

38701 F05

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

Typical applicaTions

High Efficiency 350kHz 2-Phase 3.3V and 2-Phase 1.8V Step-Down Converters

10k

10Ω

LTC3887-1

LTC3870-1

FDMF6820A

38701 TA02

10nF

ISENSE0–

ISENSE0+

PWM0

VSENSE1

VSENSE0+

VSENSE0–

VDD25

VOUT0_CFG

VOUT1_CFG

ASEL1

ASEL0

FREQ_CFG

PHAS_CFG

TSNS0

TSNS1

SHARE_CLK

SCL

ALERT

SDA

VDD33

GPIO0

GPIO1

RUN0

RUN1

SYNC

ITH0

ITH1

1µF

10k

15.8k

16.2k

17.4k

16.2k

17.4k

30.1k

3.57k

INTVCC

82.5k

22µF x 2

25V

100nF

1µF

0.56µH

1.58k

1µF

0Ω

1µF

2 Ω

0.1µF

4.7µF

4700pF

2.55k

100nF

2 Ω

75pF

COUT3

100µF x 2

6.3V

COUT4

330µF

6.3V

VDR

VIN

7V TO 14V

VOUT1

VOUT0

7V TO 14V

COUT1,3,5,7: Murata GRM32ER60J107ME20L (100µF, 6.3V, X5R, 1210)

COUT2,4,6,8: SANYO 6TPE330MFL (330µF, 6.3V)

L1, L3: VISHAY IHLP-4040DZ-11 (1.0µH, DCR = 2.4mΩ)

L2, L4: VISHAY IHLP-4040DZ-11 (0.56µH, DCR = 1.61mΩ)

RUN0

RUN1

SYNC

ITH0

ITH1

FAULT0

FAULT1

EXTVCC

VCC0

VCC1

ISENSE0–

ISENSE0+

PWM0

ISENSE1–

ISENSE1+

PWM1

FREQ

PHASMD

ILIM

MODE0

MODE1

GND

VIN INTVCC

GND

BOOT

SMOD#

VIN

PWM

VDRV

DISB#

VCIN

PHASE

VSWH

THWN#

PGND

CGND

ISENSE1–

ISENSE1+

PWM1

1.58k

22µF x 2

25V

100nF

1µF

1.0µH

1µF

0Ω

1µF

0.22µF

COUT1

100µF x 2

6.3V

COUT2

330µF

6.3V

VDR

BOOT

SMOD#

VIN

PWM

VDRV

DISB#

VCIN

PHASE

VSWH

THWN#

PGND

CGND

22µF x 2

25V

100nF

1µF

0.56µH

1.58k

1µF

0Ω

1µF

100nF

COUT7

100µF x 2

6.3V

COUT8

330µF

6.3V

VDR

BOOT

SMOD#

VIN

PWM

VDRV

DISB#

VCIN

PHASE

VSWH

THWN#

PGND

CGND

1.58k

22µF x 2

25V

100nF

1µF

1.0µH

1µF

0Ω

1µF

0.22µF

COUT5

100µF x 2

6.3V

COUT6

330µF

6.3V

VDR

BOOT

SMOD#

VIN

PWM

VDRV

DISB#

VCIN

PHASE

VSWH

THWN#

PGND

CGND

0.1µF

180pF

4.7µF

180pF

1500pF

13.7k

75pF

VOUT0

3.3V/30A

VOUT1

1.8V/40A

VCC0

VCC1

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

Typical applicaTions

High Efficiency 425kHz 4-Phase 1.0V Step-Down Converter

10k

LTC3887-1

LTC3870-1

FDMF5820DC

38701 TA03

10nF

ISENSE0–

ISENSE0+

PWM0

VSENSE1

VSENSE0+

ISENSE0–

VDD25

VOUT0_CFG

VOUT1_CFG

ASEL1

ASEL0

FREQ_CFG

PHAS_CFG

TSNS0

TSNS1

SDA

SCL

ALERT

SHARE_CLK

VDD33

GPIO0

GPIO1

RUN0

RUN1

SYNC

ITH0

ITH1

1µF

24.9k

7.32k

20k

17.8k

24.9k

4.32k

30.1k

1.96k

INTVCC

100k

22µF x 2

25V

100nF

1µF

25k

0.16µH

1.78k

1µF

0.1µF

0Ω

1µF

2 Ω

0.1µF

4.7µF

4700pF

2.55k

100nF

2 Ω

47pF

COUT3

100µF x 6

6.3V

COUT4

470µF

2.5V

VDR

VIN

7V TO 14V

VOUT

7V TO 14V

COUT1,3,5,7: Murata GRM32ER60J107ME20L (100µF, 6.3V, X5R, 1210)

COUT2,4,6,8: SANYO 2R5TPE470M9 (470µF, 2.5V)

L1-4: COILCRAFT XAL7070-161 (0.16µH, DCR = 0.75mΩ)

RUN0

RUN1

SYNC

ITH0

ITH1

FAULT0

FAULT1

EXTVCC

VCC0

VCC1

ISENSE0–

ISENSE0+

PWM0

ISENSE1–

ISENSE1+

PWM1

FREQ

PHASMD

ILIM

MODE0

MODE1

GND

VIN INTVCC

GND

BOOT

ZCD#

VIN

PWM

PVCC

EN/FAULT#

VCC

PHASE

TMON

PGND

AGND

ISENSE1–

ISENSE1+

PWM1

1.78k

22µF x 2

25V

100nF

1µF

25k

0.16µH

1.78k

1µF

0.1µF

0Ω

1µF

100nF

COUT1

100µF x 6

6.3V

COUT2

470µF

2.5V

VDR

BOOT

ZCD#

VIN

PWM

PVCC

EN/FAULT#

VCC

PHASE

TMON

PGND

AGND

1.78k

22µF x 2

25V

100nF

1µF

25k

0.16µH

1.78k

1µF

0.1µF

0Ω

1µF

100nF

COUT7

100µF x 6

6.3V

COUT8

470µF

2.5V

VDR

BOOT

ZCD#

VIN

PWM

PVCC

EN/FAULT#

VCC

PHASE

TMON

PGND

AGND

1.78k

22µF x 2

25V

100nF

1µF

25k

0.16µH

1.78k

1µF

0.1µF

0Ω

1µF

100nF

COUT5

100µF x 6

6.3V

COUT6

470µF

2.5V

VDR

BOOT

ZCD#

VIN

PWM

PVCC

EN/FAULT#

VCC

PHASE

TMON

PGND

AGND

1.78k

0.1µF

4.7µF

47pF

VOUT

1.0V/120A

VCC0

VCC1

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

package DescripTion

Please refer to http://www.linear.com/product/LTC3870-1#packaging for the most recent package drawings.

4.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ±0.10

2423

BOTTOM VIEW—EXPOSED PAD

2.45 ±0.10

(4-SIDES)

0.75 ±0.05 R = 0.115

TYP

0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UF24) QFN 0105 REV B

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.70 ±0.05

0.25 ±0.05

0.50 BSC

2.45 ±0.05

(4 SIDES)

3.10 ±0.05

4.50 ±0.05

PACKAGE OUTLINE

PIN 1 NOTCH

R = 0.20 TYP OR

0.35 ×

45° CHAMFER

UF Package

24-Lead Plastic QFN (4mm × 4mm)

(Reference LTC DWG # 05-08-1697 Rev B)

LTC3870-1

38701f

For more information www.linear.com/LTC3870-1

 LINEAR TECHNOLOGY CORPORATION 2015

LT 1115 • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC3870-1

Typical applicaTion

LTC3870-1

100Ω

1000pF

0.42µH

4.7µF

530µF

84.5k

0.0015Ω

100Ω

1000pF

100Ω

DrMOS

RUN0

RUN1

FAULT0

FAULT1

TH0

SYNC

TH1

FREQ

PHASMD

MODE1

MODE0

GND

LIM

SENSE1

SENSE0

ISENSE0+

SENSE1

CC1

VCC0

PWM0

PWM1

INTV

EXTV

VOUT

1.5V

80A

RUN0

RUN1

GPIO0

GPIO1

TH0

SYNC

TH1

LTC3887-1

SENSE0

SENSE1

1.5V

* REFER TO LTC3887-1 DATA SHEET

FOR MASTER SETUP

VIN

7V TO 14V

0.42µH

38701 TA04

DrMOS: FAIRCHILD FDMF6820A

4-Phase 1.5V/80A Step-Down Converter with Sensing Resistors

relaTeD parTs

PART

NUMBER DESCRIPTION COMMENTS

LTM4676A Dual 13A or Single 26A Step-Down DC/DC µModule Regulator

with Digital Power System Management

4.5V ≤ VIN ≤ 17V, 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface,

16mm×16mm× 5mm, BGA Package

LTM4675 Dual 9A or Single 18A μModule Regulator

with Digital Power System Management

4.5V ≤ VIN ≤1 7V; 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, I2C/PMBus Interface,

11.9mm×16mm× 5mm, BGA Package

LTM4677 Dual 18A or Single 18A μModule Regulator

with Digital Power System Management

4.5V ≤ VIN ≤ 16V; 0.5V ≤ VOUT (±0.5%) ≤ 1.8V, I2C/PMBus Interface,

16mm× 16mm× 5.01mm, BGA Package

LTC3884 Dual Output Multiphase Step-Down Controller with Sub MilliOhm DCR

Sensing Current Mode Control and Digital Power System Management

4.5V ≤ VIN ≤ 38V, 0.5V ≤ VOUT (±0.5%) ≤ 5.5V, 70ms Start-Up, I2C/PMBus

Interface, Programmable Analog Loop Compensation, Input Current Sense

LTC3887/

LTC3887-1

Dual Output Multiphase Step-Down DC/DC Controller

with Digital Power System Management, 70ms Start-Up

4.5V ≤ VIN ≤ 24V, 0.5V ≤ VOUT0,1 (±0.5%) ≤ 5.5V, 70ms Start-Up, I2C/

PMBus Interface, –1 Version Uses DrMOS and Power Blocks

LTC3882/

LTC3882-1

Dual Output Multiphase Step-Down DC/DC Voltage Mode

Controller with Digital Power System Management

3V ≤ VIN ≤ 38V, 0.5V ≤ VOUT1,2 ≤ 5.25V, ±0.5% VOUT Accuracy

I2C/PMBus Interface, Uses DrMOS or Power Blocks

LTC3886 60V Dual Output Step-Down Controller

with Digital Power System Management

4.5V ≤ VIN ≤ 60V, 0.5V ≤ VOUT0,1 (±0.5%) ≤ 13.8V, 70ms Start-Up,

I2C/PMBus Interface, Input Current Sense

LTC3883/

LTC3883-1

Single Phase Step-Down DC/DC Controller

with Digital Power System Management

VIN Up to 24V, 0.5V ≤ VOUT ≤ 5.5V, Input Current Sense Amplifier,

I2C/PMBus Interface with EEPROM and 16-Bit ADC, ±0.5% VOUT Accuracy

LTC3815 6A Monolithic Synchronous DC/DC Step-Down Converter

with Digital Power System Management

2.25V ≤ VIN ≤ 5.5V, 0.4V ≤ VOUT ≤ 0.72VIN, Programmable VOUT Range

±25% with 0.1% Resolution, Up to 3MHz Operation with 13-bit ADC

LTC3874 Multiphase Step-Down Synchronous Slave Controller

with Sub MilliOhm DCR Sensing

4.5V ≤ VIN ≤ 38V, VOUT Up to 5.5V, Very High Output Current,

Accurate Current Sharing, Current Mode Applications

LTC3880/

LTC3880-1

Dual Output Multiphase Step-Down DC/DC Controller

with Digital Power System Management

4.5V ≤ VIN ≤ 24V, 0.5V ≤ VOUT0 (±0.5%) ≤ 5.4V, 145ms Start-Up,

I2C/PMBus Interface with EEPROM and 16-Bit ADC