LTC1967 Precision Extended Bandwidth, RMS-to-DC Converter DESCRIPTIO U FEATURES High Linearity: 0.02% Linearity Allows Simple System Calibration Wide Input Bandwidth: Bandwidth to 0.1% Additional Gain Error: 40kHz Bandwidth Independent of Input Voltage Amplitude No-Hassle Simplicity: True RMS-DC Conversion with Only One External Capacitor Delta Sigma Conversion Technology Low Supply Current: 330A Typ Ultralow Shutdown Current: 0.1A Flexible Inputs: Differential or Single Ended Rail-to-Rail Common Mode Voltage Range Up to 1VPEAK Differential Voltage Flexible Output: Rail-to-Rail Output Separate Output Reference Pin Allows Level Shifting Small Size: Space Saving 8-Pin MSOP Package The LTC(R)1967 is a true RMS-to-DC converter that uses an innovative delta-sigma computational technique. The benefits of the LTC1967 proprietary architecture when compared to conventional log-antilog RMS-to-DC converters are higher linearity and accuracy, bandwidth independent of amplitude and improved temperature behavior. The LTC1967 operates with single-ended or differential input signals (for EMI/RFI rejection) and supports crest factors up to 4. Common mode input range is rail-to-rail. Differential input range is 1VPEAK, and offers unprecedented linearity. The LTC1967 allows hassle-free system calibration at any input voltage. The LTC1967 has a rail-to-rail output with a separate output reference pin providing flexible level shifting; it operates on a single power supply from 4.5V to 5.5V. A low power shutdown mode reduces supply current to 0.1A. The LTC1967 is packaged in the space-saving MSOP package, which is ideal for portable applications. , LTC and LT are registered trademarks of Linear Technology Corporation. Protected under U.S. Patent Numbers 6,359,576, 6,362,677 and 6,516,291 U APPLICATIO S True RMS Digital Multimeters and Panel Meters True RMS AC + DC Measurements U TYPICAL APPLICATIO Single Supply RMS-to-DC Converter 4.5V TO 5.5V V+ DIFFERENTIAL INPUT 0.1F OPT. AC COUPLING IN1 OUTPUT LTC1967 IN2 OUT RTN EN GND 1967 TA01 CAVE 1F + VOUT - LINEARITY ERROR (VOUT mV DC - VIN mV ACRMS) Linearity Performance 0.2 LTC1967, 0 -0.2 -0.4 -0.6 CONVENTIONAL LOG/ANTILOG -0.8 -1.0 60Hz SINEWAVE 0 100 200 300 VIN (mV ACRMS) 400 500 1967 TA01b 1967f 1 LTC1967 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) Supply Voltage V+ to GND ............................................................. 6V Input Currents (Note 2) ..................................... 10mA Output Current (Note 3) ..................................... 10mA ENABLE Voltage ......................................... -0.3V to 6V OUT RTN Voltage ........................................ -0.3V to V+ Operating Temperature Range (Note 4) LTC1967C/LTC1967I ......................... - 40C to 85C Specified Temperature Range (Note 5) LTC1967C/LTC1967I ......................... - 40C to 85C Maximum Junction Temperature ......................... 150C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C ORDER PART NUMBER TOP VIEW GND IN1 IN2 NC 1 2 3 4 8 7 6 5 LTC1967CMS8 LTC1967IMS8 ENABLE V+ OUT RTN VOUT MS8 PACKAGE 8-LEAD PLASTIC MSOP MS8 PART MARKING TJMAX = 150C, JA = 220C/ W LTTJ Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. V+ = 5V, VOUTRTN = 2.5V, CAVE = 10F, VIN = 200mVRMS, VENABLE = 0.5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 0.1 0.3 0.4 % % 0.1 0.55 mV 2 10 Conversion Accuracy GERR Low Frequency Gain Error 50Hz to 5kHz Input (Notes 6, 7) VOOS Output Offset Voltage (Notes 6, 7) VOOS/T Output Offset Drift (Note 11) LINERR Linearity Error 50mV to 350mV (Notes 7, 8) PSRRG Power Supply Rejection (Note 9) VIOS Input Offset Voltage (Notes 6, 7, 10) VIOS/T Input Offset Drift (Note 11) CF = 3 CF = 5 V/C 0.02 0.15 % 0.02 0.15 0.20 %/V %/V 0.2 1.5 mV 1 10 V/C 60Hz Fundamental, 200mVRMS 0.2 mV 60Hz Fundamental, 200mVRMS 5 mV Accuracy = 1% (Note 14) Additional Error vs Crest Factor (CF) Input Characteristics VIMAX Maximum Peak Input Swing IVR Input Voltage Range ZIN Input Impedance Average, Differential (Note 12) Average, Common Mode (Note 12) CMRRI Input Common Mode Rejection (Note 13) VIMIN Minimum RMS Input PSRRI Power Supply Rejection 1 1.05 0 5 100 50 (Note 9) V V+ 250 V M M 400 V/V 5 mV 600 V/V 1967f 2 LTC1967 ELECTRICAL CHARACTERISTICS The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. V+ = 5V, VOUTRTN = 2.5V, CAVE = 10F, VIN = 200mVRMS, VENABLE = 0.5V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Output Characteristics OVR Output Voltage Range 0 ZOUT Output Impedance (Note 12) 40 CMRRO Output Common Mode Rejection (Note 13) VOMAX Maximum Differential Output Swing Accuracy = 1%, DC Input (Note 14) PSRRO Power Supply Rejection (Note 9) 1.0 0.9 V+ V 50 65 k 50 250 V/V 1.05 250 V V 1000 V/V Frequency Response f1P 0.1% Additional Gain Error (Note 15) 40 kHz f- 3dB 3dB Frequency (Note 15) 4 MHz Power Supplies V+ Supply Voltage IS Supply Current IN1 = 20mV, IN2 = 0V IN1 = 200mV, IN2 = 0V 4.5 5.5 V 320 340 390 A A 0.1 10 Shutdown Characteristics A ISS Supply Current VENABLE = 4.5V IIH ENABLE Pin Current High VENABLE = 4.5V -1 - 0.1 IIL ENABLE Pin Current Low VENABLE = 0.5V -3 -0.5 VTH ENABLE Threshold Voltage 2.1 V VHYS ENABLE Threshold Hysteresis 0.1 V Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The inputs (IN1, IN2) are protected by shunt diodes to GND and V+. If the inputs are driven beyond the rails, the current should be limited to less than 10mA. Note 3: The LTC1967 output (VOUT) is high impedance and can be overdriven, either sinking or sourcing current, to the limits stated. Note 4: The LTC1967C/LTC1967I are guaranteed functional over the operating temperature range of - 40C to 85C. Note 5: The LTC1967C is guaranteed to meet specified performance from 0C to 70C. The LTC1967C is designed, characterized and expected to meet specified performance from - 40C to 85C but is not tested nor QA sampled at these temperatures. The LTC1967I is guaranteed to meet specified performance from - 40C to 85C. Note 6: High speed automatic testing cannot be performed with CAVE = 10F. The LTC1967 is 100% tested with CAVE = 47nF. Correlation tests have shown that the performance limits can be guaranteed with the additional testing being performed to guarantee proper operation of all the internal circuitry. Note 7: High speed automatic testing cannot be performed with 60Hz inputs. The LTC1967 is 100% tested with DC and 10kHz input signals. Measurements with DC inputs from 50mV to 350mV are used to calculate A - 0.1 A the four parameters: GERR, VOOS, VIOS and linearity error. Correlation tests have shown that the performance limits can be guaranteed with the additional testing being performed to guarantee proper operation of all internal circuitry. Note 8: The LTC1967 is inherently very linear. Unlike older log/antilog circuits, its behavior is the same with DC and AC inputs, and DC inputs are used for high speed testing. Note 9: The power supply rejections of the LTC1967 are measured with DC inputs from 50mV to 350mV. The change in accuracy from V+ = 4.5V to V+ = 5.5V is divided by 1V. Note 10: Previous generation RMS-to-DC converters required nonlinear input stages as well as a nonlinear core. Some parts specify a "DC reversal error," combining the effects of input nonlinearity and input offset voltage. The LTC1967 behavior is simpler to characterize and the input offset voltage is the only significant source of "DC reversal error." Note 11: Guaranteed by design. Note 12: The LTC1967 is a switched capacitor device and the input/output impedance is an average impedance over many clock cycles. The input impedance will not necessarily lead to an attenuation of the input signal measured. Refer to the Applications Information section titled "Input Impedance" for more information. 1967f 3 LTC1967 ELECTRICAL CHARACTERISTICS Note 13: The common mode rejection ratios of the LTC1967 are measured with DC inputs from 50mV to 350mV. The input CMRR is defined as the change in VIOS measured between input levels of 0V to 350mV and input levels of V+ - 350mV to V+ divided by V+ - 350mV. The output CMRR is defined as the change in VOOS measured with OUT RTN = 0V and OUT RTN = V+ - 350mV divided by V+ - 350mV. Note 14: The LTC1967 input and output voltage swings are limited by internal clipping. However, its topology is relatively tolerant of momentary internal clipping. Note 15: The LTC1967 exploits oversampling and noise shaping to reduce the quantization noise of internal 1-bit analog-to-digital conversions. At higher input frequencies, increasingly large portions of this noise are aliased down to DC. Because the noise is shifted in frequency, it becomes a low frequency rumble and is only filtered at the expense of increasingly long settling times. The LTC1967 is inherently wideband, but the output accuracy is degraded by this aliased noise. U W TYPICAL PERFOR A CE CHARACTERISTICS Gain and Offset vs Input Common Mode Voltage 0.2 50mV VIN(PEAK) 350mV GAIN ERROR 0.4 0.6 0.3 0.4 VIOS -0.1 0.2 -0.2 0 VOOS -0.3 -0.2 1.0 50mV VIN(PEAK) 350mV 0.8 GAIN ERROR 0.6 0.4 0.2 0.1 0.2 VOOS 0 0 -0.1 -0.2 -0.4 -0.4 -0.4 -0.5 -0.6 -0.3 -0.6 -0.6 -0.8 -0.4 -0.8 -0.7 -1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT COMMON MODE VOLTAGE (V) -0.5 -1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 OUTPUT COMMON MODE VOLTAGE (V) 1967 G02 1967 G01 Gain and Offset vs Supply Voltage Gain and Offsets vs Temperature 0.05 0.4 0.03 0.3 0.3 0.02 0.2 VOOS 0.01 0.1 GAIN ERROR 0 0 -0.1 -0.01 VIOS -0.02 -0.2 GAIN ERROR (%) 0.4 50mV VIN(PEAK) 350mV 1.0 50mV VIN(PEAK) 350mV 0.8 0.6 0.2 0.4 GAIN ERROR 0.2 0.1 VOOS 0 0 VIOS -0.1 -0.2 -0.2 -0.4 -0.03 -0.3 -0.3 -0.6 -0.04 -0.4 -0.4 -0.8 -0.05 -40 -0.5 -0.5 -15 35 10 TEMPERATURE (C) 60 85 1967 G03 4.5 4.8 5.7 5.4 5.1 SUPPLY VOLTAGE (V) OFFSET VOLTAGE (mV) 0.5 OFFSET VOLTAGE (mV) 0.5 0.04 GAIN ERROR (%) -0.2 VIOS OFFSET VOLTAGE (mV) 0 0.5 0.8 OFFSET VOLTAGE (mV) GAIN ERROR (%) 0.1 1.0 GAIN ERROR (%) 0.3 Gain and Offset vs Output Common Mode Voltage -1.0 6.0 1967 G04 1967f 4 LTC1967 U W TYPICAL PERFOR A CE CHARACTERISTICS Performance vs Crest Factor 200.2 200.0 199.8 1kHz 199.6 199.4 199.0 2 1 3 CREST FACTOR 10Hz 1kHz 200 190 60Hz 10kHz 180 170 160 5 DC Linearity 7 0 100 200 300 VIN1 (mV ACRMS) 400 500 1967 G07 Supply Current vs Temperature 345 VS = 5V 400 340 0.04 0.02 0 -0.02 -0.04 350 SUPPLY CURRENT (A) SUPPLY CURRENT (A) {VOUTDC - |VINDC|} (mV) -0.20 8 Supply Current vs Supply Voltage 0.06 300 250 200 150 100 0 300 335 330 325 320 50 500 1 0 2 4 3 SUPPLY VOLTAGE (V) 1967 G08 5 315 -55 -35 -15 6 1967 G10 Input Signal Bandwidth vs RMS Value 400 200 300 IEN 0 200 -100 100 -200 0 -300 -100 -400 4 3 5 2 ENABLE PIN VOLTAGE (V) 6 1967 G11 1% ERROR ENABLE PIN CURRENT (nA) 100 0.1% ERROR Input Signal Bandwidth 202 10% ERROR 200 OUTPUT DC VOLTAGE (mV) 300 1000 OUTPUT DC VOLTAGE (mV) 500 IS 5 25 45 65 85 105 125 TEMPERATURE (C) 1967 G09 Shutdown Current vs ENABLE Voltage SUPPLY CURRENT (A) 0 -0.15 450 CAVE = 1F 0.08 VIN2 = MIDSUPPLY 1 0.05 1967 G06 0.10 0 0.10 -0.10 140 1967 G05 -0.06 EFFECTS OF OFFSETS -0.08 MAY BE POSITIVE OR NEGATIVE AT VIN = 0V -0.10 -300 100 -500 -100 VIN1 (mV) 60Hz SINEWAVES CAVE = 10F VIN2 = MIDSUPPLY 0.15 -0.05 150 200mVRMS SCR WAVEFORMS 130 CAVE = 10F 5%/DIV 120 6 2 3 5 4 1 CREST FACTOR 60Hz 4 20Hz VOUT (mV DC) - VIN (mV ACRMS) 200.4 199.2 0.20 210 OUTPUT VOLTAGE (mV DC) OUTPUT VOLTAGE (mV DC) 200mVRMS SCR WAVEFORMS 200.8 CAVE = 10F O.1%/DIV 200.6 20Hz AC Linearity Performance vs Large Crest Factors 220 201.0 100 10 -3dB 1 100 1k 10k 100k 1M INPUT SIGNAL FREQUENCY (Hz) 10M 1967 G12 198 196 194 192 190 188 186 184 1%/DIV CAVE = 1F 182 1k 10k 100k 1M 100 INPUT SIGNAL FREQUENCY (Hz) 10M 1967 G13 1967f 5 LTC1967 U W TYPICAL PERFOR A CE CHARACTERISTICS 202 40 0.5%/DIV CAVE = 47F 201 Input Common Mode Rejection Ratio vs Frequency DC Transfer Function Near Zero Bandwidth to 200kHz 100 VIN2 = MIDSUPPLY THREE REPRESENTATIVE UNITS 35 80 199 198 INPUT CMRR (dB) 25 VOUT (mV DC) OUTPUT VOLTAGE (mV) 30 200 20 15 10 5 197 196 195 0 50k 100k 150k INPUT FREQUENCY (Hz) 200k 0 -20 0 10 -10 VIN1 (mV DC) 20 100 10k 100k 1M 1k INPUT FREQUENCY (Hz) VIN2 = MIDSUPPLY DC -1% ERROR -10 AC - 60Hz SINEWAVE -20 1 VIN1 (VRMS) 10M 1967 G16 Output Noise vs Input Frequency 1 PEAK OUTPUT NOISE (% OF READING) {VOUT (mV DC) - VIN (mVRMS)} (mV) 10 30 1967 G15 -5 0.5 30 10 0 0 40 -5 -10 -30 5 -15 50 20 Output Accuracy vs Signal Amplitude 1% ERROR 70 60 0 1967 G14 10 4.5V COMMON MODE INPUT CONVERSION TO DC OUTPUT 90 1.5 2 1967 G17 PEAK NOISE DURING 10 SECOND MEASUREMENT 0.1 CAVE = 1F CAVE = 10F 0.01 CAVE = 100F 0.001 1k 10k INPUT FREQUENCY (Hz) 100k 1967 G18 1967f 6 LTC1967 U U U PI FU CTIO S GND (Pin 1): Ground. The power return pin. IN1 (Pin 2): Differential Input. DC coupled (polarity is irrelevant). IN2 (Pin 3): Differential Input. DC coupled (polarity is irrelevant). VOUT (Pin 5): Output Voltage. This is high impedance. The RMS averaging is accomplished with a single shunt capacitor from this node to OUT RTN. The transfer function is given by: ( VOUT - OUT RTN) = OUT RTN (Pin 6): Output Return. The output voltage is created relative to this pin. The VOUT and OUT RTN pins are not balanced and this pin should be tied to a low impedance, both AC and DC. Although it is often tied to GND, it can be tied to any arbitrary voltage: GND < OUT RTN < (V+ - Max Output) V+ (Pin 7): Positive Voltage Supply. 4.5V to 5.5V. ENABLE (Pin 8): An Active-Low Enable Input. LTC1967 is debiased if open circuited or driven to V+. For normal operation, pull to GND. 2 Average (IN2 - IN1) U W U U APPLICATIO S I FOR ATIO RMS-TO-DC CONVERSION Alternatives to RMS Definition of RMS Other ways to quantify dynamic waveforms include peak detection and average rectification. In both cases, an average (DC) value results, but the value is only accurate at the one chosen waveform type for which it is calibrated, typically sine waves. The errors with average rectification are shown in Table 1. Peak detection is worse in all cases and is rarely used. RMS amplitude is the consistent, fair and standard way to measure and compare dynamic signals of all shapes and sizes. Simply stated, the RMS amplitude is the heating potential of a dynamic waveform. A 1VRMS AC waveform will generate the same heat in a resistive load as will 1V DC. Mathematically, RMS is the "Root of the Mean of the Square": VRMS = V2 1V DC + - R 1V ACRMS R 1V (AC + DC) RMS R SAME HEAT 1967 F01 Figure 1 Table 1. Errors with Average Rectification vs True RMS WAVEFORM VRMS AVERAGE RECTIFIED (V) Square Wave 1.000 1.000 11% Sine Wave 1.000 0.900 *Calibrate for 0% Error Triangle Wave 1.000 0.866 -3.8% SCR at 1/2 Power, = 90 1.000 0.637 -29.3% SCR at 1/4 Power, = 114 1.000 0.536 -40.4% ERROR* The last two entries of Table 1 are chopped sine waves as is commonly created with thyristors such as SCRs and Triacs. Figure 2a shows a typical circuit and Figure 2b shows the resulting load voltage, switch voltage and load 1967f 7 LTC1967 U W U U APPLICATIO S I FOR ATIO currents. The power delivered to the load depends on the firing angle, as well as any parasitic losses such as switch "ON" voltage drop. Real circuit waveforms will also typically have significant ringing at the switching transition, dependent on exact circuit parasitics. For the purposes of this data sheet, "SCR Waveforms" refers to the ideal chopped sine wave, though the LTC1967 will do faithful RMS-to-DC conversion with real SCR waveforms as well. The case shown is for = 90, which corresponds to 50% of available power being delivered to the load. As noted in Table 1, when = 114, only 25% of the available power is being delivered to the load and the power drops quickly as approaches 180. With an average rectification scheme and the typical calibration to compensate for errors with sine waves, the RMS level of an input sine wave is properly reported; it is only with a non-sinusoidal waveform that errors occur. Because of this calibration, and the output reading in VRMS, the term True-RMS got coined to denote the use of an actual RMS-to-DC converter as opposed to a calibrated average rectifier. the lowpass filter. The input to the LPF is the calculation from the multiplier/divider; (VIN)2/VOUT. The lowpass filter will take the average of this to create the output, mathematically: ( V )2 IN VOUT = , VOUT Because VOUT is DC, 2 ( V )2 ( VIN ) IN , so = VOUT V OUT VOUT ( V )2 IN = , and VOUT ( VOUT )2 = ( VIN )2, or VOUT = ( VIN )2 = RMS( VIN ) (VIN )2 VOUT + VLOAD - AC MAINS + ILOAD VLINE CONTROL + - VTHY VIN x / LPF VOUT 1967 F03 - 1967 F02a Figure 2a Figure 3. RMS-to-DC Converter with Implicit Computation Unlike the prior generation RMS-to-DC converters, the LTC1967 computation does NOT use log/antilog circuits, which have all the same problems, and more, of log/ antilog multipliers/dividers, i.e., linearity is poor, the bandwidth changes with the signal amplitude and the gain drifts with temperature. VLINE VLOAD VTHY ILOAD 1967 F02b Figure 2b How an RMS-to-DC Converter Works Monolithic RMS-to-DC converters use an implicit computation to calculate the RMS value of an input signal. The fundamental building block is an analog multiply/divide used as shown in Figure 3. Analysis of this topology is easy and starts by identifying the inputs and the output of How the LTC1967 RMS-to-DC Converter Works The LTC1967 uses a completely new topology for RMS-toDC conversion, in which a modulator acts as the divider, and a simple polarity switch is used as the multiplier1 as shown in Figure 4. 1Protected by multiple patents. 1967f 8 LTC1967 U W U U APPLICATIO S I FOR ATIO D Note that the internal scalings are such that the output duty cycle is limited to 0% or 100% only when VIN exceeds 4 * VOUT. VIN VOUT - REF VIN Linearity of an RMS-to-DC Converter 1 LPF VOUT 1967 F04 Figure 4. Topology of LTC1967 The modulator has a single-bit output whose average duty cycle (D) will be proportional to the ratio of the input signal divided by the output. The is a 2nd order modulator with excellent linearity. The single-bit output is used to selectively buffer or invert the input signal. Again, this is a circuit with excellent linearity, because it operates at only two points: 1 gain; the average effective multiplication over time will be on the straight line between these two points. The combination of these two elements again creates a lowpass filter input signal equal to (VIN)2/VOUT, which, as shown above, results in RMS-to-DC conversion. The lowpass filter performs the averaging of the RMS function and must be a lower corner frequency than the lowest frequency of interest. For line frequency measurements, this filter is simply too large to implement on-chip, but the LTC1967 needs only one capacitor on the output to implement the lowpass filter. The user can select this capacitor depending on frequency range and settling time requirements, as will be covered in the Design Cookbook section to follow. This topology is inherently more stable and linear than log/ antilog implementations primarily because all of the signal processing occurs in circuits with high gain op amps operating closed loop. More detail of the LTC1967 inner workings is shown in the Simplified Schematic towards the end of this data sheet. INPUT INPUT CIRCUITRY * VIOS * INPUT NONLINEARITY Linearity may seem like an odd property for a device that implements a function that includes two very nonlinear processes: squaring and square rooting. However, an RMS-to-DC converter has a transfer function, RMS volts in to DC volts out, that should ideally have a 1:1 transfer function. To the extent that the input to output transfer function does not lie on a straight line, the part is nonlinear. A more complete look at linearity uses the simple model shown in Figure 5. Here an ideal RMS core is corrupted by both input circuitry and output circuitry that have imperfect transfer functions. As noted, input offset is introduced in the input circuitry, while output offset is introduced in the output circuitry. Any nonlinearity that occurs in the output circuity will corrupt the RMS in to DC out transfer function. A nonlinearity in the input circuitry will typically corrupt that transfer function far less simply because with an AC input, the RMS-to-DC conversion will average the nonlinearity from a whole range of input values together. But the input nonlinearity will still cause problems in an RMS-to-DC converter because it will corrupt the accuracy as the input signal shape changes. Although an RMS-toDC converter will convert any input waveform to a DC output, the accuracy is not necessarily as good for all waveforms as it is with sine waves. A common way to describe dynamic signal wave shapes is Crest Factor. The crest factor is the ratio of the peak value relative to the RMS value of a waveform. A signal with a crest factor of 4, for instance, has a peak that is four times its RMS value. IDEAL RMS-TO-DC CONVERTER OUTPUT CIRCUITRY * VOOS * OUTPUT NONLINEARITY OUTPUT 1967 F05 Figure 5. Linearity Model of an RMS-to-DC Converter 1967f 9 LTC1967 U W U U APPLICATIO S I FOR ATIO Because this peak has energy (proportional to voltage squared) that is 16 times (42) the energy of the RMS value, the peak is necessarily present for at most 6.25% (1/16) of the time. The LTC1967 performs very well with crest factors of 4 or less and will respond with reduced accuracy to signals with higher crest factors. The high performance with crest factors less than 4 is directly attributable to the high linearity throughout the LTC1967. DESIGN COOKBOOK The LTC1967 RMS-to-DC converter makes it easy to implement a rather quirky function. For many applications all that will be needed is a single capacitor for averaging, appropriate selection of the I/O connections and power supply bypassing. Of course, the LTC1967 also requires power. A wide variety of power supply configurations are shown in the Typical Applications section towards the end of this data sheet. lowest frequency signals of interest. For a single averaging capacitor, the accuracy at low frequencies is depicted in Figure 6. Figure 6 depicts the so-called "DC error" that results at a given combination of input frequency and filter capacitor values2. It is appropriate for most applications, in which the output is fed to a circuit with an inherently band-limited frequency response, such as a dual slope/integrating A/D converter, a A/D converter or even a mechanical analog meter. However, if the output is examined on an oscilloscope with a very low frequency input, the incomplete averaging will be seen, and this ripple will be larger than the error depicted in Figure 6. Such an output is depicted in Figure 7. The ripple is at twice the frequency of the input 2This frequency-dependent error is in additon to the static errors that affect all readings and are therefore easy to trim or calibrate out. The "Error Analyses" section to follow discusses the effect of static error terms. ACTUAL OUTPUT WITH RIPPLE f = 2 x fINPUT The RMS or root-mean-squared value of a signal, the root of the mean of the square, cannot be computed without some averaging to obtain the mean function. The LTC1967 true RMS-to-DC converter utilizes a single capacitor on the output to do the low frequency averaging required for RMS-to-DC conversion. To give an accurate measure of a dynamic waveform, the averaging must take place over a sufficiently long interval to average, rather than track, the OUTPUT Capacitor Value Selection IDEAL OUTPUT DC ERROR (0.05%) PEAK RIPPLE (5%) PEAK ERROR = DC ERROR + PEAK RIPPLE (5.05%) DC AVERAGE OF ACTUAL OUTPUT TIME 1967 F07 Figure 7. Output Ripple Exceeds DC Error 0 -0.2 C = 10F -0.4 C = 22F C = 4.7F DC ERROR (%) -0.6 -0.8 -1.0 C = 2.2F C = 1F C = 0.47F C = 0.22F C = 0.1F -1.2 -1.4 -1.6 -1.8 -2.0 1 10 INPUT FREQUENCY (Hz) 100 1967 F06 Figure 6. DC Error vs Input Frequency 1967f 10 LTC1967 U W U U APPLICATIO S I FOR ATIO 0 -0.2 C = 100F PEAK ERROR (%) -0.4 -0.6 -0.8 C = 47F -1.0 C = 22F C = 10F C = 4.7F C = 2.2F C = 1F -1.2 -1.4 -1.6 -1.8 -2.0 1 10 INPUT FREQUENCY (Hz) 100 1967 F08 Figure 8. Peak Error vs Input Frequency with One Cap Averaging because of the computation of the square of the input. The typical values shown, 5% peak ripple with 0.05% DC error, occur with CAVE = 1.5F and fINPUT = 10Hz. If the application calls for the output of the LTC1967 to feed a sampling or Nyquist A/D converter (or other circuitry that will not average out this double frequency ripple) a larger averaging capacitor can be used. This trade-off is depicted in Figure 8. The peak ripple error can also be reduced by additional lowpass filtering after the LTC1967, but the simplest solution is to use a larger averaging capacitor. A 2.2F capacitor is a good choice for many applications. The peak error at 50Hz/60Hz will be <1% and the DC error will be <0.1% with frequencies of 10Hz or more. Note that both Figure 6 and Figure 8 assume AC-coupled waveforms with a crest factor less than 2, such as sine waves or triangle waves. For higher crest factors and/or AC + DC waveforms, a larger CAVE will generally be required. See "Crest Factor and AC + DC Waveforms." Capacitor Type Selection The LTC1967 can operate with many types of capacitors. The various types offer a wide array of sizes, tolerances, parasitics, package styles and costs. Ceramic chip capacitors offer low cost and small size, but are not recommended for critical applications. The value stability over voltage and temperature is poor with many types of ceramic dielectrics. This will not cause an RMSto-DC accuracy problem except at low frequencies, where it can aggravate the effects discussed in the previous section. If a ceramic capacitor is used, it may be necessary to use a much higher nominal value in order to assure the low frequency accuracy desired. Another parasitic of ceramic capacitors is leakage, which is again dependent on voltage and particularly temperature. If the leakage is a constant current leak, the I * R drop of the leak multiplied by the output impedance of the LTC1967 will create a constant offset of the output voltage. If the leak is Ohmic, the resistor divider formed with the LTC1967 output impedance will cause a gain error. For < 0.1% gain accuracy degradation, the parallel impedance of the capacitor leakage will need to be >1000 times the LTC1967 output impedance. Accuracy at this level can be hard to achieve with a ceramic capacitor, particularly with a large value of capacitance and at high temperature. For critical applications, a film capacitor, such as metalized polyester, will be a much better choice. Although more expensive, and larger for a given value, the value stability and low leakage make metal-film capacitors a trouble-free choice. With any type of capacitor, the self-resonance of the capacitor can be an issue with the switched capacitor LTC1967. If the self-resonant frequency of the averaging capacitor is 1MHz or less, a second smaller capacitor should be added in parallel to reduce the impedance seen by the LTC1967 output stage at high frequencies. A capacitor 100 times smaller than the averaging capacitor will typically be small enough to be a low cost ceramic with a high quality dielectric such as X7R or NPO/COG. 1967f 11 LTC1967 U W U U APPLICATIO S I FOR ATIO Input Connections work well with dual supply configurations, but in single supply configurations it will be necessary to raise the voltage on the grounded input to assure that the signal at the active input stays within the range of 0V to V+. If there is already a suitable voltage reference available, connect the second input to that point. If not, a midsupply voltage can be created with two resistors as shown in Figure 9b. The LTC1967 input is differential and DC coupled. The LTC1967 responds to the RMS value of the differential voltage between Pin 2 and Pin 3, including the DC portion of that difference. However, there is no DC-coupled path from the inputs to ground. Therefore, at least one of the two inputs must be connected with a DC-return path to ground. Finally, if the input voltage is known to be between 0V and V+, it can be AC coupled by using the configuration shown in Figure 9c. Whereas the DC return path was provided through Pin 3 in Figures 9a and 9b, in this case, the return path is provided on Pin 2, through the input signal voltages. The switched capacitor action between the two input pins of the LTC1967 will cause the voltage on the coupling capacitor connected to the second input to follow the DC average of the input voltage. Both inputs must be connected to something. If either input is left floating, a zero volt output will result. For single-ended DC-coupled applications, simply connect one of the two inputs (they are interchangeable) to the signal, and the other to ground. This will work well for dual supply configurations, but for single supply configurations it will only work well for unipolar input signals. The LTC1967 input voltage range is from rail-to-rail, and when the input is driven above V+ or below GND the gain and offset errors will increase substantially after just a few hundred millivolts of overdrive. Fortunately, most single supply circuits measuring a DC-coupled RMS value will include some reference voltage other than ground, and the second LTC1967 input can be connected to that point. For differential input applications, connect the two inputs to the differential signal. If AC coupling is desired, one of the two inputs can be connected through a series capacitor. In all of these connections, to choose the input coupling capacitor, CC, calculate the low frequency coupling time constant desired, and divide by the LTC1967 differential input impedance. Because the LTC1967 input impedance is about 100 times its output impedance, this capacitor is typically much smaller than the output averaging capacitor. Its requirements are also much less stringent, and a ceramic chip capacitor will usually suffice. For single-ended AC-coupled applications, Figure 9 shows three alternate topologies. The first one, shown in Figure 9a uses a coupling capacitor to one input while the other is grounded. This will remove the DC voltage difference from the input to the LTC1967, and it will therefore not be part of the resulting output voltage. Again, this connection will V+ CC CC LTC1967 2 VIN V+ 3 IN2 LTC1967 2 IN1 GND VIN V- V+ LTC1967 2 IN1 3 IN2 3 VIN VDC R1 20k (9a) V+ + - IN1 IN2 CC 1967 F07 R2 20k (9b) (9c) Figure 9. Single-Ended AC-Coupled Input Connection Alternatives 1967f 12 LTC1967 U W U U APPLICATIO S I FOR ATIO Output Connections The LTC1967 output is differentially, but not symmetrically, generated. That is to say, the RMS value that the LTC1967 computes will be generated on the output (Pin 5) relative to the output return (Pin 6), but these two pins are not interchangeable. For most applications, Pin 6 will be tied to ground (Pin 1). However, Pin 6 can be tied to any voltage between 0V and V+ (Pin 7) less the maximum output voltage swing desired. This last restriction keeps VOUT itself (Pin 5) within the range of 0V to V+. If a reference level other than ground is used, it should be a low impedance, both AC and DC, for proper operation of the LTC1967. In any configuration, the averaging capacitor should be connected between Pins 5 and 6. The LTC1967 RMS-DC output will be a positive voltage created at VOUT (Pin 5) with respect to OUT RTN (Pin 6). Power Supply Bypassing The LTC1967 is a switched capacitor device, and large transient power supply currents will be drawn as the switching occurs. For reliable operation, standard power supply bypassing must be included. A 0.01F capacitor from V+ (Pin 7) to GND (Pin 1) located close to the device will suffice. If there is a good quality ground plane available, the capacitors can go directly to that instead. Power supply bypass capacitors can, of course, be inexpensive ceramic types. Up and Running! If you have followed along this far, you should have the LTC1967 up and running by now! Don't forget to enable the device by grounding Pin 8, or driving it with a logic low. Keep in mind that the LTC1967 output impedance is fairly high, and that even the standard 10M input impedance of a digital multimeter (DMM) or a 10x scope probe will load down the output enough to degrade its typical gain error of 0.1%. In the end application circuit, either a buffer or another component with an extremely high input impedance (such as a dual slope integrating ADC) should be used. For laboratory evaluation, it may suffice to use a bench-top DMM with the ability to disconnect the 10M shunt. If you are still having trouble, it may be helpful to skip ahead a few pages and review the Troubleshooting Guide. What About Response Time? With a large value averaging capacitor, the LTC1967 can easily perform RMS-to-DC conversion on low frequency signals. It compares quite favorably in this regard to priorgeneration products because nothing about the circuitry is temperature sensitive. So the RMS result doesn't get distorted by signal driven thermal fluctuations like a log-antilog circuit output does. However, using large value capacitors results in a slow response time. Figure 10 shows the rising and falling step responses with a 1F averaging capacitor. Although they both appear at first glance to be standard exponentialdecay type settling, they are not. This is due to the nonlinear nature of an RMS-to-DC calculation. Also note the change in the time scale between the two; the rising edge is more than twice as fast to settle to a given accuracy. Again this is a necessary consequence of RMSto-DC calculation.3 Although shown with a step change between 0mV and 100mV, the same response shapes will occur with the LTC1967 for ANY step size. This is in marked contrast to prior generation log/antilog RMS-to-DC converters, whose averaging time constants are dependent on the signal level, resulting in excruciatingly long waits for the output to go to zero. The shape of the rising and falling edges will be dependent on the total percent change in the step, but for less than the 100% changes shown in Figure 10, the responses will be less distorted and more like a standard exponential decay. For example, when the input amplitude is changed from 3 To convince oneself of this necessity, consider a pulse train of 50% duty cycle between 0mV and 100mV. At very low frequencies, the LTC1967 will essentially track the input. But as the input frequency is increased, the average result will converge to the RMS value of the input. If the rise and fall characteristics were symmetrical, the output would converge to 50mV. In fact though, the RMS value of a 100mV DC-coupled 50% duty cycle pulse train is 70.71mV, which the asymmetrical rise and fall characteristics will converge to as the input frequency is increased. 1967f 13 LTC1967 U W U U APPLICATIO S I FOR ATIO 100mV to 110mV (+10%) and back (-10%), the step responses are essentially the same as a standard exponential rise and decay between those two levels. In such cases, the time constant of the decay will be in between that of the rising edge and falling edge cases of Figure 10. Therefore, the worst case is the falling edge response as it goes to zero, and it can be used as a design guide. But with 100F, the settling time to even 10% is a full 20 seconds, which is a long time to wait. What can be done about such a design? If the reason for choosing 100F is to keep the DC error with a 100mHz input less than 0.1%, the answer is: not much. The settling time to 1% of 32 seconds is just 3.2 cycles of this extremely low frequency. Averaging very low frequency signals takes a long time. Figure 11 shows the settling accuracy vs settling time for a variety of averaging capacitor values. If the capacitor value previously selected (based on error requirements) gives an acceptable settling time, your design is done. However, if the reason for choosing 100F is to keep the peak error with a 10Hz input less than 0.1%, there is another way to achieve that result with a much improved settling time. 120 CAVE = 1F 100 100 80 80 OUTPUT (mV) OUTPUT (mV) 120 60 40 20 CAVE = 1F 60 40 20 0 0 0 0.05 0.1 0.15 TIME (SEC) 0.2 0.25 0 0.1 0.2 0.3 TIME (SEC) 0.4 1967 F10a 0.5 1967 F10b Figure 10b. LTC1967 Falling Edge with CAVE = 1F Figure 10a. LTC1967 Rising Edge with CAVE = 1F SETTLING ACCURACY (%) 10 C = 0.1F C = 0.22F C = 0.47F C = 1F C = 2.2F C = 4.7F C = 10F C = 22F C = 47F C = 100F 1 0.1 0.01 0.1 1 SETTLING TIME (SEC) 10 100 1966 F12 Figure 11. Settling Time with One Cap Averaging 1967f 14 LTC1967 U W U U APPLICATIO S I FOR ATIO Reducing Ripple with a Post Filter The output ripple is always much larger than the DC error, so filtering out the ripple can reduce the peak error substantially, without the large settling time penalty of simply increasing the averaging capacitor. Figure 12 shows a basic 2nd order post filter, for a net 3rd order filtering of the LTC1967 RMS calculation. It uses the 50k output impedance of the LTC1967 as the first resistor of a 3rd order Sallen-Key active-RC filter. This topology features a buffered output, which can be desirable depending on the application. However, there are disadvantages to this topology, the first of which is that the op amp input voltage and current errors directly degrade the effective LTC1967 VOOS. The table inset in Figure 12 shows these errors for four of Linear Technology's op amps. A second disadvantage is that the op amp output has to operate over the same range as the LTC1967 output, including ground, which in single supply applications is the negative supply. Although the LTC1967 output will function fine just millivolts from the rail, most op amp output stages (and even some input stages) will not. There are at least two ways to address this. First of all, the op amp can be operated split supply if a negative supply is available. Just the op amp would need to do so; the LTC1967 can remain single supply. A second way to address this issue is to create a signal reference voltage a half volt or so above ground. This is most attractive when the circuitry that follows has a differential input, so that the tolerance of the signal reference is not a C1 2.2F 5 LTC1967 6 R1 23.2k R2 102k CAVE 2.2F RB - + LT1880 concern. To do this, tie all three ground symbols shown in Figure 12 to the signal reference, as well as to the differential return for the circuitry that follows. Figure 13 shows an alternative 2nd order post filter, for a net 3rd order filtering of the LTC1967 RMS calculation. It also uses the 50k output impedance of the LTC1967 as the first resistor of a 3rd order active-RC filter, but this topology filters without buffering so that the op amp DC error characteristics do not affect the output. Although the output impedance of the LTC1967 is increased from 50k to 168k, this is not an issue with an extremely high input impedance load, such as a dual-slope integrating ADC like the ICL7106. And it allows a generic op amp to be used, such as the SOT-23 one shown. Furthermore, it easily works on a single supply rail by tying the noninverting input of the op amp to a low noise reference as optionally shown. This reference will not change the DC voltage at the circuit output, although it does become the AC ground for the filter, thus the (relatively) low noise requirement. Step Responses with a Post Filter Both of the post filters, shown in Figures 12 and 13, are optimized for additional filtering with clean step responses. The 50k output impedance of the LTC1967 working into a 2.2F capacitor forms a 1st order LPF with a -3dB frequency of ~1.45Hz. The two filters have 2.2F at the LTC1967 output for easy comparison with a 2.2F-only case, and both have the same relative Bessellike shape. However, because of the topological differences of pole placements between the various components within the two filters, the net effective bandwidth for Figure 12 is slightly higher (1.2 * 1.45 1.7Hz) than with 2.2F alone, while the bandwidth for Figure 13 is 5 C2 0.22F LTC1967 OP AMP LTC1967 VOOS VIOS IB/OS * R TOTAL OFFSET RB VALUE ISQ 6 R1 118k CAVE 2.2F LT1494 LT1880 LT1077 LTC2054 500V 375V 150V 60V 3V 43V 195V 329V 52V 918V 845V 889V 555V 174k SHORT 174k SHORT 1A 1.2mA 48A 150A Figure 12. Buffered Post Filter C1 0.47F R2 402k C2 0.47F - OTHER REF VOLTAGE, SEE TEXT + LT1782 1067 F13 1967 F12 Figure 13. DC Accurate Post Filter 1967f 15 LTC1967 U W U U APPLICATIO S I FOR ATIO somewhat lower (0.7 * 1.45 1Hz) than with 2.2F alone. To adjust the bandwidth of either of them, simply scale all the capacitors by a common multiple, and leave the resistors unchanged. The step responses of the LTC1967 with 2.2F-only and with the two post filters are shown in Figure 14. This is the rising edge RMS output response to a 10Hz input starting at t = 0. Although the falling edge response is the worst case for settling, the rising edge illustrates the ripple that these post filters are designed to address, so the rising edge makes for a better intuitive comparison. The initial rise of the LTC1967 will have enhanced slew rates with DC and very low frequency inputs due to saturation effects in the modulator. This is seen in Figure 14 in two ways. First, the 2.2F-only output is seen to rise very quickly in the first 40ms. The second way this effect shows up is that the post filter outputs have a modest overshoot, on the order of 3mV to 4mV, or 3% to 4%. This is only an issue with input frequency bursts at 50Hz or less, and even with the overshoot, the settling to a given level of accuracy improves due to the initial speedup. As predicted by Figure 6, the DC error with 2.2F is well under 1mV and is not noticeable at this scale. However, as predicted by Figure 8, the peak error with the ripple from a 10Hz input is much larger, in this case about 5mV. As can be clearly seen, the post filters reduce this ripple. Even the wider bandwidth of Figure 12's filter is seen to cut the ripple down substantially (to < 1mV) while the settling to 1% happens faster. With the narrower bandwidth of Figure 14's filter, the step response is somewhat slower, but the double frequency output ripple is just 150V. 200mV/ DIV INPUT BURST Figure 15 shows the step response of the same three cases with a burst of 60Hz rather than 10Hz. With 60Hz, the initial portion of the step response is free of the boost seen in Figure 14 and the two post-filter responses have less than 1% overshoot. The 2.2F-only case still has noticeable 120Hz ripple, but both filters have removed all detectable ripple on this scale. This is to be expected; the first order filter will reduce the ripple about 6:1 for a 6:1 change in frequency, while the third order filters will reduce the ripple about 63:1 or 216:1 for a 6:1 change in frequency. Again, the two filter topologies have the same relative shape, so the step response and ripple filtering trade-offs of the two are the same, with the same performance of each possible with the other by scaling it accordingly. Figures 16 and 17 show the peak error vs. frequency for a selection of capacitors for the two different filter topologies. To keep the clean step response, scale all three capacitors within the filter. Scaling the buffered topology of Figure 12 is simple because the capacitors are in a 10:1:10 ratio. Scaling the DC accurate topology of Figure 14 can be done with standard value capacitors; one decade of scaling is shown in Table 2. Table 2: One Decade of Capacitor Scaling for Figure 13 with EIA Standard Values CAVE C1 = C2 = 1F 0.22F 1.5F 0.33F 2.2F 0.47F 3.3F 0.68F 4.7F 1F 6.8F 1.5F 200mV/ DIV INPUT BURST 2.2F ONLY FIGURE 12 FIGURE 13 2.2F ONLY FIGURE 12 FIGURE 13 20mV/ DIV STEP RESPONSE 100ms/DIV 1967 F14 Figure 14. Step Responses with 10Hz Burst STEP RESPONSE 20mV/ DIV 100ms/DIV 1967 F15 Figure 15. Step Responses with 60Hz Burst 1967f 16 LTC1967 U W U U APPLICATIO S I FOR ATIO 0 -0.2 C = 22F PEAK ERROR (%) -0.4 -0.6 -0.8 -1.0 C = 10F C = 4.7F C = 2.2F C = 1F C = 0.47F C = 0.22F -1.2 -1.4 -1.6 -1.8 -2.0 10 INPUT FREQUENCY (Hz) 1 100 1967 F16 Figure 16. Peak Error vs Input Frequency with Buffered Post Filter 0 -0.2 C = 10F PEAK ERROR (%) -0.4 -0.6 -0.8 -1.0 C = 4.7F C = 2.2F C = 1F C = 0.47F C = 0.22F C = 0.1F -1.2 -1.4 -1.6 -1.8 -2.0 1 10 INPUT FREQUENCY (Hz) 100 1967 F17 Figure 17. Peak Error vs Input Frequency with DC-Accurate Post Filter Figures 18 and 19 show the settling time versus settling accuracy for the Buffered and DC accurate post filters, respectively. The different curves represent different scalings of the filters, as indicated by the CAVE value. These are comparable to the curves in Figure 11 (single capacitor case), with somewhat less settling time for the buffered post filter, and somewhat more settling time for the DC-accurate post filter. These differences are due to the change in overall bandwidth as mentioned earlier. Although the settling times for the post-filtered configurations shown on Figures 18 and 19 are not that much different from those with a single capacitor, the point of using a post filter is that the settling times are far better for a given level peak error. The filters dramatically reduce the low frequency averaging ripple with far less impact on settling time. Crest Factor and AC + DC Waveforms In the preceding discussion, the waveform was assumed to be AC coupled, with a modest crest factor. Both assumptions ease the requirements for the averaging capacitor. With an AC-coupled sine wave, the calculation engine squares the input, so the averaging filter that follows is required to filter twice the input frequency, making its job easier. But with a sinewave that includes DC offset, the square of the input has frequency content at the input frequency and the filter must average out that lower frequency. So with AC + DC waveforms, the required value for CAVE should be based on half of the lowest input frequency, using the same design curves presented in Figures 6, 8, 16 and 17. 1967f 17 LTC1967 U W U U APPLICATIO S I FOR ATIO 10 SETTLING ACCURACY (%) C = 220F C = 0.1F C = 0.22F C = 0.47F C = 1F C = 2.2F C = 4.7F C = 10F C = 22F C = 47F C = 100F 1 0.1 0.01 0.1 1 SETTLING TIME (SEC) 10 100 1967 F18 Figure 18. Settling Time with Buffered Post Filter 10 SETTLING ACCURACY (%) C = 220F C = 0.1F C = 0.22F C = 0.47F C = 1F C = 2.2F C = 4.7F C = 22F C = 10F C = 47F C = 100F 1 0.1 0.01 0.1 1 SETTLING TIME (SEC) 10 100 1967 F19 Figure 19. Settling Time with DC-Accurate Post Filter Crest factor, which is the peak to RMS ratio of a dynamic signal, also effects the required CAVE value. With a higher crest factor, more of the energy in the signal is concentrated into a smaller portion of the waveform, and the averaging has to ride out the long lull in signal activity. For busy waveforms, such as a sum of sine waves, ECG traces or SCR-chopped sine waves, the required value for CAVE should be based on the lowest fundamental input frequency divided as such: fDESIGN = fINPUT(MIN) 3 * CF - 2 using the same design curves presented in Figures 6, 8, 16 and 17. For the worst case of square top pulse trains, that are always either zero volts or the peak voltage, base the selection on the lowest fundamental input frequency divided by twice as much: fDESIGN = fINPUT(MIN) 6 * CF - 2 The effects of crest factor and DC offsets are cumulative. So for example, a 10% duty cycle pulse train from 0VPEAK to 1VPEAK (CF = 10 = 3.16) repeating at 16.67ms (60Hz) input is effectively only 30Hz due to the DC asymmetry and is effectively only: fDESIGN = 30 = 3.78Hz 6 * 3.16 - 2 for the purposes of Figures 6, 8, 16 and 17. Obviously, the effect of crest factor is somewhat simplified above given the factor of two difference based on a subjective description of the waveform type. The results will vary somewhat based on actual crest factor and 1967f 18 LTC1967 U W U U APPLICATIO S I FOR ATIO waveform dynamics and the type of filtering used. The above method is conservative for some cases and about right for others. The LTC1967 works well with signals whose crest factor is 4 or less. At higher crest factors, the internal modulator will saturate, and results will vary depending on the exact frequency, shape and (to a lesser extent) amplitude of the input waveform. The output voltage could be higher or lower than the actual RMS of the input signal. The modulator may also saturate when signals with crest factors less than 4 are used with insufficient averaging. This will only occur when the output droops to less than 1/4 of the input voltage peak. For instance, a DCcoupled pulse train with a crest factor of 4 has a duty cycle of 6.25% and a 1VPEAK input is 250mVRMS. If this input is 50Hz, repeating every 20ms, and CAVE = 1F, the output will droop during the inactive 93.75% of the waveform. This droop is calculated as: INACTIVE TIME - VRMS VMIN = 1- e 2 * ZOUT * CAVE 2 For the LTC1967, whose output impedance (ZOUT) is 50k, this droop works out to - 8.54%, so the output would be reduced to 229mV at the end of the inactive portion of the input. When the input signal again climbs to 1VPEAK, the peak/output ratio is 4.36. With CAVE = 10F, the droop is only - 0.929% to 247.7mV and the peak/output ratio is just 4.038, which the LTC1967 has enough margin to handle without error. For crest factors less than 3.5, the selection of CAVE as previously described should be sufficient to avoid this droop and modulator saturation effect. But with crest factors above 3.5, the droop should also be checked for each design. Error Analyses Once the RMS-to-DC conversion circuit is working, it is time to take a step back and do an analysis of the accuracy of that conversion. The LTC1967 specifications include three basic static error terms, VOOS, VIOS and GAIN. The output offset is an error that simply adds to (or subtracts from) the voltage at the output. The conversion gain of the LTC1967 is nominally 1.000 VDCOUT/VRMSIN and the gain error reflects the extent to which this conversion gain is not perfectly unity. Both of these affect the results in a fairly obvious way. Input offset on the other hand, despite its conceptual simplicity, effects the output in a nonobvious way. As its name implies, it is a constant error voltage that adds directly with the input. And it is the sum of the input and VIOS that is RMS converted. This means that the effect of VIOS is warped by the nonlinear RMS conversion. With 0.2mV (typ) VIOS, and a 200mVRMS AC input, the RMS calculation will add the DC and AC terms in an RMS fashion and the effect is negligible: VOUT = (200mV AC)2 + (0.2mV DC)2 = 200.0001mV = 200mV + 1/2ppm But with 10x less AC input, the error caused by VIOS is 100x larger: VOUT = (20mV AC)2 + (0.2mV DC)2 = 20.001mV = 20mV + 50ppm This phenomena, although small, is one source of the LTC1967's residual nonlinearity. On the other hand, if the input is DC coupled, the input offset voltage adds directly. With +200mV and a +0.2mV VIOS, a 200.2mV output will result, an error of 0.1% or 1000ppm. With DC inputs, the error caused by VIOS can be positive or negative depending if the two have the same or opposing polarity. The total conversion error with a sine wave input using the typical values of the LTC1967 static errors is computed as follows: VOUT = ((500mV AC)2 + (0.2mV DC)2) * 1.001 + 0.1mV = 500.600mV = 500mV + 0.120% VOUT = ((50mV AC)2 + (0.2mV DC)2) * 1.001 + 0.1mV = 50.150mV = 50mV + 0.301% 1967f 19 LTC1967 U W U U APPLICATIO S I FOR ATIO VOUT = ((5mV AC)2 + (0.2mV DC)2) * 1.001 + 0.1mV = 5.109mV = 5mV + 2.18% As can be seen, the gain term dominates with large inputs, while the offset terms become significant with smaller inputs. In fact, 5mV is the minimum RMS level needed to keep the LTC1967 calculation core functioning normally, so this represents the worst-case of usable input levels. Using the worst-case values of the LTC1967 static errors, the total conversion error is: VOUT = ((500mV AC)2 + (1.5mV DC)2) * 1.003 + 0.55mV = 502.05mV = 500mV + 0.41% VOUT = ((50mV AC)2 + (1.5mV DC)2) * 1.003 + 0.55mV = 50.723mV = 50mV + 1.45% VOUT = ((5mV AC)2 + (1.5mV DC)2) * 1.003 + 0.55mV = 5.786mV = 5mV + 15.7% These static error terms are in addition to dynamic error terms that depend on the input signal. See the Design Cookbook for a discussion of the DC conversion error with low frequency AC inputs. The LTC1967 bandwidth limitations cause additional errors with high frequency inputs. Another dynamic error is due to crest factor. The LTC1967 performance versus crest factor is shown in the Typical Performance Characteristics. Output Errors Versus Frequency As mentioned in the design cookbook, the LTC1967 performs very well with low frequency and very low frequency inputs, provided a large enough averaging capacitor is used. However, the LTC1967 will have additional dynamic errors as the input frequency is increased. The LTC1967 is designed for high accuracy RMS-to-DC conversion of signals beyond the audible range. The input sampling amplifiers have a - 3dB frequency of 2MHz or so. However, the switched capacitor circuitry samples the inputs at a modest 500kHz nominal. The response versus frequency is depicted in the Typical Performance Characteristics titled Input Signal Bandwidth. Although there is a pattern to the response versus frequency that repeats every sample frequency, the errors are not overwhelming. This is because LTC1967 RMS calculation is inherently wideband, operating properly with minimal oversampling, or even undersampling, using several proprietary techniques to exploit the fact that the RMS value of an aliased signal is the same as the RMS value of the original signal. However, a fundamental feature of the modulator is that sample estimation noise is shaped such that minimal noise occurs with input frequencies much less than the sampling frequency, but such noise peaks when input frequency reaches half the sampling frequency. Fortunately the LTC1967 output averaging filter greatly reduces this error, but the RMS-to-DC topology frequency shifts the noise to low (baseband) frequencies. See Output Noise vs Input Frequency in the Typical Performance Characteristics. Input Impedance The LTC1967 true RMS-to-DC converter utilizes a 0.8pF capacitor to sample the input at a nominal 500kHz sample frequency. This accounts for the 5M input impedance. See Figure 20 for the equivalent analog input circuit. Note however, that the 5M input impedance does not directly affect the input sampling accuracy. For instance, if a 62k source resistance is used to drive the LTC1967, the sampling action of the input stage will drag down the voltage seen at the input pins with small spikes at every sample clock edge as the sample capacitor is connected to be charged. The time constant of this combination is small, 0.8pF * 62k = 50ns, and during the 500ns period VDD IIN1 RSW (TYP) 2k IN1 IIN2 CEQ 0.8pF (TYP) VDD VSS VSS - VIN1 ( )AVG = VIN2REQ I IN2 RSW (TYP) 2k IN2 ( )AVG = VIN1R-EQVIN2 I IN1 REQ = 5M CEQ 0.8pF (TYP) 1967 F20 Figure 20. LTC1967 Equivalent Analog Input Circuit 1967f 20 LTC1967 U W U U APPLICATIO S I FOR ATIO devoted to sampling, ten time constants elapse. This allows each sample to settle to within 46ppm and it is these samples that are used to compute the RMS value. This is a much higher accuracy than the LTC1967 conversion limits, and far better than the accuracy computed via the simplistic resistive divider model: Output Impedance The LTC1967 output impedance during operation is similarly due to a switched capacitor action. In this case, 20pF of on-chip capacitance operating at 500kHz translates into 100k. The closed-loop RMS-to-DC calculation cuts that in half to the nominal 50k specified. In order to create a DC result, a large averaging capacitor is required. Capacitive loading and time constants are not an issue on the output. RIN RIN + RSOURCE 5M = VSOURCE 5M + 62 k = VSOURCE - 1.25% VIN = VSOURCE However, resistive loading is an issue and the 10M impedance of a DMM or 10x scope probe will drag the output down by -0.5% typ. During shutdown, the switching action is halted and a fixed 50k resistor shunts VOUT to OUT RTN so that CAVE is discharged. Interfacing with an ADC This resistive divider calculation does give the correct model of what voltage is seen at the input terminals by a parallel load averaged over a several clock cycles, which is what a large shunt capacitor will do--average the current spikes over several clock cycles. When high source impedances are used, care must be taken to minimize shunt capacitance at the LTC1967 input so as not to increase the settling time. Shunt capacitance of just 0.8pF will double the input settling time constant and the error in the above example grows from 46ppm to 0.67% (6700ppm). As a consequence, it is important to not try to filter the input with large input capacitances unless driven by a low impedance. Keep time constant << 500ns. When the LTC1967 is driven by op amp outputs, whose low DC impedance can be compromised by sharp capacitive load switching, a small series resistor may be added. A 1k resistor will easily settle with the 0.8pF input sampling capacitor to within 1ppm. These are important points to consider both during design and debug. During lab debug, and even production testing, a high value series resistor to any test point is advisable. The LTC1967 output impedance and the RMS averaging ripple need to be considered when using an analog-todigital converter (ADC) to digitize the LTC1967 RMS result. The simplest configuration is to connect the LTC1967 directly to the input of a type 7106/7136 ADC as shown in Figure 21a. These devices are designed specifically for DVM/DPM use and include display drivers for a 3 1/2 digit LCD segmented display. Using a dual-slope conversion, the input is sampled over a long integration window, which results in rejection of line frequency ripple when integration time is an integer number of line cycles. Finally, these parts have an input impedance in the G range, with specified input leakage of 10pA to 20pA. Such a leakage, combined with the LTC1967 output impedance, results in just 1V to 2V of additional output offset voltage. Another type of ADC that has inherent rejection of RMS averaging ripple is an oversampling ADC such as the LTC2420. Its input impedance is 6.5M, but only when it is sampling. Since this occurs only half the time at most, if it directly loads the LTC1967, a gain error of -0.32% to -0.43% results. In fact, the LTC2420 DC input current is 1967f 21 LTC1967 U W U U APPLICATIO S I FOR ATIO LTC1967 OUTPUT OUT RTN 7106 TYPE 5 31 6 CAVE 30 IN HI IN LO 1967 F21a Figure 21a. Interfacing to DVM/DPM ADC LTC1967 OUTPUT OUT RTN LTC2420 5 6 3 CAVE 4 VIN SDO GND SCK CS 1967 F21b SERIAL DATA DIGITALLY CORRECT LOADING ERRORS Figure 21b. Interfacing to LTC2420 not zero at 0V, but rather at one half its reference, so both an output offset and a gain error will result. These errors will vary from part to part, but with a specific LTC1967 and LTC2420 combination, the errors will be fixed, varying less than 0.05% over temperature. So a system that has digital calibration can be quite accurate despite the nominal gain and offset error. With 20 bits of resolution, this part is more accurate than the LTC1967, but the extra resolution is helpful because it reduces nonlinearity at the LSB transitions as a digital gain correction is made. Furthermore, its small size and ease of use make it attractive. This connection is shown in Figure 21b, where the LTC2420 is set to continuously convert by grounding the CS pin. The gain error will be less if CS is driven at a slower rate, however, the rate should either be consistent or at a rate low enough that the LTC1967 and its output capacitor have fully settled by the beginning of each conversion, so that the loading errors are consistent. Other types of ADCs sample the input signal once and perform a conversion on that one sample. With these ADCs (Nyquist ADCs), a post filter will be needed in most cases to reduce the peak error with low input frequencies. The DC-accurate filter of Figure 13 is attractive from an error standpoint, but it increases the impedance at the ADC input. In most cases, the buffered post filter of Figure 12 will be more appropriate for use with Nyquist analog-todigital converters. SYSTEM CALIBRATION The LTC1967 static accuracy can be improved with endsystem calibration. Traditionally, calibration has been done at the factory, or at a service depot only, typically using manually adjusted potentiometers. Increasingly, systems are being designed for electronic calibration where the accuracy corrections are implemented in digital code wherever possible, and with calibration DACs where necessary. Additionally, many systems are now designed for self calibration, in which the calibration occurs inside the machine, automatically without user intervention. Whatever calibration scheme is used, the linearity of the LTC1967 will improve the calibrated accuracy over that achievable with older log/antilog RMS-to-DC converters. Additionally, calibration using DC reference voltages are essentially as accurate with the LTC1967 as those using AC reference voltages. Older log/antilog RMS-to-DC converters required nonlinear input stages (rectifiers) whose linearity would typically render DC-based calibration unworkable. The following are four suggested calibration methods. Implementations of the suggested adjustments are dependent on the system design, but in many cases, gain and output offset can be corrected in the digital domain, and will include the effect of all gains and offsets from the LTC1967 output through the ADC. Input offset voltage, on the other hand, will have to be corrected with adjustment to the actual analog input to the LTC1967. AC-Only, 1 Point The dominant error at full scale will be caused by the gain error, and by applying a full-scale sine wave input, this error can be measured and corrected for. Unlike older log/ antilog RMS-to-DC converters, the correction should be made for zero error at full scale to minimize errors throughout the dynamic range. The best frequency for the calibration signal is roughly ten times the -0.1% DC error frequency. For 1F, -0.1% DC error occurs at 10Hz, so 100Hz is a good calibration frequency, although anywhere from 60Hz to 100Hz should suffice. 1967f 22 LTC1967 U W U U APPLICATIO S I FOR ATIO The trade-off here is that on the one hand, the DC error is input frequency dependent, so a calibration signal frequency high enough to make the DC error negligible should be used. On the other hand, as low a frequency as can be used is best to avoid attenuation of the calibrated AC signal, either from parasitic RC loading or insufficient op amp gain. For instance, with a 1kHz calibration signal, a 1MHz op amp will typically only have 60dB of open-loop gain, so it could attenuate the calibration signal a full 0.1%. AC-Only, 2 Point The next most significant error for AC-coupled applications will be the effect of output offset voltage, noticeable at the bottom end of the input scale. This too can be calibrated out if two measurements are made, one with a full-scale sine wave input and a second with a sine wave input (of the same frequency) at 10% of full scale. The trade-off in selecting this second level is that it should be small enough that the gain error effect becomes small compared to the gain error effect at full scale, while on the other hand, not using so small an input that the input offset voltage becomes an issue. The calculations of the error terms for a 200mV full-scale case are: Gain = Reading at 200mV - Reading at 20mV 180mV Output Offset = Reading at 20mV - 20mV Gain DC, 2 Point DC-based calibration is preferable in many cases because a DC voltage of known, good accuracy is easier to generate than such an AC calibration voltage. The only down side is that the LTC1967 input offset voltage plays a role. It is therefore suggested that a DC-based calibration scheme check at least two points: full scale. Applying the -full-scale input can be done by physically inverting the voltage or by applying the same +full-scale input to the opposite LTC1967 input. For an otherwise AC-coupled application, only the gain term may be worth correcting for, but for DC-coupled applications, the input offset voltage can also be calculated and corrected for. The calculations of the error terms for a 200mV full-scale case are: Gain = Reading at 200mV + Reading at - 200mV 400mV Input Offset = Reading at - 200mV - Reading at 200mV 2 *Gain Note: Calculation of and correction for input offset voltage are the only way in which the two LTC1967 inputs (IN1, IN2) are distinguishable from each other. The calculation above assumes the standard definition of offset; that a positive offset is the case of a positive voltage error inside the device that must be corrected by applying a like negative voltage outside. The offset is referred to whichever pin is driven positive for the +full-scale reading. DC, 3 Point One more point is needed with a DC calibration scheme to determine output offset voltage: +10% of full scale. The calculation of the input offset is the same as for the 2-point calibration above, while the gain and output offset are calculated for a 200mV full-scale case as: Gain = Reading at 200mV - Reading at 20mV 180mV Output Offset = Reading at 200mV +Reading at - 200mV - 400mV * Gain 2 1967f 23 LTC1967 U W U U APPLICATIO S I FOR ATIO TROUBLESHOOTING GUIDE Top Ten LTC1967 Application Mistakes 1. Circuit won't work-Dead On Arrival-no power drawn. - Probably forgot to enable the LTC1967 by pulling Pin 8 low. 4. Gain is low by a few percent, along with other screwy results. - Probably tried to use output in a floating, differential manner. Solution: Tie Pin 6 to a low impedance. See "Output Connections" in the Design Cookbook. Solution: Tie Pin 8 to Pin 1. GROUND PIN 6 2. Circuit won't work, but draws power. Zero or very little output, single-ended input application. - Probably didn't connect both input pins. Solution: Tie both inputs to something. See "Input Connections" in the Design Cookbook. IN1 3 OUT RTN 5 31 6 30 TYPE 7136 ADC HI LO 5. Offsets perceived to be out of specification because 0V in 0V out. - The offsets are not specified at 0V in. No RMS-toDC converter works well at 0 due to a divide-by-zero calculation. LTC1967 NC VOUT 1967 TS04 CONNECT PIN 3 2 LTC1967 IN2 1967TS02 3. Screwy results, particularly with respect to linearity or high crest factors; differential input application. - Probably AC-coupled both input pins. Solution: Make at least one input DC-coupled. See "Input Connections" in the Design Cookbook. DC-COUPLE ONE INPUT 2 DC-CONNECT ONE INPUT 2 IN1 LTC1967 3 IN2 Solution: Measure VIOS/VOOS by extrapolating readings > 5mVDC. 6. Linearity perceived to be out of specification particularly with small input signals. - This could again be due to using 0V in as one of the measurement points. Solution: Check Linearity from 5mV RMS to 500mVRMS. - The input offset voltage can cause small AC linear ityerrors at low input amplitudes as well. See "Error Analyses" section. IN1 Possible Solution: Include a trim for input offset. LTC1967 3 IN2 1967 TS03 1967f 24 LTC1967 U W U U APPLICATIO S I FOR ATIO 7. Output is noisy with >50kHz inputs. - This is a fundamental characteristic of this topology. The LTC1967 is designed to work very well with inputs of 20kHz or less. It works okay as high as 1MHz, but it is limited by aliased noise. Solution: Bandwidth limit the input or digitally filter the resulting output. 8. Large errors occur at crest factors approaching, but less than 4. - Insufficient averaging. Solution: Increase CAVE. See "Crest Factor and AC + DC Waveforms" section for discussion of output droop. 10. Gain is low by 1% or more, no other problems. - Probably due to circuit loading. With a DMM or a 10x scope probe, ZIN = 10M. The LTC1967 output is 50k, resulting in - 0.5% gain error. Output impedance is higher with the DC accurate post filter. Solution: Remove the shunt loading or buffer the output. - Loading can also be caused by cheap averaging capacitors. Solution: Use a high quality metal film capacitor for CAVE. LOADING DRAGS DOWN GAIN 9. Screwy results, errors > spec limits, typically 1% to 5%. - High impedance (50k) and high accuracy (0.1%) require clean boards! Flux residue, finger grime, etc. all wreak havoc at this level. LTC1967 Solution: Wash the board. VOUT KEEP BOARD CLEAN mV 5 50k OUT RTN 6 DCV 10M DMM 200mVRMS IN -0.5% LTC1967 1967 TS10 1967 TS09 1967f 25 LTC1967 W W SI PLIFIED SCHE ATIC V+ C12 GND C1 Y1 Y2 C2 IN1 2nd ORDER MODULATOR IN2 C3 C5 C7 + C9 + A1 - C4 OUTPUT C8 CAVE C11 A2 - OUT RTN 1967 SS C6 C10 CLOSED DURING SHUTDOWN EN TO BIAS CONTROL 50k BLEED RESISTOR FOR CAVE U TYPICAL APPLICATIO S Single Supply RMS Current Measurement 5V Single Supply, Differential, AC-Coupled RMS-to-DC Converter V+ 5V V+ LTC1967 AC INPUTS (1VPEAK DIFFERENTIAL) IN1 VOUT IN2 OUT RTN CC 0.1F GND CAVE 1F DC OUTPUT AC CURRENT 75A MAX 50Hz TO 400Hz T1 IN1 LTC1967 VOUT 10 IN2 OUT RTN 20k EN GND CAVE 1F VOUT = 4mVDC/ARMS EN 1967 TA03 1967 TA02 0.1F 20k T1: CR MAGNETICS CR8348-2500-N www.crmagnetics.com 1967f 26 LTC1967 U TYPICAL APPLICATIO S 2.5V Supplies, Single Ended, DC-Coupled RMS-to-DC Converter with Shutdown 0.1F X7R 2.5V 2V OFF ON 2.5V VOLTAGE NOISE IN -2.5V -2V 2.5V 100 LTC1967 IN1 V+ + V+ EN DC + AC INPUT (1VPEAK) RMS Noise Measurement VOUT CAVE 1F IN2 OUT RTN LTC1967 1k 1/2 LTC6203 GND -2.5V 100 -2.5V EN 0.1F 100k 1mVDC 1VRMS NOISE CAVE 1F IN2 OUT RTN GND 1967 TA04 VOUT IN1 - DC OUTPUT VOUT = 1967 TA05 -2.5V BW 1kHz TO 100kHz INPUT SENSITIVITY = 1VRMS TYP 1.5F U PACKAGE DESCRIPTIO MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 0.889 0.127 (.035 .005) 5.23 (.206) MIN 3.20 - 3.45 (.126 - .136) 0.42 0.038 (.0165 .0015) TYP 3.00 0.102 (.118 .004) (NOTE 3) 0.65 (.0256) BSC 8 7 6 5 0.52 (.0205) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 0.102 (.118 .004) (NOTE 4) 4.90 0.152 (.193 .006) DETAIL "A" 0 - 6 TYP GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL "A" 1 2 3 4 1.10 (.043) MAX 0.86 (.034) REF 0.18 (.007) SEATING PLANE 0.22 - 0.38 (.009 - .015) TYP 0.65 (.0256) NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.127 0.076 (.005 .003) MSOP (MS8) 0204 1967f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LTC1967 U TYPICAL APPLICATIO Audio Amplitude Compressor R5 5.9k ATTENUATE BY 1/4 V+ LT1256 R2 1k VIN R1 100k C2 0.47F R3 7.5k 2 - 1 + 9 A1 R4 2.49k C1 47nF 14 7 A2 13 - ATTENUATION CONTROL R9 10k R6 2k VOUT + GAIN OF 4 R8 15k R15 47 8 V- V + VC RC 3 5 RFS 10 VFS R13 3.3k 12 R14 3.3k C3 0.1F R7 5.9k V+ V+ - + V- VDD R10 200k LT1636 C5 0.22F C4 0.33F LTC1967 IN1 VOUT OUT RTN IN2 GND EN R12 10k 0.1F VS = 5V 1967 TA07 RELATED PARTS PART NUMBER (R) DESCRIPTION COMMENTS LT 1077 Micropower, Single Supply Precision Op Amp 48A ISY, 60V VOS(MAX), 450pA IOS(MAX) LT1175-5 Negative, -5V Fixed, Micropower LDO Regulator 45A IQ, Available in SO-8 or SOT-223 LT1494 1.5A Max, Precision Rail-to-Rail I/O Op Amp 375V VOS(MAX), 100pA IOS(MAX) LT1782 General Purpose SOT-23 Rail-to-Rail Op Amp 40A ISY, 800V VOS(MAX), 2nA IOS(MAX) LT1880 SOT-23 Rail-to-Rail Output Precision Op Amp 1.2mA ISY, 150V VOS(MAX), 900pA IOS(MAX) LTC2054 Zero Drift Op Amp in SOT-23 150A ISY, 3V VOS(MAX), 150pA IB(MAX) LT2178/LT2178A 17A Max, Single Supply Precision Dual Op Amp 14A ISY, 120V VOS(MAX), 350pA IOS(MAX) LTC1966 Precision Micropower RMS-to-DC Converter 155A ISY LTC2402 2-Channel, 24-bit, Micropower, No Latency TM ADC 200A ISY, 4ppm INL, 10ppm TUE LTC2420 20-bit, Micropower, No Latency ADC in SO-8 200A ISY, 8ppm INL, 16ppm TUE LTC2422 2-Channel, 20-bit, Micropower, No Latency ADC Dual channel version of LTC2420 No Latency is a trademark of Linear Technology Corporation. 1967f 28 Linear Technology Corporation LT/TP 0504 1K * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2004