XC17S200XLSOG20I - Xilinx, Inc. - Datasheet.Directory

DS030 (v1.5) April 4, 2000 1

Introduction

The Spartan™ family of PROMs provide an easy-to-use,

cost-effective method for storing Spartan device configura-

tion bitstreams.

When the Spartan device is in Master Serial mode, it gen -

erates a configuration clock that drives the Spartan PROM.

A short access time after the rising clock edge, data

appears on the PROM DA T A output pin that is connected to

the Spartan device DIN pin. The Spartan device generates

the appropriate number of clock pulses to complete the

configuration. Once configured, it disables the PROM.

When a Spartan device is in Slave Serial mode, the PROM

and the Spartan device must both be clocked by an incom-

ing signal.

For device programming, either the Xilinx Alliance or the

Foundation series development systems compiles the

Spartan device design file into a standard HEX format

which is then transferred to most commercial PROM pro-

grammers.

Spartan PR OM Features

•Configuration one-time programmable (OTP) read-only

memory designed to store configuration bitstreams for

Spartan, Spartan-XL, and S partan-II FPGA devices

•Simple interface to the Spartan device requires only

one user I/O pin

•Programmable reset polarity (active High or active Low)

•Low-power CMOS floating gate process

•Available in 5V and 3.3V versions

•Available in compact plastic 8-pin DIP, 8-pin VOIC, or

20-pin SOIC (XC17S40 only) packages.

•Programming support by leading programmer

manufacturers.

•Design support using the Xilinx Alliance and

Foundation series software packages.

Spartan Fam i ly of PROMs

DS030 (v1.5) April 4, 2000 05*

Product Specification

Spartan FPGA Configuration Bits Compatible Spartan PROM

XCS05 53,984 XC17S05

XCS05XL 54,544 XC17S05XL

XCS10 95,008 XC17S10

XCS10XL 95,752 XC17S10XL

XC2S15 197,728 XC17S15XL

XCS20 178,144 XC17S20

XCS20XL 179,160 XC17S20XL

XCS30 247,968 XC17S30

XCS30XL 249,168 XC17S30XL

XC2S30 336,768 XC17S30XL

XCS40 329,312 XC17S40

XCS40XL 330,696 XC17S40XL

XC2S50 559,232 XC17S50XL

XC2S100 781,248 XC17S100XL

XC2S150 1,040,128 XC17S150XL

XC2S200 1,335,872 XC17S200XL

Sp art an Fami l y of PROMs

2DS030 (v1.5) April 4, 2000

Pin Description

Table 1: Spartan PROM Pinouts

Pin Name 8-pin

PDIP & VOIC 20-pin

SOIC Pin Description

DATA 1 1 Data output, 3-stated when either CE or OE are inactive. During pro-

gramming, the DATA pin is I/O. Note that OE can be programmed to

be either active High or active Low.

CLK 2 3 Each rising edge on the CLK input increments the internal address

counter, if both CE and OE are active.

RESET/OE

(OE/RESET)38

When High, this input holds the address counter reset and 3-states

the DATA output. The polarity of this input pin i s pr ogrammable as ei-

ther RESET/O E or OE/RESET. To avoid confusion, this document

describes the pin as RESET/OE, although the opposite polarity is

possible on all devices. When RESET is active, the address counter

is held at zero, and the DATA output is 3-stated. The polarity of this

input is programmable. The default is active High RESET, but the

preferred option is active Low RE SET , because it can be driven by

the FPGAs INIT pin.

The polarity of this pin is controlled in the programmer interface. This

input pin is easily inverted using the Xilinx HW-130 programmer soft-

ware. Third-party programmers have different methods to inver t this

pin.

CE 4 10 When High, this pin disables the internal address counter, 3-states

the DATA output, and forces the device into low-ICC standby mode.

GND 5 11 GND is the ground connection.

VCC 7, 8 18, 20 The VCC pins are to be connected to the positive voltage supply.

DS030 (v1.5) April 4, 2000 3

Sparta n Family of PR OMs

Co nt rol ling P R OMs

Connecting the Spartan device with the PROM:

•The DATA output of the PROM drives the DIN input of

the lead Spartan device.

•The Master Spartan device CCLK output drives the

CLK input of the P ROM .

•The RESET/OE input of the PROM is driven by the INIT

output of the Spartan device. This connection assures

that the PROM address counter is reset befor e the start

of any (re)configuration, even when a reconfiguration is

initiated by a VCC glitch. Other methods – such as

driving RESET/OE from LDC or system reset – assume

that the PROM internal power-on-reset is always in step

with the FPGA’s internal power-on-reset, which may not

be a safe assumption.

•The CE input of the PROM is driven by the DONE

output of the Spartan device, provided that DONE is not

permanently grounded. Otherwise, LDC can be used to

drive CE, but m ust then be unconditionally High during

user operation. CE can also be permanently tied Low,

but this keeps the DATA output active and causes an

unnecessary supply current of 10 mA maximum.

FPG A Master Serial Mode Summary

The I/O and logic functions of the Configurable Logic Block

(CLB) and their associated interconnections are estab-

lished by a configuration program. The program is loaded

either automatically upon power up, or on command,

depending on the state of the Spartan device MODE pin. In

Master Serial mode, the Spartan device automatically

loads the configuration progr am from an external memory.

The Spartan PROM has been designed for compatibility

with the Master Serial mode.

Upon power-up or reconfiguration, the Spartan device

enters the Master Serial mode when the MODE pin is Low.

Data is read from the PROM sequentially on a single data

line. Synchronization is provided by the rising edge of the

temporary signal CCLK, which is generated during confi gu-

ration.

Master Serial mode provides a simple configuration inter-

face. Only a serial data line and two control lines are

required to configure the Spartan device. Data from the

PROM is read sequentially, accessed via the internal

address and bit counters which are incremented on every

valid rising edge of CCLK .

If the user-programmable, dual-function DIN pin on the

Spartan device i s used only for configur ation, it must stil l be

held at a defined level during normal operation. The Spar -

tan family takes care of this automatically with an on-chip

default pull-up resistor.

Prog r am mi n g the F PG A Wi th Counte r s

Unc hange d Up on Completion

When multiple-configurations for a single Spartan device

are stored in a PROM, the OE pin should be tied Low . Upon

power-up, the internal address counters are reset and con-

figuration begins with the first program stored in memory.

Since the OE pin is held Low, the address counters are left

unchanged after configuration is complete. Therefore, to

reprogram the FPGA with another program, the DONE line

is pulled Low and configuration begins at the last value of

the address counters.

This method fails if a user applies RESET during the Spar-

tan device configuration process. The Spartan device

aborts the configuration and then restarts a new configura-

tion, as intended, but the PROM does not reset its address

counter , since it never saw a High level on its OE input. The

new configuration, therefore, reads the remaining data in

the PR OM an d interprets it as pr eamble, length count etc.

Since the Spartan device is the Master, it issues the neces-

sary number of CCLK pulses, up to 16 million (224) and

DONE g oes High. However, the Spartan device configura-

tion will be completely wrong, with potential contentions

inside the Spartan device and on its output pins. This

method must, therefore, never be used when there is any

chance of external reset during configuration.

Sp art an Fami l y of PROMs

4DS030 (v1.5) April 4, 2000

Figure 1: Master Serial Mode. The one-time-programmable Spartan PROM supports automatic loading of con figuration

programs. An ear ly DO NE inhib its the PROM data output one CCLK cycle before the Spartan FPGA I/Os become active.

DIN

CCLK

INIT

DONE Spartan

PROM

DATA

3.3V

CLK

Spartan

Master Serial

(Low Resets the Address Pointer)

DS030_01_040400

CCLK

(Output)

DIN

DOUT

(Output)

OE/RESET

MODE 4.7K

VCC

VCC VPP

DS030 (v1.5) April 4, 2000 5

Sparta n Family of PR OMs

Standby Mode

The PROM enters a low-power standby mode whenever

CE is asserted High. The output remains in a high imped-

ance state regardless of the state of the OE input.

Progr am ming the Spartan Fam i ly

PROMs

The devices can be programmed on programmers suppli ed

by Xilinx or qualified third-party vendors. The user must

ensure that the appropriate pr ogramming algorithm and the

latest version of the programmer software are used. The

wrong choice can permanently damage the device.

Important: Always tie the two VCC pins together in your application.

Notes: 1. The XC17S00 RESET inpu t has progra mmable polarity

2. TC = Terminal Count = highest address value. TC+1 = address 0.

Figure 2: Simplified Block Diagram (does not show program m ing circuit)

Table 2: Truth Table for XC17S00 Con trol Inputs

Control Inputs Internal A ddress Outputs

RESET CE DATA Icc

Inactive Low If address < TC: increment

If address > TC: don’t change Active

3-state Active

Reduced

Active Low Held reset 3-state Active

Inactive High Not chang ing 3-state Standby

Active High Held reset 3-state Standby

EPROM

Cell

Matrix

Address Counter

DATA

Output

CLK

VCC GND

DS030_02_011300

RESET/

OE/

RESET

Sp art an Fami l y of PROMs

6DS030 (v1.5) April 4, 2000

XC17S05, XC17S10, XC17S20, XC17S30, XC17S40

Absolute Maximum Ratings

Note: Stresses beyon d tho se l iste d under Abso lu te Max imum Rat i ngs m ay cause permanent dam age to the dev ic e. These ar e

stre ss ra ting s onl y, and func tional opera tion of the device at these or any other conditions beyo nd th ose listed under

Oper atin g C ondit io ns i s not impl i ed. Exposure to Absolut e Ma xi mu m Ra tings condi ti ons f or ex te nded period s of time may

affect device reliabi lit y.

O peratin g Conditi ons

Note: Durin g nor ma l read opera tion bo th VCC pins mus t be co nnec te d to get her.

DC Characteristics Over Operating Conditio n

Symbol Description Value Units

VCC Supply voltage relative to GND –0 .5 to +7.0 V

VIN Input voltage relative to GND –0.5 to VCC +0.5 V

VTS Voltage applied to 3-state output –0.5 to VCC +0.5 V

TSTG Storage tempe rature (ambient) –65 to +150 °C

TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 °C

Symbol Description Min Max Units

VCC Commercial Supply voltage relative to GND (TA = 0°C to +70°C) 4.75 5.25 V

Industrial Supply voltage relative to GND (TA = –40°C to +85°C) 4.50 5.50 V

Symbol Description Min Max Units

VIH High-level input voltage 2.0 VCC V

VIL Low-level input voltage 0 0.8 V

VOH High-level output voltage (IOH = –4 mA) Commercial 3.86 V

VOL Low-level output voltage (IOL = +4 mA) 0.32 V

VOH High-level output voltage (IOH = –4 mA) Industrial 3.76 V

VOL Low-level output voltage (IOL = +4 mA) 0.37 V

ICCA Supply current, active mode (at maximum frequency) 10.0 mA

ICCS Supply current, standby mode XC 17S05, XC17S10,

XC17S20, XC17S30 50.0 µA

XC17S40 100.0 µA

ILInput or output leakage current –10.0 10.0 µA

CIN Input Capacitance (VIN = GND, f = 1.0 MHz) 10.0 pF

COUT Output Capacitance (VIN = G ND, f = 1.0 MHz) 10.0 pF

DS030 (v1.5) April 4, 2000 7

Sparta n Family of PR OMs

XC17S 05XL, XC1 7S10XL, XC17S15X L, XC17S 20XL, XC17S30X L,

XC17S 40XL, XC1 7S50XL, XC17S 100XL, XC17S150XL , XC17S200XL

Absolute Maximum Ratings

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings onl y, and f unctiona l op era tion of the devi ce at these or any othe r con di tions beyond th ose list ed unde r O per at ing

Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device

reliability.

O peratin g Conditi ons

Note: Durin g nor ma l read opera tion bo th VCC pins mus t be co nnec te d to get her.

DC Characteristics Over Operating Conditio n

Symbol Description Value Units

VCC Supply voltage relative to GND –0.5 to +4.0 V

VIN Input voltage with respect to G ND –0.5 to VCC +0.5 V

VTS Voltage applied to 3-state output –0.5 to VCC +0.5 V

TSTG Storage temperature (ambient) –65 to +150 °C

TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 °C

Symbol Description Min Max Units

VCC Commercial Supply voltage relative to GND (TA = 0°C to +70°C) 3.0 3.6 V

Industrial Supply voltage relative to GND (TA = –40°C to +85°C) 3.0 3.6 V

Symbol Description Min Max Units

VIH High-level input voltage 2.0 VCC V

VIL Low-level input voltage 0 0.8 V

VOH High-level output voltage (IOH = –3 mA) 2.4 V

VOL Low-level output voltage (IOL = +3 mA) 0.4 V

ICCA Supply current, active mode (at maximum frequency) 5.0 mA

ICCS Supply current, standby mode 50.0 µA

ILInput or output leakage current –10.0 10.0 µA

CIN Input Capacitance (VIN = GND, f = 1.0 MHz) 10.0 pF

COUT Output Capacitance (VIN = G ND, f = 1.0 MHz) 10.0 pF

Sp art an Fami l y of PROMs

8DS030 (v1.5) April 4, 2000

AC Characteristics Over Operating Conditio n

Notes: 1. AC test load = 50 pF

2. Guarant eed by des ign , no t test ed.

3. Float del ays are m eas ured with 5 pF AC lo ads. Transi tion is measured at ±200 m V from ste ady st ate act i ve l eve ls .

4. All AC par am et er s are mea sur ed wi th VIL = 0.0V and VIH = 3.0V.

RESET/OE

CLK

DATA TCE

TOE

TLC

TSCE TSCE THCE

THOE

TCAC TOH TDF

TOH

THC

DS0306_03_011300

TCYC

Symbol Description Min Max Units

TOE RESET/OE to Data Delay 45 ns

TCE CE to Data Delay 60 ns

TCAC CLK to Data Delay 80 ns

TOH Data Hold From CE, RESET/ OE, or CLK(2) 0ns

TDF CE or RESET/OE to Data Float Delay(2,3) 50 ns

TCYC Clock Per iods 100 ns

TLC CLK Low Tim e (2) 50 ns

THC CLK High Time(2) 50 ns

TSCE CE Setup Time to CLK (to guarantee proper counting) 25 ns

THCE CE Hold Time to CLK (to guarantee proper counting) 0 ns

THOE RESET/OE Hold Time (guaran tees counte rs are reset) 25 ns

DS030 (v1.5) April 4, 2000 9

Sparta n Family of PR OMs

O rdering In f ormat io n

Vali d Or d e rin g Combina tions

* In development

Spartan 5V Spar tan 5V Spartan 3.3V Spartan 3.3V Spa rtan3.3V

XC17S05PD8C XC17S20PD8C XC17S05XLPD8C XC17S20XLPD8C XC17S50XLPD8C

XC17S05VO8C XC17S20VO8C XC17S05XLVO8C XC17S20XLVO8C XC17S50XLSO20C

XC17S05PD8I XC17S20PD8I XC17S05XLPD8I XC17S20XLPD8I XC17S50XLPD8I

XC17S05VO8I XC17S20VO8I XC17S05XLVO8I XC17S20XLVO8I XC17S50XLSO20I

XC17S10PD8C XC17S30PD8C XC17S10XLPD8C XC17S30XLPD8C XC17S100XLPD8C

XC17S10VO8C XC17S30VO8C XC17S10XLVO8C XC17S30XLVO8C XC17S100XLSO20C

XC17S10PD8I XC17S30PD8I XC17S10XLPD8I XC17S30XLPD8I XC17S100XLPD8I

XC17S10VO8I XC17S30VO8I XC17S10XLVO8I XC17S30XLVO8I XC17S100XLSO20I

XC17S40PD8C XC17S15XLPD8C XC17S40XLPD8C XC17S150XLPD8C

XC17S40SO20C XC17S15XLVO8C XC17S40XLSO20C XC17S150XLSO20C

XC17S40PD8I XC17S15XLPD8I XC17S40XLVO8C* XC17S150XLPD8I

XC17S40SO20I XC17S15XLVO8I XC17S40XLPD8I XC17S150XLSO20I

XC17S40XLSO20I

XC17S40XLVO8I* XC17S200XLPD8C

XC17S200XLSO20C

XC17S200XLPD8I

XC17S200XLSO20I

XC17S20XL VO8 C

Operating Range/Processing

C=Commercial (TA = 0°C to +70 °C)

I = Industrial (TA = –40°C to + 8 5 °C)

Package Type

PD 8 = 8-pin Pla s ti c DIP

VO8 = 8-pin Plas tic S m all -Out l ine Thi n P ack age

SO20 = 20- pi n P last ic Smal l-Outline P ac kage

Device Number

XC17S05

XC17S05XL

XC17S10

XC17S10XL

XC17S15XL

XC17S20

XC17S20XL

XC17S30

XC17S30XL

XC17S40

XC17S40XL

XC17S50XL

XC17S100XL

XC17S150XL

XC17S200XL

Sp art an Fami l y of PROMs

10 DS030 (v1.5) April 4, 2000

Marki ng In form atio n

Due to the small size of the PROM package, the complete ordering part number cannot be marked on the package. The XC

prefix is deleted and the package code is simplified. Device marking is as follows.

Note: When mar king the de vice num ber on the X L par t s, an L is us ed in plac e of an XL.

Revision Contro l

Date Revision Revision

7/14/98 1.1 Cosmetic edits for pages 1, 2, 3 & 4.

9/8/98 1.2 Clarified the SPARTA N FPGA and PR OM interface by removing references to CEO pin. Re-

moved the ESD notation in Absolute Maximum table since it is now included in Xilinx’s Reliability

Monitor Report.

01/20/00 1.3 Added additional Spartan-XL parts, changed SPROM to P ROM .

02/18/00 1.4 Changed device ordering numbers, added 4.7K resistor to OE/RES ET in Figure 1.

04/04/00 1.5 Added X C17S200XL PROM for Spartan XC2S200.

17S20L V C

Operating Rang e/Processing

C = Commercial (TA = 0 °C to +70°C)

I = Industrial (TA = –40°C to +85°C)Package Type

P = 8-pin Plast ic DIP

V = 8-pin Plast ic S ma ll-O utline Thi n Package

S = 20-pin Pl ast ic S m al l-O ut line Pa ckage

Device Number

XC17S05

XC17S05L

XC17S10

XC17S10L

XC17S15L

XC17S20

XC17S20L

XC17S30

XC17S30L

XC17S40

XC17S40L

XC17S50L

XC17S100L

XC17S150L

XC17S200L