DA14580-01UNA - Dialog Semiconductor

DA14580 Low Power Bluetooth Smart SoC

DATASHEET -

General description

The DA14580 integrated circuit has a fully integrated

radio transceiver and baseband processor for Blue-

tooth® Smart. It can be used as a standalone applica-

tion processor or as a data pump in hosted systems.

The DA14580 supports a flexible memory architecture

for storing Bluetooth profiles and custom application

code, which can be updated over the air (OTA). The

qualified Bluetooth Smart protocol stack is stored in a

dedicated ROM. All software runs on the ARM® Cor-

tex®-M0 processor via a simple scheduler.

The Bluetooth Smart firmware includes the L2CAP ser-

vice layer protocols, Security Manager (SM), Attribute

Protocol (ATT), the Generic Attribute Profile (GATT)

and the Generic Access Profile (GAP). All profiles pub-

lished by the Bluetooth SIG as well as custom profiles

are supported.

The transceiver interfaces directly to the antenna and

is fully compliant with the Bluetooth 4.1 standard.

The DA14580 has dedicated hardware for the Link

Layer implementation of Bluetooth Smart and interface

controllers for enhanced connectivity capabilities.

Features

Complies with Bluetooth V4.1, ETSI EN 300 328 and

EN 300 440 Class 2 (Europe), FCC CFR47 Part 15

(US) and ARIB STD-T66 (Japan)

Processing power

16 MHz 32 bit ARM Cortex-M0 with SWD inter-

face

Dedicated Link Layer Processor

AES-128 bit encryption Processor

Memories

32 kB One-Time-Programmable (OTP) memory

42 kB System SRAM

84 kB ROM

8 kB Retention SRAM

Power management

Integrated Buck/Boost DC-DC converter

P0, P1, P2 and P3 ports with 3.3 V tolerance

Easy decoupling of only 4 supply pins

Supports coin (typ. 3.0 V) and alkaline (typ. 1.5 V)

battery cells

10-bit ADC for battery voltage measurement

Digital controlled oscillators

16 MHz crystal (±20 ppm max) and RC oscillator

32 kHz crystal (±50 ppm, ±500 ppm max) and

RCX oscillator

General purpose, Capture and Sleep timers

Digital interfaces

General purpose I/Os: 14 (WLCSP34 package),

24 (QFN40 package), 32 (QFN48 package)

2 UARTs with hardware flow control up to 1 MBd

SPI+™ interface

I2C bus at 100 kHz, 400 kHz

3-axes capable Quadrature Decoder

Analog interfaces

4-channel 10-bit ADC

Radio transceiver

Fully integrated 2.4 GHz CMOS transceiver

Single wire antenna: no RF matching or RX/TX

switching required

Supply current at VBAT3V:

TX: 3.4 mA, RX: 3.7 mA (with ideal DC-DC)

0 dBm transmit output power

-20 dBm output power in “Near Field Mode”

-93 dBm receiver sensitivity

Packages:

WLCSP 34 pins, 2.436 mm x 2.436 mm

QFN 40 pins, 5 mm x 5 mm

QFN 48 pins, 6 mm x 6 mm

KGD (wafer, dice)

________________________________________________________________________________________________

System diagram

JANUARY 29, 2015 V3.1

DA14580

Low Power Bluetooth Smart SoC

FINAL

DA14580 Low Power Bluetooth Smart SoC

1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3. System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1 ARM CORTEXM0 CPU . . . . . . . . . . . . . . . . . . 9

3.2 BLUETOOTH SMART. . . . . . . . . . . . . . . . . . . . 9

3.2.1 BLE Core . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.2.2 Radio Transceiver . . . . . . . . . . . . . . . . . 10

3.2.3 SmartSnippets  

3.3 MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.4 FUNCTIONAL MODES . . . . . . . . . . . . . . . . . . 11

3.5 POWER MODES. . . . . . . . . . . . . . . . . . . . . . . 12

3.6 INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.6.1 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.6.2 SPI+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.6.3 I2C interface . . . . . . . . . . . . . . . . . . . . . 12

3.6.4 General purpose ADC . . . . . . . . . . . . . . 13

3.6.5 Quadrature decoder. . . . . . . . . . . . . . . . 13

3.6.6 Keyboard controller . . . . . . . . . . . . . . . . 13

3.6.7 Input/output ports . . . . . . . . . . . . . . . . . . 13

3.7 TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.7.1 General purpose timers . . . . . . . . . . . . . 13

3.7.2 Wake-Up timer . . . . . . . . . . . . . . . . . . . . 14

3.7.3 Watchdog timer . . . . . . . . . . . . . . . . . . . 14

3.8 CLOCK/RESET . . . . . . . . . . . . . . . . . . . . . . . . 14

3.8.1 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.8.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.9 POWER MANAGEMENT . . . . . . . . . . . . . . . . 15

4. Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

6. Package information . . . . . . . . . . . . . . . . . . . . . . 154

6.1 MOISTURE SENSITIVITY LEVEL (MSL) . . . 154

6.2 WLCSP HANDLING . . . . . . . . . . . . . . . . . . . 154

6.3 SOLDERING INFORMATION . . . . . . . . . . . . 154

6.4 PACKAGE OUTLINES . . . . . . . . . . . . . . . . . 155

DA14580 Low Power Bluetooth Smart SoC

1. Block diagram

Figure 1 DA14580 block diagram

24 April 2012

ARM Cortex M0

SWD (JTAG)

CORE POReset

BLE Core

LINK LAYER

HARDWARE

AES-128

Radio

Transceiver

APB bridge

POWER/CLOCK

Management (PMU)

DCDC

(BUCK/BOOST)

GPIO MULTIPLEXING

XTAL

16 MHz

XTAL

32.768 kHz

32 kHz

SW TIMER

GP ADC

SPI

ROM

84 KB

System/

Exchange

RAM

42 KB

Ret. RAM

2 KB

16 MHz

Memory Controller

OTP

32 KB

DMA

OTPC

QUAD

DECODER

LDO

SYS

LDO

RET

LDO

SYS

LDO

SYS

LDO

WAKE UP

TIMER

Ret. RAM2

3 KB

Ret. RAM3

2 KB

Ret. RAM4

1 KB

KEYBOARD

CTRL

UART

FIFO

UART2

FIFO

I2C

FIFO

RCX

Timer 0

1xPWM

Timer 2

3xPWM

DA14580 Low Power Bluetooth Smart SoC

2. Pinout

The DA14580 comes in three packages:

1. A Wafer Level Chip Scale Package (WLCSP) with

34 balls

2. A Quad Flat Package No Leads (QFN) with 48 pins

3. A Quad Flat Package No Leads (QFN) with 40 pins

The actual pin/ball assignment is depicted in the follow-

ing figures:

Figure 2 WLCSP34 ball assignment

12345

RFIOm

RFIOp

XTAL16Mm

XTAL16Mp

SW_CLK

SWDIO

VBAT1V

SWITCH

VDCDC_RF

P1_3

P1_2

P1_1

P1_0

VDCDC

GND

RST

VBAT_RF

GND

VBAT3V

XTAL32Kp

XTAL32Km

GND

P0_1

P0_2

P0_4

P0_7

VPP

P0_0

P0_3

P0_5

P0_6

GND GND

Figure 3 QFN48 pin assignment

Pin 0: GND plane

RFIOp

DA14580

(Top View)

P0_1

P0_2

P0_3

P3_0

P0_4

P0_5

P0_6

P0_7

P2_1

P3_1

XTAL32Kp

P2_2

VBAT_RF

P3_4

VBAT3V

GND

RST

P2_3 22

XTAL32Km

VDCDC

35 XTAL16Mm

XTAL16Mp

P1_3

P1_2

SW_CLK

SWDIO

P1_1

VBAT1V

SWITCH

P1_0

VPP

P2_8

P2_7

RFIOm

P2_6

P2_5

P3_7

P2_9

P0_0

P3_2

VDCDC_RF

48 P2_0

P3_3

P2_4

P3_5

P3_6

DA14580 Low Power Bluetooth Smart SoC

Figure 4 QFN40 pin assignment

Pin 0: GND

plane

P2_7

P0_0

P0_1

P0_2

P0_3

P0_4

P2_1

XTAL16Mm

XTAL16Mp

P1_3

P1_2

SW_CLK

SWDIO

P1_1

VBAT1V

XTAL32Kp

P2_2

VBAT_RF

VBAT3V

GND

RST

P2_3

VDCDC

P2_9

VPP

P2_8

RFIOp

RFIOm

P2_6

P2_5

P0_7

VDCDC_RF

P2_0

XTAL32Km

P2_4

SWITCH

P1_0

DA14580

(Top View)

P0_5

P0_6

Table 1: Ordering information (samples)

Part number Package Size (mm) Shipment form Pack quantity

DA14580-01UNA WLSCP34 2.436 x 2.436 Mini-reel 50/100/1000

DA14580-01A31 QFN48 6 x 6 Tray 50

DA14580-01AT1 QFN40 5 x 5 Tray 50

Table 2: Ordering information (production)

Part number Package Size (mm) Shipment form Pack quantity

DA14580-01UNA WLSCP34 2.436 x 2.436 Mini-reel 5000

DA14580-01A32 QFN48 6 x 6 Reel 4000

DA14580-01AT2 QFN40 5 x 5 Reel 5000

DA14580-01WO4 KGD wafer Contact Dialog Semiconductor sales office

DA14580-01WC4 KGD dice Contact Dialog Semiconductor sales office

DA14580 Low Power Bluetooth Smart SoC

Table 3: Pin Description

PIN NAME TYPE Drive

(mA)

Reset

state

(Note )

DESCRIPTION

General Purpose I/Os

P0_0

P0_1

P0_2

P0_3

P0_4

P0_5

P0_6

P0_7

DIO

4.8 I-PD

I-PD

INPUT/OUTPUT with selectable pull up/down resistor. Pull-down

enabled during and after reset. General purpose I/O port bit or

alternate function nodes. Contains state retention mechanism

during power down.

P1_0

P1_1

P1_2

P1_3

P1_4/SWCLK

P1_5/SW_DIO

DIO

4.8 I-PD

I-PD

I-PU

INPUT/OUTPUT with selectable pull up/down resistor. Pull-down

enabled during and after reset. General purpose I/O port bit or

alternate function nodes. Contains state retention mechanism

during power down.

This signal is the JTAG clock by default

This signal is the JTAG data I/O by default

P2_0

P2_1

P2_2

P2_3

P2_4

P2_5

P2_6

P2_7

P2_8

P2_9

DIO

4.8 I-PD

I-PD

INPUT/OUTPUT with selectable pull up/down resistor. Pull-down

enabled during and after reset. General purpose I/O port bit or

alternate function nodes. Contains state retention mechanism

during power down.

NOTE: This port is only available on the QFN40/QFN48 pack-

ages.

P3_0

P3_1

P3_2

P3_3

P3_4

P3_5

P3_6

P3_7

DIO

4.8 I-PD

I-PD

INPUT/OUTPUT with selectable pull up/down resistor. Pull-down

enabled during and after reset. General purpose I/O port bit or

alternate function nodes. Contain state retention mechanism dur-

ing power down.

NOTE: This port is only available on the QFN48 package.

Debug interface

SWDIO/P1_5 DIO 4.8 I-PU INPUT/OUTPUT. JTAG Data input/output. Bidirectional data and

control communication. Can also be used as a GPIO

SW_CLK/

P1_4

DIO 4.8 I-PD INPUT JTAG clock signal. Can also be used as a GPIO

Clocks

XTAL16Mp AI INPUT. Crystal input for the 16 MHz XTAL

XTAL16Mm AO OUTPUT. Crystal output for the 16 MHz XTAL

XTAL32kp AI INPUT. Crystal input for the 32.768 kHz XTAL

XTAL32km AO OUTPUT. Crystal output for the 32.768 kHz XTAL

Quadrature decoder

QD_CHA_X DI INPUT. Channel A for the X axis. Mapped on Px ports

QD_CHB_X DI INPUT. Channel B for the X axis. Mapped on Px ports

QD_CHA_Y DI INPUT. Channel A for the Y axis. Mapped on Px ports

QD_CHB_Y DI INPUT. Channel B for the Y axis. Mapped on Px ports

DA14580 Low Power Bluetooth Smart SoC

QD_CHA_Z DI INPUT. Channel A for the Z axis. Mapped on Px ports

QD_CHB_Z DI INPUT. Channel B for the Z axis. Mapped on Px ports

SPI bus interface

SPI_CLK DO INPUT/OUTPUT. SPI Clock. Mapped on Px ports

SPI_DI DI INPUT. SPI Data input. Mapped on Px ports

SPI_DO DO OUTPUT. SPI Data output. Mapped on Px ports

SPI_EN DI INPUT. SPI Clock enable (active LOW). Mapped on Px ports

I2C bus interface

SDA DIO/DIOD INPUT/OUTPUT. I2C bus Data with open drain port. Mapped on

Px ports

SCL DIO/DIOD INPUT/OUTPUT. I2C bus Clock with open drain port. In open

drain mode, SCL is monitored to support bit stretching by a

slave. Mapped on Px ports.

UART interface

UTX DO OUTPUT. UART transmit data. Mapped on Px ports

URX DI INPUT. UART receive data. Mapped on Px ports

URTS DO OUTPUT. UART Request to Send. Mapped on Px ports

UCTS DI INPUT. UART Clear to Send. Mapped on Px ports

UTX2 DO OUTPUT. UART 2 transmit data. Mapped on Px ports

URX2 DI INPUT. UART 2 receive data. Mapped on Px ports

URTS2 DO OUTPUT. UART 2 Request to Send. Mapped on Px ports

UCTS2 DI INPUT. UART 2 Clear to Send. Mapped on Px ports

Analog interface

ADC[0] AI INPUT. Analog to Digital Converter input 0. Mapped on P0[0]

ADC[1] AI INPUT. Analog to Digital Converter input 1. Mapped on P0[1]

ADC[2] AI INPUT. Analog to Digital Converter input 2. Mapped on P0[2]

ADC[3] AI INPUT. Analog to Digital Converter input 3. Mapped on P0[3]

Radio transceiver

RFIOp AIO RF input/output. Impedance 50 

RFIOm AIO RF ground

Miscellaneous

RST DI INPUT. Reset signal (active high). Must be connected to GND if

not used.

VBAT_RF AIO Connect to VBAT3V on the PCB

VDCDC_RF AIO Connect to VDCDC on the PCB

VPP AI INPUT. This pin is used while OTP programming and testing.

OTP programming: VPP = 6.8 V ± 0.25 V

OTP Normal operation: leave VPP floating

Power supply

VBAT3V AIO INPUT/OUTPUT. Battery connection. Used for a single coin bat-

tery (3 V). If an alkaline or a NiMH battery (1.5 V) is attached to

pin VBAT1V, this is the second output of the DC-DC converter.

Table 3: Pin Description

PIN NAME TYPE Drive

(mA)

Reset

state

(Note )

DESCRIPTION

DA14580 Low Power Bluetooth Smart SoC

VBAT1V AI INPUT. Battery connection. Used for an alkaline or a NiMh bat-

tery (1.5 V). If a single coin battery (3 V) is attached to pin

VBAT3V,this pin must be connected to GND.

SWITCH AIO INPUT/OUTPUT. Connection for the external DC-DC converter

inductor.

VDCDC AO Output of the DC-DC converter

GND AIO - - Ground

Table 3: Pin Description

PIN NAME TYPE Drive

(mA)

Reset

state

(Note )

DESCRIPTION

DA14580 Low Power Bluetooth Smart SoC

3. System overview

The DA14580 contains the following internal blocks:

3.1 ARM CORTEXM0 CPU

The Cortex-M0 processor is a 32-bit Reduced Instruc-

tion Set Computing (RISC) processor with a von Neu-

mann architecture (single bus interface). It uses an

instruction set called Thumb, which was first supported

in the ARM7TDMI processor; however, several newer

instructions from the ARMv6 architecture and a few

instructions from the Thumb-2 technology are also

included. Thumb-2 technology extended the previous

Thumb instruction set to allow all operations to be car-

ried out in one CPU state. The instruction set in

Thumb-2 includes both 16-bit and 32-bit instructions;

most instructions generated by the C compiler use the

16-bit instructions, and the 32-bit instructions are used

when the 16-bit version cannot carry out the required

operations. This results in high code density and

avoids the overhead of switching between two instruc-

tion sets.

In total, the Cortex-M0 processor supports only 56

base instructions, although some instructions can have

more than one form. Although the instruction set is

small, the Cortex-M0 processor is highly capable

because the Thumb instruction set is highly optimized.

Academically, the Cortex-M0 processor is classified as

load-store architecture, as it has separate instructions

for reading and writing to memory, and instructions for

arithmetic or logical operations that use registers.

Features

• Thumb instruction set. Highly efficient, high code

density and able to execute all Thumb instructions

from the ARM7TDMI processor.

• High performance. Up to 0.9 DMIPS/MHz (Dhrys-

tone 2.1) with fast multiplier.

• Built-in Nested Vectored Interrupt Controller (NVIC).

This makes interrupt configuration and coding of

exception handlers easy. When an interrupt request

is taken, the corresponding interrupt handler is exe-

cuted automatically without the need to determine

the exception vector in software.

• Interrupts can have four different programmable pri-

ority levels. The NVIC automatically handles nested

interrupts.

• The design is configured to respond to exceptions

(e.g. interrupts) as soon as possible (minimum 16

clock cycles).

• Non maskable interrupt (NMI) input for safety critical

systems.

• Easy to use and C friendly. There are only two

modes (Thread mode and Handler mode). The

whole application, including exception handlers, can

be written in C without any assembler.

• Built-in System Tick timer for OS support. A 24-bit

timer with a dedicated exception type is included in

the architecture, which the OS can use as a tick

timer or as a general timer in other applications with-

out an OS.

• SuperVisor Call (SVC) instruction with a dedicated

SVC exception and PendSV (Pendable SuperVisor

service) to support various operations in an embed-

ded OS.

• Architecturally defined sleep modes and instructions

to enter sleep. The sleep features allow power con-

sumption to be reduced dramatically. Defining sleep

modes as an architectural feature makes porting of

software easier because sleep is entered by a spe-

cific instruction rather than implementation defined

control registers.

• Fault handling exception to catch various sources of

errors in the system.

• Support for 24 interrupts.

• Little endian memory support.

• Wake up Interrupt Controller (WIC) to allow the pro-

cessor to be powered down during sleep, while still

allowing interrupt sources to wake up the system.

• Halt mode debug. Allows the processor activity to

stop completely so that register values can be

accessed and modified. No overhead in code size

and stack memory size.

• CoreSight technology. Allows memories and periph-

erals to be accessed from the debugger without halt-

ing the processor.

• Supports Serial Wire Debug (SWD) connections.

The serial wire debug protocol can handle the same

debug features as the JTAG, but it only requires two

wires and is already supported by a number of

debug solutions from various tools vendors.

• Four (4) hardware breakpoints and two (2) watch

points.

• Breakpoint instruction support for an unlimited num-

ber of software breakpoints.

• Programmer’s model similar to the ARM7TDMI pro-

cessor. Most existing Thumb code for the

ARM7TDMI processor can be reused. This also

makes it easy for ARM7TDMI users, as there is no

need to learn a new instruction set.

3.2 BLUETOOTH SMART

3.2.1 BLE Core

The BLE (Bluetooth Low Energy) core is a qualified

Bluetooth baseband controller compatible with the

Bluetooth Smart specification and it is in charge of

packet encoding/decoding and frame scheduling.

Features

• All device classes support (Broadcaster, Central,

Observer, Peripheral)

DA14580 Low Power Bluetooth Smart SoC

• All packet types (Advertising / Data / Control)

• Encryption (AES / CCM)

• Bit stream processing (CRC, Whitening)

• FDMA/TDMA/events formatting and synchronization

• Frequency hopping calculation

• Operating clock 16 MHz or 8 MHz

• Low power modes supporting 32.0 kHz or

32.768 kHz

• Supports power down of the baseband during the

protocol’s idle periods

• AHB Slave interface for register file access

• AHB Slave interface for Exchange Memory access

of CPU via BLE core

• AHB Master interface for direct access of BLE core

to Exchange Memory space

3.2.2 Radio Transceiver

The Radio Transceiver implements the RF part of the

Bluetooth Smart protocol. Together with the Bluetooth

4.0 PHY layer, this provides a 93 dB RF link budget for

reliable wireless communication.

All RF blocks are supplied by on-chip low-drop out-reg-

ulators (LDOs). The bias scheme is programmable per

block and optimized for minimum power consumption.

The Bluetooth LE radio comprises the Receiver, Trans-

mitter, Synthesizer, Rx/Tx combiner block, and Biasing

LDOs.

Features

• Single ended RFIO interface, 50  matched

• Alignment free operation

• -93 dBm receiver sensitivity

• 0 dBm transmit output power

• Ultra low power consumption

• Fast frequency tuning minimises overhead

3.2.3 SmartSnippets

The DA14580 comes complete with Dialog’s Smart-

Snippets Bluetooth Software platform which includes

a qualified Bluetooth Smart single-mode stack on chip.

Numerous Bluetooth Smart profiles for consumer well-

ness, sport, fitness, security and proximity applications

are supplied as standard, while additional customer

profiles can be developed and added as needed.

The SmartSnippets software development environ-

ment is based on Keil’s uVision mature tools and

contains example application code for both embedded

and hosted modes.

Apart from the protocol stack, the Software platform

supports a Hardware Abstraction Layer (HAL) which

enables easy access to peripheral’s features from a

programmer’s point of view, as presented in the follow-

ing figure.

Figure 5 SmartSnippets stack

DA14580 Low Power Bluetooth Smart SoC

Core drivers are provided for each interface of the

DA14580 enabling optimized usage of the hardware’s

capabilities. These drivers provide an easy-to-use

interface towards the hardware engines without having

to interfere with the register programming directly.

On top of the core drivers, a number of sample drivers

is also provided enabling communication with basic

Bluetooth Smart application components: accelerome-

ters, FLASH/EEPROM non-volatile memories, etc.

3.3 MEMORIES

The following memories are part of the DA14580’s

internal blocks:

ROM. This is a 84 kB ROM containing the Bluetooth

Smart protocol stack as well as the boot code

sequence.

OTP. This is a 32 kB One-Time Programmable mem-

ory array, used to store the application code as well as

Bluetooth Smart profiles. It also contains the system

configuration and calibration data.

System SRAM. This is a 42 kB system SRAM (Sys-

RAM) which is primarily used for mirroring the program

code from the OTP when the system wakes/powers

up. It also serves as Data RAM for intermediate varia-

bles and various data that the protocol requires.

Optionally, it can be used as extra memory space for

the BLE TX and RX data structures.

Retention RAMs. These are 4 special low leakage

SRAM cells (2 kB + 2 kB + 3 kB + 1 kB) used to store

various data of the Bluetooth Smart protocol as well as

the system’s global variables and processor stack

when the system goes into Deep Sleep mode. Storage

of this data ensures secure and quick configuration of

the BLE Core after the system wakes up. Every cell

can be powered on or off according to the application

needs for retention area when in Deep Sleep mode.

3.4 FUNCTIONAL MODES

The DA14580 is optimized for deeply embedded appli-

cations such as health monitoring, sports measuring,

human interaction devices etc. Customers are able to

develop and test their own applications. Upon comple-

tion of the development, the application code can be

programmed into the OTP. In general, the system has

three functional modes of operation:

A. Development mode: During this phase application

code is developed using the ARM Cortex-M0 SW envi-

ronment. The compiled code is then downloaded into

the System RAM or any Retention RAMs by means of

SWD (JTAG) or any serial interface (e.g. UART).

Address 0x00 is remapped to the physical memory that

contains the code and the CPU is configured to reset

and execute code from the remapped device. This

mode is enabling application development, debugging

and on-the-fly testing.

B. Normal mode: After the application is ready and

verified, the code can be burned into the OTP. When

the system boots/wakes up, the DMA of the OTP con-

troller will automatically copy the program code from

the OTP into the system RAM. Next, a SW reset or a

jump to the System RAM occurs and code execution is

started. Hence, in this mode, the system is autono-

mous, contains the required SW in OTP and is ready

for integration into the final product.

C. Calibration mode: Between Development and Nor-

mal mode, there is an intermediate stage where the

chip needs to be calibrated with respect to two impor-

tant features:

• Programming of the Bluetooth device address

• Programming of the trimming value for the external

16 MHz crystal.

This mode of operation applies to the final product and

is performed by the customer. During this phase, cer-

Figure 6 Hardware abstraction layer

GPIO

Driver

Application

Accelerometer

Driver

SPI

Driver

UART

Driver

SPIFLASH

Driver

ADC

Driver

Battery

Driver

Quadrature

EEPROM

I2C

Driver

Sample

Drivers

CORE

Drivers

Timers

DA14580 Low Power Bluetooth Smart SoC

tain fields in the OTP should be programmed

3.5 POWER MODES

There are four different power modes in the DA14580:

•Active mode: System is active and operates at full

speed.

•Sleep mode: No power gating has been pro-

grammed, the ARM CPU is idle, waiting for an inter-

rupt. PD_SYS is on. PD_PER and PED_RAD

depending on the programmed enabled value.

•Extended Sleep mode: All power domains are off

except for the PD_AON, the programmed PD_RRx

and the PD_SR. Since the SysRAM retains its data,

no OTP mirroring is required upon waking up the

system.

•Deep Sleep mode: All power domains are off except

for the PD_AON and the programmed PD_RRx.

This mode dissipates the minimum leakage power.

However, since the SysRAM has not retained its

data, an OTP mirror action is required upon waking

up the system.

3.6 INTERFACES

3.6.1 UARTs

The UART is compliant to the industry-standard 16550

and is used for serial communication with a peripheral,

modem (data carrier equipment, DCE) or data set.

Data is written from a master (CPU) over the APB bus

to the UART and it is converted to serial form and

transmitted to the destination device. Serial data is also

received by the UART and stored for the master (CPU)

to read back.

There is no DMA support on the UART block since its

contains internal FIFOs. Both UARTs support hard-

ware flow control signals (RTS, CTS, DTR, DSR).

Features

• 16 bytes Transmit and receive FIFOs

• Hardware flow control support (CTS/RTS)

• Shadow registers to reduce software overhead and

also include a software programmable reset

• Transmitter Holding Register Empty (THRE) inter-

rupt mode

• IrDA 1.0 SIR mode supporting low power mode.

• Functionality based on the 16550 industry standard:

• Programmable character properties, such as num-

ber of data bits per character (5-8), optional

• parity bit (with odd or even select) and number of

stop bits (1, 1.5 or 2)

• Line break generation and detection

• Prioritized interrupt identification

• Programmable serial data baud rate as calculated

by the following: baud rate = (serial clock frequency)/

(divisor).

3.6.2 SPI+

This interface supports a subset of the Serial Periph-

eral Interface (SPITM). The serial interface can transmit

and receive 8, 16 or 32 bits in master/slave mode and

transmit 9 bits in master mode. The SPI+ interface has

enhanced functionality with bidirectional 2x16-bit word

FIFOs.

SPI is a trademark of Motorola, Inc.

Features

• Slave and Master mode

• 8 bit, 9 bit, 16 bit or 32 bit operation

• Clock speeds upto 16 MHz for the SPI controller.

Programmable output frequencies of SPI source

clock divided by 1, 2, 4, 8

• SPI clock line speed up to 8 MHz

• SPI mode 0, 1, 2, 3 support (clock edge and phase)

• Programmable SPI_DO idle level

• Maskable Interrupt generation

• Bus load reduction by unidirectional writes-only and

reads-only modes.

Built-in RX/TX FIFOs for continuous SPI bursts.

3.6.3 I2C interface

The I2C interface is a programmable control bus that

provides support for the communications link between

Integrated Circuits in a system. It is a simple two-wire

bus with a software-defined protocol for system control,

which is used in temperature sensors and voltage level

translators to EEPROMs, general-purpose I/O, A/D

and D/A converters.

Features

• Two-wire I2C serial interface consists of a serial data

line (SDA) and a serial clock (SCL)

• Two speeds are supported:

• Standard mode (0 to 100 kbit/s)

• Fast mode (<= 400 kbit/s)

• Clock synchronization

• 32 deep transmit/receive FIFOs

• Master transmit, Master receive operation

• 7 or 10-bit addressing

• 7 or 10-bit combined format transfers

• Bulk transmit mode

• Default slave address of 0x055

• Interrupt or polled-mode operation

DA14580 Low Power Bluetooth Smart SoC

• Handles Bit and Byte waiting at both bus speeds

• Programmable SDA hold time

3.6.4 General purpose ADC

The DA14580 is equipped with a high-speed ultra low

power 10-bit general purpose Analog-to-Digital Con-

verter (GPADC). It can operate in unipolar (single

ended) mode as well as in bipolar (differential) mode.

The ADC has its own voltage regulator (LDO) of 1.2 V,

which represents the full scale reference voltage.

Features

• 10-bit dynamic ADC with 65 ns conversion time

• Maximum sampling rate 3.3 Msample/s

• Ultra low power (5 A typical supply current at

100 ksample/s)

• Single-ended as well as differential input with two

input scales

• Four single-ended or two differential external input

channels

• Battery monitoring function

• Chopper function

• Offset and zero scale adjust

• Common-mode input level adjust

3.6.5 Quadrature decoder

This block decodes the pulse trains from a rotary

encoder to provide the step and the direction of the

movement of an external device. Three axes (X, Y, Z)

are supported.

The integrated quadrature decoder can automatically

decode the signals for the X, Y and Z axes of a HID

input device, reporting step count and direction: the

channels are expected to provide a pulse train with 90

degrees phase difference; depending on whether the

reference channel is leading or lagging, the direction

can be determined.

This block can be used for waking up the chip as soon

as there is any kind of movement from the external

device connected to it.

Features

• Three 16-bit signed counters that provide the step

count and direction on each of the axes (X, Y and Z)

• Programmable system clock sampling at maximum

16 MHz.

• APB interface for control and programming

• Programmable source from P0, P1 and P2 ports

• Digital filter on the channel inputs to avoid spikes

3.6.6 Keyboard controller

The Keyboard controller can be used for debouncing

the incoming GPIO signals when implementing a key-

board scanning engine. It generates an interrupt to the

CPU (KEYBR_IRQ).

In parallel, five extra interrupt lines can be triggered by

a state change on 32 selectable GPIOs (GPIOx_IRQ).

Features

• Monitors any of the 32 available GPIOs (12 in the

WLCSP package, 22 in the QFN40 and 32 in the

QFN48)

• Generates a keyboard interrupt on key press or key

release

• Implements debouncing time from 0 upto 63 ms

• Supports five separate interrupt generation lines

from GPIO toggling

3.6.7 Input/output ports

The DA14580 has software-configurable I/O pin

assignment, organized into ports Port 0, Port1, Port2

and Port 3. Port 2 is only available at the QFN40 pack-

age while ports 2 and 3 are available at the QFN48

package.

Features

• Port 0: 8 pins, Port 1: 6 pins (including SW_CLK and

SWDIO), Port 2: 10 pins, Port 3: 8 pins

• Fully programmable pin assignment

• Selectable 25 k pull-up, pull-down resistors per pin

• Pull-up voltage either VBAT3V (BUCK mode) or

VBAT1V (BOOST mode) configurable per pin

• Fixed assignment for analog pin ADC[3:0]

• Pins retain their last state when system enters the

Extended or Deep Sleep mode.

3.7 TIMERS

3.7.1 General purpose timers

The Timer block contains 2 timer modules that are soft-

ware controlled, programmable and can be used for

various tasks.

Timer 0

• 16-bit general purpose timer

• Ability to generate 2 Pulse Width Modulated signals

(PWM0 and PWM1, with common programming)

• Programmable output frequency:

f16, 8, 4, 2 MHz or 32 kHz

M1+N1++

------------------------------------------------------------------------=

DA14580 Low Power Bluetooth Smart SoC

with N = 0 to (216-1), M = 0 to (216-1)

• Programmable duty cycle:

• Separately programmable interrupt timer:

Timer 2

• 14-bit general purpose timer

• Ability to generate 3 Pulse Width Modulated signals

(PWM2, PWM3 and PWM4)

• Input clock frequency:

with N = 1, 2, 4 or 8

and sys_clk = 16 MHz or 32 kHz

• Programmable output frequency:

• Three outputs with Programmable duty cycle from

0 % to 100 %

• Used for white LED intensity (on/off) control

3.7.2 Wake-Up timer

The Wake-up timer can be programmed to wake up the

DA14580 from power down mode after a prepro-

grammed number of GPIO events.

Features

• Monitors any GPIO state change

• Implements debouncing time from 0 upto 63 ms

• Accumulates external events and compares the

number to a programmed value

• Generates an interrupt to the CPU

3.7.3 Watchdog timer

The Watchdog timer is an 8-bit timer with sign bit that

can be used to detect an unexpected execution

sequence caused by a software run-away and can

generate a full system reset or a Non-Maskable Inter-

rupt (NMI).

Features

• 8 bits down counter with sign bit, clocked with a

10.24 ms clock for a maximum 2.6 s time-out.

• Non-Maskable Interrupt (NMI) or WDOG reset.

• Optional automatic WDOG reset if NMI handler fails

to update the Watchdog register.

• Non-maskable Watchdog freeze of the Cortex-M0

Debug module when the Cortex-M0 is halted in

Debug state.

Maskable Watchdog freeze by user program. Note that

if the system is not remapped, i.e. SysRAM is at

address 0x20000000, then a watchdog fire will trigger

the BootROM code to be executed again.

3.8 CLOCK/RESET

3.8.1 Clocks

The Digital Controlled Xtal Oscillator (DXCO) is a

Pierce configured type of oscillator designed for low

power consumption and high stability. There are two

such crystal oscillators in the system, one at 16

MHz(XTAL16M) and a second at 32.768 kHz

(XTAL32K). The 32.768 kHz oscillator has no trimming

capabilities and is used as the clock of the Extended/

Deep Sleep modes. The 16 MHz oscillator can be

trimmed.

The principle schematic of the two oscillators is shown

in Figure 7 below. No external components to the

DA14580 are required other than the crystal itself. If

the crystal has a case connection, it is advised to con-

nect the case to ground.

There are 3 RC oscillators in the DA14580: one provid-

ing 16 MHz (RC16M), one providing 32 kHz (RC32K)

and one providing a frequency in the range of 10.5 kHz

(RCX).

3.8.2 Reset

The DA14580 comprises an RST pad which is active

high. It contains an RC filter for spikes suppression

with 400 k and 2.8 pF for the resistor and the capaci-

tor respectively. It also contains a 25 k pull-down

resistor. This pad should be connected to ground if not

needed by the application. The typical latency of the

RST pad is in the range of 2 s.

M1+

M1+N1++

-------------------------------------------- 100 %=

T16, 8, 4, 2 MHz or 32 kHz

ON 1+

------------------------------------------------------------------------=

fIN

sys_clk

-------------------=

fOUT

fIN

------





to fIN

214 1–

------------------







Figure 7 Crystal oscillator circuits

XTAL16Mp

clock16MHz

XTAL16Mm

16 MHz

XTAL32Kp

clock32kHz

XTAL32Km

32.768 kHz

0-22.4 pF

DA14580 Low Power Bluetooth Smart SoC

3.9 POWER MANAGEMENT

The DA14580 has a complete power management

function integrated with Buck or Boost DC-DC con-

verter and separate LDOs for the different power

domains of the system.

Features

• On-chip LDOs, without external capacitors

• Synchronous DC-DC converter which can be config-

ured as either:

• Boost (step-up) converter, starting from 0.9 V,

when running from an Alkaline/NiMH cell.

• Buck (step-down) converter for increased effi-

ciency when running from a Lithium coin-cell or 2

Alkaline batteries down to 2.35 V.

• Battery voltage measurement ADC (multiplexed

input from general purpose ADC)

• Use of small external components (2.2 H inductor

and 1F capacitor)

The Power Block contains a DC-DC converter which

can be configured to operate as a Step-Up or a Step-

Down converter. The converter provides power to four

LDO groups in the system:

1. LDO RET: This is the LDO providing power to the

Retention domain (PD_AON). It powers the Retention

RAMs and the digital part which is always on.

2. LDO OTP: This is the LDO powering the OTP macro

cell. This is the reason for using the step-up DC-DC

converter when running from an Alkaline battery.

3. LDO SYS: This is the LDO providing the system with

the actual VDD power required for the digital part to

operate. Note that the Power Block implements seam-

less switching from the LDO SYS to the LDO RET

when the system enters Deep Sleep mode. In the latter

case, a low voltage is applied to the PD_AON power

domain to further reduce leakage.

4. LDO (various): This a group of LDOs used for the

elaborate control of the powering up/down of the

Radio, the GP ADC and the XTAL16M oscillator.

There are two ways of connecting external batteries to

the Power Block of the DA14580. They depend on the

specific battery cell used and its voltage range. Battery

cells are distinguished into Lithium coin cells (2.35 V to

3.3 V) and Alkaline cells (1.0 V to 1.8 V). The connec-

tion diagrams are presented in Figure 9 and Figure 8

respectively:

Figure 8 Supply overview, Coin-cell application

Buck Converter

LDO

VBAT1V

SWITCH

VBAT3V

VDCDC

LDO LDO

Lithium

coin-cell

digital analog/RF

retention

2.35 V to 3.3 V

DA14580

VDCDC_RF

VBAT_RF

analog/RF

DA14580 Low Power Bluetooth Smart SoC

The usage of Boost or Buck mode with respect to the

provided voltage ranges is illustrated in the following

figure which also illustrates the efficiency of the engine

assuming a 10 mA constant load.

The X axis represents the supply voltage. BOOST

mode should be used when voltage ranges from 0.9 V

to 2.0 V to sustain a decent efficiency over 70 %. From

that point on, the power dissipation becomes quite

large.

BUCK mode can operate correctly with voltages in the

range of 2.35 V to 3.3 V.

There are two voltage areas in Figure 10 designated by

dashed lines. The first one (0 V to 0.9 V) indicates that

the DA14580 is not operational when the voltage is

below 0.9 V. This is the absolute threshold for the DC-

DC converter Boost mode.

The second area (1.8 V to 2.2 V) indicates that Deep

Sleep mode is not allowed when the DC-DC converter

is configured in BUCK mode and the voltage is within

this range, because the OTP will not be readable any

more. However, this part of the voltage range can be

covered by the BOOST mode. Furthermore, when

BUCK mode is mandatory, Extended Sleep mode can

be activated instead of Deep Sleep mode, thus not

using the OTP for the code mirroring but retain the

code in SysRAM.

Note: The system should never be cold booted when

the supply voltage is less than 2.5 V. A manual power

up with a power supply less than 2.5 V in buck mode

might create instability.

Figure 9 Supply overview, Alkaline-cell application

Boost Converter

LDO

VBAT1V SWITCH

VBAT3V

VDCDC

LDO LDO

digital

0.9 V to 2.0 V

< 0.9 V

analog/RF

retention

Alkaline

NiMH

DA14580

internal supply for boost conv.

VDCDC_RF

VBAT_RF

Figure 10 DC-DC efficiency in Buck/Boost mode at

various voltage levels

50%

55%

60%

65%

70%

75%

80%

85%

90%

95%

00.511.522.533.5

DC‐DCEfficiencyvsVoltage

Buck Boost Boost(Vout>1.4V)

1.80.9 2.35

DA14580 Low Power Bluetooth Smart SoC

4. Registers

This section contains a detailed view of the DA14580 registers. It is organized as follows: An overview table is pre-

sented initially, which depicts all register names, addresses and descriptions. A detailed bit level description of each

The register file of the ARM Cortex-M0 can be found in the following documents, available on the ARM website:

Devices Generic User Guide:

DUI0497A_cortex_m0_r0p0_generic_ug.pdf

Technical Reference Manual:

DDI0432C_cortex_m0_r0p0_trm.pdf

These documents contain the register descriptions for the Nested Vectored Interrupt Controller (NVIC), the System

Control Block (SCB) and the System Timer (SysTick).

DA14580 Low Power Bluetooth Smart SoC

Table 4: Register map

Address Port Description

0x40008000 OTPC_MODE_REG Mode register

0x40008004 OTPC_PCTRL_REG Bit-programming control register

0x40008008 OTPC_STAT_REG Status register

0x4000800C OTPC_AHBADR_REG AHB master start address

0x40008010 OTPC_CELADR_REG Macrocell start address

0x40008014 OTPC_NWORDS_REG Number of words

0x40008018 OTPC_FFPRT_REG Ports access to fifo logic

0x4000801C OTPC_FFRD_REG Latest read data from the OTPC_FFPRT_REG

0x40008400 PATCH_VALID_REG Validity Control Register

0x40008404 PATCH_VALID_SET_REG Validity Set Control Register

0x40008408 PATCH_VALID_RESET_REG Validity Reset Control Register

0x40008410 PATCH_ADDR0_REG Patch entry 0: Address field

0x40008414 PATCH_DATA0_REG Patch entry 0: Data field

0x40008418 PATCH_ADDR1_REG Patch entry 1: Address field

0x4000841C PATCH_DATA1_REG Patch entry 1: Data field

0x40008420 PATCH_ADDR2_REG Patch entry 2: Address field

0x40008424 PATCH_DATA2_REG Patch entry 2: Data field

0x40008428 PATCH_ADDR3_REG Patch entry 3: Address field

0x4000842C PATCH_DATA3_REG Patch entry 3: Data field

0x40008430 PATCH_ADDR4_REG Patch entry 4: Address field

0x40008434 PATCH_DATA4_REG Patch entry 4: Data field

0x40008438 PATCH_ADDR5_REG Patch entry 5: Address field

0x4000843C PATCH_DATA5_REG Patch entry 5: Data field

0x40008440 PATCH_ADDR6_REG Patch entry 6: Address field

0x40008444 PATCH_DATA6_REG Patch entry 6: Data field

0x40008448 PATCH_ADDR7_REG Patch entry 7: Address field

0x4000844C PATCH_DATA7_REG Patch entry 7: Data field

0x50000000 CLK_AMBA_REG HCLK, PCLK, divider and clock gates

0x50000002 CLK_FREQ_TRIM_REG Xtal frequency trimming register

0x50000004 CLK_PER_REG Peripheral divider register

0x50000008 CLK_RADIO_REG Radio PLL control register

0x5000000A CLK_CTRL_REG Clock control register

0x50000010 PMU_CTRL_REG Power Management Unit control register

0x50000012 SYS_CTRL_REG System Control register

0x50000014 SYS_STAT_REG System status register

0x50000016 TRIM_CTRL_REG Control trimming of the XTAL16M

0x50000020 CLK_32K_REG 32 kHz oscillator register

0x50000022 CLK_16M_REG 16 MHz RC-oscillator register

0x50000024 CLK_RCX20K_REG 20 kHz RXC-oscillator control register

0x50000028 BANDGAP_REG Bandgap trimming

0x5000002A ANA_STATUS_REG Status bit of analog (power management) circuits

0x50000100 WKUP_CTRL_REG Control register for the wakeup counter

0x50000102 WKUP_COMPARE_REG Number of events before wakeup interrupt

DA14580 Low Power Bluetooth Smart SoC

0x50000104 WKUP_RESET_IRQ_REG Reset wakeup interrupt

0x50000106 WKUP_COUNTER_REG Actual number of events of the wakeup counter

0x50000108 WKUP_RESET_CNTR_REG Reset the event counter

0x5000010A WKUP_SELECT_P0_REG Select which inputs from P0 port can trigger wkup

counter

0x5000010C WKUP_SELECT_P1_REG Select which inputs from P1 port can trigger wkup

counter

0x5000010E WKUP_SELECT_P2_REG Select which inputs from P2 port can trigger wkup

counter

0x50000110 WKUP_SELECT_P3_REG Select which inputs from P3 port can trigger wkup

counter

0x50000112 WKUP_POL_P0_REG Select the sensitivity polarity for each P0 input

0x50000114 WKUP_POL_P1_REG Select the sensitivity polarity for each P1 input

0x50000116 WKUP_POL_P2_REG Select the sensitivity polarity for each P2 input

0x50000118 WKUP_POL_P3_REG Select the sensitivity polarity for each P3 input

0x50000200 QDEC_CTRL_REG Quad Decoder control register

0x50000202 QDEC_XCNT_REG Counter value of the X Axis

0x50000204 QDEC_YCNT_REG Counter value of the Y Axis

0x50000206 QDEC_CLOCKDIV_REG Clock divider register

0x50000208 QDEC_CTRL2_REG Quad Decoder control register

0x5000020A QDEC_ZCNT_REG Z_counter

0x50001000 UART_RBR_THR_DLL_REG Receive Buffer Register

0x50001004 UART_IER_DLH_REG Interrupt Enable Register

0x50001008 UART_IIR_FCR_REG Interrupt Identification Register/FIFO Control Register

0x5000100C UART_LCR_REG Line Control Register

0x50001010 UART_MCR_REG Modem Control Register

0x50001014 UART_LSR_REG Line Status Register

0x50001018 UART_MSR_REG Modem Status Register

0x5000101C UART_SCR_REG Scratchpad Register

0x50001020 UART_LPDLL_REG Low Power Divisor Latch Low

0x50001024 UART_LPDLH_REG Low Power Divisor Latch High

0x50001030 UART_SRBR_STHR0_REG Shadow Receive/Transmit Buffer Register

0x50001034 UART_SRBR_STHR1_REG Shadow Receive/Transmit Buffer Register

0x50001038 UART_SRBR_STHR2_REG Shadow Receive/Transmit Buffer Register

0x5000103C UART_SRBR_STHR3_REG Shadow Receive/Transmit Buffer Register

0x50001040 UART_SRBR_STHR4_REG Shadow Receive/Transmit Buffer Register

0x50001044 UART_SRBR_STHR5_REG Shadow Receive/Transmit Buffer Register

0x50001048 UART_SRBR_STHR6_REG Shadow Receive/Transmit Buffer Register

0x5000104C UART_SRBR_STHR7_REG Shadow Receive/Transmit Buffer Register

0x50001050 UART_SRBR_STHR8_REG Shadow Receive/Transmit Buffer Register

0x50001054 UART_SRBR_STHR9_REG Shadow Receive/Transmit Buffer Register

0x50001058 UART_SRBR_STHR10_REG Shadow Receive/Transmit Buffer Register

0x5000105C UART_SRBR_STHR11_REG Shadow Receive/Transmit Buffer Register

0x50001060 UART_SRBR_STHR12_REG Shadow Receive/Transmit Buffer Register

0x50001064 UART_SRBR_STHR13_REG Shadow Receive/Transmit Buffer Register

Table 4: Register map

Address Port Description

DA14580 Low Power Bluetooth Smart SoC

0x50001068 UART_SRBR_STHR14_REG Shadow Receive/Transmit Buffer Register

0x5000106C UART_SRBR_STHR15_REG Shadow Receive/Transmit Buffer Register

0x5000107C UART_USR_REG UART Status register.

0x50001080 UART_TFL_REG Transmit FIFO Level

0x50001084 UART_RFL_REG Receive FIFO Level.

0x50001088 UART_SRR_REG Software Reset Register.

0x5000108C UART_SRTS_REG Shadow Request to Send

0x50001090 UART_SBCR_REG Shadow Break Control Register

0x50001094 UART_SDMAM_REG Shadow DMA Mode

0x50001098 UART_SFE_REG Shadow FIFO Enable

0x5000109C UART_SRT_REG Shadow RCVR Trigger

0x500010A0 UART_STET_REG Shadow TX Empty Trigger

0x500010A4 UART_HTX_REG Halt TX

0x500010F4 UART_CPR_REG Component Parameter Register

0x500010F8 UART_UCV_REG Component Version

0x500010FC UART_CTR_REG Component Type Register

0x50001100 UART2_RBR_THR_DLL_REG Receive Buffer Register

0x50001104 UART2_IER_DLH_REG Interrupt Enable Register

0x50001108 UART2_IIR_FCR_REG Interrupt Identification Register/FIFO Control Register

0x5000110C UART2_LCR_REG Line Control Register

0x50001110 UART2_MCR_REG Modem Control Register

0x50001114 UART2_LSR_REG Line Status Register

0x50001118 UART2_MSR_REG Modem Status Register

0x5000111C UART2_SCR_REG Scratchpad Register

0x50001120 UART2_LPDLL_REG Low Power Divisor Latch Low

0x50001124 UART2_LPDLH_REG Low Power Divisor Latch High

0x50001130 UART2_SRBR_STHR0_REG Shadow Receive/Transmit Buffer Register

0x50001134 UART2_SRBR_STHR1_REG Shadow Receive/Transmit Buffer Register

0x50001138 UART2_SRBR_STHR2_REG Shadow Receive/Transmit Buffer Register

0x5000113C UART2_SRBR_STHR3_REG Shadow Receive/Transmit Buffer Register

0x50001140 UART2_SRBR_STHR4_REG Shadow Receive/Transmit Buffer Register

0x50001144 UART2_SRBR_STHR5_REG Shadow Receive/Transmit Buffer Register

0x50001148 UART2_SRBR_STHR6_REG Shadow Receive/Transmit Buffer Register

0x5000114C UART2_SRBR_STHR7_REG Shadow Receive/Transmit Buffer Register

0x50001150 UART2_SRBR_STHR8_REG Shadow Receive/Transmit Buffer Register

0x50001154 UART2_SRBR_STHR9_REG Shadow Receive/Transmit Buffer Register

0x50001158 UART2_SRBR_STHR10_REG Shadow Receive/Transmit Buffer Register

0x5000115C UART2_SRBR_STHR11_REG Shadow Receive/Transmit Buffer Register

0x50001160 UART2_SRBR_STHR12_REG Shadow Receive/Transmit Buffer Register

0x50001164 UART2_SRBR_STHR13_REG Shadow Receive/Transmit Buffer Register

0x50001168 UART2_SRBR_STHR14_REG Shadow Receive/Transmit Buffer Register

0x5000116C UART2_SRBR_STHR15_REG Shadow Receive/Transmit Buffer Register

0x5000117C UART2_USR_REG UART Status register.

0x50001180 UART2_TFL_REG Transmit FIFO Level

Table 4: Register map

Address Port Description

DA14580 Low Power Bluetooth Smart SoC

0x50001184 UART2_RFL_REG Receive FIFO Level.

0x50001188 UART2_SRR_REG Software Reset Register.

0x5000118C UART2_SRTS_REG Shadow Request to Send

0x50001190 UART2_SBCR_REG Shadow Break Control Register

0x50001194 UART2_SDMAM_REG Shadow DMA Mode

0x50001198 UART2_SFE_REG Shadow FIFO Enable

0x5000119C UART2_SRT_REG Shadow RCVR Trigger

0x500011A0 UART2_STET_REG Shadow TX Empty Trigger

0x500011A4 UART2_HTX_REG Halt TX

0x500011F4 UART2_CPR_REG Component Parameter Register

0x500011F8 UART2_UCV_REG Component Version

0x500011FC UART2_CTR_REG Component Type Register

0x50001200 SPI_CTRL_REG SPI control register 0

0x50001202 SPI_RX_TX_REG0 SPI RX/TX register0

0x50001204 SPI_RX_TX_REG1 SPI RX/TX register1

0x50001206 SPI_CLEAR_INT_REG SPI clear interrupt register

0x50001208 SPI_CTRL_REG1 SPI control register 1

0x50001300 I2C_CON_REG I2C Control Register

0x50001304 I2C_TAR_REG I2C Target Address Register

0x50001308 I2C_SAR_REG I2C Slave Address Register

0x50001310 I2C_DATA_CMD_REG I2C Rx/Tx Data Buffer and Command Register

0x50001314 I2C_SS_SCL_HCNT_REG Standard Speed I2C Clock SCL High Count Register

0x50001318 I2C_SS_SCL_LCNT_REG Standard Speed I2C Clock SCL Low Count Register

0x5000131C I2C_FS_SCL_HCNT_REG Fast Speed I2C Clock SCL High Count Register

0x50001320 I2C_FS_SCL_LCNT_REG Fast Speed I2C Clock SCL Low Count Register

0x5000132C I2C_INTR_STAT_REG I2C Interrupt Status Register

0x50001330 I2C_INTR_MASK_REG I2C Interrupt Mask Register

0x50001334 I2C_RAW_INTR_STAT_REG I2C Raw Interrupt Status Register

0x50001338 I2C_RX_TL_REG I2C Receive FIFO Threshold Register

0x5000133C I2C_TX_TL_REG I2C Transmit FIFO Threshold Register

0x50001340 I2C_CLR_INTR_REG Clear Combined and Individual Interrupt Register

0x50001344 I2C_CLR_RX_UNDER_REG Clear RX_UNDER Interrupt Register

0x50001348 I2C_CLR_RX_OVER_REG Clear RX_OVER Interrupt Register

0x5000134C I2C_CLR_TX_OVER_REG Clear TX_OVER Interrupt Register

0x50001350 I2C_CLR_RD_REQ_REG Clear RD_REQ Interrupt Register

0x50001354 I2C_CLR_TX_ABRT_REG Clear TX_ABRT Interrupt Register

0x50001358 I2C_CLR_RX_DONE_REG Clear RX_DONE Interrupt Register

0x5000135C I2C_CLR_ACTIVITY_REG Clear ACTIVITY Interrupt Register

0x50001360 I2C_CLR_STOP_DET_REG Clear STOP_DET Interrupt Register

0x50001364 I2C_CLR_START_DET_REG Clear START_DET Interrupt Register

0x50001368 I2C_CLR_GEN_CALL_REG Clear GEN_CALL Interrupt Register

0x5000136C I2C_ENABLE_REG I2C Enable Register

0x50001370 I2C_STATUS_REG I2C Status Register

0x50001374 I2C_TXFLR_REG I2C Transmit FIFO Level Register

Table 4: Register map

Address Port Description

DA14580 Low Power Bluetooth Smart SoC

0x50001378 I2C_RXFLR_REG I2C Receive FIFO Level Register

0x5000137C I2C_SDA_HOLD_REG I2C SDA Hold Time Length Register

0x50001380 I2C_TX_ABRT_SOURCE_REG I2C Transmit Abort Source Register

0x50001394 I2C_SDA_SETUP_REG I2C SDA Setup Register

0x50001398 I2C_ACK_GENERAL_CALL_REG I2C ACK General Call Register

0x5000139C I2C_ENABLE_STATUS_REG I2C Enable Status Register

0x500013A0 I2C_IC_FS_SPKLEN_REG I2C SS and FS spike suppression limit Size

0x50001400 GPIO_IRQ0_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ0

0x50001402 GPIO_IRQ1_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ1

0x50001404 GPIO_IRQ2_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ2

0x50001406 GPIO_IRQ3_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ3

0x50001408 GPIO_IRQ4_IN_SEL_REG GPIO interrupt selection for GPIO_IRQ4

0x5000140C GPIO_DEBOUNCE_REG debounce counter value for GPIO inputs

0x5000140E GPIO_RESET_IRQ_REG GPIO interrupt reset register

0x50001410 GPIO_INT_LEVEL_CTRL_REG high or low level select for GPIO interrupts

0x50001412 KBRD_IRQ_IN_SEL0_REG GPIO interrupt selection for KBRD_IRQ for P0

0x50001414 KBRD_IRQ_IN_SEL1_REG GPIO interrupt selection for KBRD_IRQ for P1 and P2

0x50001416 KBRD_IRQ_IN_SEL2_REG GPIO interrupt selection for KBRD_IRQ for P3

0x50001500 GP_ADC_CTRL_REG General Purpose ADC Control Register

0x50001502 GP_ADC_CTRL2_REG General Purpose ADC Second Control Register

0x50001504 GP_ADC_OFFP_REG General Purpose ADC Positive Offset Register

0x50001506 GP_ADC_OFFN_REG General Purpose ADC Negative Offset Register

0x50001508 GP_ADC_CLEAR_INT_REG General Purpose ADC Clear Interrupt Register

0x5000150A GP_ADC_RESULT_REG General Purpose ADC Result Register

0x5000150C GP_ADC_DELAY_REG General Purpose ADC Delay Register

0x5000150E GP_ADC_DELAY2_REG General Purpose ADC Second Delay Register

0x50001600 CLK_REF_SEL_REG Select clock for oscillator calibration

0x50001602 CLK_REF_CNT_REG Count value for oscillator calibration

0x50001604 CLK_REF_VAL_L_REG XTAL16M reference cycles, lower 16 bits

0x50001606 CLK_REF_VAL_H_REG XTAL16M reference cycles, upper 16 bits

0x50003000 P0_DATA_REG P0 Data input / output register

0x50003002 P0_SET_DATA_REG P0 Set port pins register

0x50003004 P0_RESET_DATA_REG P0 Reset port pins register

0x50003006 P00_MODE_REG P00 Mode Register

0x50003008 P01_MODE_REG P01 Mode Register

0x5000300A P02_MODE_REG P02 Mode Register

0x5000300C P03_MODE_REG P03 Mode Register

0x5000300E P04_MODE_REG P04 Mode Register

0x50003010 P05_MODE_REG P05 Mode Register

0x50003012 P06_MODE_REG P06 Mode Register

0x50003014 P07_MODE_REG P07 Mode Register

0x50003020 P1_DATA_REG P1 Data input / output register

0x50003022 P1_SET_DATA_REG P1 Set port pins register

0x50003024 P1_RESET_DATA_REG P1 Reset port pins register

Table 4: Register map

Address Port Description

DA14580 Low Power Bluetooth Smart SoC

0x50003026 P10_MODE_REG P10 Mode Register

0x50003028 P11_MODE_REG P11 Mode Register

0x5000302A P12_MODE_REG P12 Mode Register

0x5000302C P13_MODE_REG P13 Mode Register

0x5000302E P14_MODE_REG P14 Mode Register

0x50003030 P15_MODE_REG P15 Mode Register

0x50003040 P2_DATA_REG P2 Data input / output register

0x50003042 P2_SET_DATA_REG P2 Set port pins register

0x50003044 P2_RESET_DATA_REG P2 Reset port pins register

0x50003046 P20_MODE_REG P20 Mode Register

0x50003048 P21_MODE_REG P21 Mode Register

0x5000304A P22_MODE_REG P22 Mode Register

0x5000304C P23_MODE_REG P23 Mode Register

0x5000304E P24_MODE_REG P24 Mode Register

0x50003050 P25_MODE_REG P25 Mode Register

0x50003052 P26_MODE_REG P26 Mode Register

0x50003054 P27_MODE_REG P27 Mode Register

0x50003056 P28_MODE_REG P28 Mode Register

0x50003058 P29_MODE_REG P29 Mode Register

0x50003070 P01_PADPWR_CTRL_REG Ports 0 and 1 Output Power Control Register

0x50003072 P2_PADPWR_CTRL_REG Port 2 Output Power Control Register

0x50003074 P3_PADPWR_CTRL_REG Port 3 Output Power Control Register

0x50003080 P3_DATA_REG P3 Data input / output register

0x50003082 P3_SET_DATA_REG P3 Set port pins register

0x50003084 P3_RESET_DATA_REG P3 Reset port pins register

0x50003086 P30_MODE_REG P30 Mode Register

0x50003088 P31_MODE_REG P31 Mode Register

0x5000308A P32_MODE_REG P32 Mode Register

0x5000308C P33_MODE_REG P33 Mode Register

0x5000308E P34_MODE_REG P34 Mode Register

0x50003090 P35_MODE_REG P35 Mode Register

0x50003092 P36_MODE_REG P36 Mode Register

0x50003094 P37_MODE_REG P37 Mode Register

0x50003100 WATCHDOG_REG Watchdog timer register.

0x50003102 WATCHDOG_CTRL_REG Watchdog control register.

0x50003200 CHIP_ID1_REG Chip identification register 1.

0x50003201 CHIP_ID2_REG Chip identification register 2.

0x50003202 CHIP_ID3_REG Chip identification register 3.

0x50003203 CHIP_SWC_REG Software compatibility register.

0x50003204 CHIP_REVISION_REG Chip revision register.

0x50003205 CHIP_CONFIG1_REG Chip configuration register 1.

0x50003206 CHIP_CONFIG2_REG Chip configuration register 2.

0x50003207 CHIP_CONFIG3_REG Chip configuration register 3.

0x5000320A CHIP_TEST1_REG Chip test register 1.

Table 4: Register map

Address Port Description

DA14580 Low Power Bluetooth Smart SoC

0x5000320B CHIP_TEST2_REG Chip test register 2.

0x50003300 SET_FREEZE_REG Controls freezing of various timers/counters.

0x50003302 RESET_FREEZE_REG Controls unfreezing of various timers/counters.

0x50003304 DEBUG_REG Various debug information register.

0x50003306 GP_STATUS_REG General purpose system status register.

0x50003308 GP_CONTROL_REG General purpose system control register.

0x50003400 TIMER0_CTRL_REG Timer0 control register

0x50003402 TIMER0_ON_REG Timer0 on control register

0x50003404 TIMER0_RELOAD_M_REG 16 bits reload value for Timer0

0x50003406 TIMER0_RELOAD_N_REG 16 bits reload value for Timer0

0x50003408 PWM2_DUTY_CYCLE Duty Cycle for PWM2

0x5000340A PWM3_DUTY_CYCLE Duty Cycle for PWM3

0x5000340C PWM4_DUTY_CYCLE Duty Cycle for PWM4

0x5000340E TRIPLE_PWM_FREQUENCY Frequency for PWM 2,3 and 4

0x50003410 TRIPLE_PWM_CTRL_REG PWM 2 3 4 Control

Table 4: Register map

Address Port Description

Table 5: OTPC_MODE_REG (0x40008000)

Bit Mode Symbol Description Reset

31:30 --Reserved 0x0

29:28 R/W OTPC_MODE_PRG_

PORT_MUX

Selects the source that is connected to the prg_port port of

the controller.

00 - {16'd0, BANDGAP_REG[15:0]}

01 - {RF_RSSI_COMP_CTRL_REG[15:0], 8'd0,

RFIO_CTRL1_REG{7:0]}

10 - {3'd0, RF_LNA_CTRL3_REG[4:0],

RF_LNA_CTRL2_REG[11:0], RF_LNA_CTRL1_REG[11:0]}

11 - {28'd0, RF_VCO_CTRL_REG[3:0]}

See OTPC_MODE_PRG_PORT_SEL about the use of the

prg_port

0x0

27:9 --Reserved 0x0

8R/W OPTC_MODE_PRG_

FAST

Defines the timing that will be used for all the programming

activities (APROG, MPROG and TWR)

0 - Selects the normal timing

1 - Selects the fast timing

7R/W OTPC_MODE_PRG_

PORT_SEL

Selects an alternative data source for the programming of the

OTP macrocells, when the controller is configured in APROG

mode.

0 - The fifo will be used as the data source. The fifo will be

filled with a way defined by the register

OTPC_MODE_USE_DMA. The number of words that will be

programmed is defined by OTPC_NWORDS.

1 - Only one word will programmed. The value of the word is

contained in the prg_port port of the controller. The values of

the registers OTPC_MODE_USE_DMA, OTPC_NWORDS

and the contents of the FIFO will not be used.

0x0

6R/W OTPC_MODE_TWO_

CC_ACC

Defines the duration of each read from the OTP macrocells.

0 - Reads 16 bits of data every one clock cycle.

1 - Reads 16 bits of data every two clock cycles.

0x0

DA14580 Low Power Bluetooth Smart SoC

5R/W OTPC_MODE_FIFO_

FLUSH

Writing 1, removes any content from the FIFO. This bit returns

automatically to 0.

0x0

4R/W OTPC_MODE_USE_

DMA

Selects the use of the dma, when the controller is configured

in one of the modes: AREAD or APROG.

0 - DMAis not used. The data should be transfered from/to

controller through OTPC_FFPRT_REG

1 - DMA is used. Data transfers from/to controller are per-

formed automatically. The AHB base address should be con-

figured in OTPC_AHBADR_REG before the selection of the

mode.

If programming of the OTPC_MODE_REG is performed

through the serial interface,the OTPC_MODE_USE_DMA will

be set to 0 automatically.

If the controller is in APROG mode and the

OTPC_MODE_PRG_PORT_SEL is enabled, the dma will

stay inactive.

0x0

3--Reserved 0x0

2:0 R/W OTPC_MODE_MODE Defines the mode of operation of the OTPC controller. The

encoding of the modes is as follows:

000 - STBY mode

001 - MREAD mode

010 - MPROG mode

011 - AREAD mode

100 - APROG mode

101 - Test mode. Reserved

110 - Test mode. Reserved

111 - Test mode. Reserved

To manually move between modes, always return to STBY

mode first.

0x0

Table 5: OTPC_MODE_REG (0x40008000)

Bit Mode Symbol Description Reset

Table 6: OTPC_PCTRL_REG (0x40008004)

Bit Mode Symbol Description Reset

31:28 --Reserved 0x0

27 R/W OTPC_PCTRL_ENU Enables the programming in the upper bank of the OTP.

0 - Programming sequence is not applied in the upper bank.

1 - Programming sequence is applied in the upper bank.

0x0

26 R/W OTPC_PCTRL_BITU Defines the value of the selected bit in the upper bank, after

the programming sequence.

0x0

25 R/W OTPC_PCTRL_ENL Enables the programming in the lower bank.

0 - The programming sequence is not applied in the lower

bank.

1 -The programming sequence is applied in the lower bank.

0x0

24 R/W OTPC_PCTRL_BITL Defines the value of the selected bit in the lower bank, after

the programming sequence.

0x0

23 R/W OTPC_PCTRL_BSEL

Selects between the U1 and U0 byte for the programming

sequence in the upper bank.

0 - Program the U0 byte

1 - Program the U1 byte

0x0

22:20 R/W OTPC_PCTRL_BADR

Selects the bit inside the Ux (x=0,1) byte, which will be pro-

grammed in the upper bank.

0x0

19 R/W OTPC_PCTRL_BSEL

Selects between the L1 and L0 byte for the programming

sequence in the lower bank.

0 - Program the L0 byte

1 - Program the L1 byte

0x0

DA14580 Low Power Bluetooth Smart SoC

18:16 R/W OTPC_PCTRL_BADR

Selects the bit inside the Lx (x=0,1) byte, which will be pro-

grammed in the lower bank.

0x0

15:13 --Reserved 0x0

12:0 R/W OTPC_PCTRL_WAD

Defines the address of a 32 bits word {U1,L1,U0,L0} in the

macrocells, where one or two bits will be programmed. There

are two macrocell banks, with 8 bits each. Each bank contrib-

ute with two memory positions for each 32 bits word. The Ux,

Lx represent the bytes of the upper and lower bank respec-

tively.

0x0

Table 6: OTPC_PCTRL_REG (0x40008004)

Bit Mode Symbol Description Reset

Table 7: OTPC_STAT_REG (0x40008008)

Bit Mode Symbol Description Reset

31:29 --Reserved 0x0

28:16 ROTPC_STAT_NWOR

Contains the current value of the words to be processed. 0

15 ROTPC_STAT_TERR_

Indicates the upper bank as the source of a test error. This

value is valid when OTPC_STAT_TERROR is valid.

0 - There is no test error in the upper bank

1 - A test error has occured in the upper bank

0x0

14 ROTPC_STAT_TERR_L Indicates the lower bank as the source of a test error. The

value is valid when OTPC_STAT_TERROR is valid.

0 - There is no test error in the lower bank

1 - A test error has occured in the lower bank

0x0

13 ROTPC_STAT_PERR_

Indicates the upper bank as the source of a programming

error. The value is valid when OTPC_STAT_PERROR is

valid.

0 - There is no programming error in the upper bank

1 - A programming error has occured in the upper bank

0x0

12 ROTPC_STAT_PERR_

Indicates the lower bank as the source of a programming

error. The value is valid when OTPC_STAT_PERROR is

valid.

0 - There is no programming error in the lower bank

1 - A programming error has occured in the lower bank

0x0

11:8 ROTPC_STAT_FWORD

Indicates the number of words which contained in the fifo of

the controller.

0x0

7:5 --Reserved 0x0

4ROTPC_STAT_ARDY Monitors the progress of read or programming operations

while in the AREAD or APROG modes.

0 - The controller is busy while reading or programming

(AREAD or APROG modes).

1 - The controller is not busy in AREAD or APROG mode.

0x1

3ROTPC_STAT_TERRO

Indicates the result of a test sequence. Should be checked

after the end of a TBLANK, TDEC and TWR mode

(OTPC_STAT_TRDY= 1).

0 - The test sequence ends with no error.

1 - The test sequence has failed.

0x0

2ROTPC_STAT_TRDY Indicates the state of a test mode. Should be used to monitor

the progress of the TBLANK, TDEC and TWR modes.

0 - The controller is busy. A test mode is in progress.

1 - There is no active test mode.

0x1

DA14580 Low Power Bluetooth Smart SoC

1ROTPC_STAT_PERRO

Indicates that an error has occurred during the bit-program-

ming process.

0 - No error during the bit-programming process.

1 - The process of bit-programming failed.

When the controller is in MPROG mode, this bit should be

checked after the end of the programming process

(OTPC_STAT_PRDY= 1).

During APROG mode, the value of this field is normal to

change periodically. Upon finishing the operation in the

APROG mode (OTPC_STAT_ARDY= 1), this field indicates if

the programming has failed or ended succesfully.

0x0

0ROTPC_STAT_PRDY Indicates the state of a bit-programming process.

0 - The controller is busy. A bit-programming is in progress

1 - The logic which performs bit-programming is idle.

When the controller is in MPROG mode, this bit should be

used to monitor the progress of a programming request.

During APROG mode, the value of this field it is normal to

changing periodically.

0x1

Table 7: OTPC_STAT_REG (0x40008008)

Bit Mode Symbol Description Reset

Table 8: OTPC_AHBADR_REG (0x4000800C)

Bit Mode Symbol Description Reset

31:2 R/W OTPC_AHBADR Tthe AHB address used by the AHB master interface of the

controller (

bits [31:2]).

0x0

1:0 --Reserved 0x0

Table 9: OTPC_CELADR_REG (0x40008010)

Bit Mode Symbol Description Reset

31:13 --Reserved 0x0

12:0 R/W OTPC_CELADR Defines a word address inside the macrocell. Used in modes

AREAD and APROG and is automatically updated.

0x0

Table 10: OTPC_NWORDS_REG (0x40008014)

Bit Mode Symbol Description Reset

31:13 --Reserved 0x0

12:0 R/W OTPC_NWORDS The number of words (minus one) for reading/programming

during the AREAD/APROG mode.

If in APROG mode, and the OTPC_MODE_PRG_PORT_SEL

is enabled (=1), this register will not be used and will stay

unchanged.

During mirroring, this register reflects the current amount of

data that will be copied. It keeps its value until be written by

the software with a new value. The number of the words that

remaining to be processed by the controller is contained in

the field OTPC_STAT_NWORDS.

0x0

DA14580 Low Power Bluetooth Smart SoC

Table 11: OTPC_FFPRT_REG (0x40008018)

Bit Mode Symbol Description Reset

31:0 R/W OTPC_FFPRT Provides access to the fifo through an access port. Write this

is selected and the DMA is disabled. Read from this register

the corresponding data, when the AREAD mode is selected

and the DMA is disabled.

Check OTPC_STAT_FWORDS register for data/space availa-

bility, before accessing the fifo.

0x0

Table 12: OTPC_FFRD_REG (0x4000801C)

Bit Mode Symbol Description Reset

31:0 ROTPC_FFRD Contains the value read from the fifo, after a read of the

OTPC_FFPRT_REG register.

0x0

Table 13: PATCH_VALID_REG (0x40008400)

Bit Mode Symbol Description Reset

31:8 --Reserved 0x0

7:0 R/W PATCH_VALID Indicates which patch entry is valid. For example, when bit 0

is high it indicates that entry 0 is valid, i.e. the values of

PATCH_ADDR0_REG / PATCH_DATA0_REG, are effective.

0x0

Table 14: PATCH_VALID_SET_REG (0x40008404)

Bit Mode Symbol Description Reset

31:8 --Reserved 0x0

7:0 R/W PATCH_VALID_SET Writing a bit with 1 will set the corresponding bit of

PATCH_VALID_REG to 1. Writing a bit with 0 is ignored.

Read always as 0.

0x0

Table 15: PATCH_VALID_RESET_REG (0x40008408)

Bit Mode Symbol Description Reset

31:8 --Reserved 0x0

7:0 R/W PATCH_VALID_RESE

Writing a bit with 1 will clear the corresponding bit of

PATCH_VALID_REG to 0. Writing a bit with zero is ignored.

Read always as 0.

0x0

Table 16: PATCH_ADDR0_REG (0x40008410)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the

AHB. If a match occurs, the data bus willl be filled with the

value in the respective PATCH_DATAx_REG. Bits [1:0] are

read-only and always read as "0".

Never use the base address 0x0 for values in

PATCH_ADDRx_REG because HW Patch block is located

after the Address Remapping block.

0x0

DA14580 Low Power Bluetooth Smart SoC

Table 17: PATCH_DATA0_REG (0x40008414)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if

there is a match on the comparison of the address with the

respective PATCH_ADDRx_REG

0x0

Table 18: PATCH_ADDR1_REG (0x40008418)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the

AHB. If a match occurs, the data bus willl be filled with the

value in the respective PATCH_DATAx_REG. Bits [1:0] are

read-only and always read as "0".

Never use the base address 0x0 for values in

PATCH_ADDRx_REG because HW Patch block is located

after the Address Remapping block.

0x0

Table 19: PATCH_DATA1_REG (0x4000841C)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if

there is a match on the comparison of the address with the

respective PATCH_ADDRx_REG

0x0

Table 20: PATCH_ADDR2_REG (0x40008420)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the

AHB. If a match occurs, the data bus willl be filled with the

value in the respective PATCH_DATAx_REG. Bits [1:0] are

read-only and always read as "0".

Never use the base address 0x0 for values in

PATCH_ADDRx_REG because HW Patch block is located

after the Address Remapping block.

0x0

Table 21: PATCH_DATA2_REG (0x40008424)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if

there is a match on the comparison of the address with the

respective PATCH_ADDRx_REG

0x0

Table 22: PATCH_ADDR3_REG (0x40008428)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the

AHB. If a match occurs, the data bus willl be filled with the

value in the respective PATCH_DATAx_REG. Bits [1:0] are

read-only and always read as "0".

Never use the base address 0x0 for values in

PATCH_ADDRx_REG because HW Patch block is located

after the Address Remapping block.

0x0

DA14580 Low Power Bluetooth Smart SoC

Table 23: PATCH_DATA3_REG (0x4000842C)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if

there is a match on the comparison of the address with the

respective PATCH_ADDRx_REG

0x0

Table 24: PATCH_ADDR4_REG (0x40008430)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the

AHB. If a match occurs, the data bus willl be filled with the

value in the respective PATCH_DATAx_REG. Bits [1:0] are

read-only and always read as "0".

Never use the base address 0x0 for values in

PATCH_ADDRx_REG because HW Patch block is located

after the Address Remapping block.

0x0

Table 25: PATCH_DATA4_REG (0x40008434)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if

there is a match on the comparison of the address with the

respective PATCH_ADDRx_REG

0x0

Table 26: PATCH_ADDR5_REG (0x40008438)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the

AHB. If a match occurs, the data bus willl be filled with the

value in the respective PATCH_DATAx_REG. Bits [1:0] are

read-only and always read as "0".

Never use the base address 0x0 for values in

PATCH_ADDRx_REG because HW Patch block is located

after the Address Remapping block.

0x0

Table 27: PATCH_DATA5_REG (0x4000843C)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if

there is a match on the comparison of the address with the

respective PATCH_ADDRx_REG

0x0

Table 28: PATCH_ADDR6_REG (0x40008440)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the

AHB. If a match occurs, the data bus willl be filled with the

value in the respective PATCH_DATAx_REG. Bits [1:0] are

read-only and always read as "0".

Never use the base address 0x0 for values in

PATCH_ADDRx_REG because HW Patch block is located

after the Address Remapping block.

0x0

DA14580 Low Power Bluetooth Smart SoC

Table 29: PATCH_DATA6_REG (0x40008444)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if

there is a match on the comparison of the address with the

respective PATCH_ADDRx_REG

0x0

Table 30: PATCH_ADDR7_REG (0x40008448)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_ADDR This is the value which will be compared to the address on the

AHB. If a match occurs, the data bus willl be filled with the

value in the respective PATCH_DATAx_REG. Bits [1:0] are

read-only and always read as "0".

Never use the base address 0x0 for values in

PATCH_ADDRx_REG because HW Patch block is located

after the Address Remapping block.

0x0

Table 31: PATCH_DATA7_REG (0x4000844C)

Bit Mode Symbol Description Reset

31:0 R/W PATCH_DATA This is the value which will be injected into the data bus if

there is a match on the comparison of the address with the

respective PATCH_ADDRx_REG

0x0

Table 32: CLK_AMBA_REG (0x50000000)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

7R/W OTP_ENABLE Clock enable for OTP controller 0x0

6--Reserved 0x0

5:4 R/W PCLK_DIV APB interface clock (PCLK). Divider is cascaded with

HCLK_DIV. PCLK is HCLK divided by:

0x0: divide by 1

0x1: divide by 2

0x2: divide by 4

0x3: divide by 8

0x2

3:2 --Reserved 0x0

1:0 R/W HCLK_DIV AHB interface and microprocessor clock (HCLK). HCLK is

source clock divided by:

0x0: divide by 1

0x1: divide by 2

0x2: divide by 4

0x3: divide by 8

0x2

Table 33: CLK_FREQ_TRIM_REG (0x50000002)

Bit Mode Symbol Description Reset

15:11 --Reserved 0x0

10:8 R/W COARSE_ADJ Xtal frequency course trimming register.

0x0: lowest frequency

0x7: highest frequencyIncrement or decrement the binary

value with 1. Wait approximately 200 us to allow the adjust-

ment to settle.

0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W FINE_ADJ Xtal frequency fine trimming register.

0x00: lowest frequency

0xFF: highest frequency

0x0

Table 33: CLK_FREQ_TRIM_REG (0x50000002)

Bit Mode Symbol Description Reset

Table 34: CLK_PER_REG (0x50000004)

Bit Mode Symbol Description Reset

15 R/W QUAD_ENABLE Enable the Quadrature clock 0x0

14:13 --Reserved 0x0

11 R/W SPI_ENABLE Enable SPI clock 0x0

10 --Reserved 0x0

9:8 R/W SPI_DIV Division factor for SPI

0x0: divide by 1

0x1: divide by 2

0x2: divide by 4

0x3: divide by 8

0x0

7R/W UART1_ENABLE Enable UART1 clock 0x0

6R/W UART2_ENABLE Enable UART2 clock 0x0

5R/W I2C_ENABLE Enable I2C clock 0x0

4R/W WAKEUPCT_ENABLE Enable Wakeup CaptureTimer clock 0x0

3R/W TMR_ENABLE Enable TIMER0 and TIMER2 clock 0x0

2--Reserved 0x0

1:0 R/W TMR_DIV Division factor for TIMER0

0x0: divide by 1

0x1: divide by 2

0x2: divide by 4

0x3: divide by 8

0x0

Table 35: CLK_RADIO_REG (0x50000008)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

7R/W BLE_ENABLE Enable the BLE core clocks 0x0

6R/W BLE_LP_RESET Reset for the BLE LP timer 0x1

5:4 R/W BLE_DIV Division factor for BLE core blocks

0x0: divide by 1

0x1: divide by 2

0x2: divide by 4

0x3: divide by 8

The programmed frequency should not be lower than 8 MHz

and not faster than the programmed CPU clock frequency.

Refer also to BLE_CNTL2_REG[BLE_CLK_SEL].

0x0

3R/W RFCU_ENABLE Enable the RF control Unit clock 0x0

2--Reserved 0x0

1:0 R/W RFCU_DIV Division factor for RF Control Unit

0x0: divide by 1

0x1: divide by 2

0x2: divide by 4

0x3: divide by 8

The programmed frequency must be exactly 8 MHz.

0x0

DA14580 Low Power Bluetooth Smart SoC

Table 36: CLK_CTRL_REG (0x5000000A)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

7RRUNNING_AT_XTAL1

Indicates that the XTAL16M clock is used as clock, and may

not be switched off

0x1

6RRUNNING_AT_RC16

Indicates that the RC16M clock is used as clock 0x0

5RRUNNING_AT_32K Indicates that either the RC32k or XTAL32k is being used as

clock

0x0

4--Reserved 0x0

3R/W XTAL16M_SPIKE_FLT

_DISABLE

Disable spikefilter in digital clock 0x0

2R/W XTAL16M_DISABLE Setting this bit instantaneously disables the 16 MHz crystal

oscillator. Also, after sleep/wakeup cycle, the oscillator will not

be enabled. This bit may not be set to '1'when

"RUNNING_AT_XTAL16M is '1' to prevent deadlock. After

resetting this bit, wait for XTAL16_SETTLED or

XTAL16_TRIM_READY to become '1' before switching to

XTAL16 clock source.

0x0

1:0 R/W SYS_CLK_SEL Selects the clock source.

0x0: XTAL16M (check the XTAL16_SETTLED and

XTAL16_TRIM_READY bits!!)

0x1: RC16M

0x2/0x3: either RC32k or XTAL32k is used

0x0

Table 37: PMU_CTRL_REG (0x50000010)

Bit Mode Symbol Description Reset

15:12 --Reserved 0x0

11:8 R/W RETENTION_MODE Select the retainability of the 4 retention RAM macros.

'1' is retainable, '0' is power gated.

(3) is RETRAM4

(2) is RETRAM3

(1) is RETRAM2

(0) is RETRAM1

0x0

7R/W FORCE_BOOST Force the DCDC into boost mode at next wakeup.

Setting this bit reduces the deepsleep current.

FORCE_BOOST has highest priority.

When either FORCE_BOOST or FORCE_BUCK have been

written, these bits cannot be changed.

0x0

6R/W FORCE_BUCK Force the DCDC into buck mode at next wakeup.

Setting this bit reduces the deepsleep current.

FORCE_BOOST has highest priority.

When either FORCE_BOOST or FORCE_BUCK have been

written, these bits cannot be changed.

0x0

5:4 R/W OTP_COPY_DIV Sets the HCLK division during OTP mirroring 0x0

2R/W RADIO_SLEEP Put the digital part of the radio in powerdown 0x1

1R/W PERIPH_SLEEP Put all peripherals (I2C, UART, SPI, ADC) in powerdown 0x1

0R/W RESET_ON_WAKEU

Perform a Hardware Reset after waking up. Booter will be

started.

0x0

DA14580 Low Power Bluetooth Smart SoC

Table 38: SYS_CTRL_REG (0x50000012)

Bit Mode Symbol Description Reset

15 WSW_RESET Writing a '1' to this bit will reset the device, except for:

SYS_CTRL_REG

CLK_FREQ_TRIM_REG

...

0x0

9R/W TIMEOUT_DISABLE Disables timeout in Power statemachine. By default, the

statemachine continues if after 2 ms the blocks are not

started up. This can be read back from

ANA_STATUS_REG.

0x0

8--Reserved 0x0

7R/W DEBUGGER_ENABL

Enable the debugger. This bit is set by the booter according to

the OTP header. If not set, the SWDIO and SW_CLK can be

used as gpio ports.

0x0

6R/W OTPC_RESET_REQ Reset request for the OTP controller. 0x0

5R/W PAD_LATCH_EN Latches the control signals of the pads for state retention in

powerdown mode.

0: Control signals are retained

1: Latch is transparant, pad can be recontrolled

0x1

4R/W OTP_COPY Enables OTP to SysRAM copy action after waking up

PD_SYS

0x0

3R/W CLK32_SOURCE Sets the clock source of the 32 kHz clock

0 = RC-oscillator

1 = 32 kHz crystal oscillator

0x0

2R/W RET_SYSRAM Sets the development phase mode.

The PD_SYS is not actually power gated (SysRAM is

retained).

No copy action to SysRAM is done when the system wakes

up.

For emulating startup time, the OTP_COPY bit still needs to

be set.

0x0

1:0 R/W REMAP_ADR0 Controls which memory is located at address 0x0000 for exe-

cution.

0x0: ROM

0x1: OTP

0x2: SysRAM

0x3: RetRAM

0x0

Table 39: SYS_STAT_REG (0x50000014)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

7RXTAL16_SETTLED Indicates that XTAL16 has had > 2 ms of settle time 0x0

6RXTAL16_TRIM_READ

Indicates that XTAL trimming mechanism is ready, i.e. the

trimming equals CLK_FREQ_TRIM_REG.

0x1

5RDBG_IS_UP Indicates that PD_DBG is functional 0x0

4RDBG_IS_DOWN Indicates that PD_DBG is in power down 0x1

3RPER_IS_UP Indicates that PD_PER is functional 0x0

2RPER_IS_DOWN Indicates that PD_PER is in power down 0x1

1RRAD_IS_UP Indicates that PD_RAD is functional 0x0

0RRAD_IS_DOWN Indicates that PD_RAD is in power down 0x1

DA14580 Low Power Bluetooth Smart SoC

Note 1: The period duration of 250 us is derived by dividing the RC16M clock signal by 4000. Consequently, the period duration may vary over tem-

perature.

Table 40: TRIM_CTRL_REG (0x50000016)

Bit Mode Symbol Description Reset

7:4 R/W TRIM_TIME Defines the delay between XTAL16M enable and applying the

CLK_FREQ_TRIM_REG in steps of 250 us.

0x0: apply directly

0x1: wait between 0 and 250 us

0x2: wait between 250 us and 500 us

etc.

(Note 1)

0xA

3:0 R/W SETTLE_TIME Defines the delay between applying CLK_FREQ_TRIM_REG

and XTAL16_SETTLED in steps of 250 us.

0x0: XTAL16_SETTLED is set direcly

0x1: wait between 0 and 250 us

0x2: wait between 250 us and 500 us

etc.

0x2

Table 41: CLK_32K_REG (0x50000020)

Bit Mode Symbol Description Reset

15:13 --Reserved 0x0

12 R/W XTAL32K_DISABLE_

AMPREG

Setting this bit disables the amplitude regulation of the

XTAL32kHz oscillator.

Set this bit to '1' for an external clock applied at XTAL32Kp.

Keep this bit '0' with a crystal between XTAL32Kp and

XTAL32Km.

0x0

11:8 R/W RC32K_TRIM Controls the frequency of the RC32K oscillator.

0x0: lowest frequency

0x7: default

0xF: highest frequency

0x7

7R/W RC32K_ENABLE Enables the 32 kHz RC oscillator 0x1

6:3 R/W XTAL32K_CUR Bias current for the 32kHz XTAL oscillator.

0x0: minimum

0x3: default

0xF: maximum

For each application there is an optimal setting for which the

startup behaviour is optimal.

0x3

2:1 R/W XTAL32K_RBIAS Setting for the bias resistor of the 32 kHz XTAL oscillator.

0x0: maximum

0x3: minimum

Prefered setting will be provided by Dialog.

0x2

0R/W XTAL32K_ENABLE Enables the 32 kHz XTAL oscillator 0x0

Table 42: CLK_16M_REG (0x50000022)

Bit Mode Symbol Description Reset

15:10 --Reserved 0x0

9R/W XTAL16_NOISE_FILT

_ENABLE

Enables noise flter in 16 MHz crystal oscillator 0x0

8R/W XTAL16_BIAS_SH_E

NABLE

Enables Ibias sample/hold function in 16 MHz crystal oscilla-

tor. This bit should be set when the system wake up and reset

before entering deep or extended sleep mode.

0x0

DA14580 Low Power Bluetooth Smart SoC

Note 2: 0xF is the lowest voltage, but is too low for reliable startup at high temperature in combination with extended sleep. 0xA is 100 mV higher

and considered to be the lowest value which is safe to use. 0x0 or 0x1 is again 100 mV higher and 0x0 is the reset value. 0x4 is the maxi-

mum voltage.

7:5 R/W XTAL16_CUR_SET Bias current for the 16 MHz XTAL oscillator.

0x0: minimum

0x7: maximum

0x5

4:1 R/W RC16M_TRIM Controls the frequency of the RC16M oscillator.

0x0: lowest frequency

0xF: highest frequency

0x0

0R/W RC16M_ENABLE Enables the 16 MHz RC oscillator 0x0

Table 42: CLK_16M_REG (0x50000022)

Bit Mode Symbol Description Reset

Table 43: CLK_RCX20K_REG (0x50000024)

Bit Mode Symbol Description Reset

12 R/W RCX20K_SELECT Selects RCX oscillator.

0 : RC32K oscillator

1: RCX oscillator

11 R/W RCX20K_ENABLE Enable the RCX oscillator 0

10 R/W RCX20K_LOWF Extra low frequency 0

9:8 R/W RCX20K_BIAS Bias control 1

7:4 R/W RCX20K_NTC Temperature control 7

3:0 R/W RCX20K_TRIM Controls the frequency of the RCX oscillator.

0x0: lowest frequency

0x7: default

0xF: highest frequency

Table 44: BANDGAP_REG (0x50000028)

Bit Mode Symbol Description Reset

15 --Reserved 0x0

14 R/W BGR_LOWPOWER Test-mode, do not use.

It disables the bandgap core (voltages will continue for some

time, but will slowely drift away)

0x0

13:10 R/W LDO_RET_TRIM (Note 2) 0x0

9:5 R/W BGR_ITRIM Current trimming for bias 0x0

4:0 R/W BGR_TRIM Trim register for bandgap 0x0

Table 45: ANA_STATUS_REG (0x5000002A)

Bit Mode Symbol Description Reset

15:10 --Reserved 0x0

9RBOOST_SELECTED Indicates that DCDC is in boost mode 0x0

8--Reserved 0x0

7RBANDGAP_OK Indicates that BANDGAP is OK 0x1

6RBOOST_VBAT_OK Indicates that VBAT is above threshold while in BOOST con-

verter mode.

0x0

5RLDO_ANA_OK Indicates that LDO_ANA is in regulation. This LDO is used for

the general-purpose ADC only

0x0

4RLDO_VDD_OK Indicates that LDO_VDD is in regulation 0x1

3RLDO_OTP_OK Indicates that LDO_OTP is in regulation 0x0

DA14580 Low Power Bluetooth Smart SoC

2RVDCDC_OK Indicates that VDCDC is above threshold. 0x0

1RVBAT1V_OK Indicates that VBAT1V is above threshold. 0x0

0RVBAT1V_AVAILABLE Indicates that VBAT1V is available. 0x0

Table 45: ANA_STATUS_REG (0x5000002A)

Bit Mode Symbol Description Reset

Table 46: WKUP_CTRL_REG (0x50000100)

Bit Mode Symbol Description Reset

15:14 --Reserved 0x0

7R/W WKUP_ENABLE_IRQ 0: no interrupt will be enabled

1: if the event counter reaches the value set by

WKUP_COMPARE_REG an IRQ will be generated

0x0

6R/W WKUP_SFT_KEYHIT 0: no effect

1: emulate key hit. The event counter will increment by 1

(after debouncing if enabled). First make this bit 0 before any

new key hit can be sensed.

0x0

5:0 R/W WKUP_DEB_VALUE Keyboard debounce time (N*1 ms with N = 1 to 63).

0x0: no debouncing

0x1 to 0x3F: 1 ms to 63 ms debounce time

0x0

Table 47: WKUP_COMPARE_REG (0x50000102)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

7:0 R/W COMPARE The number of events that have to be counted before the

wakeup interrupt will be given

0x0

Table 48: WKUP_RESET_IRQ_REG (0x50000104)

Bit Mode Symbol Description Reset

15:0 WWKUP_IRQ_RST writing any value to this register will reset the interrupt. read-

ing always returns 0.

0x0

Table 49: WKUP_COUNTER_REG (0x50000106)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

7:0 REVENT_VALUE This value represents the number of events that have been

counted so far. It will be reset by resetting the interrupt.

0x0

Table 50: WKUP_RESET_CNTR_REG (0x50000108)

Bit Mode Symbol Description Reset

15:0 WWKUP_CNTR_RST writing any value to this register will reset the event counter 0x0

Table 51: WKUP_SELECT_P0_REG (0x5000010A)

Bit Mode Symbol Description Reset

7:0 R/W WKUP_SELECT_P0 0: input P0x is not enabled for wakeup event counter

1: input P0x is enabled for wakeup event counter

0x0

DA14580 Low Power Bluetooth Smart SoC

Table 52: WKUP_SELECT_P1_REG (0x5000010C)

Bit Mode Symbol Description Reset

5:0 R/W WKUP_SELECT_P1 0: input P1x is not enabled for wakeup event counter

1: input P1x is enabled for wakeup event counter

0x0

Table 53: WKUP_SELECT_P2_REG (0x5000010E)

Bit Mode Symbol Description Reset

9:0 R/W WKUP_SELECT_P2 0: input P2x is not enabled for wakeup event counter

1: input P2x is enabled for wakeup event counter

0x0

Table 54: WKUP_SELECT_P3_REG (0x50000110)

Bit Mode Symbol Description Reset

7:0 R/W WKUP_SELECT_P3 0: input P3x is not enabled for wakeup event counter

1: input P3x is enabled for wakeup event counter

0x0

Table 55: WKUP_POL_P0_REG (0x50000112)

Bit Mode Symbol Description Reset

7:0 R/W WKUP_POL_P0 0: enabled input P0x will increment the event counter if that

input goes high

1: enabled input P0x will increment the event counter if that

input goes low

0x0

Table 56: WKUP_POL_P1_REG (0x50000114)

Bit Mode Symbol Description Reset

5:0 R/W WKUP_POL_P1 0: enabled input P1x will increment the event counter if that

input goes high

1: enabled input P1x will increment the event counter if that

input goes low

0x0

Table 57: WKUP_POL_P2_REG (0x50000116)

Bit Mode Symbol Description Reset

9:0 R/W WKUP_POL_P2 0: enabled input P2x will increment the event counter if that

input goes high

1: enabled input P2x will increment the event counter if that

input goes low

0x0

Table 58: WKUP_POL_P3_REG (0x50000118)

Bit Mode Symbol Description Reset

7:0 R/W WKUP_POL_P3 0: enabled input P3x will increment the event counter if that

input goes high

1: enabled input P3x will increment the event counter if that

input goes low

0x0

Table 59: QDEC_CTRL_REG (0x50000200)

Bit Mode Symbol Description Reset

15:10 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

9:3 R/W QD_IRQ_THRES The number of events on either counter (X or Y) that need to

be reached before an interrupt is generated. If 0 is written,

then threshold is considered to be 1.

0x2

2RQD_IRQ_STATUS Interrupt Status. If 1 an interrupt has occured. 0x0

1R/W QD_IRQ_CLR Writing 1 to this bit clears the interrupt. This bit is autocleared 0x0

0R/W QD_IRQ_MASK 0: interrupt is masked

1: interrupt is enabled

0x0

Table 59: QDEC_CTRL_REG (0x50000200)

Bit Mode Symbol Description Reset

Table 60: QDEC_XCNT_REG (0x50000202)

Bit Mode Symbol Description Reset

15:0 RX_COUNTER Contains a signed value of the events. Zero when channel is

disabled

0x0

Table 61: QDEC_YCNT_REG (0x50000204)

Bit Mode Symbol Description Reset

15:0 RY_COUNTER Contains a signed value of the events. Zero when channel is

disabled

0x0

Table 62: QDEC_CLOCKDIV_REG (0x50000206)

Bit Mode Symbol Description Reset

9:0 R/W CLOCK_DIVIDER Contains the number of the input clock cycles minus one, that

are required to generate one logic clock cycle.

0x0

Table 63: QDEC_CTRL2_REG (0x50000208)

Bit Mode Symbol Description Reset

15:12 --Reserved 0

11:8 R/W CHZ_PORT_SEL Defines which GPIOs are mapped on Channel Z

0: none

1: P0[0] -> CHZ_A, P0[1] -> CHZ_B

2: P0[2] -> CHZ_A, P0[3] -> CHZ_B

3: P0[4] -> CHZ_A, P0[5] -> CHZ_B

4: P0[6] -> CHZ_A, P0[7] -> CHZ_B

5: P1[0] -> CHZ_A, P1[1] -> CHZ_B

6: P1[2] -> CHZ_A, P1[3] -> CHZ_B

7: P2[3] -> CHZ_A, P2[4] -> CHZ_B

8: P2[5] -> CHZ_A, P2[6] -> CHZ_B

9: P2[7] -> CHZ_A, P2[8] -> CHZ_B

10: P2[9] -> CHZ_A, P2[0] -> CHZ_B

11..15: None

DA14580 Low Power Bluetooth Smart SoC

7:4 R/W CHY_PORT_SEL Defines which GPIOs are mapped on Channel Y

0: none

1: P0[0] -> CHY_A, P0[1] -> CHY_B

2: P0[2] -> CHY_A, P0[3] -> CHY_B

3: P0[4] -> CHY_A, P0[5] -> CHY_B

4: P0[6] -> CHY_A, P0[7] -> CHY_B

5: P1[0] -> CHY_A, P1[1] -> CHY_B

6: P1[2] -> CHY_A, P1[3] -> CHY_B

7: P2[3] -> CHY_A, P2[4] -> CHY_B

8: P2[5] -> CHY_A, P2[6] -> CHY_B

9: P2[7] -> CHY_A, P2[8] -> CHY_B

10: P2[9] -> CHY_A, P2[0] -> CHY_B

11..15: None

3:0 R/W CHX_PORT_SEL Defines which GPIOs are mapped on Channel X

0: none

1: P0[0] -> CHX_A, P0[1] -> CHX_B

2: P0[2] -> CHX_A, P0[3] -> CHX_B

3: P0[4] -> CHX_A, P0[5] -> CHX_B

4: P0[6] -> CHX_A, P0[7] -> CHX_B

5: P1[0] -> CHX_A, P1[1] -> CHX_B

6: P1[2] -> CHX_A, P1[3] -> CHX_B

7: P2[3] -> CHX_A, P2[4] -> CHX_B

8: P2[5] -> CHX_A, P2[6] -> CHX_B

9: P2[7] -> CHX_A, P2[8] -> CHX_B

10: P2[9] -> CHX_A, P2[0] -> CHX_B

11..15: None

Table 63: QDEC_CTRL2_REG (0x50000208)

Bit Mode Symbol Description Reset

Table 64: QDEC_ZCNT_REG (0x5000020A)

Bit Mode Symbol Description Reset

15:0 RZ_COUNTER Contains a signed value of the events. Zero when channel is

disabled

Table 65: UART_RBR_THR_DLL_REG (0x50001000)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W RBR_THR_DLL Receive Buffer Register: This register contains the data byte

received on the serial input port (sin) in UART mode or the

serial infrared input (sir_in) in infrared mode. The data in this

tus Register (LSR) is set. If FIFOs are disabled (FCR[0] set to

zero), the data in the RBR must be read before the next data

arrives, otherwise it will be overwritten, resulting in an overrun

error. If FIFOs are enabled (FCR[0] set to one), this register

accesses the head of the receive FIFO. If the receive FIFO is

full and this register is not read before the next data character

arrives, then the data already in the FIFO will be preserved

but any incoming data will be lost. An overrun error will also

occur. Transmit Holding Register: This register contains data

to be transmitted on the serial output port (sout) in UART

mode or the serial infrared output (sir_out_n) in infrared

mode. Data should only be written to the THR when the THR

Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost. Divisor Latch (Low): This

sor Latch register that contains the baud rate divisor for the

UART. This register may only be accessed when the DLAB bit

(LCR[7]) is set. The output baud rate is equal to the serial

clock (sclk) frequency divided by sixteen times the value of

the baud rate divisor, as follows: baud rate = (serial clock freq)

/ (16 * divisor) Note that with the Divisor Latch Registers (DLL

and DLH) set to zero, the baud clock is disabled and no serial

communications will occur. Also, once the DLL is set, at least

8 clock cycles of the slowest DW_apb_uart clock should be

allowed to pass before transmitting or receiving data.

0x0

Table 65: UART_RBR_THR_DLL_REG (0x50001000)

Bit Mode Symbol Description Reset

Table 66: UART_IER_DLH_REG (0x50001004)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

7R/W PTIME_DLH7 Interrupt Enable Register: PTIME, Programmable THRE

Interrupt Mode Enable. This is used to enable/disable the

generation of THRE Interrupt. 0 = disabled 1 = enabled Divi-

sor Latch (High): Bit[7] of the 8 bit DLH register.

0x0

6:4 --Reserved 0x0

3R/W EDSSI_DLH3 Interrupt Enable Register: EDSSI, Enable Modem Status

Interrupt. This is used to enable/disable the generation of

Modem Status Interrupt. This is the fourth highest priority

interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[3]

of the 8 bit DLH register

0x0

2R/W ELSI_DHL2 Interrupt Enable Register: ELSI, Enable Receiver Line Status

Interrupt. This is used to enable/disable the generation of

Receiver Line Status Interrupt. This is the highest priority

interrupt. 0 = disabled 1 = enabled Divisor Latch (High): Bit[2]

of the 8 bit DLH register.

0x0

DA14580 Low Power Bluetooth Smart SoC

1R/W ETBEI_DLH1 Interrupt Enable Register: ETBEI, Enable Transmit Holding

generation of Transmitter Holding Register Empty Interrupt.

This is the third highest priority interrupt. 0 = disabled 1 = ena-

bled Divisor Latch (High): Bit[1] of the 8 bit DLH register.

0x0

0R/W ERBFI_DLH0 Interrupt Enable Register: ERBFI, Enable Received Data

Available Interrupt. This is used to enable/disable the genera-

tion of Received Data Available Interrupt and the Character

Timeout Interrupt (if in FIFO mode and FIFO's enabled).

These are the second highest priority interrupts. 0 = disabled

1 = enabled Divisor Latch (High): Bit[0] of the 8 bit DLH regis-

ter.

0x0

Table 66: UART_IER_DLH_REG (0x50001004)

Bit Mode Symbol Description Reset

Table 67: UART_IIR_FCR_REG (0x50001008)

Bit Mode Symbol Description Reset

15:0 R/W IIR_FCR Interrupt Identification Register, reading this register; FIFO

Control Register, writing to this register. Interrupt Identification

to indicate whether the FIFO's are enabled or disabled. 00 =

disabled. 11 = enabled. Bits[3:0], Interrupt ID (or IID): This

indicates the highest priority pending interrupt which can be

one of the following types: 0000 = modem status. 0001 = no

interrupt pending. 0010 = THR empty. 0100 = received data

available. 0110 = receiver line status. 0111 = busy detect.

1100 = character timeout. Bits[7:6], RCVR Trigger (or RT):.

This is used to select the trigger level in the receiver FIFO at

which the Received Data Available Interrupt will be gener-

ated. In auto flow control mode it is used to determine when

the rts_n signal will be de-asserted. It also determines when

the dma_rx_req_n signal will be asserted when in certain

modes of operation. The following trigger levels are sup-

ported: 00 = 1 character in the FIFO 01 = FIFO 1/4 full 10 =

FIFO 1/2 full 11 = FIFO 2 less than full Bits[5:4], TX Empty

Trigger (or TET): This is used to select the empty threshold

level at which the THRE Interrupts will be generated when the

mode is active. It also determines when the dma_tx_req_n

signal will be asserted when in certain modes of operation.

The following trigger levels are supported: 00 = FIFO empty

01 = 2 characters in the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/

2 full Bit[3], DMA Mode (or DMAM): This determines the DMA

signalling mode used for the dma_tx_req_n and

dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 Bit[2],

XMIT FIFO Reset (or XFIFOR): This resets the control portion

of the transmit FIFO and treats the FIFO as empty. Note that

this bit is 'self-clearing' and it is not necessary to clear this bit.

Bit[1], RCVR FIFO Reset (or RFIFOR): This resets the control

portion of the receive FIFO and treats the FIFO as empty.

Note that this bit is 'self-clearing' and it is not necessary to

clear this bit. Bit[0], FIFO Enable (or FIFOE): This enables/

disables the transmit (XMIT) and receive (RCVR) FIFO's.

Whenever the value of this bit is changed both the XMIT and

RCVR controller portion of FIFO's will be reset.

0x0

DA14580 Low Power Bluetooth Smart SoC

Table 68: UART_LCR_REG (0x5000100C)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

7R/W UART_DLAB Divisor Latch Access Bit.

This bit is used to enable reading and writing of the Divisor

Latch register (DLL and DLH) to set the baud rate of the

UART.

This bit must be cleared after initial baud rate setup in order to

access other registers.

0x0

6R/W UART_BC Break Control Bit.

This is used to cause a break condition to be transmitted to

the receiving device. If set to one the serial output is forced to

the spacing (logic 0) state. When not in Loopback Mode, as

determined by MCR[4], the sout line is forced low until the

Break bit is cleared. If active (MCR[6] set to one) the

sir_out_n line is continuously pulsed. When in Loopback

Mode, the break condition is internally looped back to the

receiver and the sir_out_n line is forced low.

0x0

5--Reserved 0x0

4R/W UART_EPS Even Parity Select.

This is used to select between even and odd parity, when par-

ity is enabled (PEN set to one). If set to one, an even number

of logic 1s is transmitted or checked. If set to zero, an odd

number of logic 1s is transmitted or checked.

0x0

3R/W UART_PEN Parity Enable.

This bit is used to enable and disable parity generation and

detection in transmitted and received serial character respec-

tively.

0 = parity disabled

1 = parity enabled

0x0

2R/W UART_STOP Number of stop bits.

This is used to select the number of stop bits per character

that the peripheral transmits and receives. If set to zero, one

stop bit is transmitted in the serial data.

If set to one and the data bits are set to 5 (LCR[1:0] set to

zero) one and a half stop bits is transmitted. Otherwise, two

stop bits are transmitted. Note that regardless of the number

of stop bits selected, the receiver checks only the first stop bit.

0 = 1 stop bit

1 = 1.5 stop bits when DLS (LCR[1:0]) is zero, else 2 stop bit

0x0

1:0 R/W UART_DLS Data Length Select.

This is used to select the number of data bits per character

that the peripheral transmits and receives. The number of bit

that may be selected areas follows:

00 = 5 bits

01 = 6 bits

10 = 7 bits

11 = 8 bits

0x0

Table 69: UART_MCR_REG (0x50001010)

Bit Mode Symbol Description Reset

15:7 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

6R/W UART_SIRE SIR Mode Enable.

This is used to enable/disable the IrDA SIR Mode features as

described in "IrDA 1.0 SIR Protocol" on page 53.

0 = IrDA SIR Mode disabled

1 = IrDA SIR Mode enabled

0x0

5R/W UART_AFCE Auto Flow Control Enable.

When FIFOs are enabled and the Auto Flow Control Enable

(AFCE) bit is set, hardware Auto Flow Control is enabled via

CTS and RTS.

0 = Auto Flow Control Mode disabled

1 = Auto Flow Control Mode enabled

0x0

4R/W UART_LB LoopBack Bit.

This is used to put the UART into a diagnostic mode for test

purposes.

If operating in UART mode (SIR_MODE not active, MCR[6]

set to zero), data on the sout line is held high, while serial

data output is looped back to the sin line, internally. In this

mode all the interrupts are fully functional. Also, in loopback

mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n)

are disconnected and the modem control outputs (dtr_n,

rts_n, out1_n, out2_n) are looped back to the inputs, inter-

nally.

If operating in infrared mode (SIR_MODE active, MCR[6] set

to one), data on the sir_out_n line is held low, while serial data

output is inverted and looped back to the sir_in line.

0x0

3R/W UART_OUT2 OUT2.

This is used to directly control the user-designated Output2

(out2_n) output. The value written to this location is inverted

and driven out on out2_n, that is:

0 = out2_n de-asserted (logic 1)

1 = out2_n asserted (logic 0)

Note that in Loopback mode (MCR[4] set to one), the out2_n

output is held inactive high while the value of this location is

internally looped back to an input.

0x0

2R/W UART_OUT1 OUT1.

This is used to directly control the user-designated Output1

(out1_n) output. The value written to this location is inverted

and driven out on out1_n, that is:

0 = out1_n de-asserted (logic 1)

1 = out1_n asserted (logic 0)

Note that in Loopback mode (MCR[4] set to one), the out1_n

output is held inactive high while the value of this location is

internally looped back to an input.

0x0

Table 69: UART_MCR_REG (0x50001010)

Bit Mode Symbol Description Reset

DA14580 Low Power Bluetooth Smart SoC

1R/W UART_RTS Request to Send.

This is used to directly control the Request to Send (rts_n)

output. The Request To Send (rts_n) output is used to inform

the modem or data set that the UART is ready to exchange

data.

When Auto Flow Control is disabled (MCR[5] set to zero), the

rts_n signal is set low by programming MCR[1] (RTS) to a

high. When Auto Flow Control is enabled (MCR[5] set to one)

and FIFOs are enabled (FCR[0] set to one), the rts_n output

is controlled in the same way, but is also gated with the

receiver FIFO threshold trigger (rts_n is inactive high when

above the threshold). The rts_n signal is de-asserted when

MCR[1] is set low.

Note that in Loopback mode (MCR[4] set to one), the rts_n

output is held inactive (high) while the value of this location is

internally looped back to an input.

0x0

0--Reserved 0x0

Table 69: UART_MCR_REG (0x50001010)

Bit Mode Symbol Description Reset

Table 70: UART_LSR_REG (0x50001014)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

7RUART_RFE Receiver FIFO Error bit.

This bit is only relevant when FIFOs are enabled (FCR[0] set

to one). This is used to indicate if there is at least one parity

error, framing error, or break indication in the FIFO.

0 = no error in RX FIFO

1 = error in RX FIFO

This bit is cleared when the LSR is read and the character

with the error is at the top of the receiver FIFO and there are

no subsequent errors in the FIFO.

0x0

6RUART_TEMT Transmitter Empty bit.

If FIFOs enabled (FCR[0] set to one), this bit is set whenever

the Transmitter Shift Register and the FIFO are both empty. If

FIFOs are disabled, this bit is set whenever the Transmitter

Holding Register and the Transmitter Shift Register are both

empty.

0x1

5RUART_THRE Transmit Holding Register Empty bit.

If THRE mode is disabled (IER[7] set to zero) and regardless

of FIFO's being implemented/enabled or not, this bit indicates

that the THR or TX FIFO is empty.

This bit is set whenever data is transferred from the THR or

TX FIFO to the transmitter shift register and no new data has

been written to the THR or TX FIFO. This also causes a

THRE Interrupt to occur, if the THRE Interrupt is enabled. If

both modes are active (IER[7] set to one and FCR[0] set to

one respectively), the functionality is switched to indicate the

transmitter FIFO is full, and no longer controls THRE inter-

rupts, which are then controlled by the FCR[5:4] threshold

setting.

0x1

DA14580 Low Power Bluetooth Smart SoC

4RUART_B1 Break Interrupt bit.

This is used to indicate the detection of a break sequence on

the serial input data.

If in UART mode (SIR_MODE == Disabled), it is set whenever

the serial input, sin, is held in a logic '0' state for longer than

the sum of start time + data bits + parity + stop bits.

If in infrared mode (SIR_MODE == Enabled), it is set when-

ever the serial input, sir_in, is continuously pulsed to logic '0'

for longer than the sum of start time + data bits + parity + stop

bits. A break condition on serial input causes one and only

one character, consisting of all zeros, to be received by the

UART.

In the FIFO mode, the character associated with the break

condition is carried through the FIFO and is revealed when

the character is at the top of the FIFO.

Reading the LSR clears the BI bit. In the non-FIFO mode, the

BI indication occurs immediately and persists until the LSR is

read.

0x0

3RUART_FE Framing Error bit.

This is used to indicate the occurrence of a framing error in

the receiver. A framing error occurs when the receiver does

not detect a valid STOP bit in the received data.

In the FIFO mode, since the framing error is associated with a

character received, it is revealed when the character with the

framing error is at the top of the FIFO.

When a framing error occurs, the UART tries to resynchro-

nize. It does this by assuming that the error was due to the

start bit of the next character and then continues receiving the

other bit i.e. data, and/or parity and stop. It should be noted

that the Framing Error (FE) bit (LSR[3]) is set if a break inter-

rupt has occurred, as indicated by Break Interrupt (BI) bit

(LSR[4]).

0 = no framing error

1 = framing error

Reading the LSR clears the FE bit.

0x0

2RUART_PE Parity Error bit.

This is used to indicate the occurrence of a parity error in the

receiver if the Parity Enable (PEN) bit (LCR[3]) is set.

In the FIFO mode, since the parity error is associated with a

character received, it is revealed when the character with the

parity error arrives at the top of the FIFO.

It should be noted that the Parity Error (PE) bit (LSR[2]) is set

if a break interrupt has occurred, as indicated by Break Inter-

rupt (BI) bit (LSR[4]).

0 = no parity error

1 = parity error

Reading the LSR clears the PE bit.

0x0

Table 70: UART_LSR_REG (0x50001014)

Bit Mode Symbol Description Reset

DA14580 Low Power Bluetooth Smart SoC

1RUART_OE Overrun error bit.

This is used to indicate the occurrence of an overrun error.

This occurs if a new data character was received before the

previous data was read.

In the non-FIFO mode, the OE bit is set when a new character

arrives in the receiver before the previous character was read

from the RBR. When this happens, the data in the RBR is

overwritten. In the FIFO mode, an overrun error occurs when

the FIFO is full and a new character arrives at the receiver.

The data in the FIFO is retained and the data in the receive

shift register is lost.

0 = no overrun error

1 = overrun error

Reading the LSR clears the OE bit.

0x0

0RUART_DR Data Ready bit.

This is used to indicate that the receiver contains at least one

character in the RBR or the receiver FIFO.

0 = no data ready

1 = data ready

This bit is cleared when the RBR is read in non-FIFO mode,

or when the receiver FIFO is empty, in FIFO mode.

0x0

Table 70: UART_LSR_REG (0x50001014)

Bit Mode Symbol Description Reset

Table 71: UART_MSR_REG (0x50001018)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

7RUART_DCD Data Carrier Detect.

This is used to indicate the current state of the modem control

line dcd_n. This bit is the complement of dcd_n. When the

Data Carrier Detect input (dcd_n) is asserted it is an indica-

tion that the carrier has been detected by the modem or data

set.

0 = dcd_n input is de-asserted (logic 1)

1 = dcd_n input is asserted (logic 0)

In Loopback Mode (MCR[4] set to one), DCD is the same as

MCR[3] (Out2).

0x0

6RUART_R1 Ring Indicator.

This is used to indicate the current state of the modem control

line ri_n. This bit is the complement of ri_n. When the Ring

Indicator input (ri_n) is asserted it is an indication that a tele-

phone ringing signal has been received by the modem or data

set.

0 = ri_n input is de-asserted (logic 1)

1 = ri_n input is asserted (logic 0)

In Loopback Mode (MCR[4] set to one), RI is the same as

MCR[2] (Out1).

0x0

5--Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

4RUART_CTS Clear to Send.

This is used to indicate the current state of the modem control

line cts_n. This bit is the complement of cts_n. When the

Clear to Send input (cts_n) is asserted it is an indication that

the modem or data set is ready to exchange data with the

UART Ctrl.

0 = cts_n input is de-asserted (logic 1)

1 = cts_n input is asserted (logic 0)

In Loopback Mode (MCR[4] = 1), CTS is the same as MCR[1]

(RTS).

0x0

3RUART_DDCD Delta Data Carrier Detect.

This is used to indicate that the modem control line dcd_n has

changed since the last time the MSR was read.

0 = no change on dcd_n since last read of MSR

1 = change on dcd_n since last read of MSR

Reading the MSR clears the DDCD bit. In Loopback Mode

(MCR[4] = 1), DDCD reflects changes on MCR[3] (Out2).

Note, if the DDCD bit is not set and the dcd_n signal is

asserted (low) and a reset occurs (software or otherwise),

then the DDCD bit is set when the reset is removed if the

dcd_n signal remains asserted.

0x0

2RUART_TERI Trailing Edge of Ring Indicator.

This is used to indicate that a change on the input ri_n (from

an active-low to an inactive-high state) has occurred since the

last time the MSR was read.

0 = no change on ri_n since last read of MSR

1 = change on ri_n since last read of MSR

Reading the MSR clears the TERI bit. In Loopback Mode

(MCR[4] = 1), TERI reflects when MCR[2] (Out1) has

changed state from a high to a low.

0x0

1--Reserved 0x0

0RUART_DCTS Delta Clear to Send.

This is used to indicate that the modem control line cts_n has

changed since the last time the MSR was read.

0 = no change on cts_n since last read of MSR

1 = change on cts_n since last read of MSR

Reading the MSR clears the DCTS bit. In Loopback Mode

(MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS).

Note, if the DCTS bit is not set and the cts_n signal is

asserted (low) and a reset occurs (software or otherwise),

then the DCTS bit is set when the reset is removed if the

cts_n signal remains asserted.

0x0

Table 71: UART_MSR_REG (0x50001018)

Bit Mode Symbol Description Reset

Table 72: UART_SCR_REG (0x5000101C)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

7:0 R/W UART_SCRATCH_PA

This register is for programmers to use as a temporary stor-

age space. It has no defined purpose in the UART Ctrl.

0x0

Table 73: UART_LPDLL_REG (0x50001020)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W UART_LPDLL This register makes up the lower 8-bits of a 16-bit, read/write,

Low Power Divisor Latch register that contains the baud rate

divisor for the UART, which must give a baud rate of 115.2K.

This is required for SIR Low Power (minimum pulse width)

detection at the receiver. This register may be accessed only

when the DLAB bit (LCR[7]) is set.

The output low-power baud rate is equal to the serial clock

(sclk) frequency divided by sixteen times the value of the

baud rate divisor, as follows:

Low power baud rate = (serial clock frequency)/(16* divisor)

Therefore, a divisor must be selected to give a baud rate of

115.2K.

NOTE: When the Low Power Divisor Latch registers (LPDLL

and LPDLH) are set to 0, the low-power baud clock is disa-

bled and no low-power pulse detection (or any pulse detec-

tion) occurs at the receiver. Also, once the LPDLL is set, at

least eight clock cycles of the slowest UART Ctrl clock should

be allowed to pass before transmitting or receiving data.

0x0

Table 73: UART_LPDLL_REG (0x50001020)

Bit Mode Symbol Description Reset

Table 74: UART_LPDLH_REG (0x50001024)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

7:0 R/W UART_LPDLH This register makes up the upper 8-bits of a 16-bit, read/write,

Low Power Divisor Latch register that contains the baud rate

divisor for the UART, which must give a baud rate of 115.2K.

This is required for SIR Low Power (minimum pulse width)

detection at the receiver. This register may be accessed only

when the DLAB bit (LCR[7]) is set.

The output low-power baud rate is equal to the serial clock

(sclk) frequency divided by sixteen times the value of the

baud rate divisor, as follows:

Low power baud rate = (serial clock frequency)/(16* divisor)

Therefore, a divisor must be selected to give a baud rate of

115.2K.

NOTE: When the Low Power Divisor Latch registers (LPDLL

and LPDLH) are set to 0, the low-power baud clock is disa-

bled and no low-power pulse detection (or any pulse detec-

tion) occurs at the receiver. Also, once the LPDLH is set, at

least eight clock cycles of the slowest UART Ctrl clock should

be allowed to pass before transmitting or receiving data.

0x0

Table 75: UART_SRBR_STHR0_REG (0x50001030)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 75: UART_SRBR_STHR0_REG (0x50001030)

Bit Mode Symbol Description Reset

Table 76: UART_SRBR_STHR1_REG (0x50001034)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 76: UART_SRBR_STHR1_REG (0x50001034)

Bit Mode Symbol Description Reset

Table 77: UART_SRBR_STHR2_REG (0x50001038)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 77: UART_SRBR_STHR2_REG (0x50001038)

Bit Mode Symbol Description Reset

Table 78: UART_SRBR_STHR3_REG (0x5000103C)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 78: UART_SRBR_STHR3_REG (0x5000103C)

Bit Mode Symbol Description Reset

Table 79: UART_SRBR_STHR4_REG (0x50001040)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 79: UART_SRBR_STHR4_REG (0x50001040)

Bit Mode Symbol Description Reset

Table 80: UART_SRBR_STHR5_REG (0x50001044)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 80: UART_SRBR_STHR5_REG (0x50001044)

Bit Mode Symbol Description Reset

Table 81: UART_SRBR_STHR6_REG (0x50001048)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 81: UART_SRBR_STHR6_REG (0x50001048)

Bit Mode Symbol Description Reset

Table 82: UART_SRBR_STHR7_REG (0x5000104C)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 82: UART_SRBR_STHR7_REG (0x5000104C)

Bit Mode Symbol Description Reset

Table 83: UART_SRBR_STHR8_REG (0x50001050)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 83: UART_SRBR_STHR8_REG (0x50001050)

Bit Mode Symbol Description Reset

Table 84: UART_SRBR_STHR9_REG (0x50001054)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 84: UART_SRBR_STHR9_REG (0x50001054)

Bit Mode Symbol Description Reset

Table 85: UART_SRBR_STHR10_REG (0x50001058)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 85: UART_SRBR_STHR10_REG (0x50001058)

Bit Mode Symbol Description Reset

Table 86: UART_SRBR_STHR11_REG (0x5000105C)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 86: UART_SRBR_STHR11_REG (0x5000105C)

Bit Mode Symbol Description Reset

Table 87: UART_SRBR_STHR12_REG (0x50001060)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 87: UART_SRBR_STHR12_REG (0x50001060)

Bit Mode Symbol Description Reset

Table 88: UART_SRBR_STHR13_REG (0x50001064)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 88: UART_SRBR_STHR13_REG (0x50001064)

Bit Mode Symbol Description Reset

Table 89: UART_SRBR_STHR14_REG (0x50001068)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 89: UART_SRBR_STHR14_REG (0x50001068)

Bit Mode Symbol Description Reset

Table 90: UART_SRBR_STHR15_REG (0x5000106C)

Bit Mode Symbol Description Reset

15:8 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

7:0 R/W SRBR_STHRX Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 90: UART_SRBR_STHR15_REG (0x5000106C)

Bit Mode Symbol Description Reset

Table 91: UART_USR_REG (0x5000107C)

Bit Mode Symbol Description Reset

15:5 --Reserved 0x0

4RUART_RFF Receive FIFO Full.

This is used to indicate that the receive FIFO is completely

full.

0 = Receive FIFO not full

1 = Receive FIFO Full

This bit is cleared when the RX FIFO is no longer full.

0x0

3RUART_RFNE Receive FIFO Not Empty.

This is used to indicate that the receive FIFO contains one or

more entries.

0 = Receive FIFO is empty

1 = Receive FIFO is not empty

This bit is cleared when the RX FIFO is empty.

0x0

2RUART_TFE Transmit FIFO Empty.

This is used to indicate that the transmit FIFO is completely

empty.

0 = Transmit FIFO is not empty

1 = Transmit FIFO is empty

This bit is cleared when the TX FIFO is no longer empty.

0x1

DA14580 Low Power Bluetooth Smart SoC

1RUART_TFNF Transmit FIFO Not Full.

This is used to indicate that the transmit FIFO in not full.

0 = Transmit FIFO is full

1 = Transmit FIFO is not full

This bit is cleared when the TX FIFO is full.

0x1

0--Reserved 0x0

Table 91: UART_USR_REG (0x5000107C)

Bit Mode Symbol Description Reset

Table 92: UART_TFL_REG (0x50001080)

Bit Mode Symbol Description Reset

15:0 RUART_TRANSMIT_FI

FO_LEVEL

Transmit FIFO Level.

This is indicates the number of data entries in the transmit

FIFO.

0x0

Table 93: UART_RFL_REG (0x50001084)

Bit Mode Symbol Description Reset

15:0 RUART_RECEIVE_FIF

O_LEVEL

Receive FIFO Level.

This is indicates the number of data entries in the receive

FIFO.

0x0

Table 94: UART_SRR_REG (0x50001088)

Bit Mode Symbol Description Reset

15:3 --Reserved 0x0

2WUART_XFR XMIT FIFO Reset.

This is a shadow register for the XMIT FIFO Reset bit

(FCR[2]). This can be used to remove the burden on software

having to store previously written FCR values (which are

pretty static) just to reset the transmit FIFO. This resets the

control portion of the transmit FIFO and treats the FIFO as

empty. Note that this bit is 'self-clearing'. It is not necessary to

clear this bit.

0x0

1WUART_RFR RCVR FIFO Reset.

This is a shadow register for the RCVR FIFO Reset bit

(FCR[1]). This can be used to remove the burden on software

having to store previously written FCR values (which are

pretty static) just to reset the receive FIFO This resets the

control portion of the receive FIFO and treats the FIFO as

empty.

Note that this bit is 'self-clearing'. It is not necessary to clear

this bit.

0x0

0WUART_UR UART Reset. This asynchronously resets the UART Ctrl and

synchronously removes the reset assertion. For a two clock

implementation both pclk and sclk domains are reset.

0x0

Table 95: UART_SRTS_REG (0x5000108C)

Bit Mode Symbol Description Reset

15:1 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

0R/W UART_SHADOW_RE

QUEST_TO_SEND

Shadow Request to Send.

This is a shadow register for the RTS bit (MCR[1]), this can be

used to remove the burden of having to perform a read-mod-

ify-write on the MCR. This is used to directly control the

Request to Send (rts_n) output. The Request To Send (rts_n)

output is used to inform the modem or data set that the UART

Ctrl is ready to exchange data.

When Auto Flow Control is disabled (MCR[5] = 0), the rts_n

signal is set low by programming MCR[1] (RTS) to a high.

When Auto Flow Control is enabled (MCR[5] = 1) and FIFOs

are enabled (FCR[0] = 1), the rts_n output is controlled in the

same way, but is also gated with the receiver FIFO threshold

trigger (rts_n is inactive high when above the threshold).

Note that in Loopback mode (MCR[4] = 1), the rts_n output is

held inactive-high while the value of this location is internally

looped back to an input.

0x0

Table 95: UART_SRTS_REG (0x5000108C)

Bit Mode Symbol Description Reset

Table 96: UART_SBCR_REG (0x50001090)

Bit Mode Symbol Description Reset

15:1 --Reserved 0x0

0R/W UART_SHADOW_BR

EAK_CONTROL

Shadow Break Control Bit.

This is a shadow register for the Break bit (LCR[6]), this can

be used to remove the burden of having to performing a read

modify write on the LCR. This is used to cause a break condi-

tion to be transmitted to the receiving device.

If set to one the serial output is forced to the spacing (logic 0)

state. When not in Loopback Mode, as determined by

MCR[4], the sout line is forced low until the Break bit is

cleared.

If SIR_MODE active (MCR[6] = 1) the sir_out_n line is contin-

uously pulsed. When in Loopback Mode, the break condition

is internally looped back to the receiver.

0x0

Table 97: UART_SDMAM_REG (0x50001094)

Bit Mode Symbol Description Reset

15:1 --Reserved 0x0

0R/W UART_SHADOW_DM

A_MODE

Shadow DMA Mode.

This is a shadow register for the DMA mode bit (FCR[3]). This

can be used to remove the burden of having to store the pre-

viously written value to the FCR in memory and having to

mask this value so that only the DMA Mode bit gets updated.

This determines the DMA signalling mode used for the

dma_tx_req_n and dma_rx_req_n output signals.

0 = mode 0

1 = mode 1

0x0

Table 98: UART_SFE_REG (0x50001098)

Bit Mode Symbol Description Reset

15:1 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

0R/W UART_SHADOW_FIF

O_ENABLE

Shadow FIFO Enable.

This is a shadow register for the FIFO enable bit (FCR[0]).

This can be used to remove the burden of having to store the

previously written value to the FCR in memory and having to

mask this value so that only the FIFO enable bit gets

updated.This enables/disables the transmit (XMIT) and

receive (RCVR) FIFOs. If this bit is set to zero (disabled) after

being enabled then both the XMIT and RCVR controller por-

tion of FIFOs are reset.

0x0

Table 98: UART_SFE_REG (0x50001098)

Bit Mode Symbol Description Reset

Table 99: UART_SRT_REG (0x5000109C)

Bit Mode Symbol Description Reset

15:2 --Reserved 0x0

1:0 R/W UART_SHADOW_RC

VR_TRIGGER

Shadow RCVR Trigger.

This is a shadow register for the RCVR trigger bits (FCR[7:6]).

This can be used to remove the burden of having to store the

previously written value to the FCR in memory and having to

mask this value so that only the RCVR trigger bit gets

updated.

This is used to select the trigger level in the receiver FIFO at

which the Received Data Available Interrupt is generated. It

also determines when the dma_rx_req_n signal is asserted

when DMA Mode (FCR[3]) = 1. The following trigger levels

are supported:

00 = 1 character in the FIFO

01 = FIFO Â¼ full

10 = FIFO Â½ full

11 = FIFO 2 less than full

0x0

Table 100: UART_STET_REG (0x500010A0)

Bit Mode Symbol Description Reset

15:2 --Reserved 0x0

1:0 R/W UART_SHADOW_TX

_EMPTY_TRIGGER

Shadow TX Empty Trigger.

This is a shadow register for the TX empty trigger bits

(FCR[5:4]). This can be used to remove the burden of having

to store the previously written value to the FCR in memory

and having to mask this value so that only the TX empty trig-

ger bit gets updated.

This is used to select the empty threshold level at which the

THRE Interrupts are generated when the mode is active. The

following trigger levels are supported:

00 = FIFO empty

01 = 2 characters in the FIFO

10 = FIFO Â¼ full

11 = FIFO Â½ full

0x0

Table 101: UART_HTX_REG (0x500010A4)

Bit Mode Symbol Description Reset

15:1 --Reserved 0x0

DA14580 Low Power Bluetooth Smart SoC

0R/W UART_HALT_TX This register is use to halt transmissions for testing, so that

the transmit FIFO can be filled by the master when FIFOs are

implemented and enabled.

0 = Halt TX disabled

1 = Halt TX enabled

Note, if FIFOs are implemented and not enabled, the setting

of the halt TX register has no effect on operation.

0x0

Table 101: UART_HTX_REG (0x500010A4)

Bit Mode Symbol Description Reset

Table 102: UART_CPR_REG (0x500010F4)

Bit Mode Symbol Description Reset

15:0 RCPR Component Parameter Register 0x0

Table 103: UART_UCV_REG (0x500010F8)

Bit Mode Symbol Description Reset

15:0 RUCV Component Version 0x333038

Table 104: UART_CTR_REG (0x500010FC)

Bit Mode Symbol Description Reset

15:0 RCTR Component Type Register 0x445701

Table 105: UART2_RBR_THR_DLL_REG (0x50001100)