PRELIMINARY
Spread Spectrum 3 DIMM Desktop Clock
W48S87-04
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 19, 199 9, r ev. **
Features
• Outputs
—4 CPU Clock (2.5V or 3.3V, 50 to 83.3 MHz)
—7 PCI (3.3V)
—1 48-MHz for USB (3.3V)
—1 24-MHz for Super I/O (3.3V)
—2 REF (3.3V)
—1 IOAPIC (2.5V or 3.3V)
—12 SDRAM
• Serial data interf ace provides additional f requency
select ion, indi vidual clock output disable, and other
functions
• Smooth transi tion supports dynamic frequency
assignment
• Frequency selection not aff ected during power
down/up cycle
• Suppor ts a variet y of power-saving options
• 3.3V oper ati on
• Available in 48-pi n SSO P (300 mil s)
Key Specifications
±0.5% Spread Spectrum Modulati on: ... .. ......... ..... ......±0.5%
Jitte r (C y c le -t o -C y c l e ):........ ..... ....... ........ ..... ....... ..... ....25 0 p s
Du t y C yc l e:... ..... ........ .... ........ ..... ....... ..... ....... ..... .......4 5 -5 5 %
CP U-P C I S kew:. ... .. ....... ..... ........ .... ........ ....... ..... ......1 to 4 ns
PC I -P C I or CP U -C P U S kew:. .. ..... ....... ..... ....... ..... .......25 0 ps
Notes:
1. Additional frequency selections provided by serial data interface; refer to Table 5 on page 10.
2. Signal names in parenthesis denotes function is selectable through mode pin register strapping.
Tabl e 1. Pin Selectabl e Frequency[1]
Input Address CPU, SDRAM
Clocks (MHz) PCI Clocks
(MHz)FS2 FS1 FS0
0 0 0 50.0 25.0
0 0 1 75.0 32.0
0 1 0 83.3 41.65
0 1 1 68.5 34.25
1 0 0 55.0 27.5
1 0 1 75.0 37.5
1 1 0 60.0 30.0
1 1 1 66.8 33.4
Block Diagram Pin Configurat ion[2]
VDD1
IOAPIC
VDD3
SDRAM0:11
PCI_F/FS1
PCI0/FS2
XTAL OSC
PLL Re f
PLL1
X2
X1
REF1(CPU_STOP#)
Stop
Clock
Cntrl
PCI1:4
PWR_DWN# Power Down
Control
PCI5(PWR_DWN#)
48MHZ/FS0
24MHZ/MODE
PLL2
Serial Port
SCLOCK
SDATA Device
CPU_STOP#
Control
CPU3.3#_2.5 CPU Clock
Mode Control
÷4
÷2
I/O
I/O
VDD1
MODE
4
I/O
I/O
VDD2
12
CPU0:3
4VDDL2
÷2
VDDL1
MODE
I/O REF0/CPU3.3#_2.5
Freq
Select
FS0
FS1
FS2
Freq
VDD1
REF0/CPU3.3#_2.5
GND
X1
X2
VDD2
PCI_F/FS1
PCI0/FS2
GND
PCI1
PCI2
PCI3
PCI4
VDD2
PCI5(PWR_DWN#)
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLOCK
W48S87-04
VDDL1
IOAPIC
REF1(CPU_STOP#)
GND
CPU0
CPU1
VDDL2
CPU2
CPU3
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
GND
48MHZ/FS0
24MHZ/MODE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
W48S87-04
PRELIMINARY
2
Pin Definitions
Pin Name Pin
No. Pin
Type Pin Descr iption
CPU0:3 44, 43, 41,
40 OCPU Clock Outputs 0 through 3: These four CPU clock outputs are controlled
by the CPU_ST O P# control pin. Output voltage swing is controlled by voltage
applied to VDDL2 and output characteristics are adjusted b y input
CPU3.3#_2.5.
PCI_F/FS1 7 I/O Fixed PCI Clock Output and Frequency Selection Bit 1: As an output, this
pin work s in conjunction with PCI0: 5. Output voltage swing is controll ed by
voltage applied to VDD2.
When an input, this pin functions as part of the frequency selection address.
The value of FS0:2 determines the power-up def ault frequency of device output
clocks as per the Table 1, “Pin Selectable Frequency” on page 1.
PCI0/FS2 8 I/O PCI Bus Clock Output 0 and Freq uency Selection Bi t 2: As an output, this
pin work s in conjunction with PCI1:5 and PCI_F. Output voltage swing is con-
trolled by volta ge applied to VDD2.
When an input, this pin functions as part of the frequency selection address.
The value of FS0:2 determines the power-up def ault frequency of device output
clocks as per the Table 1, “Pin Selectable Frequency” on page 1.
PCI1:4 10, 11, 12,
13 OPCI Bus Clock Outputs 1 through 4: Output voltage swing is controlled by
voltage applied to VDD2.
PCI5(PWR_DWN#) 15 I/O PCI Bus Clock Output 5 or Power-Down Contr ol: As an output, this pin works
in conj unction with PCI0:4 and PCI_F. Output voltage s w ing is controll ed by
voltage applied to VDD2.
If pr ogr ammed as an in put (ref er to MODE pin descri ption ), this pi n is used for
power-do wn control. When LOW, the de vice goes into a lo w-power standby
condition. All outputs are activel y hel d LO W while in power-down. CPU ,
SDRAM, and PCI cl ock out put s are sto pped LO W after completi ng a full cloc k
cycl e ( 2–4 CPU cl oc k cyc le l atency) . Wh en broug ht HIGH, CPU , SDRAM , an d
PCI outputs start with a full clock cycle at f ull operating frequency (3 ms max-
imum latency).
SDRAM0:11 38, 37, 35,
34, 32, 31,
29, 28, 21,
20, 18, 17
OSDRAM Clock Outp uts 0 through 11: These twelve SDRAM clock outputs
run synchronous to the CPU clock ou tput s. Outp ut voltage swing i s controlle d
by voltage appl ied to VDD3.
IOAPIC 47 O I/O APIC Cloc k Output : Pro vides 14.318-MHz fixed frequency. The output
voltage swing is controll ed by VDDL1.
48MHZ/FS0 26 I/O 48-MHz Output and Frequency Selection Bit 0: Fixed clock output that de-
f aul ts to 48 MHz fol lo wing de vi ce pow er- up. Out put v oltage s wing is control led
by voltage appl ied to VDD1.
When an input, this pin functions as part of the frequency selection address.
The value of FS0:2 determines the power-up def ault frequency of device output
clocks as per the Table 1, “Pin Selectable Frequency” on page 1.
24MHZ/MODE 25 I/O 24-MHz Output and Mode Co ntro l Input: Fixed clock output t hat defaults to
24 MHz following device power-up. Output voltage swing is control led by volt-
age applied to VDD1.
When an input, this pin is used for pin programming sele cti on. It determines
the functions f or pin s 15 and 46:
MODE Pin 15 Pin 46
0 PWR_DWN# (input) CPU_STOP# (input)
1 PCI5 (out put) REF1 (output)
W48S87-04
PRELIMINARY
3
REF0/CPU3.3#_2.5 2 I/O Fixed 14.318-MHz Output 0 and CPU Output Voltage Swing Selection
Input: As an output , this pin is used for vari ous system applicat ions. Output
v oltage swing is cont roll ed by v olt age appli ed to VDD1. REF0 is stro nger than
REF1 and should be used for drivi ng ISA slots.
When an input, this pi n selects the CPU clock ou tput buff er char acteristics th at
are optimized for either 3.3V or 2.5V operation.
CPU3.3#_2. 5 VDDQ2 Voltage (CPU0: 3 Swing)
03.3V
12.5V
This input adjusts CPU cl ock outpu t impedance so that a nominal 20Ω output
impedance is maintained. Thi s eliminates or reduces the need to adjust exter-
nal clock tuning components when changing VDDL2 voltage. CPU clock phase
is also adju sted so that both CPU and SDRAM and CPU-to-PCI clo c k ske w is
maintained over the two VDDL2 vol tage options. This in put does not adjust
IOAPIC clock output char acteristics .
REF1(CPU_Stop#) 46 I/O Fixed 14.318-MHz Out put 0 or CPU Clock Output Stop Contr ol: Used for
vario us system applications. Output voltage swing is contr olled by voltage ap-
plied to VDD1. REF0 is stronger than REF 1 and should be us ed for driving ISA
slots.
If pr ogr ammed as an in put (ref er to MODE pin descri ption ), this pi n is used for
stoppi ng the CPU clock outputs. When brought LOW, clock outputs CPU0:3
are stopped LOW afte r completing a ful l clock cycle (2–3 C PU clock latency).
When brought HIGH, clock outputs CPU0:3 are starting begi nning with a full
cl o ck cyc l e (2–3 CPU clock latency).
X1 4 I Crystal Connection or External Reference Frequency Input: This pi n has
dual functions. It can be use d as an external 14.318- M H z crystal connection
or as an external reference frequency input.
X2 5 I Crystal Connect ion: An inpu t conn ect ion for an e x ternal 14. 318- MHz c rystal .
If using an external reference, this pin must be lef t unconnected.
SDATA 23 I Seri al Data Input: Da ta inp ut for Seri a l Dat a In terface. Refer to Serial Data
Interface section that follows.
SCLOCK 24 I Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data
Interface section that follows.
VDD1 1 P Power Connection: Power sup p ly for crystal oscillator an d R EF0:1 output
buffers. Connected to 3.3V supply.
VDD2 6,14 P Power Connec ti on: Po wer supply for PCI cl ock output buffers. Connected to
3.3V supply.
VDDL1 48 P Power Connection: Power supply for IOAPIC output buffer . Connected to 2.5V
or 3.3V suppl y.
VDDL2 42 P P owe r Co nnection: Po wer suppl y for CPU cl ock out put b u ff ers. Co nnected to
2.5V or 3.3V supply.
VDD3 19, 30, 36 P Power Connection: Power supply for SDRAM clock output buffers. Connected
to 3.3V suppl y.
GND 3, 9, 16, 22,
27, 33, 39,
45
GGround Connection: Connec t all g rou nd pins to the com mon system ground
plane.
Pin Definitions (continued)
Pin Name Pin
No. Pin
Type Pin Descr iption
W48S87-04
PRELIMINARY
4
Overview
The W48S87-04, a motherboard clock synthesizer, can pro-
vide either a 2.5V or 3.3V CPU clock s w ing, ma king it suitable
for a variety of CPU options. Twelve SDRAM clocks are pro-
vide d in phase wi th the CPU clock output s. This pro vides clock
support for up to three SDRAM DlMMs. Fixed output frequency
clocks are provided for other system fu nctions.
Functional Description
I/O Pin Operation
Pins 2, 7, 8, 25, and 26 are dual-purpose l/O pins. Upon power-
up th ese pi ns act as logic in puts, al lowi ng the determinat ion of
assigned device functions. A short time after power-up, the
logic state of these pins is latched and the pins then become
clock outputs. This feature reduces device pin count by com-
bini ng clock outputs with input select pins.
An exter nal 10-kΩ “strapping” resistor is connected between
each l /O pin and gr ound or VDD3. Connecti on to gr ound s ets a
latch to “0”, connection to VDD3 sets a latch to “1”. Figure 1 an d
Figure 2 show two suggested methods for strapping resistor
connection.
Upon W48S8 7-04 pow er-up , the firs t 2 ms of oper ation is used
for input logic selection. During this period, these dual-purpose
I/O pi ns are thr ee-stated, allowing t he output s trappin g resisto r
on each l/O pin to pull the pin and its associated capacitive
clock load to either a logic HIGH or LOW state. At the end of
the 2-ms period, the established logic 0 or 1 condition of each
l/O is pin is t hen latched. Nex t the output buffers are enabled,
which conver ts the l/O pins into operating clock outputs. The
2-ms timer is started when VDD reaches 2.0V. The input bits
can only be reset by turning VDD off and then back on again.
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of bo th clock outputs i s <40Ω (nominal ) which is minimal -
ly affected by the 10-kΩ strap to ground or VDD. As with the
series termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
ground or VDD should be kept less than two inches in length
to preven t system noise coupling during input logic sampling.
When the clock outputs are enabled following the 2-ms input
period, targe t (normal) output f requenc y is deliv ered assuming
that VDD has stabili zed. If VDD has not yet reached f ull value,
output frequenc y init ially m ay be bel ow tar get but will incre ase
to target once VDD voltage has stabilized. In either case, a
short output clock cycle may be produced from the CPU clock
outputs when the outputs are enabled.
Power-on
Reset
Timer Output Three-state
Data
Latch
Hold
QD
W48S87-04
VDD
Clo ck Lo ad
22Ω
10 kΩ
Output
Buffer
(Load Option 1)
10 kΩ
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selec tion Thr ough Resistor Load Option
Power-on
Reset
Timer Output Three-state
Data
Latch
Hold
QD
W48S87-04
VDD
Clo ck Lo ad
R
10 kΩ
Output
Buffer
Output
Low
Output Strapping Resistor
Series Termination Resistor
J umper Options
Figure 2. Input Logic Sele ction Through Jum per Option
Resistor Value R
39Ω
33Ω
Output
IOAPIC, SDRAM
All other clo ck outputs
W48S87-04
PRELIMINARY
5
CPU/PCI Frequency Selection
CPU frequency is selected with I/O pins 26, 7, and 8
(48MHz/FS0, PCI_F/FS1, and PCI0/FS2, respec ti vely). Refer
to Table 1 for CPU/PCI frequency programming information.
Addit ional frequenc y select ions ar e availab le th rough the se ri-
al data inter face. Refer to Table 5 on page 10.
Output Buffer Configuration
Clock Outputs
All clock outputs are designed to drive serial terminat ed cl ock
li nes. T he W48S87- 04 output s are CM OS-type , which pr ovid e
rail-to-rail output swing. To accommodate the limited voltage
swing required by some processors, the output buffers of
CPU0:3 use a special VDDL2 power supply pin that can be
tied to 2.5V nominal.
Crystal Oscillator
The W48S87 -04 requires one input reference clock to synthe-
size all output frequencies. The refer ence clock can be either
an e xt erna lly gen erate d cloc k si gnal or the cl oc k gen erate d by
the internal crystal oscillator. When using an external clock
signal , pin X1 is used as t he clock input and pin X2 is left open.
The input threshold volta ge of pin X1 is VDD/2.
The internal crystal oscillator is used in conjunction with a
quartz cryst al con nected t o device pi ns X 1 and X2. Th is f orms
a parallel resonant crystal oscillator circuit. The W48S87-04
incorpor ates the nece ssary fee dbac k resi stor and cryst al load
capacit ors . In cludi ng typi ca l str ay ci rcuit capacit anc e, the to tal
load presented to the crystal is approximately 20 pF. For opti-
mum frequency accuracy without the addition of exter nal ca-
pacitors, a parallel-resona nt mode cryst al specifyi ng a load of
20 pF should be used. This will typically yield reference fre-
quency accuracies wit hin ±100 ppm.
Dual Supply Voltage Operation
The W48S87- 04 is designed for dual powe r supply operation.
Supply pi ns VDD1, VDD2, and VDD3 are co nnect ed to a 3. 3V
supply and supply power to the internal core circuit and to t he
clock output buf fers, ex cept for outputs CPU0: 3 and IOAPIC.
Supply pins VDDL1 and VDDL2 may be c onnected to either a
2.5V or 3.3V supply.
W48S87-04
PRELIMINARY
6
Spread Sp ectr u m Ge n er ator
The device generates a clock that is frequency modulated in
order to increa se the bandwidth that it occu pies. By increas ing
the bandwi dth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 3.
As depicted in Figure 3, a harmonic of a modulated clock has
a much lower amplitude than that of an unmodulated signal.
The reduction in amplitude is dependent on the harmonic num-
ber and the frequency deviation or spread. The equation for
the reduction is
dB = 6.5 + 9*log10(P) + 9*log10(F)
Where P is the per centage of de viat ion and F is the f requency
in MHz where the reduction is me asured.
The output clock is modulated with a waveform depicted in
Figure 4. This waveform, as discussed in “Spread Spectrum
Cloc k Gener ation f or the Reduction of Radiated Emiss ions” by
Bush, Fessler, and Hardin produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
devi at ion sel ected f o r this chip i s ±0.5% of the ce nter fr equen -
cy. Figure 4 details the Cypress spreading pattern. Cypress
does offer options with more spread and greater EMI reduc-
tion. Contact your local Sales representative for details on
these device s.
Spread Spectrum clocking is activated or deactivated by se-
lecti ng the approp riate v alues f or bit s 1–0 in data byte 0 of the
I2C data stream. Refer to Table 4 for mor e d e ta ils.
Figure 3. Clock Harmonic with and wit hout SSCG Modulation Frequency Domain Representati on
SSFTG Typical C lock
Frequenc y Span (MH z) +1.0
-SS% +SS%
Amplitude (dB)
5dB/div
Figure 4. Typical Modulation Profile
MAX (+.0.5%)
MIN. (–0.5%)
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
FREQUENCY
W48S87-04
PRELIMINARY
7
Serial Da ta Interface
The W48S87-04 features a two- pin, serial data i nt erface that
can be used to configure internal registe r set ting s that co ntrol
particular device functions. Upon power-up, the W48S87-04
ini tialize s with def ault registe r set tings, theref ore the use of t his
serial data interface is optional. The serial interface is write-
only (to the clock chip) and is the dedicated function of devic e
pins SDATA and SCLOCK. In motherboard applications,
SDATA and SCLOCK are typically dri ven by two logic out puts
of the chipset. Clock device register changes are normally
made upon syst em initia li zation, i f any are required. The inter-
fa ce can also be used duri ng system operat ion fo r power man-
agement functions. Table 2 summarizes the control functions
of the serial data inter face .
Operation
Data is written to the W48S87-04 in ten bytes of eight bits
each. Bytes are written in the order shown i n Table 3.
Table 2. Serial Data Interface Control Func ti ons Sum mary
Control Functi on Description Co mmon Application
Clock Output Disable Any individual clock output(s) ca n be disab led. Dis-
abled outpu ts are active ly held LO W. Unuse d outputs are disab led to reduce EM I
and system power . Examples are clock out-
puts to unu sed SDRAM DIMM socket or PCI
slot.
CPU Clock Frequency
Selection Provides CPU/PCI frequency selections beyond the
50- and 66.8- M Hz selections that are pro vided by
the FS0:2 po wer-on def ault se lecti on. Fr equency is
changed in a smooth and controll ed fashion.
For alternate CPU devices, and pow er man-
agement options. Smooth frequency transi-
tion all ows CPU frequen cy change un der n or-
mal system operation.
Output Three-state Puts all clock outputs into a high-im pedance state. Production PCB testing.
Test Mode All clock outputs toggle in relation with X1 input ,
internal PLL is b ypassed. Refer to Ta ble 4.Pr oduction PCB testing.
(Reserved) Reserved function f or future device revision or pro-
duction devi c e test in g. No user appl icat ion. Regi ster bit must be writ-
ten as 0.
Table 3. Byte W riting Sequence
Byte Sequence Byte Nam e Bit Sequence Byte Descri ption
1 Slave Address 11010010 Commands the W48S87-04 t o accept the bits in Data Byte s 0–6 for
internal register configuration. Since other devices may exist on the
same common seri al data b us, it is necess ary to hav e a specific sla ve
address for each potential receiver. The slave receiver address for the
W48S87-0 4 is 1101 0010. Re giste r setting wi ll not be made if the Slav e
Add ress i s n ot correct (o r is for an alt e rn ate slave r e ce i ve r ) .
2 Command
Code Don’t Care Unused by the W48S87-04, therefor e bit values are ignored (“don’t
care”). This byte must be included in the data write sequence to maintain
proper b yte allocati on. The Command Co de Byte is part of the standar d
serial communication protocol and may be used when writing to another
addressed slave receiver on the serial dat a bus.
3 Byte Count Don’t Care Unused by the W48S87-04, therefore bit values are ignored (“don’t
care”). This byte must be included in the data write sequence to maintain
proper byte allocation. The Byte Count Byte is part of the standard serial
communi cation protoc ol and may be used when writing to another ad-
dressed sla ve receiver on the serial data bus.
4 Data Byte 0 Refer to Ta ble 4 The data bits in these bytes set internal W48S87-04 registers that con-
trol devic e operati on. The dat a bits are only a ccepted when the Address
Byte bit sequence is 110 10010, as noted above. F or description of bit
control functions, refer to Table 4, Data Byte Serial Configuration Map.
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6
W48S87-04
PRELIMINARY
8
Writing D a ta Bytes
Each bit in the data bytes control a par ticular device functi on
except f or th e “reserved” bits which must be writt en as a logic
0. Bits are written MSB (most signi ficant bit) f irst, which is bit
7. Tabl e 4 gives the bit formats for registers located in Data
Bytes 0–6. Table 5 details addi tional frequency sel ectio ns that
are available through the serial data interface. Table 6 de tai ls
the select functions for Byte 0, bi ts 1 and 0.
Table 4. Data Byt es 0–6 Serial Conf iguration Map
Bit(s)
Affected Pin
Control Function
Bit Control
DefaultPin No. Pin Name 0 1
Data Byte 0
7-- --(Reserved) -- -- 0
6 -- -- BYT0_SEL2 Refer to Table 5 0
5 -- -- BYT0_SEL1 Refer to Table 5 0
4 -- -- BYT0_SEL0 Refer to Table 5 0
3 BYT0 _FS# Frequency
Control le d by
FS (2:0)
Frequency
Controlled by
BYT0_SEL (2:0)
0
222 (Reserved) 0
1–0 -- -- Bit 1 Bit 0 Function (See Table 6 for function details)
0 0 Normal Operation
01 Test Mode
1 0 Spread Spectrum On
1 1 All Outputs Three-st ated
00
Data Byte 1
7 26 48MHZ Clock Output Disable Low Acti ve 1
6 25 24MHZ Clock Output Disable Low Acti ve 1
5-- --(Reserved) -- -- 0
4-- --(Reserved) -- -- 0
3 40 CPU3 Clock Output Disable Low Acti ve 1
2 41 CPU2 Clock Output Disable Low Acti ve 1
1 43 CPU1 Clock Output Disable Low Acti ve 1
0 44 CPU0 Clock Output Disable Low Acti ve 1
Data Byte 2
7-- --(Reserved) -- -- 0
6 7 PCI_F Clock Output Disable Low Acti ve 1
5 15 PCI 5 Clock Output Disable Low Acti ve 1
4 13 PCI 4 Clock Output Disable Low Acti ve 1
3 12 PCI 3 Clock Output Disable Low Acti ve 1
2 11 PCI 2 Clock Output Disable Low Acti ve 1
1 10 PCI 1 Clock Output Disable Low Acti ve 1
0 8 PCI0 Clock Output Disable Low Active 1
W48S87-04
PRELIMINARY
9
Data Byte 3
7 28 SDRAM7 Clock Output Disable Low Active 1
6 29 SDRAM6 Clock Output Disable Low Active 1
5 31 SDRAM5 Clock Output Disable Low Active 1
4 32 SDRAM4 Clock Output Disable Low Active 1
3 34 SDRAM3 Clock Output Disable Low Active 1
2 35 SDRAM2 Clock Output Disable Low Active 1
1 37 SDRAM1 Clock Output Disable Low Active 1
0 38 SDRAM0 Clock Output Disable Low Active 1
Data Byte 4
7-- --(Reserved) -- -- 0
6-- --(Reserved) -- -- 0
5-- --(Reserved) -- -- 0
4-- --(Reserved) -- -- 0
3 17 SDRAM11 Cl ock Output Disable Low Active 1
2 18 SDRAM10 Cl ock Output Disable Low Active 1
1 20 SDRAM9 Clock Output Disable Low Active 1
0 21 SDRAM8 Clock Output Disable Low Active 1
Data Byte 5
7-- --(Reserved) -- -- 0
5-- --(Reserved) -- -- 0
5-- --(Reserved) -- -- 0
4 47 IOAPIC Clock Output Disable Low Acti ve 1
3-- --(Reserved) -- -- 0
2-- --(Reserved) -- -- 0
1 46 REF1 Clock Output Disable Low Active 1
0 2 REF0 Clock Output Disable Low Active 1
Data Byte 6
7-- --(Reserved) -- -- 0
6-- --(Reserved) -- -- 0
5-- --(Reserved) -- -- 0
4-- --(Reserved) -- -- 0
3-- --(Reserved) -- -- 0
2-- --(Reserved) -- -- 0
1-- --(Reserved) -- -- 0
0-- --(Reserved) -- -- 0
Table 4. Data Byt es 0–6 Serial Conf iguration Map (continued)
Bit(s)
Affected Pin
Control Function
Bit Control
DefaultPin No. Pin Name 0 1
W48S87-04
PRELIMINARY
10
Note:
3. CPU, SDRAM, and PCI frequency selections are listed in Table 1 and Table 5.
4. In Test Mode, the 48/24MHz clock outputs are:
- X1/2 for 48-MHz output.
- X1/4 for 24-MHz output.
Table 5. Additional Frequenc y Selections t hrough Serial Data Interface Data Byt es
Input Condi ti ons Output Frequency
Data Byte 0, Bit 3 = 1
CPU, SDRAM Clocks
(MHz) PCI Clocks
(MHz)
Bit 6
BYT0_SEL2 Bit 5
BYT0_SEL1 Bit 4
BYT0_SEL0
0 0 0 50 25
00175.032
0 1 0 83.3 41.65
0 1 1 68.5 34.25
1 0 0 55.0 27.5
1 0 1 75.0 37.5
1 1 0 60.0 30.0
1 1 1 66.8 33.4
Table 6. Select Function for Data Byte 0, Bits 0:1
Function
Input Conditions Output Condi ti ons
Data Byte 0 CPU0:3,
SRAM0:11 PCI_F,
PC I0 : 5 RE F 0 :1 , IOAPI C 48 /2 4 M H ZB it 1 Bit 0
Normal Operation 0 0 No te 3 Note 3 14.318 MHz 48/24 MHz
Test Mode 0 1 X1/2 X1/4 X1 Note 4
Spread Spectrum 1 0 Note 3
SS±0.5% Note 3
SS±0.5% 14.3 18 MHz 48/24 MHz
Three-state 1 1 Hi-Z Hi-Z Hi-Z Hi-Z
W48S87-04
PRELIMINARY
11
How To Use the Serial Data Interface
Electrical Requi rements
Figur e 5 ill ustr ates el ec trical ch ar acteri stics f or the seri al i nter-
face bus used with the W48S87-04. Devices send data over
the b us with an open dr ain logic output that can ( a) pull the bus
li ne LO W, or (b ) let the b u s def au lt t o logi c 1. The pu ll- up resi s-
tors on t he bus ( both clock and data lines) establish a default
logic 1. All bus devices generally have logic inputs t o receive
data.
Although the W48S87-04 is a receive-only device (no data
write-back capability), it does transmit an “acknowledge” data
pulse after each byte is received. Thus, the SDATA line can
both transmit and receive data.
The pull-up resist or should be sized to meet the rise and fal l
times s peci fie d in A C p ar ameters , takin g int o con sider ation to -
tal bus line capacitance.
DATA IN
DATA OUT
N
CLOCK IN
CLOCK OUT
CHIP SET
(SERIAL BUS MASTER TRANSMITTER)
SDCLK SDATA
SERIAL BUS CLOCK LINE
SERIAL BUS DATA LINE
N
DATA IN
DATA OUT
CLOCK IN
CLOCK DEVICE
(SERIAL BUS SLAVE RECEIVER)
SCLOCK SDATA
N
~ 2k
Ω
~ 2k
Ω
VDD VDD
Figure 5. Serial Interface Bus Electrical Characteristics
W48S87-04
PRELIMINARY
12
Si g na l ing Re quir e m en ts
As sho wn in Figur e 6, val id data bi ts are defined as stable lo gic
0 or 1 condition on the data line during a clock HIGH (logi c 1)
puls e. A tr ansit ionin g data li ne during a cloc k HI GH pulse ma y
be interpreted as a start or stop pulse (it will be interpreted as
a start or stop pulse if the start/stop timing parameters are
met).
A write seque nce i s ini tiated b y a “st art bit ” as shown i n Figure
7. A “stop bit ” signifies that a transmission has ended.
As st at ed previousl y, t he W48 S87-04 s ends an “acknowledge”
pulse after receiving eight data bits in each byte as shown in
Figure 8.
Sending Data t o the W48S87-04
The device accepts data once it has detected a valid start bit
and address byte sequence. Device functionality is changed
upon the rec eipt of each data bit (regi sters are not double buf f-
ered). P arti al tr ansmission is all owed meaning t hat a tran smis-
sion can be truncated as soon as the desired data bits are
tran smitted ( remaini ng registers wil l be u nmodified) . Tran smis-
sion is truncated with either a stop bit or new star t bit (rest art
condition).
SDATA
SCLOCK
Valid
Data
Bit
Change
of Data Allowed
Figure 6. Serial Data Bus Valid Data Bit
SDATA
SCLOCK
Start
Bit Stop
Bit
Figure 7. Serial Data Bus Start and Stop Bit
W48S87-04
PRELIMINARY
13
MSB
12345678A12345678A 1234SCLOCK 12345678A
11010010LSB MSB MSB LSBSDATA
SDATA
Signaling from System Core Logic
Start Condition
MSB LSB
Slave Address
(First Byte) Command Code
(Second Byte) Last Data Byte
(Last Byte)
Byte Count
(Third By te)
Stop Condition
Signaling by Clock Device Acknowledgment Bit
from Clock Device
Figure 8. Serial Data Bus Wri te Sequence
tSTHD
tLOW
tR
tHIGH
tF
tDSU tDHD tSP
tSPSU tSTHD
tSPSU
tSPF
SDATA
SCLOCK
Figure 9. Serial Data Bus Timing Diagr am
W48S87-04
PRELIMINARY
14
Absolute Maximum Ratings
Stre sses g reater th an tho se listed i n this t able may cause per-
mane nt damage to the de vice. These represent a stress rat ing
only. Operation of the device at these or any other conditions
above those specified in the operating sect ions of this spec if i-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
.
Parameter Description Rating Unit
VDD, VIN Vol tage on any pin with respect to GND –0.5 to +7 .0 V
TSTG Storage Temperature –65 to +150 °C
TAOpera ting Temp erature 0 to +70 °C
TBAmbient Temperature under Bias –55 to +125 °C
ESDPROT Input ESD Protection 2 (min.) kV
Crystal Oscillator
P arameter Description Test Conditi on Min. Typ. Max. Unit
VTH X1 Input Thre shold Voltag e[5] 1.65 V
CLOAD Load Capacitance, Imposed on
Externa l Crystal[6] 20 pF
CIN,X1 X1 Input Capacitance[7] Pin X2 unconnect ed 40 pF
3.3V D C Electr ic al C h ar acte risti cs (CPU3.3#_2.5 Input = 0)
TA = 0°C to +70°C, VDD1:3 = VDDL1:2 = 3. 3V±5% (3. 135–3.465V)
P arameter Description Test Conditi on Min. Typ. Max. Unit
Supply Curr ent
IDD Combin ed 3.3V Supply Curre nt CPU0:3 =66.8 MH z
Outputs Loaded[8] 160 mA
Logic Input s (All refer enced to VDDQ3 = 3.3V)
VIL Input Lo w Voltage 0.8 V
VIH Input High Voltage 2.0 V
IIL Input Low Current [9] 10 µA
IIH Input High Current[9] 10 µA
Clock Outp uts
VOL Outpu t Low Volt age IOL = 1 mA 50 mV
VOH Output High V oltage IOH = –1 mA 3.1 V
IOL Output Low Current CPU0:3[10] VOL = 1.5V 55 75 105 mA
SDRAM0:11 80 110 155
PCI_F, PCI0 :5 55 75 105
IOAPIC 100 135 190
REF0 60 75 90
REF1 45 60 75
48/24MHZ 55 75 105
Notes:
5. X1 input threshold voltage (typical) is VDD/2.
6. The W48S87-04 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal
is 20 pF; this includes typical stray capacitance of short PCB traces to crystal.
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
8. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section.
9. W48S87-04 logic inputs have internal pull-up devices.
10. CPU0:3 loaded by 60Ω, 6-inch long transmission lines ending with 20-pF capacitors.
W48S87-04
PRELIMINARY
15
IOH Output High Curr ent CPU0:3 [10] VOH = 1.5V 55 85 125 mA
SDRAM0:11 80 120 175
PCI_F, PCI0 :5 55 85 125
IOAPIC 100 150 220
REF0 60 85 110
REF1 45 65 90
48/24MHZ 55 85 125
Pin Capacitance/In ductance
CIN Input Pin Capacitance Except X1 and X2 5 pF
COUT Output Pin Capacitance 6 pF
LIN Inp ut Pi n Inducta nce 7nH
Serial Input Port
VIL Input Lo w Voltage VDD = 3.3V 0.3VDD V
VIH Input High Voltage VDD = 3.3V 0.7VDD V
IIL Input Low Current No internal pull-up/ down
on SCLOCK 10 µA
IIH Input Hi gh Curr ent No interna l pull-up/down
on SCLOCK 10 µA
IOL Sink Current into SDATA,
Open Drain N- Channel Device On IOL = 0.3VDD 6mA
CIN Input Capac it ance of SDATA and
SCLOCK 10 pF
CSDATA Total Capacitance of SDATA Bus 400 pF
CSCLOCK Total Capacitance of SCLOCK Bus 400 pF
3.3V D C Electr ic al C h ar acte risti cs (CPU3.3#_2.5 Input = 0) (continued)
TA = 0°C to +70°C, VDD1:3 = VDDL1:2 = 3. 3V±5% (3. 135–3.465V)
P arameter Description Test Conditi on Min. Typ. Max. Unit
2.5V D C Electr ic al C h ar acte risti cs (CPU3.3#_2.5 Input = 1)
TA = 0°C to +70°C, VDD1:3 = 3.3V±5% (3. 135–3.456V), VDDL1:2 = 2.5V±5% (2.375–2.625V)
P arameter Description Test Conditi on Min. Typ. Max. Unit
Supply Curr ent
IDD-3.3V 3.3V Suppl y Current CPU0:3 = 66.4 MHz
Outputs Loaded[8] 300 mA
IDD-2.5 2.5V Suppl y Current CPU0:3= 66.4 MHz
Outputs Loaded[8] 50 mA
Logic Inputs
VIL Input Lo w Voltage 0.8 V
VIH Input High Voltage 2.0 V
IIL Input Low Current [9] 10 µA
IIH Input High Current[9] 10 µA
W48S87-04
PRELIMINARY
16
3.3V AC Elec trical C h ar acteris t i cs (CPU3.3#_2. 5 Input = 0)
TA = 0°C to +70°C, VDD1:3 = VDD1:3 = 3.3V±5% (3. 135–3.465V), fXTL = 14.31818 MHz
Spread Spectrum function tur ned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
cl o ck outp ut.
Clock Outp uts
VOL Outpu t Low Volt age IOL = 1 mA 50 mV
VOH Output High V oltage IOH = –1 mA 2.2 V
IOL Output Low Current CPU0:3[10] VOL = 1.25V 45 70 105 mA
IOAPIC VOL = 1.25V 55 85 130
IOH Output High Curr ent CPU0:3 [10] VOH = 1.25V 40 65 95 mA
IOAPIC VOH = 1.25V 50 80 120
Pin Capacitance/In ductance
CIN Input Pin Capacitance Except X1 and X2 5 pF
COUT Output Pin Capacitance 6 pF
LIN Inp ut Pi n Inducta nce 7nH
Serial Input Port
VIL Input Lo w Voltage VDD = 2.5V 0.3VDD V
VIH Input High Voltage VDD = 2.5V 0.7VDD V
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
P arameter Descript ion Test Condi ti on/Comments
CPU = 66.8 MHz CPU = 60 MHz
UnitMin. Typ. Max. Min. Typ. Max.
tPPeriod Measured on rising edge at 1.5V 15 16.7 ns
f Frequency, Actual Determined by PLL divider ratio 66.8 59.876 MHz
tHHigh Ti me Duration of cloc k cycle above 2.4V 5.2 6 ns
tLLow Time Duration of clock cycle below 0.4V 5 5.8 ns
tROutput Rise Edge Rate Measured from 0.4V to 2.4V 1 4 1 4 V/ns
tFOutput F all Edge Rate Measured from 2.4V to 0.4V 1 4 1 4 V/ns
tDDuty Cycle Meas ured on risi ng and fal ling edg e at
1.5V 45 55 45 55 %
tJC Jit ter, Cycle -to-Cy cle Measure d on rising edg e at 1.5V. Max-
imum dif ferenc e of cycle t ime between
two adjacent cycles.
250 250 ps
tSK Output Skew Measur ed on r ising edge at 1.5V 250 250 ps
fST F r equenc y Stabi liza tion
from Power-up ( cold
start)
Assum es full supply volt age reached
with in 1 ms fr om power-up. Short cy-
cles exist prior to frequency stabiliza-
tion.
33ms
ZoAC Output Im pedance Average value dur ing sw itching transi-
tion. Used for determining series termi-
nation v alue.
15 20 30 15 20 30 Ω
2.5V D C Electr ic al C h ar acte risti cs (CPU3.3#_2.5 Input = 1) (continued)
TA = 0°C to +70°C, VDD1:3 = 3.3V±5% (3. 135–3.456V), VDDL1:2 = 2.5V±5% (2.375–2.625V)
P arameter Description Test Conditi on Min. Typ. Max. Unit
W48S87-04
PRELIMINARY
17
3.3V AC Elec trical C h ar acteris t i cs (CPU3.3#_2. 5 Input = 0) (continued)
SDRAM Clock Outp uts, SDRAM0:11 (Lump Capa cit ance Test Load = 30 pF)
P arameter Description Tes t Condi tion/Comments
CPU = 66.8 MHz CPU = 60 MHz
UnitMin. Typ. Max. Min. Typ. Max.
tPPeriod Measured on rising edge at 1.5V 15 1 6.7 ns
f Frequency, Actual Determined by PLL divider ratio 66.8 59. 876 MHz
tROutpu t Rise Edge Rate Measured from 0.4V to 2.4V 1 4 1 4 V/ns
tFOutpu t Fall Edge Rate Measured from 2.4V to 0.4V 1 4 1 4 V/ns
tDDuty Cycle Measur ed on rising and fal ling edge a t
1.5V 45 55 45 55 %
tJC Jitt er, Cycle-to-Cycl e Measur ed on risi ng edge at 1.5V. Max-
imum diff erence of cycle time between
two adjacent cycles.
250 250 ps
tSK Outpu t Skew Measur ed on ris ing edge at 1.5V 100 100 ps
tSK CPU to SDRAM Cl ock
Skew Covers all CPU/SDRAM outputs. Mea-
sured on rising edge at 1.5V. 500 500 ps
fST Frequency Stabilization
from Power-up (cold
start)
Assumes full suppl y voltage reached
within 1 ms from power-up. Short cy-
cles exist prior to fr equency stabili za-
tion.
33ms
ZoA C Output Impedance Av erage va lue during switchi ng transi-
tion. Used for determining series ter-
minati on value .
10 15 20 10 15 20 Ω
PCI Cloc k Outputs, PCI_F and PCI0 :5 (L ump Capacit ance Test Load = 30 pF)
Parameter Description Test Condition/Comments
CPU = 66.8 MHz CPU = 60 MHz
UnitMin. Typ. Max. Min. Typ. Max.
tPPeriod Measured on rising edge at 1.5V 30 3 3.3 ns
f Frequency, Actual Determined by PLL divider ratio 33.4 29.938 MHz
tHHigh Time Duration of clock cycle above 2.4V 12 13.3 ns
tLLow Tim e Durati on of clock cycl e below 0.4V 12 13.3 ns
tROutpu t Rise Edge Rate Measured from 0.4V to 2.4V 1 4 1 4 V/ns
tFOutpu t Fall Edge Rate Measured from 2.4V to 0.4V 1 4 1 4 V/ns
tDDuty Cyc le Measur ed o n rising and f al lin g edg e at
1.5V 45 55 45 55 %
tJC Jitt er , Cycle-t o-Cycl e Measur ed on rising edge a t 1.5V. Max-
imum dif ferenc e of cycle time between
two adjacent cycles.
250 250 ps
tSK Outpu t Skew Measur ed on ris ing edge at 1.5V 250 250 ps
tOCPU to PCI Clock Skew Cove rs all CPU/PCI outputs . Mea-
sured on rising edge at 1.5V. CPU
leads PCI output.
1414ns
fST Frequency Stabilization
from Power-up (cold
start)
Assumes full suppl y voltage reached
within 1 ms from power-up. Short cy-
cles exist prior to fr equency stabiliza -
tion.
33ms
ZoAC Output Impedance Average value during switching transi-
tion. Used f or determining series termi-
nati o n value.
15 20 30 15 20 30 Ω
W48S87-04
PRELIMINARY
18
3.3V AC Elec trical C h ar acteris t i cs (CPU3.3#_2. 5 Input = 0) (continued)
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter Description Test Condition/Comments
CPU = 60/66.8 MHz
UnitMin. Typ. Max.
f Frequency, Act ual Frequency generated by crystal oscillator 14.31818 MHz
tROutpu t Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns
tFOutpu t Fall Edge Rat e Measured from 2.4V to 0.4V 1 4 V/ns
tDDuty Cycle Measured on rising and falling edge at 1.5V 45 55 %
fST F requency St abilizat ion
from Power-up (cold star t) Assumes full suppl y voltage reached within
1 ms fr om power -up. Short cycl es exist prior to
frequency stabilization.
1.5 ms
ZoAC Output Impedance Average value dur ing switching transition.
Used for de termi ning series t erminat ion va lue. 81215Ω
REF0 Clock Output (Lump Capacitance Test Load = 45 pF)
Parameter Descript ion Test Condition/Comments
CPU = 60/66.8 MHz
UnitMin. Typ. Max.
f Frequency, Actual F requency generated by crystal oscil lator 14.31818 MHz
tROutpu t Rise Edge Rate Measured from 0. 4V to 2. 4V 1 4 V/ns
tFOutpu t Fall Edge Rat e Measu red from 2.4V to 0. 4V 1 4 V/ns
tDDuty Cycle Measured on rising and falling edge at 1.5V 40 60 %
fST Frequency Stabili zation
from Power-up (c old start) Assum es ful l supply voltage reached withi n
1 ms from pow er-up. Short cycles e xist pri or to
frequency stabilization.
1.5 ms
ZoA C Output Impedance Av erage value duri ng switching transit ion.
Use d fo r d eterm ining series term inati o n val u e. 17 20 25 Ω
REF1 Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter Descr iption Test Condition/Comments
CPU = 60/66.8 MHz
UnitMin. Typ. Max.
f Frequency, Actual Frequency generated by crystal oscillator 14.31818 M Hz
tROutpu t Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns
tFOutpu t Fall Edge Rat e Measured from 2.4V to 0.4V 1 4 V/ns
tDDuty Cycle Measured on rising and falling edge at 1.5V 40 55 %
fST Frequency Stabili zation
from Power-up (cold star t) Assumes full suppl y voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
1.5 ms
ZoAC Output Impedance Average value dur ing switching transition.
Used f or determining series t erminat ion val ue. 20 25 35 Ω
W48S87-04
PRELIMINARY
19
3.3V AC Elec trical C h ar acteris t i cs (CPU3.3#_2. 5 Input = 0) (continued)
48-/24-MHZ Clock Outputs (Lump Capacitance Test Load = 20 pF)
P arameter Descript ion T est Condition/Comment s
CPU = 60/66.8 MHz
UnitMin. Typ. Max.
f Frequency, Actual Determined by PLL divider ratio
(see n/m belo w) 48.008/24.004 MHz
fDDe viation from 48 MHz (48.008 – 48)/48 +167 ppm
m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) 57/17
tROutpu t Rise Edge Rate Measured from 0.4V to 2.4V 1 4 V/ns
tFOutpu t Fall Edge Rat e Measured from 2. 4V to 0. 4V 1 4 V/ns
tDDuty Cycle Measu red on rising and f alling edge at 1.5V 40 55 %
tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V. Maximum
diff er enc e of cy cle t ime between tw o adjac ent
cycles.
500 ps
fST Frequency Stabili zation
from P ow er-up (col d start) Assum es ful l supply voltage reac hed within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3ms
ZoA C Output Impedance Average value during switchi ng transition.
Used f or determining series termination valu e. 15 20 30 Ω
Serial Input P ort
Parameter Description Test Condition Min. Typ. Max. Unit
fSCLOCK SCLOCK Frequency Nor mal Mode 0 100 kHz
tSTHD Start Hold Time 4.0 µs
tLOW SCLOCK Low Time 4.7 µs
tHIGH SCLOCK High Tim e 4.0 µs
tDSU Data Setup Time 250 ns
tDHD Data Hold Time (Transmitt er shoul d provide a 300-ns hol d
time to ensure proper timing at the receiver.) 0ns
tRRise Time , SDATA and
SCLOCK From 0.3VDD to 0.7VDD 1000 ns
tFFall Tim e, SDATA and
SCLOCK From 0.7VDD to 0.3VDD 300 ns
tSTSU Stop Setup Time 4.0 µs
tSPF Bus F ree Time betw een
Stop and Star t Condition 4.7 µs
tSP Allowable Noise Spike
Pulse Width 50 ns
W48S87-04
PRELIMINARY
20
2.5V AC Elec trical C h ar acteris t i cs (CPU3.3#_2. 5 Input = 1)
TA = 0°C to +70°C, VDD1:3 = 3.3V± 5% (3.135–3.465V), VDDL1:2 = 2.5V±5% (2.375–2.625V),
fXTL = 14.31818 MH z
Spread Spectrum function tur ned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
cl o ck outp ut.
Document #: 38-00859
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
P arameter Des cri ption Tes t Condi tion/Comment s
CPU = 66.8 MHz CPU = 60 MHz
UnitMin. Typ. Max. Min. Typ. Max.
tPPeriod Measured on rising edge at 1.25V 15 16.7 ns
f Frequency, Actual Det ermined by PLL divider ratio 66.8 59.876 MHz
tHHigh Time Duration of clock cycle above 2.0V 5. 2 6 ns
tLLow Tim e Durati on of clock cycl e below 0.4V 5 5.8 ns
tROutput Rise Edge Rate Measur ed from 0.4V to 2.0V 0.8 3 0.8 3 V/ns
tFOutpu t Fall Edge Rat e Measured from 2.0V to 0.4V 0.8 3 0 .8 3 V/ns
tDDuty Cycle M easured on rising and falling edge at
1.25V 45 55 45 55 %
tJC Jitt er, Cycle-to-Cycl e Measur ed on rising edge at 1.25V. Ma x-
imum difference of cycle ti m e between
two adjacent cycles.
250 250 ps
tSK Outpu t Skew Measured on ris ing edge at 1.25V 250 250 ps
fST F requency St abiliza-
tion from Power-up
(cold st art)
Assumes full suppl y voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
33ms
ZoAC Output Impedance Average value during switchi ng transi-
tion. Used for determining series termi -
nati o n value.
12 20 30 12 20 30 Ω
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter Description Test Condition/Comments
CPU = 60/66.8 MHz
UnitMin. Typ. Max.
f Frequency, Actual Frequency generated by crystal oscillator 14.31818 MHz
tROutpu t Rise Edge Rate Measured from 0.4V to 2.0V 1 4 V/ns
tFOutpu t Fall Edge Rate Measured from 2.0V to 0.4V 1 4 V/ns
tDDuty Cycle Measured on rising and falling edge at 1.25V 45 55 %
fST F requency St abilizat ion
from Power-up (cold star t) Assumes full suppl y voltage reached within
1 ms fr om pow er -up . Sh ort cycl es e xi st prior t o
frequency stabilization.
1.5 ms
ZoAC Output Impedance Average value during switching transition. Used
for determini ng series termination value. 10 15 25 Ω
Orde ring Information
Ordering Code Freq. Mask
Code Package
Name P ackage Type
W48S87 04 H48-pin SSOP (300 mils)
W48S87-04
PRELIMINARY
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it conv ey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package D i ag ra m
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
Summary of nominal di mensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Leng th: 0. 62 5
Body Height: 0.102
