DAC712
DAC712
1
FEATURES DESCRIPTION
VOUT
V
+10V
REFOUT
Reference
Circuit 16-BitD/AConverter
D/ALatch
16
GainAdjust
InputLatch
16
A1
A0
WR
CLR
DB0 DB15
BipolarOffsetAdjust
DAC712
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................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009
16-BIT DIGITAL-TO-ANALOG CONVERTERwith 16-Bit Bus Interface
2
•HIGH-SPEED, 16-BIT PARALLEL
The DAC712 is a complete 16-bit resolutionDOUBLE-BUFFERED INTERFACE
digital-to-analog (D/A) converter with 16 bits ofmonotonicity over temperature.•VOLTAGE OUTPUT: ± 10V•13-, 14-, AND 15-BIT LINEARITY GRADES
The DAC712 has a precision +10Vtemperature-compensated voltage reference, ± 10V•16-BIT MONOTONIC OVER TEMPERATURE
output amplifier, and 16-bit port bus interface.(L GRADE)
The digital interface is fast, 60ns minimum write pulse•POWER DISSIPATION: 600mW max
width, double-buffered, and has a CLEAR function•GAIN AND OFFSET ADJUST:
that resets the analog output to bipolar zero.Convenient for Auto-Cal D/A Converters
GAIN and OFFSET adjustment inputs are arranged•28-LEAD DIP AND SOIC PACKAGES
so that they can be easily trimmed by external D/Aconverters as well as by potentiometers.
The DAC712 is available in two linearity errorperformance grades: ± 4LSB and ± 2LSB, and threedifferential linearity grades: ± 4LSB, ± 2LSB, and± 1LSB. The DAC712 is specified at power-supplyvoltages of ± 12V and ± 15V.
The DAC712 is packaged in a 28-pin, 0.3" wideplastic DIP and in a 28-lead, wide-body plastic SOIC.The DAC712P, U, PB, and UB are specified over the– 40 ° C to +85 ° C temperature range and theDAC712PK, UK, PL, and UL are specified over the0 ° C to +70 ° C range.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
A0
A1
DAC712
SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 .................................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
(1)
DIFFERENTIALLINEARITY ERROR MAX LINEARITY ERROR MAX PACKAGE- PACKAGE SPECIFIEDPRODUCT AT +25 ° C AT +25 ° C LEAD DESIGNATOR TEMPERATURE RANGE
DAC712P ± 4LSB ± 4LSB PDIP-28 NT – 40 ° C to +85 ° CDAC712U ± 4LSB ± 4LSB SOIC-28 DW – 40 ° C to +85 ° CDAC712PB ± 2LSB ± 2LSB PDIP-28 NT – 40 ° C to +85 ° CDAC712UB ± 2LSB ± 2LSB SOIC-28 DW – 40 ° C to +85 ° C
DAC712PK ± 2LSB ± 2LSB PDIP-28 NT 0 ° C to +70 ° CDAC712UK ± 2LSB ± 2LSB SOIC-28 DW 0 ° C to +70 ° CDAC712PL ± 2LSB ± 1LSB PDIP-28 NT 0 ° C to +70 ° CDAC712UL ± 2LSB ± 1LSB SOIC-28 DW 0 ° C to +70 ° C
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .
DAC712 UNIT
+V
CC
to COMMON 0, +17 V– V
CC
to COMMON 0, – 17 V+V
CC
to – V
CC
34 VDigital Inputs to COMMON – 1 to +V
CC
– 0.7 VExternal Voltage Applied to BPO and Range Resistors ± V
CC
VV
REF OUT
Indefinite Short to COMMONV
OUT
Indefinite Short to COMMONPower Dissipation 750 mWStorage Temperature Range – 60 to +150 ° C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not implied.
TRUTH TABLE
WR CLR DESCRIPTION
0 1 1 →0→1 1 Load Input Latch1 0 1 →0→1 1 Load D/A Latch1 1 1 →0→1 1 No Change0 0 0 1 Latches TransparentX X 1 1 No ChangeX X X 0 Reset D/A Latch
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ELECTRICAL CHARACTERISTICS: DAC712P, U, PB, UB
DAC712
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................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009
At T
A
= +25 ° C, +V
CC
= +12V and +15V, and – V
CC
= – 12V and – 15V, unless otherwise noted.
DAC712P, U DAC712PB, UB
(1)TESTPARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
INPUT
RESOLUTION
Resolution 16 Bits
DIGITAL INPUTS
Input Code Binary Twos ComplementLogic Levels
(2)
V
IH
+2.0 +V
CC
– 1.4 VV
IL
0 +0.8 VI
IH
(V
I
= +2.7V) ± 10 µAI
IL
(V
I
= +0.4V) ± 10 µA
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error ± 4 ± 2 LSBT
MIN
to T
MAX
± 8 ± 4 LSBDifferential Linearity Error ± 4 ± 2 LSBT
MIN
to T
MAX
± 8 ± 4 LSBMonotonicity Over Temperature 13 14 BitsGain Error
(3)
± 0.1 %T
MIN
to T
MAX
± 0.2 ± 0.15 %Bipolar Zero Error
(3)
± 0.1 % FSR
(4)
± 20 mVT
MIN
to T
MAX
± 0.2 ± 0.15 % FSR± 40 ± 30 mV± 0.003 % FSR/% V
CCPower-Supply Sensitivity of Full-Scale
± 30 ppm FSR/% V
CC
DYNAMIC PERFORMANCE
Settling Time (to ± 0.003%FSR, 5k Ω|| 500pF Load)
(5)
20V Output Step 6 10 µs1LSB Output Step
(6)
4µsOutput Slew Rate 10 V/ µsTotal Harmonic Distortion + Noise0dB, 1001Hz, f
S
= 100kHz 0.005 %– 20dB, 1001Hz, f
S
= 100kHz 0.03 %– 60dB, 1001Hz, f
S
= 100kHz 3.0 %SINAD
1001Hz, f
S
= 100kHz 87 dBDigital Feedthrough
(6)
2 nV-sDigital-to-Analog Glitch Impulse
(6)
15 nV-sOutput Noise Voltage (Includes Reference) 120 nV/ √Hz
(1) Shaded cells indicate same specification as the DAC712P, U grade.(2) Digital inputs are TTL- and +5V CMOS-compatible over the specified temperature range.(3) Errors externally adjustable to zero.(4) FSR means Full-Scale Range. For example, for a ± 10V output, FSR = 20V.(5) Maximum represents the 3 σlimit. Not 100% tested for this parameter.(6) For the worst-case code changes: FFFFh to 0000h and 0000h to FFFFh. These are binary twos complement (BTC) codes.
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DAC712
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ELECTRICAL CHARACTERISTICS: DAC712P, U, PB, UB (continued)At T
A
= +25 ° C, +V
CC
= +12V and +15V, and – V
CC
= – 12V and – 15V, unless otherwise noted.
DAC712P, U DAC712PB, UB
(1)TESTPARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
ANALOG OUTPUT
Output Voltage Range+V
CC
, – V
CC
= ± 11.4V ± 10 VOutput Current ± 5 mAOutput Impedance 0.1 Ω
Short-Circuit to ACOM, Duration Indefinite
REFERENCE VOLTAGE
Voltage +9.975 +10.000 +10.025 VT
MIN
to T
MAX
+9.960 +10.040 VOutput Resistance 1 Ω
Source Current 2 mAShort-Circuit to ACOM, Duration Indefinite
POWER-SUPPLY REQUIREMENTS
Voltage
+V
CC
+11.4 +15 +16.5 V– V
CC
– 11.4 – 15 – 16.5 VCurrent (No Load, ± 15V Supplies)+V
CC
13 15 mA– V
CC
22 25 mAPower Dissipation
(7)
525 600 mW
TEMPERATURE RANGES
Specified Temperature Range (All Grades) – 40 +85 ° CStorage Temperature Range – 60 +150 ° CThermal Coefficient, θ
JA
DIP Package 75 ° C/WSOIC Package 75 ° C/W
(7) Typical supply voltages times maximum currents.
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ELECTRICAL CHARACTERISTICS: DAC712PK, UK, PL, UL
DAC712
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................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009
At T
A
= +25 ° C, +V
CC
= +12V and +15V, and – V
CC
= – 12V and – 15V, unless otherwise noted.
DAC712PK, UK DAC712PL, UL
(1)TESTPARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
INPUT
RESOLUTION
Resolution 16 Bits
DIGITAL INPUTS
Input Code Binary Twos ComplementLogic Levels
(2)
V
IH
+2.0 +V
CC
– 1.4 VV
IL
0 +0.8 VI
IH
(V
I
= +2.7V) ± 10 µAI
IL
(V
I
= +0.4V) ± 10 µA
TRANSFER CHARACTERISTICS
ACCURACY
Linearity Error ± 2 LSBT
MIN
to T
MAX
± 2 LSBDifferential Linearity Error ± 2 ± 1 LSBT
MIN
to T
MAX
± 2 ± 1 LSBMonotonicity Over Temperature 15 16 BitsGain Error
(3)
± 0.1 %T
MIN
to T
MAX
± 0.15 ± 0.2 %Bipolar Zero Error
(3)
± 0.1 % FSR
(4)
± 20 mVT
MIN
to T
MAX
± 0.15 % FSR± 30 mV± 0.003 % FSR/% V
CCPower-Supply Sensitivity of Full-Scale
± 30 ppm FSR/% V
CC
DYNAMIC PERFORMANCE
Settling Time (to ± 0.003%FSR, 5k Ω|| 500pF Load)
(5)
20V Output Step 6 10 µs1LSB Output Step
(6)
4µsOutput Slew Rate 10 V/ µsTotal Harmonic Distortion + Noise0dB, 1001Hz, f
S
= 100kHz 0.005 %– 20dB, 1001Hz, f
S
= 100kHz 0.03 %– 60dB, 1001Hz, f
S
= 100kHz 3.0 %SINAD
1001Hz, f
S
= 100kHz 87 dBDigital Feedthrough
(6)
2 nV-sDigital-to-Analog Glitch Impulse
(6)
15 nV-sOutput Noise Voltage (Includes Reference) 120 nV/ √Hz
(1) Shaded cells indicate same specification as the DAC712PK, UK grade.(2) Digital inputs are TTL- and +5V CMOS-compatible over the specified temperature range.(3) Errors externally adjustable to zero.(4) FSR means Full-Scale Range. For example, for a ± 10V output, FSR = 20V.(5) Maximum represents the 3 σlimit. Not 100% tested for this parameter.(6) For the worst-case code changes: FFFFh to 0000h and 0000h to FFFFh. These are binary twos complement (BTC) codes.
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DAC712
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ELECTRICAL CHARACTERISTICS: DAC712PK, UK, PL, UL (continued)At T
A
= +25 ° C, +V
CC
= +12V and +15V, and – V
CC
= – 12V and – 15V, unless otherwise noted.
DAC712PK, UK DAC712PL, UL
(1)TESTPARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNIT
ANALOG OUTPUT
Output Voltage Range+V
CC
, – V
CC
= ± 11.4V ± 10 VOutput Current ± 5 mAOutput Impedance 0.1 Ω
Short-Circuit to ACOM, Duration Indefinite
REFERENCE VOLTAGE
Voltage +9.975 +10.000 +10.025 VT
MIN
to T
MAX
+9.960 +10.040 VOutput Resistance 1 Ω
Source Current 2 mAShort-Circuit to ACOM, Duration Indefinite
POWER-SUPPLY REQUIREMENTS
Voltage
+V
CC
+11.4 +15 +16.5 V– V
CC
– 11.4 – 15 – 16.5 VCurrent (No Load, ± 15V Supplies)+V
CC
13 15 mA– V
CC
22 25 mAPower Dissipation
(7)
525 600 mW
TEMPERATURE RANGES
Specified Temperature Range (All Grades) 0 +70 ° CStorage Temperature Range – 60 +150 ° CThermal Coefficient, θ
JA
DIP Package 75 ° C/WSOIC Package 75 ° C/W
(7) Typical supply voltages times maximum currents.
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Product Folder Link(s): DAC712
PIN CONFIGURATION
DCOM
ACOM
VOUT
OffsetAdjust
VREFOUT
GainAdjust
+VCC
-VCC
CLR
WR
A1
A0
D15MSB
D14
LSBD0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DAC712
DAC712
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................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009
DW AND NT PACKAGES
SOIC-28 AND PDIP-28(TOP VIEW)
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A1
A0
DAC712
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PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1 DCOM Power-Supply return for digital currents2 ACOM Analog Supply Return3 V
OUT
± 10V D/A Output4 Offset Adjust Offset Adjust (Bipolar)5 V
REF OUT
Voltage Reference Output6 Gain Adjust Gain Adjust7 +V
CC
+12V to +15V Supply8 – V
CC
– 12V to – 15V Supply9 CLR CLEAR; Sets D/A output to Bipolar Zero (Active Low)10 WR Write (Active Low)
11 Enable for D/A latch (Active Low)
12 Enable for Input latch (Active Low)
13 D15 Data Bit 15 (Most Significant Bit)14 D14 Data Bit 1415 D13 Data Bit 1316 D12 Data Bit 1217 D11 Data Bit 1118 D10 Data Bit 1019 D9 Data Bit 920 D8 Data Bit 821 D7 Data Bit 722 D6 Data Bit 623 D5 Data Bit 524 D4 Data Bit 425 D3 Data Bit 326 D2 Data Bit 227 D1 Data Bit 128 D0 Data Bit 0 (Least Significant Bit)
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TIMING CHARACTERISTICS
WR
A ,A
0 1
D0-D15
tDH
tAW
tWP
tDW
tAH
TIMING REQUIREMENTS
A0
,
A1
Valid to End of WR
A0
,
A1
Hold after End of WR
DAC712
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................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009
Figure 1. Timing Diagram
At T
A
= – 40 ° C to +85 ° C, +V
CC
= +12V or +15V, and – V
CC
= – 12V or – 15V, unless otherwise noted.
DAC712
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
DW
Data Valid to End of WR 50 ns
t
AW
50 ns
t
AH
10 ns
t
DH
Data Hold after End of WR 10 nst
WP
(1)
Write Pulse Width 50 nst
CP
CLEAR Pulse Width 200 ns
(1) For single-buffered operation, t
WP
is 80ns minimum; see the Single-Buffered Operation section.
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TYPICAL CHARACTERISTICS
2.0
-0.85 0 2.55 4.25 5.95 6.8
1.0
0
-1.0
-2.0
0.85 1.7 3.4 5.1
DATA
WR,A ,A
0 1
CLR
VDigitalInput
IDigitalInput( A)m
Frequency(Hz)
[ChangeinFSR]/[ChangeinSupplyVoltage]
(ppmofFSR/%)
1k
10 100 1k 10k 100k 1M
100
10
1
0.1
+VCC
-VCC
Time(10 s/div)m
V (V)
OUT
WR
Time(1 s/div)m
2500
2000
1500
1000
500
0
-500
-1000
-1500
-2000
-2500
D mV)
Around+10V(
+5V
0V
1000
100
10
1
1 10 100 1k 10k 100k 1M 10M
Frequency(Hz)
nV/ÖHz
DAC712
SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 .................................................................................................................................................
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At T
A
= +25 ° C and V
CC
= ± 15V, unless otherwise noted.
POWER-SUPPLY REJECTION vsPOWER-SUPPLY RIPPLE FREQUENCY LOGIC vs V LEVEL
Figure 2. Figure 3.
± FULL-SCALE OUTPUT SWING SETTLING TIME, +10V TO – 10V
Figure 4. Figure 5.
SETTLING TIME, +10V TO – 10V SPECTRAL NOISE DENSITY
Figure 6. Figure 7.
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Product Folder Link(s): DAC712
DISCUSSION OF SPECIFICATIONS
LINEARITY ERROR TOTAL HARMONIC DISTORTION + NOISE
DIFFERENTIAL LINEARITY ERROR
SIGNAL-TO-NOISE AND DISTORTION RATIO
MONOTONICITY
DIGITAL-TO-ANALOG GLITCH IMPULSE
DIGITAL FEEDTHROUGHSETTLING TIME
DAC712
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................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009
Linearity error is defined as the deviation of the Total harmonic distortion + noise is defined as theanalog output from a straight line drawn between the ratio of the square root of the sum of the squares ofend points of the transfer characteristic. the values of the harmonics and noise to the value ofthe fundamental frequency. It is expressed in % ofthe fundamental frequency amplitude at sampling ratef
S
.Differential linearity error (DLE) is the deviation from1LSB of an output change from one adjacent state tothe next. A DLE specification of ± 1/2LSB means that
(SINAD)the output step size can range from 1/2LSB to3/2LSB when the digital input code changes from one SINAD includes all the harmonic and outstandingcode word to the adjacent code word. If the DLE is spurious components in the definition of output noisemore positive than – 1LSB, the D/A converter is said power in addition to quantizing and internal randomto be monotonic. noise power. SINAD is expressed in dB at a specifiedinput frequency and sampling rate, f
S
.
A D/A converter is monotonic if the output eitherincreases or remains the same for increasing digital The amount of charge injected into the analog outputinput values. Monotonicity of the DAC712 is ensured from the digital inputs when the inputs change state.over the specified temperature range to 13, 14, 15, It is measured at half-scale at the input codes whereand 16 bits for performance grades DAC712P/U, as many switches as possible change state — fromDAC712PB/UB, DAC712PK/UK, and DAC712PL/UL, 7FFFh to 8000h.respectively.
When the analog-to-digital (A/D) converter is notSettling time is the total time (including slew time) for selected, high-frequency logic activity on the digitalthe D/A output to settle to within an error band inputs is coupled through the device and shows up asaround its final value after a change in input. Settling output noise. This noise is digital feedthrough.times are specified to within ± 0.003% of Full-ScaleRange (FSR) for an output step change of 20V and1LSB. The 1LSB change is measured at the MajorCarry (FFFFh to 0000h, and 0000h to FFFFh: BTCcodes), the input transition at which worst-casesettling time occurs.
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OPERATION
INTERFACE LOGIC
DB15
MSB
16-BitInputLatch
16-BitD/ALatch
28 27 26 25 24 23 22 21 20 19 18 17
DB0
LSB
6 5
+10V
Reference
2 1
7
DCOM
+VCC
ACOM
VREFOUT
GainAdjust
10
WR
12A0
11A1
9CLR
8
-VCC
16 15 14 13
Bipolar
Offset
Adjust
4
3VOUT
D/ASwitches
-VCC
+2.5V
15kW
170W
9750W
250W
10kW
DAC712
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The DAC712 is a monolithic integrated-circuit, 16-bit All latches are level-triggered. Data present when theD/A converter complete with 16-bit D/A converter enable inputs are logic '0' enter the latch. When theswitches and ladder network, voltage reference, enable inputs return to logic '1', the data are latched.output amplifier, and microprocessor bus interface.
The CLR input resets both the input latch and the D/Alatch to give a bipolar zero output.
The DAC712 has double-buffered data latches. Theinput data latch holds a 16-bit data word beforeloading it into the second latch, the D/A latch. Thisdouble-buffered organization permits simultaneousupdate of several D/A converters. All digital controlinputs are active low. Refer to the block diagram ofFigure 8 .
Figure 8. DAC712 Block Diagram
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LOGIC INPUT COMPATIBILITY GAIN AND OFFSET ADJUSTMENTS
+Full-Scale
AllBits
Logic0
1LSB
Rangeof
OffsetAdjust
OffsetAdjust
Translates
theLine DigitalInput
AllBits
Logic1
AnalogOutput
Full-Scale
Range GainAdjust
RotatestheLine
-Full-Scale
MSBonAll
OthersOff
Bipolar
Offset
Rangeof
GainAdjust
» ±0.3%
» ±0.3%
R
R=1k:A ,A , ,WRCLR
0 1
3k:D ...D
0 15
ESDProtectionCircuit
6.8V 5pF
Digital
Input
-VCC
+VCC
INPUT CODING
INTERNAL REFERENCE
OUTPUT VOLTAGE SWING
Offset Adjustment
DAC712
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................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009
The DAC712 digital inputs are TTL-compatible (1.4V Figure 10 illustrates the relationship of offset and gainswitching level) with low-leakage, high-impedance adjustments for a bipolar connected D/A converter.inputs. Thus, the inputs are suitable for being driven Offset should be adjusted first to avoid interaction ofby any type of 5V logic such as 5V CMOS logic. An adjustments. Table 1 shows calibration values andequivalent circuit of a digital input is shown in codes. These adjustments have a minimum range ofFigure 9 . ± 0.3%.
Data inputs float to logic '0' and control inputs float tologic '0' if left unconnected. It is recommended thatany unused inputs be connected to DCOM to improvenoise immunity.
Digital inputs remain high-impedance when power isoff.
Figure 10. Relationship of Offset and GainFigure 9. Equivalent Circuit of Digital Inputs
Adjustments
Table 1. Digital Input and Analog Output VoltageCalibration ValuesThe DAC712 is designed to accept positive-truebinary twos complement (BTC) input codes that are
DAC712 CALIBRATION VALUES1 LEAST SIGNIFICANT BIT = 305 µVcompatible with bipolar analog output operation. Forbipolar analog output configuration, a digital input of
DIGITAL INPUTCODE BINARY7FFFh gives a positive full-scale output, 8000h gives
TWOSa negative full-scale output, and 0000h gives bipolar
COMPLEMENT, ANALOG OUTPUTzero output.
BTC (V) DESCRIPTION
Positive Full-Scale –7FFFh +9.999695
1LSB4000h +5.000000 3/4 ScaleThe DAC712 contains a +10V reference.
0001h +0.000305 BPZ + 1LSBThe reference output may be used to drive external
0000h 0.000000 Bipolar Zero (BPZ)loads, sourcing up to 2mA. The load current should
FFFFh – 0.000305 BPZ – 1LSBbe constant, otherwise the gain and bipolar offset ofthe converter will vary.
C000h – 5.000000 1/4 Scale8000h – 10.00000 Negative Full-Scale
The output amplifier of the DAC712 is committed to a± 10V output range. The DAC712 provides a ± 10V
Apply the digital input code that produces theoutput swing while operating on ± 11.4V or higher
maximum negative output voltage and adjust thevoltage supplies.
offset potentiometer or the offset adjust D/A converterfor – 10V.
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Gain Adjustment
INSTALLATION
GENERAL CONSIDERATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+
0.01 Fm
DCOM
ACOM
VOUT
VREFOUT
+VCC
-VCC
0.01 Fm+
+12Vto+15V
-12Vto -15V
POWER-SUPPLY AND REFERENCE
DAC712
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Apply the digital input that gives the maximumpositive voltage output. Adjust the gain potentiometeror the gain adjust D/A converter for this positivefull-scale voltage.
Because of the high accuracy of these D/Aconverters, system design problems such asgrounding and contact resistance become veryimportant. A 16-bit converter with a 20V full-scalerange has a 1LSB value of 305mV. With a loadcurrent of 5 µA, series wiring and connectorresistance of only 60m Ωcauses a voltage drop of300 µV. To understand what this means in terms of asystem layout, the resistivity of a typical 1-ouncecopper-clad printed circuit board (PCB) is 1/2m Ωpersquare. For a 5mA load, a 10 mil (0.010 inch) wideprinted circuit conductor 60 milli-inches long results ina voltage drop of 150 µV.
Figure 11. Power-Supply ConnectionsThe analog output of the DAC712 has an LSB size of305 µV ( – 96dB). The noise floor of the D/A converter
The DAC712 has separate ANALOG COMMON andmust remain below this level in the frequency range
DIGITAL COMMON pins. The current through DCOMof interest. The DAC712 noise spectral density (which
is mostly switching transients and are up to 1mAincludes the noise contributed by the internal
peak in amplitude. The current through ACOM isreference) is shown in the Typical Characteristics
typically 5 µA for all codes.section.
Use separate analog and digital ground planes with aWiring to high-resolution D/A converters should be
single interconnection point to minimize ground loops.routed to provide optimum isolation from sources of
The analog pins are located adjacent to each other toradio frequency interference (RFI) and
help isolate analog from digital signals. Analogelectromagnetic interference (EMI). The key to
signals should be routed as far as possible fromelimination of RF radiation or pickup is a small loop
digital signals and should cross them at right angles.area. Signal leads and the return conductors should
A solid analog ground plane around the D/Abe kept close together such that they present a small
converter package, as well as under it in the vicinitycapture cross-section for any external field.
of the analog and power-supply pins, isolates the D/AWire-wrap construction is not recommended.
converter from switching currents. It is recommendedthat DCOM and ACOM be connected directly to theground planes under the package.CONNECTIONS
If several DAC712s are used, or if the DAC712Power-supply decoupling capacitors should be added
shares supplies with other components, connectingas shown in Figure 11 . Best performance occurs
the ACOM and DCOM lines together once at theusing a 1 µF to 10 µF tantalum capacitor at – V
CC
.
power supplies rather than at each chip may giveApplications with less critical settling time may be
better results.able to use 0.01 µF at – V
CC
as well as at +V
CC
. Thecapacitors should be located close to the package.
14 Submit Documentation Feedback Copyright © 2000 – 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC712
LOAD CONNECTIONS
R1
Sense
Output
RL
R2
R3
AlternateGround
SenseConnection
SystemGround
ACOMDCOM
Bus
Interface
DAC712
Analog
Power
Supply
0.01 Fm(1)
0.01 Fm
To+VCC
To V-CC
VOUT
10kW10kW
VREF
DAC712
www.ti.com
................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009
In some applications it is impractical to return the loadto the ACOM pin of the D/A converter. Sensing theBecause the reference point for V
OUT
and V
REF OUT
is
output voltage at the SYSTEM GROUND point isthe ACOM pin, it is important to connect the D/A
reasonable, because there is no change in theconverter load directly to the ACOM pin; see
DAC712 ACOM current, provided that R
3
is aFigure 12 .
low-resistance ground plane or conductor. In thiscase, DCOM may be connected to SYSTEMLead and contact resistances are represented by R
1
GROUND as well.through R
3
. As long as the load resistance R
L
isconstant, R
1
simply introduces a gain error and canbe removed by gain adjustment of the D/A converteror system-wide gain calibration. R
2
is part of R
L
if theoutput voltage is sensed at ACOM.
(1) Locate close to the DAC712 package.
Figure 12. System Ground Considerations for High-Resolution D/A Converters
Copyright © 2000 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): DAC712
GAIN AND OFFSET ADJUST
Connections Using Potentiometers
OUTPUT VOLTAGE RANGE CONNECTIONS
Using D/A Converters
10kW
3
4
6
±10VVOUT
9.75kW
IDAC
0mA-2mA
»+2.5V
15kW
R
27kW
3R
10kW
4
120W180W
R
500W
1R
500W
2
5
170W250W
Internal
+10VReference VREFOUT
GainAdjust
BipolarOffsetAdjust
2ACOM
DAC712
SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 .................................................................................................................................................
www.ti.com
Nominal values of GAIN and OFFSET occur whenthe D/A converter outputs are at approximately halfscale, +5V.
GAIN and OFFSET adjust pins provide for trim usingexternal potentiometers. 15-turn potentiometersprovide sufficient resolution. Range of adjustment of
The DAC712 output amplifier is connected internallythese trims is at least ± 0.3% of Full-Scale Range; see
for the ± 10V bipolar (20V) output range. That is, theFigure 13 .
bipolar offset resistor is connected to an internalreference voltage and the 20V range resistor isconnected internally to V
OUT
. The DAC712 cannot beconnected for unipolar operation.The GAIN ADJUST and OFFSET ADJUST circuits ofthe DAC712 have been arranged so that these pointsmay be easily driven by external D/A converters; seeFigure 14 . 12-bit D/A converters provide an OFFSETadjust resolution and a GAIN adjust resolution of30 µV to 50 µV per LSB step.
(1) For no external adjustments, pins 4 and 6 are not connected. External Resistors R
1
to R
4
are standard ± 1% values. Range of adjustmentis at least ± 0.3% FSR.
Figure 13. Manual Offset and Gain Adjust Circuits
16 Submit Documentation Feedback Copyright © 2000 – 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC712
10kW
3
4
6
±10VVOUT
DAC712
9.75kW
IDAC
0mA-2mA
15kW
R
20kW
3
0Vto+10V
R
10kW
4
170W250W
Internal
+10VReference VREFOUT
GainAdjust(1)
BipolarOffsetAdjust(1)
R
340W
1R
500W
2
RFB VREFA
5
RFB VREFB
0Vto10V
5kW
10kW
+10V 10kW
-10V
(2)
(3)
(4)
DIGITAL INTERFACE
BUS INTERFACE SINGLE-BUFFERED OPERATION
enabled by connecting
A0
to DCOM. If
A1
is not used
A0
is the enable control for the DATA INPUT LATCH.
A1
is the enable for the D/A LATCH. WR is used tostrobe data into latches enabled by
A0
and
A1
. Refer
TRANSPARENT INTERFACE
transparent by asserting
A0
,
A1
, and WR LOW, and
DAC712
www.ti.com
................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009
(1) For no external adjustments, pins 4 and 6 are not connected. External Resistors R
1
to R
4
tolerance is ± 1% values. Range of adjustmentis at least ± 0.3% FSR.(2) Suggested op amps: OPA177GP, GS or OPA604AP, AU .(3) Suggested op amps: single OPA177GP, GS or dual OPA2604AP, AU .(4) Suggested D/A converters: dual DAC7800 (serial input, 12-bit resolution); dual DAC7801 (8-bit port input, 12-bit resolution); dualDAC7802 (12-bit port input, 12-bit resolution); dual DAC7545 (12-bit port input, 12-bit resolution); or single DAC8043 (serial input, 12-bitresolution). BIPOLAR (complete): DAC813 (use 11-bit resolution for 0V to +10V output; no op-amps required).
Figure 14. Gain and Offset Adjustment Using D/A Converters
The DAC712 has 16-bit, double-buffered data bus To operate the DAC712 interface as a single-bufferedinterface with control lines for easy interface to latch, the DATA INPUT LATCH is permanentlyinterface to a 16-bit bus. The double-buffered featurepermits update of several D/A converters
to enable the D/A converter, it should be connectedsimultaneously.
to DCOM as well. For this mode of operation, thewidth of WR must be at least 80ns minimum to passdata through the DATA INPUT LATCH and into theD/A LATCH.
to the block diagram of Figure 8 and to Figure 1 .
CLR sets the INPUT DATA LATCH to all zeros and
The digital interface of the DAC712 can be madethe D/A LATCH to a code that gives bipolar 0V at theD/A converter output.
asserting CLR HIGH.
Copyright © 2000 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): DAC712
DAC712
SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 .................................................................................................................................................
www.ti.com
Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (September 200) to Revision A ................................................................................................. Page
•Updated document format to current standards .................................................................................................................... 1•Changed max specification for Accuracy, Gain Error, T
MIN
to T
MAX
parameter in Electrical Characteristics:DAC712PK, UK, PL, UL table ................................................................................................................................................ 5
18 Submit Documentation Feedback Copyright © 2000 – 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC712
PACKAGE OPTION ADDENDUM
www.ti.com 28-Oct-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC712P NRND PDIP NT 28 13 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC712PB NRND PDIP NT 28 13 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC712PBG4 NRND PDIP NT 28 13 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC712PG4 NRND PDIP NT 28 13 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC712PK NRND PDIP NT 28 13 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC712PKG4 NRND PDIP NT 28 13 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC712PL NRND PDIP NT 28 13 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC712PLG4 NRND PDIP NT 28 13 Green (RoHS
& no Sb/Br) CU NIPDAU N / A for Pkg Type
DAC712U ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC712UB ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC712UB/1K OBSOLETE SOIC DW 28 TBD Call TI Call TI
DAC712UB/1KG4 OBSOLETE SOIC DW 28 TBD Call TI Call TI
DAC712UBG4 ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC712UG4 ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC712UK ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC712UK/1K OBSOLETE SOIC DW 28 TBD Call TI Call TI
DAC712UK/1KG4 OBSOLETE SOIC DW 28 TBD Call TI Call TI
DAC712UKG4 ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
PACKAGE OPTION ADDENDUM
www.ti.com 28-Oct-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
DAC712UL ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC712UL/1K OBSOLETE SOIC DW 28 TBD Call TI Call TI
DAC712UL/1KG4 OBSOLETE SOIC DW 28 TBD Call TI Call TI
DAC712ULG4 ACTIVE SOIC DW 28 20 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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