IRFB52N15DPBF - INFINEON TECHNOLOGIES AG

Notes  through  are on page 11

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09/22/10

HEXFET® Power MOSFET

lHigh frequency DC-DC converters

lPlasma Display Panel

Benefits

Applications

lLow Gate-to-Drain Charge to

Reduce\ Switching Losses

lFully Characterized Capacitance

Including Effective COSS to Simplify

Design, (See App. Note AN1001)

lFully Characterized Avalanche

Voltage and Current

lLead-Free

IRFB52N15DPbF

IRFS52N15DPbF

IRFSL52N15DPbF

D2Pak

IRFS52N15DPbF

TO-220AB

IRFB52N15DPbF

TO-262

IRFSL52N15DPbF

* RθJC (end of life) for D2Pak and TO-262 = 0.65°C/W. This is the maximum measured value after 1000 temperature

cycles from -55 to 150°C and is accounted for by the physical wearout of the die attach medium.

Thermal Resistance

Parameter Typ. Max. Units

RθJC Junction-to-Case ––– 0.47*

RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W

RθJA Junction-to-Ambient––– 62

RθJA Junction-to-Ambient––– 40

Parameter Max. Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 51*

ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 36* A

IDM Pulsed Drain Current 240

PD @TA = 25°C Power Dissipation 3.8 W

PD @TC = 25°C Power Dissipation  230*

Linear Derating Factor  1.5* W/°C

VGS Gate-to-Source Voltage ± 30 V

dv/dt Peak Diode Recovery dv/dt 5.5 V/ns

TJOperating Junction and -55 to + 175

TSTG Storage Temperature Range

Soldering Temperature, for 10 seconds 300 (1.6mm from case )

°C

Mounting torqe, 6-32 or M3 screw 10 lbf•in (1.1N•m)

Absolute Maximum Ratings

VDS 150 V

VDS (Avalanche) min. 200 V

RDS(ON) max @ 10V 32 m

TJ max 175 °C

Key Parameters

PD - 97002A

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IRFB52N15DPbF/IRFS52N15DPbF/IRFSL52N15DPbF

Parameter Min. Typ. Max. Units Conditions

gfs Forward Transconductance 19 ––– ––– S VDS = 50V, ID = 36A

QgTotal Gate Charge ––– 60 89 ID = 36A

Qgs Gate-to-Source Charge ––– 18 27 nC VDS = 75V

Qgd Gate-to-Drain ("Miller") Charge ––– 28 42 VGS = 10V, 

td(on) Turn-On Delay Time ––– 16 ––– VDD = 75V

trRise Time ––– 47 ––– ID = 36A

td(off) Turn-Off Delay Time ––– 28 ––– RG = 2.5Ω

tfFall Time ––– 25 ––– VGS = 10V 

Ciss Input Capacitance ––– 2770 ––– VGS = 0V

Coss Output Capacitance ––– 590 ––– VDS = 25V

Crss Reverse Transfer Capacitance ––– 110 ––– pF ƒ = 1.0MHz

Coss Output Capacitance ––– 3940 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz

Coss Output Capacitance ––– 260 ––– VGS = 0V, VDS = 120V, ƒ = 1.0MHz

Coss eff. Effective Output Capacitance ––– 550 ––– VGS = 0V, VDS = 0V to 120V 

Dynamic @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units Conditions

ISContinuous Source Current MOSFET symbol

(Body Diode) ––– ––– showing the

ISM Pulsed Source Current integral reverse

(Body Diode)  ––– ––– p-n junction diode.

VSD Diode Forward Voltage ––– ––– 1.5 V TJ = 25°C, IS = 36A, VGS = 0V 

trr Reverse Recovery Time ––– 140 210 nS TJ = 25°C, IF = 36A

Qrr Reverse RecoveryCharge ––– 780 1170 nC di/dt = 100A/µs 

ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Diode Characteristics

240

Static @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units Conditions

V(BR)DSS Drain-to-Source Breakdown Voltage 150 ––– ––– V VGS = 0V, ID = 250µA

∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.16 ––– V/°C Reference to 25°C, ID = 1mA

RDS(on) Static Drain-to-Source On-Resistance ––– ––– 32 mΩVGS = 10V, ID = 36A 

VGS(th) Gate Threshold Voltage 3.0 ––– 5.0 V VDS = VGS, ID = 250µA

––– ––– 25 µA VDS = 150V, VGS = 0V

––– ––– 250 VDS = 120V, VGS = 0V, TJ = 150°C

Gate-to-Source Forward Leakage ––– ––– 100 VGS = 30V

Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -30V

IGSS

IDSS Drain-to-Source Leakage Current

Avalanche Characteristics

Parameter Units

EAS Single Pulse Avalanche Energy

IAR Avalanche Current

c

EAR Repetitive Avalanche Energy

VDS (Avalanche) Repetitive Avalanche Voltage

V200 ––– –––

–––

450

–––

Max.

470

Min. Typ.

––––––

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IRFB52N15DPbF/IRFS52N15DPbF/IRFSL52N15DPbF

Fig 4. Normalized On-Resistance

Vs. Temperature

Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics

-60 -40 -20 020 40 60 80 100 120 140 160 180

0.0

0.5

1.0

1.5

2.0

2.5

3.0

T , Junction Temperature ( C)

R , Drain-to-Source On Resistance

(Normalized)

DS(on)

V =

I =

10V

60A

0.1 110 100

VDS, Drain-to-Source Voltage (V)

0.1

100

1000

ID, Drain-to-Source Current (A)

5.0V

300µs PULSE WIDTH

Tj = 25°C

VGS

TOP 15V

12V

10V

8.0V

7.0V

6.0V

5.5V

BOTTOM 5.0V

0.1 110 100

VDS, Drain-to-Source Voltage (V)

0.1

100

1000

ID, Drain-to-Source Current (A)

5.0V

300µs PULSE WIDTH

Tj = 175°C

VGS

TOP 15V

12V

10V

8.0V

7.0V

6.0V

5.5V

BOTTOM 5.0V

5.0 7.0 9.0 11.0 13.0 15.0

VGS, Gate-to-Source Voltage (V)

1.00

10.00

100.00

1000.00

ID, Drain-to-Source Current (Α)

TJ = 25°C

TJ = 175°C

VDS = 15V

300µs PULSE WIDTH

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IRFB52N15DPbF/IRFS52N15DPbF/IRFSL52N15DPbF

Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge Vs.

Gate-to-Source Voltage

Fig 5. Typical Capacitance Vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain Diode

Forward Voltage

110 100 1000

VDS, Drain-to-Source Voltage (V)

100

1000

10000

100000

C, Capacitance(pF)

Coss

Crss

Ciss

VGS

= 0V, f = 1 MHZ

Ciss

= C

+ C

gd, C

SHORTED

Crss

= C

Coss

= C

+ C

0.0 0.5 1.0 1.5 2.0 2.5

VSD, Source-toDrain Voltage (V)

0.10

1.00

10.00

100.00

1000.00

ISD, Reverse Drain Current (A)

TJ = 25°C

TJ = 175°C

VGS = 0V

1 10 100 1000

VDS , Drain-toSource Voltage (V)

0.1

100

1000

ID, Drain-to-Source Current (A)

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREA

LIMITED BY RDS(on)

100µsec

0 10203040506070

QG Total Gate Charge (nC)

VGS, Gate-to-Source Voltage (V)

VDS= 120V

VDS= 75V

ID= 36A

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IRFB52N15DPbF/IRFS52N15DPbF/IRFSL52N15DPbF

Fig 10a. Switching Time Test Circuit

90%

10%

d(on)

d(off)

Fig 10b. Switching Time Waveforms

VDS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

VGS

D.U.T.

10V

VDD

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9. Maximum Drain Current Vs.

Case Temperature

25 50 75 100 125 150 175

T , Case Temperature ( C)

I , Drain Current (A)

0.001

0.01

0.1

0.00001 0.0001 0.001 0.01 0.1 1

Notes:

1. Duty factor D = t / t

2. Peak T = P x Z + T

1 2

JDM thJC C

t , Rectangular Pulse Duration (sec)

Thermal Response (Z )

thJC

0.01

0.02

0.05

0.10

0.20

D = 0.50

SINGLE PULSE

(THERMAL RESPONSE)

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IRFB52N15DPbF/IRFS52N15DPbF/IRFSL52N15DPbF

Charge

D.U.T. V

3mA

.3µF

50KΩ

.2µF

12V

Current Regulator

Same Type as D.U.T.

Current Sampling Resistors

10 V

Fig 13b. Gate Charge Test Circuit

Fig 13a. Basic Gate Charge Waveform

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

0.01

Ω

D.U.T

VDS

-V

DRIVER

15V

20V

25 50 75 100 125 150 175

180

360

540

720

900

Starting Tj, Junction Temperature ( C)

E , Single Pulse Avalanche Energy (mJ)

TOP

BOTTOM

15A

26A

36A

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IRFB52N15DPbF/IRFS52N15DPbF/IRFSL52N15DPbF

P.W. Period

di/dt

Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

=10V

Driver Gate Drive

D.U.T. I

Waveform

D.U.T. V

Waveform

Inductor Curent

D = P. W .

Period

Fig 14. For N-Channel HEXFET® Power MOSFETs

* VGS = 5V for Logic Level Devices

Peak Diode Recovery dv/dt Test Circuit







VDD

• dv/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer



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IRFB52N15DPbF/IRFS52N15DPbF/IRFSL52N15DPbF

TO-220AB Part Marking Information

TO-220AB Package Outline

Dimensions are shown in millimeters (inches)

Note: "P" inassembly line position

indicates "L ead - F ree"

LINE C

WEEK 19

PART NUMBER

DAT E CODE

YEAR 7 = 1997

AS S E MBLED ON WW 19, 1997

THIS IS AN IRF1010 EXAMPLE:

IN T HE ASSEMBLY LINE "C"

LOT CODE 1789 INT ERNAT IONAL

ASSEMBLY

LOT CODE

RECT IFIER

LOGO

TO-220 package is not recommended for Surface Mount Application.

Notes:

1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/

2. For the most current drawing please refer to IR website at http://www.irf.com/package/

www.irf.com 9

IRFB52N15DPbF/IRFS52N15DPbF/IRFSL52N15DPbF

D2Pak Part Marking Information

DAT E CODE

YEAR 0 = 2000

WEEK 02

A = ASSEMBLY SITE CODE

RECTIFIER

INTERNATIONAL PART NUMBER

P = DE S IGNAT E S L E AD - F R E E

PRODUCT (OPTIONAL)

F530S

IN THE ASSEMBLY LINE "L"

AS SE MBLE D ON WW 02, 2000

T HIS IS AN IRF 530S WIT H

LOT CODE 8024 INTERNATIONAL

LOGO

RECTIFIER

LOT CODE

ASSEMBLY YE AR 0 = 2000

PART NUMBER

DAT E CODE

LINE L

WEEK 02

F530S

LOGO

ASSEMBLY

LOT CODE

D2Pak Package Outline

Dimensions are shown in millimeters (inches)

Notes:

1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/

2. For the most current drawing please refer to IR website at http://www.irf.com/package/

10 www.irf.com

IRFB52N15DPbF/IRFS52N15DPbF/IRFSL52N15DPbF

TO-262 Part Marking Information

TO-262 Package Outline

Dimensions are shown in millimeters (inches)

LOGO

RECT IFIER

INT E RNAT IONAL

LOT CODE

AS S E MB L Y

LOGO

RECT IFIER

INTERNATIONAL

DAT E CODE

WE E K 1 9

YEAR 7 = 1997

PART NUMBER

A = AS S E MB L Y S I T E COD E

PRODUCT (OPTIONAL)

P = DE S I GN AT E S L E AD - F R E E

EXAMPLE: T HIS IS AN IRL3103L

LOT CODE 1789

AS S E MB L Y

PART NUMBE R

DAT E CODE

WE E K 1 9

LINE C

LOT CODE

YEAR 7 = 1997

ASS EMBLED ON WW 19, 1997

IN THE ASSEMBLY LINE "C"

IGBT

1- GATE

Notes:

1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/

2. For the most current drawing please refer to IR website at http://www.irf.com/package/

www.irf.com 11

IRFB52N15DPbF/IRFS52N15DPbF/IRFSL52N15DPbF

 1% Duty cycle, 100 pulses, limited by

max. junction temperature.

 Starting TJ = 25°C, L = 0.72mH

RG = 25Ω, IAS = 36A.

ISD ≤ 36A, di/dt ≤ 400A/µs, VDD ≤ V(BR)DSS,

TJ ≤ 175°C.

 Pulse width ≤ 300µs; duty cycle ≤ 2%.

Notes:

 Coss eff. is a fixed capacitance that gives the same charging time

as Coss while VDS is rising from 0 to 80% VDSS.

 This is only applied to TO-220AB package.

 This is applied to D2Pak, when mounted on 1" square PCB

(FR-4 or G-10 Material ). For recommended footprint and soldering

techniques refer to application note #AN-994.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.09/2010

D2Pak Tape & Reel Information

TRR

FEED DIRECTION

1.85 (.073)

1.65 (.065)

1.60 (.063)

1.50 (.059)

4.10 (.161)

3.90 (.153)

TRL

FEED DIRECTION

10.90 (.429)

10.70 (.421)

16.10 (.634)

15.90 (.626)

1.75 (.069)

1.25 (.049)

11.60 (.457)

11.40 (.449) 15.42 (.609)

15.22 (.601)

4.72 (.136)

4.52 (.178)

24.30 (.957)

23.90 (.941)

0.368 (.0145)

0.342 (.0135)

1.60 (.063)

1.50 (.059)

13.50 (.532)

12.80 (.504)

330.00

(14.173)

MAX.

27.40 (1.079)

23.90 (.941)

60.00 (2.362)

MIN.

30.40 (1.197)

MAX.

26.40 (1.039)

24.40 (.961)

NOTES :

1. COMFORMS TO EIA-418.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION MEASURED @ HUB.

4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.