INTEGRATED CIRCUITS DATA SHEET Family Specifications January 1995 File under Integrated Circuits, IC04 Philips Semiconductors Family Specifications INTRODUCTION These specifications cover the common electrical characteristics of the entire HE4000B family, unless otherwise specified in the individual device data sheet. The LOCMOS HE4000B family devices will operate over a recommended VDD power supply range of 3 to 15 V, as referenced to VSS (usually ground). Parametric limits are guaranteed for VDD of 5, 10 and 15 V. Because of the wide operating voltage, power supply regulation is less critical than with other types of logic. The lower limit of the supply voltage is 3 V, or as determined by required system speed and/or noise immunity or interface to other logic. The recommended upper limit is 15 V or as determined by power dissipation constraints or interface to other logic. Unused inputs must be connected to VDD, VSS or another input. Inputs and outputs are protected against electrostatic effects in a wide variety of device-handling situations. However, to be totally safe, it is desirable to take handling precautions into account. RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDD Supply voltage -0.5 - +18 VI Voltage on any input -0.5 - VDD + 0.5 V I DC current into any input or output - - 10 mA Ptot Power dissipation per package 750 mW HEF (plastic and ceramic DIL) Tamb = -40 to +70 C Tamb = +70 to +85 C HEF (plastic SO mini-pack) HEC (ceramic DIL) derate linearly with 12 mW/K Tamb = -40 to +70 C Tamb = +70 to +85 C 500 mW derate linearly with 8 mW/K Tamb = -55 to +70 C Tamb = +70 to +125 C V 500 mW derate linearly with 8 mW/K P Power dissipation per output - - 100 mW Tstg Storage temperature -65 - +150 C Tamb Operating ambient temperature (HEF) -40 - +85 C Tamb Operating ambient temperature (HEC) -55 - +125 C January 1995 2 Philips Semiconductors January 1995 DC CHARACTERISTICS FOR HEF VSS = 0 V; for all devices unless otherwise specified. Tamb (C) SYMBOL VDD (V) PARAMETER -40 MIN. IDD buffers, flip-flops MSI LSI 3 VOH VIH MIN. MAX. MIN. UNIT CONDITIONS MAX. Output voltage LOW Output voltage HIGH Input voltage LOW (buffered stages only) Input voltage HIGH (buffered stages only) 5 - 1.0 - 1.0 - 7.5 10 - 2.0 - 2.0 - 15.0 15 - 4.0 - 4.0 - 30.0 5 - 4.0 - 4.0 - 30 10 - 8.0 - 8.0 - 60 15 - 16.0 - 16.0 - 120 5 - 20 - 20 - 150 10 - 40 - 40 - 300 15 - 80 - 80 - 600 5 - 50 - 50 - 375 10 - 100 - 100 - 750 15 - 200 - 200 - 1500 5 - 0.05 - 0.05 - 0.05 10 - 0.05 - 0.05 - 0.05 15 - 0.05 - 0.05 - 0.05 5 4.95 - 4.95 - 4.95 - A all valid input combinations; VI = VSS or VDD; IO = 0 A A A V VI = VSS or VDD; IO < 1 A V VI = VSS or VDD; IO < 1 A V VO = 0.5 V or 4.5 V; IO < 1 A 10 9.95 - 9.95 - 9.95 - 15 14.95 - 14.95 - 14.95 - 5 - 1.5 - 1.5 - 1.5 10 - 3.0 - 3.0 - 3.0 VO = 1.0 V or 9.0 V; IO < 1 A 15 - 4.0 - 4.0 - 4.0 VO = 1.5 V or 13.5 V; IO < 1 A 5 3.5 - 3.5 - 3.5 - 10 7.0 - 7.0 - 7.0 - VO = 1.0 V or 9.0 V; IO < 1 A 15 11.0 - 11.0 - 11.0 - VO = 1.5 V or 13.5 V; IO < 1 A V VO = 0.5 V or 4.5 V; IO < 1 A Family Specifications VIL MAX. +85 Quiescent device current gates VOL +25 Philips Semiconductors January 1995 Tamb (C) SYMBOL VDD (V) PARAMETER -40 MIN. VIL VIH IOL -IOH Input voltage LOW (unbuffered stages only) Input voltage HIGH (unbuffered stages only) Output (sink) current LOW Output (source) current HIGH +25 MAX. MIN. +85 MAX. MIN. UNIT CONDITIONS MAX. 5 - 1 - 1 - 1 10 - 2 - 2 - 2 VO = 1.0 V or 9.0 V; IO < 1 A 15 - 2.5 - 2.5 - 2.5 VO = 1.5 V or 13.5 V; IO < 1 A 5 4 - 4 - 4 - 10 8 - 8 - 8 - 15 12.5 - 12.5 - 12.5 - 5 0.52 - 0.44 - 0.36 - 10 1.3 - 1.1 - 0.9 - 15 3.6 - 3.0 - 2.4 - 5 0.52 - 0.44 - 0.36 - 10 1.3 - 1.1 - 0.9 - V V VO = 0.5 V or 4.5 V; IO < 1 A VO = 0.5 V or 4.5 V; IO < 1 A VO = 1.0 V or 9.0 V; IO < 1 A VO = 1.5 V or 13.5 V; IO < 1 A mA VO = 0.4 V; VI = 0 or 5 V VO = 0.5 V; VI = 0 or 10 V VO = 1.5 V; VI = 0 or 15 V mA VO = 4.6 V; VI = 0 or 5 V VO = 9.5 V; VI = 0 or 10 V 3.6 - 3.0 - 2.4 - Output (source) current HIGH 5 1.7 - 1.4 - 1.1 - mA VO = 2.5 V; VI = 0 or 5 V IIN Input leakage current 15 - 0.3 - 0.3 - 1.0 A VI = 0 or 15 V IOZH 3-state output leakage current; HIGH 15 - 1.6 - 1.6 - 12.0 A output returned to VDD -IOZL 3-state output leakage current; LOW 15 - 1.6 - 1.6 - 12.0 A output returned to VSS 4 15 -IOH VO = 13.5 V; VI = 0 or 15 V Family Specifications Philips Semiconductors January 1995 DC CHARACTERISTICS FOR HEC VSS = 0 V; for all devices unless otherwise specified. Tamb (C) SYMBOL VDD (V) PARAMETER -55 MIN. IDD buffers, flip-flops MSI LSI 5 VOH VIH MIN. MAX. MIN. UNIT CONDITIONS MAX. Output voltage LOW Output voltage HIGH Input voltage LOW (buffered stages only) Input voltage HIGH (buffered stages only) 5 - 0.25 - 0.25 - 7.5 10 - 0.5 - 0.5 - 15.0 15 - 1.0 - 1.0 - 30.0 5 - 1.0 - 1.0 - 30 10 - 2.0 - 2.0 - 60 15 - 4.0 - 4.0 - 120 5 - 5.0 - 5.0 - 150 10 - 10.0 - 10.0 - 300 15 - 20.0 - 20.0 - 600 5 - 15 - 15 - 375 10 - 25 - 25 - 750 15 - 50 - 50 - 1500 5 - 0.05 - 0.05 - 0.05 10 - 0.05 - 0.05 - 0.05 15 - 0.05 - 0.05 - 0.05 5 4.95 - 4.95 - 4.95 - A all valid input combinations; VI = VSS or VDD; IO = 0 A A A V VI = VSS or VDD; IO < 1 A V VI = VSS or VDD; IO < 1 A V VO = 0.5 V or 4.5 V; IO < 1 A 10 9.95 - 9.95 - 9.95 - 15 14.95 - 14.95 - 14.95 - 5 - 1.5 - 1.5 - 1.5 10 - 3.0 - 3.0 - 3.0 VO = 1.0 V or 9.0 V; IO < 1 A 15 - 4.0 - 4.0 - 4.0 VO = 1.5 V or 13.5 V; IO < 1 A 5 3.5 - 3.5 - 3.5 - 10 7.0 - 7.0 - 7.0 - VO = 1.0 V or 9.0 V; IO < 1 A 15 11.0 - 11.0 - 11.0 - VO = 1.5 V or 13.5 V; IO < 1 A V VO = 0.5 V or 4.5 V; IO < 1 A Family Specifications VIL MAX. +125 Quiescent device current gates VOL +25 Philips Semiconductors January 1995 Tamb (C) SYMBOL VDD (V) PARAMETER -55 MIN. VIL VIH IOL -IOH Input voltage LOW (unbuffered stages only) Input voltage HIGH (unbuffered stages only) Output (sink) current LOW Output (source) current HIGH +25 MAX. MIN. +125 MAX. MIN. UNIT CONDITIONS MAX. 5 - 1 - 1 - 1 10 - 2 - 2 - 2 VO = 1.0 V or 9.0 V; IO < 1 A 15 - 2.5 - 2.5 - 2.5 VO = 1.5 V or 13.5 V; IO < 1 A 5 4 - 4 - 4 - 10 8 - 8 - 8 - 15 12.5 - 12.5 - 12.5 - 5 0.64 - 0.5 - 0.36 - 10 1.6 - 1.3 - 0.9 - 15 4.2 - 3.4 - 2.4 - 5 0.64 - 0.5 - 0.36 - 10 1.6 - 1.3 - 0.9 - V V VO = 0.5 V or 4.5 V; IO < 1 A VO = 0.5 V or 4.5 V; IO < 1 A VO = 1.0 V or 9.0 V; IO < 1 A VO = 1.5 V or 13.5 V; IO < 1 A mA VO = 0.4 V; VI = 0 or 5 V VO = 0.5 V; VI = 0 or 10 V VO = 1.5 V; VI = 0 or 15 V mA VO = 4.6 V; VI = 0 or 5 V VO = 9.5 V; VI = 0 or 10 V 4.2 - 3.4 - 2.4 - Output (source) current HIGH 5 1.7 - 1.4 - 1.1 - mA VO = 2.5 V; VI = 0 or 5 V IIN Input leakage current 15 - 0.1 - 0.1 - 1.0 A VI = 0 or 15 V IOZH 3-state output leakage current; HIGH 15 - 0.4 - 0.4 - 12.0 A output returned to VDD -IOZL 3-state output leakage current; LOW 15 - 0.4 - 0.4 - 12.0 A output returned to VSS 6 15 -IOH VO = 13.5 V; VI = 0 or 15 V Family Specifications Philips Semiconductors Family Specifications MGK555 0 MGK556 6 handbook, halfpage handbook, halfpage ID (mA) ID (mA) min -2 4 -4 2 typ min typ -6 -5 -4 -3 -2 -1 0 0 VDS (V) 0 VDD = 5 V; Tamb = 25 C 1 2 3 4 5 VDS (V) VDD = 5 V; Tamb = 25 C Fig.1 P-channel drain characteristics (source). Fig.2 N-channel drain characteristics (sink). MGK557 0 MGK558 30 handbook, halfpage handbook, halfpage ID (mA) ID (mA) typ min -10 20 -20 10 min typ -30 -10 -8 -6 -4 -2 0 0 VDS (V) 0 VDD = 10 V; Tamb = 25 C 4 6 8 10 VDS (V) VDD = 10 V; Tamb = 25 C Fig.3 P-channel drain characteristics (source). January 1995 2 Fig.4 N-channel drain characteristics (sink). 7 Philips Semiconductors Family Specifications MGK553 0 D (mA) -10 MGK554 60 D (mA) 50 handbook, I halfpage handbook, I halfpage min -20 40 -30 30 -40 20 typ min -50 typ -60 -15 10 -10 -5 0 VDS (V) 0 0 VDD = 15 V; Tamb = 25 C 10 VDS (V) 15 VDD = 15 V; Tamb = 25 C Fig.5 P-channel drain characteristics (source). Fig.6 N-channel drain characteristics (sink). Note: temperature coefficient: -0.4%/C January 1995 5 8 Philips Semiconductors Family Specifications AC CHARACTERISTICS Clock input rise and fall times (tr, tf) The upper limits on tr and tf vary widely from device to device and with supply voltage. Unless otherwise specified in the individual data sheets it is recommended that input rise and fall times be less than 15 s for VDD = 5 V; 4 s for VDD = 10 V; 1 s for VDD = 15 V. Output transition times (tTLH, tTHL) VSS = 0; Tamb = 25 C; CL = 50 pF; input transition times 20 ns. SYMBOL VDD (V) PARAMETER MIN. TYP. MAX. UNIT TYPICAL EXTRAPOLATION FORMULA output transition times tTHL tTLH HIGH to LOW LOW to HIGH 5 60 120 ns 10 ns + (1.0 ns/pF) CL 10 30 60 ns 9 ns + (0.42 ns/pF) CL 15 20 40 ns 6 ns + (0.28 ns/pF) CL 5 60 120 ns 10 ns + (1.0 ns/pF) CL 10 30 60 ns 9 ns + (0.42 ns/pF) CL 15 20 40 ns 6 ns + (0.28 ns/pF) CL Temperature coefficient (typical values) Propagation delays +0.35%/C Output transition times +0.35%/C Input capacitance (digital inputs) Maximum input capacitance CI = 7.5 pF January 1995 9 Philips Semiconductors Family Specifications tr handbook, full pagewidth tf VDD 90% CLOCK INPUT 50% 10% VSS tWCPH tWCPL thold thold VDD DATA INPUT 50% tsu VSS tsu tTLH tTHL 90% OUTPUT 50% 10% tR SET, RESET, PRESET INPUT VOH tPLH tPHL VOL VDD 50% MGK561 In the waveforms above the active transition of the clock input is going from LOW to HIGH and the active level of the forcing signals (SET, CLEAR and PRESET) is HIGH. The actual direction of the active transition of the clock input and the actual active levels of the forcing signals are specified in the individual device data sheet. Fig.7 Set-up times, hold times, recovery times and propagation delays for sequential logic circuits. January 1995 10 Philips Semiconductors Family Specifications 20 ns handbook, full pagewidth 20 ns VDD 90% OUTPUT ENABLE 50% 10% tPLZ VSS tPZL VDD 90% OUTPUT LOW-to-OFF OFF-to-LOW 10% VOL tPZH tPHZ VOH 90% OUTPUT HIGH-to-OFF OFF-to-HIGH 10% outputs connected MGK559 VSS outputs connected outputs disconnected Fig.8 Propagation delays of 3-state outputs. handbook, halfpage other inputs output disable IC with 3-state outputs RL = 1 k VDD for tPLZ, tPZL VSS for tPHZ, tPZH CL = 50 pF MGK560 Fig.9 Test circuit of 3-state output ICs. January 1995 11 Philips Semiconductors Family Specifications DEFINITIONS OF SYMBOLS AND TERMS USED IN DATA SHEETS Currents Voltages Positive current is defined as conventional current flow into a device. Negative current is defined as conventional current flow out of a device. All voltages are referenced to VSS, which is the most negative potential applied to the device. IIN Input current; the current flowing into a device at specified input voltage and VDD. IOH Output current HIGH; the drive current flowing out of a device at specified HIGH output voltage and VDD. IOL Output current LOW; the drive current flowing into a device at specified LOW output voltage and VDD. IDD Quiescent power supply current; the current flowing into the VDD lead at specified input and VDD conditions. IOZ Output OFF current; the leakage current flowing into or out of the output of a 3-state device in the OFF state when the output is connected to VDD or VSS. IIL Input current LOW; the current flowing into a device at a specified LOW level input voltage and a specified VDD. IIH Input current HIGH; the current flowing into a device at a specified HIGH level input voltage and a specified VDD. IDDL Quiescent power supply current LOW; the current flowing into the VDD lead with a specified LOW level input voltage on all inputs and specified VDD conditions. IDDH Quiescent power supply current HIGH; the current flowing into the VDD lead with a specified HIGH level input voltage on all inputs and specified VDD conditions. IZ OFF state leakage current; the leakage current flowing into the output of a 3-state device in the OFF state at a specified output voltage and VDD. January 1995 VDD Supply voltage; the most positive potential on the device. VSS Supply voltage; for a device with a single negative power supply, the most negative power supply, used as the reference level for other voltages; typically ground. VEE Supply voltage; one of two (VSS and VEE) negative power supplies. For a device with dual negative power supply, the most negative power supply as a reference level for other voltages. VIH Input voltage HIGH; the range of input voltages that represents a logic HIGH level in the system. VIL Input voltage LOW; the range of input voltages that represents a logic LOW level in the system. VOH Output voltage HIGH; the range of voltages at an output terminal with a specified output loading and supply voltage. Device inputs are conditioned to establish a HIGH level at the output. VOL Output voltage LOW; the range of voltages at an output terminal with a specified output loading and supply voltage. Device inputs are conditioned to establish a LOW level at the output. VP Trigger threshold voltage; positive-going signal. VN Trigger threshold voltage; negative-going signal. Analogue terms 12 RON ON resistance; the effective ON state resistance of an analogue transmission gate, at specified input voltage, output load and VDD. RON ON resistance; the difference in effective ON resistance between any two transmission gates of an analogue device at specified input voltage, output load and VDD. Philips Semiconductors Family Specifications AC switching parameters fi Input frequency; for combinatorial logic devices the maximum number of inputs and outputs switching in accordance with the device truth table. For sequential logic devices the clock frequency using alternate HIGH and LOW for data input or using the toggle mode, whichever is applicable. fo Output frequency; each output. fmax Clock frequency; clock input waveform should have a 50% duty cycle and be such as to cause the outputs to be switching from 10%VDD to 90%VDD in accordance with the device truth table. tr, tf Clock input rise and fall times; 10% and 90% value. tPLH Propagation delay time; the time between the specified reference points, normally the 50% points on the input and output waveforms, with the output changing from the defined LOW level to the defined HIGH level. tPHL Propagation delay time; the time between the specified reference points, normally the 50% points on the input and output waveforms, with the output changing from the defined HIGH level to the defined LOW level. tTLH Transition time, LOW-to-HIGH; the time between two specified reference points on a waveform, normally 10% and 90% points, that is changing from LOW to HIGH. tTHL Transition time, HIGH-to-LOW; the time between two specified reference points on a waveform, normally 90% and 10% points, that is changing from HIGH to LOW. tW Pulse width; the time between the 50% amplitude points on the leading and trailing edges of a pulse. thold Hold time; the interval immediately following the active transition of the timing pulse (usually the clock pulse) or following the transition of the control input to its latching level, during which interval the data to be recognized must be maintained at the input to ensure their continued recognition. A negative hold time indicates that the correct logic level may be released prior to the timing pulse and still be recognized. January 1995 13 tsu Set-up time; the interval immediately preceding the active transition of the timing pulse (usually the clock pulse) or preceding the transition of the control input to its latching level, during which interval the data to be recognized must be maintained at the input to ensure their recognition. A negative set-up time indicates that the correct logic level may be initiated sometime after the active transition of the timing pulse and still be recognized. tPHZ 3-state output disable time, HIGH to Z; the time between the specified reference points, normally the 50% point on the output enable input voltage waveform and a point representing a 0.1 VOH drop on the output voltage waveform of a 3-state device, with the output changing from the output HIGH level (VOH) to a high impedance OFF-state. tPLZ 3-state output disable time, LOW to Z; the time between the specified reference points, normally the 50% point on the output enable input voltage waveform and a point representing a 0.1 (VDD - VOL) rise on the output voltage waveform of a 3-state device, with the output changing from the output LOW level (VOL) to a high impedance OFF-state. tPZH 3-state output enable time, Z to HIGH; the time between the specified reference points, normally the 50% point on the output enable input voltage waveform and a point representing a 0.1 VOH rise on the output voltage waveform of a 3-state device, with the output changing from a high impedance OFF-state to the output HIGH level (VOH). tPZL 3-state output enable time, Z to LOW; the time between the specified reference points, normally the 50% point on the output enable input voltage waveform and a point representing a 0.1 (VDD - VOL) voltage drop on the output voltage waveform of a 3-state device, with the output changing from a high impedance OFF-state to the output LOW level (VOL). tR Recovery time; the time between the end of an overriding asynchronous input, typically a clear or reset input, and the earliest permissible beginning of a synchronous control input, typically a clock input, normally measured at 50% points on both input voltage waveforms.