DATA SH EET
File under Integrated Circuits, IC04 January 1995
INTEGRATED CIRCUITS
Family Specifications
January 1995 2
Philips Semiconductors
Family Specifications
INTRODUCTION
These specifications cover the common electrical characteristics of the entire HE4000B family, unless otherwise
specified in the individual device data sheet.
The LOCMOS HE4000B family devices will operate over a recommended VDD power supply range of 3 to 15 V, as
referenced to VSS (usually ground). Parametric limits are guaranteed for VDD of 5, 10 and 15 V. Because of the wide
operating voltage, power supply regulation is less critical than with other types of logic. The lower limit of the supply
voltage is 3 V, or as determined by required system speed and/or noise immunity or interface to other logic. The
recommended upper limit is 15 V or as determined by power dissipation constraints or interface to other logic. Unused
inputs must be connected to VDD, VSS or another input. Inputs and outputs are protected against electrostatic effects in
a wide variety of device-handling situations. However, to be totally safe, it is desirable to take handling precautions into
account.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VDD Supply voltage −0.5 −+18 V
VIVoltage on any input −0.5 −VDD + 0.5 V
±I DC current into any input or output −−10 mA
Ptot Power dissipation per package
HEF (plastic and ceramic DIL) Tamb = −40 to +70 °C 750 mW
Tamb = +70 to +85 °C derate linearly with 12 mW/K
HEF (plastic SO mini-pack) Tamb = −40 to +70 °C 500 mW
Tamb = +70 to +85 °C derate linearly with 8 mW/K
HEC (ceramic DIL) Tamb = −55 to +70 °C 500 mW
Tamb = +70 to +125 °C derate linearly with 8 mW/K
P Power dissipation per output −−100 mW
Tstg Storage temperature −65 −+150 °C
Tamb Operating ambient temperature (HEF) −40 −+85 °C
Tamb Operating ambient temperature (HEC) −55 −+125 °C
January 1995 3
Philips Semiconductors
Family Specifications
DC CHARACTERISTICS FOR HEF
VSS = 0 V; for all devices unless otherwise specified.
SYMBOL PARAMETER VDD
(V)
Tamb (°C)
UNIT CONDITIONS−40 +25 +85
MIN. MAX. MIN. MAX. MIN. MAX.
IDD Quiescent device current
gates 5 −1.0 −1.0 −7.5 µA all valid input combinations;
VI=V
SS or VDD; IO=0
10 −2.0 −2.0 −15.0
15 −4.0 −4.0 −30.0
buffers, flip-flops 5 −4.0 −4.0 −30 µA
10 −8.0 −8.0 −60
15 −16.0 −16.0 −120
MSI 5 −20 −20 −150 µA
10 −40 −40 −300
15 −80 −80 −600
LSI 5 −50 −50 −375 µA
10 −100 −100 −750
15 −200 −200 −1500
VOL Output voltage LOW 5 −0.05 −0.05 −0.05 V VI=V
SS or VDD;IO<1µA
10 −0.05 −0.05 −0.05
15 −0.05 −0.05 −0.05
VOH Output voltage HIGH 5 4.95 −4.95 −4.95 −VV
I
=V
SS or VDD;IO<1µA
10 9.95 −9.95 −9.95 −
15 14.95 −14.95 −14.95 −
VIL Input voltage LOW
(buffered stages only) 5−1.5 −1.5 −1.5 V VO= 0.5 V or 4.5 V; IO<1µA
10 −3.0 −3.0 −3.0 VO= 1.0 V or 9.0 V; IO<1µA
15 −4.0 −4.0 −4.0 VO= 1.5 V or 13.5 V; IO<1µA
V
IH Input voltage HIGH
(buffered stages only) 5 3.5 −3.5 −3.5 −VV
O
= 0.5 V or 4.5 V; IO<1µA
10 7.0 −7.0 −7.0 −VO= 1.0 V or 9.0 V; IO<1µA
15 11.0 −11.0 −11.0 −VO= 1.5 V or 13.5 V; IO<1µA
January 1995 4
Philips Semiconductors
Family Specifications
VIL Input voltage LOW
(unbuffered stages only) 5−1−1−1VV
O
= 0.5 V or 4.5 V; IO<1µA
10 −2−2−2V
O
= 1.0 V or 9.0 V; IO<1µA
15 −2.5 −2.5 −2.5 VO= 1.5 V or 13.5 V; IO<1µA
V
IH Input voltage HIGH
(unbuffered stages only) 54 −4−4−VV
O
= 0.5 V or 4.5 V; IO<1µA
10 8 −8−8−VO= 1.0 V or 9.0 V; IO<1µA
15 12.5 −12.5 −12.5 −VO= 1.5 V or 13.5 V; IO<1µA
I
OL Output (sink) current LOW 5 0.52 −0.44 −0.36 −mA VO= 0.4 V; VI=0or5V
10 1.3 −1.1 −0.9 −VO= 0.5 V; VI= 0 or 10 V
15 3.6 −3.0 −2.4 −VO= 1.5 V; VI= 0 or 15 V
−IOH Output (source) current
HIGH 5 0.52 −0.44 −0.36 −mA VO= 4.6 V; VI=0or5V
10 1.3 −1.1 −0.9 −VO= 9.5 V; VI= 0 or 10 V
15 3.6 −3.0 −2.4 −VO= 13.5 V; VI= 0 or 15 V
−IOH Output (source) current
HIGH 5 1.7 −1.4 −1.1 −mA VO= 2.5 V; VI=0or5V
± IIN Input leakage current 15 −0.3 −0.3 −1.0 µAV
I
= 0 or 15 V
IOZH 3-state output leakage
current; HIGH 15 −1.6 −1.6 −12.0 µA output returned to VDD
−IOZL 3-state output leakage
current; LOW 15 −1.6 −1.6 −12.0 µA output returned to VSS
SYMBOL PARAMETER VDD
(V)
Tamb (°C)
UNIT CONDITIONS−40 +25 +85
MIN. MAX. MIN. MAX. MIN. MAX.
January 1995 5
Philips Semiconductors
Family Specifications
DC CHARACTERISTICS FOR HEC
VSS = 0 V; for all devices unless otherwise specified.
SYMBOL PARAMETER VDD
(V)
Tamb (°C)
UNIT CONDITIONS−55 +25 +125
MIN. MAX. MIN. MAX. MIN. MAX.
IDD Quiescent device current
gates 5 −0.25 −0.25 −7.5 µA all valid input combinations;
VI=V
SS or VDD; IO=0
10 −0.5 −0.5 −15.0
15 −1.0 −1.0 −30.0
buffers, flip-flops 5 −1.0 −1.0 −30 µA
10 −2.0 −2.0 −60
15 −4.0 −4.0 −120
MSI 5 −5.0 −5.0 −150 µA
10 −10.0 −10.0 −300
15 −20.0 −20.0 −600
LSI 5 −15 −15 −375 µA
10 −25 −25 −750
15 −50 −50 −1500
VOL Output voltage LOW 5 −0.05 −0.05 −0.05 V VI=V
SS or VDD;IO<1µA
10 −0.05 −0.05 −0.05
15 −0.05 −0.05 −0.05
VOH Output voltage HIGH 5 4.95 −4.95 −4.95 −VV
I
=V
SS or VDD;IO<1µA
10 9.95 −9.95 −9.95 −
15 14.95 −14.95 −14.95 −
VIL Input voltage LOW
(buffered stages only) 5−1.5 −1.5 −1.5 V VO= 0.5 V or 4.5 V; IO<1µA
10 −3.0 −3.0 −3.0 VO= 1.0 V or 9.0 V; IO<1µA
15 −4.0 −4.0 −4.0 VO= 1.5 V or 13.5 V; IO<1µA
V
IH Input voltage HIGH
(buffered stages only) 5 3.5 −3.5 −3.5 −VV
O
= 0.5 V or 4.5 V; IO<1µA
10 7.0 −7.0 −7.0 −VO= 1.0 V or 9.0 V; IO<1µA
15 11.0 −11.0 −11.0 −VO= 1.5 V or 13.5 V; IO<1µA
January 1995 6
Philips Semiconductors
Family Specifications
VIL Input voltage LOW
(unbuffered stages only) 5−1−1−1VV
O
= 0.5 V or 4.5 V; IO<1µA
10 −2−2−2V
O
= 1.0 V or 9.0 V; IO<1µA
15 −2.5 −2.5 −2.5 VO= 1.5 V or 13.5 V; IO<1µA
V
IH Input voltage HIGH
(unbuffered stages only) 54 −4−4−VV
O
= 0.5 V or 4.5 V; IO<1µA
10 8 −8−8−VO= 1.0 V or 9.0 V; IO<1µA
15 12.5 −12.5 −12.5 −VO= 1.5 V or 13.5 V; IO<1µA
I
OL Output (sink) current LOW 5 0.64 −0.5 −0.36 −mA VO= 0.4 V; VI=0or5V
10 1.6 −1.3 −0.9 −VO= 0.5 V; VI= 0 or 10 V
15 4.2 −3.4 −2.4 −VO= 1.5 V; VI= 0 or 15 V
−IOH Output (source) current
HIGH 5 0.64 −0.5 −0.36 −mA VO= 4.6 V; VI=0or5V
10 1.6 −1.3 −0.9 −VO= 9.5 V; VI= 0 or 10 V
15 4.2 −3.4 −2.4 −VO= 13.5 V; VI= 0 or 15 V
−IOH Output (source) current
HIGH 5 1.7 −1.4 −1.1 −mA VO= 2.5 V; VI=0or5V
± IIN Input leakage current 15 −0.1 −0.1 −1.0 µAV
I
= 0 or 15 V
IOZH 3-state output leakage
current; HIGH 15 −0.4 −0.4 −12.0 µA output returned to VDD
−IOZL 3-state output leakage
current; LOW 15 −0.4 −0.4 −12.0 µA output returned to VSS
SYMBOL PARAMETER VDD
(V)
Tamb (°C)
UNIT CONDITIONS−55 +25 +125
MIN. MAX. MIN. MAX. MIN. MAX.
January 1995 7
Philips Semiconductors
Family Specifications
Fig.1 P-channel drain characteristics (source).
VDD = 5 V; Tamb = 25 °C
handbook, halfpage
−50
0
−6
−4
−2
MGK555
−4−3−2−1VDS (V)
ID
(mA)
typ
min
Fig.2 N-channel drain characteristics (sink).
VDD = 5 V; Tamb = 25 °C
handbook, halfpage
05
6
0
2
4
MGK556
1234
V
DS (V)
ID
(mA)
typ
min
Fig.3 P-channel drain characteristics (source).
VDD = 10 V; Tamb = 25 °C
handbook, halfpage
−10 0
0
−20
−30
−10
MGK557
−8−6−4−2
ID
(mA)
VDS (V)
typ
min
Fig.4 N-channel drain characteristics (sink).
VDD = 10 V; Tamb = 25 °C
handbook, halfpage
010
30
10
0
20
MGK558
2468
I
D
(mA)
VDS (V)
typ
min
January 1995 8
Philips Semiconductors
Family Specifications
Fig.5 P-channel drain characteristics (source).
VDD = 15 V; Tamb = 25 °C
handbook, halfpage
−15 −10 0
0
−60
MGK553
−5
−50
−40
−30
−10
−20
VDS (V)
ID
(mA)
typ
min
Fig.6 N-channel drain characteristics (sink).
VDD = 15 V; Tamb = 25 °C
handbook, halfpage
05 15
60
0
MGK554
10
10
20
30
50
40
VDS (V)
ID
(mA) typ
min
Note: temperature coefficient: −0.4%/°C
January 1995 9
Philips Semiconductors
Family Specifications
AC CHARACTERISTICS
Clock input rise and fall times (tr, tf)
The upper limits on tr and tf vary widely from device to device and with supply voltage. Unless otherwise specified in the
individual data sheets it is recommended that input rise and fall times be less than 15 µs for VDD = 5 V; 4 µs for
VDD = 10 V; 1 µs for VDD =15V.
Output transition times (tTLH, tTHL)
VSS = 0; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns.
Temperature coefficient (typical values)
Propagation delays +0.35%/°C
Output transition times +0.35%/°C
Input capacitance (digital inputs)
Maximum input capacitance CI= 7.5 pF
SYMBOL PARAMETER VDD
(V) MIN. TYP. MAX. UNIT TYPICAL EXTRAPOLATION
FORMULA
output transition times
tTHL HIGH to LOW 5 60 120 ns 10 ns + (1.0 ns/pF) CL
10 30 60 ns 9 ns + (0.42 ns/pF) CL
15 20 40 ns 6 ns + (0.28 ns/pF) CL
tTLH LOW to HIGH 5 60 120 ns 10 ns + (1.0 ns/pF) CL
10 30 60 ns 9 ns + (0.42 ns/pF) CL
15 20 40 ns 6 ns + (0.28 ns/pF) CL
January 1995 10
Philips Semiconductors
Family Specifications
Fig.7 Set-up times, hold times, recovery times and propagation delays for sequential logic circuits.
In the waveforms above the active transition of the clock input is going from LOW to HIGH and
the active level of the forcing signals (SET, CLEAR and PRESET) is HIGH.
The actual direction of the active transition of the clock input and the actual active levels of the
forcing signals are specified in the individual device data sheet.
handbook, full pagewidth
MGK561
10%
90%
50%
CLOCK
INPUT
VDD
VSS
VOH
VOL
50%
DATA
INPUT
VDD
VSS
10%
90%
50%
OUTPUT
tsu
tPHL
tPLH
tsu tTLH tTHL
50%
SET,
RESET,
PRESET
INPUT
VDD
trtf
tWCPH
thold thold
tWCPL
tR
January 1995 11
Philips Semiconductors
Family Specifications
Fig.8 Propagation delays of 3-state outputs.
handbook, full pagewidth
MGK559
tPLZ
tPHZ
outputs
disconnected outputs
connected
90%
10%
10%
90%
50%
outputs
connected
OUTPUT
LOW-to-OFF
OFF-to-LOW
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
OUTPUT
ENABLE
VDD
VSS
VDD
VSS
VOL
VOH
tPZL
tPZH
90%
10%
20 ns 20 ns
Fig.9 Test circuit of 3-state output ICs.
handbook, halfpage
MGK560
IC
with
3-state
outputs
other
inputs
output
disable
RL = 1 kΩ
CL = 50 pF
VDD for tPLZ, tPZL
VSS for tPHZ, tPZH
January 1995 12
Philips Semiconductors
Family Specifications
DEFINITIONS OF SYMBOLS AND TERMS USED IN
DATA SHEETS
Currents
Positive current is defined as conventional current flow
into a device.
Negative current is defined as conventional current flow
out of a device.
IIN Input current; the current flowing into a device
at specified input voltage and VDD.
IOH Output current HIGH; the drive current flowing
out of a device at specified HIGH output voltage
and VDD.
IOL Output current LOW; the drive current flowing
into a device at specified LOW output voltage
and VDD.
IDD Quiescent power supply current; the current
flowing into the VDD lead at specified input and
VDD conditions.
IOZ Output OFF current; the leakage current
flowing into or out of the output of a 3-state
device in the OFF state when the output is
connected to VDD or VSS.
IIL Input current LOW; the current flowing into a
device at a specified LOW level input voltage
and a specified VDD.
IIH Input current HIGH; the current flowing into a
device at a specified HIGH level input voltage
and a specified VDD.
IDDL Quiescent power supply current LOW; the
current flowing into the VDD lead with a
specified LOW level input voltage on all inputs
and specified VDD conditions.
IDDH Quiescent power supply current HIGH; the
current flowing into the VDD lead with a
specified HIGH level input voltage on all inputs
and specified VDD conditions.
IZOFF state leakage current; the leakage current
flowing into the output of a 3-state device in the
OFF state at a specified output voltage and
VDD.
Voltages
All voltages are referenced to VSS, which is the most
negative potential applied to the device.
Analogue terms
VDD Supply voltage; the most positive potential on
the device.
VSS Supply voltage; for a device with a single
negative power supply, the most negative
power supply, used as the reference level for
other voltages; typically ground.
VEE Supply voltage; one of two (VSS and VEE)
negative power supplies. For a device with dual
negative power supply, the most negative
power supply as a reference level for other
voltages.
VIH Input voltage HIGH; the range of input voltages
that represents a logic HIGH level in the
system.
VIL Input voltage LOW; the range of input voltages
that represents a logic LOW level in the system.
VOH Output voltage HIGH; the range of voltages at
an output terminal with a specified output
loading and supply voltage. Device inputs are
conditioned to establish a HIGH level at the
output.
VOL Output voltage LOW; the range of voltages at
an output terminal with a specified output
loading and supply voltage. Device inputs are
conditioned to establish a LOW level at the
output.
VPTrigger threshold voltage; positive-going signal.
VNTrigger threshold voltage; negative-going
signal.
RON ON resistance; the effective ON state
resistance of an analogue transmission gate, at
specified input voltage, output load and VDD.
∆RON ∆ON resistance; the difference in effective ON
resistance between any two transmission gates
of an analogue device at specified input
voltage, output load and VDD.
January 1995 13
Philips Semiconductors
Family Specifications
AC switching parameters
fiInput frequency; for combinatorial logic devices
the maximum number of inputs and outputs
switching in accordance with the device truth
table. For sequential logic devices the clock
frequency using alternate HIGH and LOW for
data input or using the toggle mode, whichever is
applicable.
foOutput frequency; each output.
fmax Clock frequency; clock input waveform should
have a 50% duty cycle and be such as to cause
the outputs to be switching from 10%VDD to
90%VDD in accordance with the device truth
table.
tr, tfClock input rise and fall times; 10% and 90%
value.
tPLH Propagation delay time; the time between the
specified reference points, normally the 50%
points on the input and output waveforms, with
the output changing from the defined LOW level
to the defined HIGH level.
tPHL Propagation delay time; the time between the
specified reference points, normally the 50%
points on the input and output waveforms, with
the output changing from the defined HIGH level
to the defined LOW level.
tTLH Transition time, LOW-to-HIGH; the time between
two specified reference points on a waveform,
normally 10% and 90% points, that is changing
from LOW to HIGH.
tTHL Transition time, HIGH-to-LOW; the time between
two specified reference points on a waveform,
normally 90% and 10% points, that is changing
from HIGH to LOW.
tWPulse width; the time between the 50% amplitude
points on the leading and trailing edges of a
pulse.
thold Hold time; the interval immediately following the
active transition of the timing pulse (usually the
clock pulse) or following the transition of the
control input to its latching level, during which
interval the data to be recognized must be
maintained at the input to ensure their continued
recognition. A negative hold time indicates that
the correct logic level may be released prior to
the timing pulse and still be recognized.
tsu Set-up time; the interval immediately preceding
the active transition of the timing pulse (usually
the clock pulse) or preceding the transition of the
control input to its latching level, during which
interval the data to be recognized must be
maintained at the input to ensure their
recognition. A negative set-up time indicates that
the correct logic level may be initiated sometime
after the active transition of the timing pulse and
still be recognized.
tPHZ 3-state output disable time, HIGH to Z; the time
between the specified reference points, normally
the 50% point on the output enable input voltage
waveform and a point representing a 0.1 VOH
drop on the output voltage waveform of a 3-state
device, with the output changing from the output
HIGH level (VOH) to a high impedance OFF-state.
tPLZ 3-state output disable time, LOW to Z; the time
between the specified reference points, normally
the 50% point on the output enable input voltage
waveform and a point representing a
0.1 (VDD −VOL) rise on the output voltage
waveform of a 3-state device, with the output
changing from the output LOW level (VOL) to a
high impedance OFF-state.
tPZH 3-state output enable time, Z to HIGH; the time
between the specified reference points, normally
the 50% point on the output enable input voltage
waveform and a point representing a 0.1 VOH rise
on the output voltage waveform of a 3-state
device, with the output changing from a high
impedance OFF-state to the output HIGH level
(VOH).
tPZL 3-state output enable time, Z to LOW; the time
between the specified reference points, normally
the 50% point on the output enable input voltage
waveform and a point representing a
0.1 (VDD −VOL) voltage drop on the output
voltage waveform of a 3-state device, with the
output changing from a high impedance
OFF-state to the output LOW level (VOL).
tRRecovery time; the time between the end of an
overriding asynchronous input, typically a clear or
reset input, and the earliest permissible
beginning of a synchronous control input,
typically a clock input, normally measured at 50%
points on both input voltage waveforms.
