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H8/3664 Group
Hardware Manual
16
User’s Manual
Rev.6.00 2006.03
Renesas 16-Bit Single-Chip Microcomputer
H8 Family/H8/300H Tiny Series
H8/3664N HD64N3664
H8/3664F HD64F3664
H8/3664 HD6433664
H8/3663 HD6433663
H8/3662 HD6433662
H8/3661 HD6433661
H8/3660 HD6433660
Rev. 6.00 Mar. 24, 2006 Page ii of xxviii
Rev. 6.00 Mar. 24, 2006 Page iii of xxviii
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a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-
party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
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4. When using any or all of the information contained in these materials, including product data,
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8. Please contact Renesas Technology Corp. for further details on these materials or the products
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Keep safety first in your circuit designs!
Notes regarding these materials
Rev. 6.00 Mar. 24, 2006 Page iv of xxviii
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused In put Pi ns
Note: Fix all unused input pins to high or low level.
Generally, the inp ut pi ns of C MOS products are hig h-i m ped ance in p ut pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibiti on of Access t o Un d e fi ned or Reserved Ad dres ses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
Rev. 6.00 Mar. 24, 2006 Page v of xxviii
Configuration of This Manual
This manual comprises th e following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Mo dules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each sectio n.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 6.00 Mar. 24, 2006 Page vi of xxviii
Preface
The H8/3664 Gro up are sin g l e-chi p microcomputers made up of the high-speed H8/300H CPU
employing Renesas Technology original architecture as their cores, and the peripheral functions
required to configure a system. The H8/300H CPU has an instruction set that is compatible with
the H8/300 CPU.
Target Users: This manual was written for users who will be using the H8/3664 Group in the
design of application systems. Target users are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective: This manual was written to exp lain the hardware function s and electrical
characteristics of the H8/3664 Group to the target users.
Refer to the H8/300H Series Software Manual for a detailed description of the
instruction set.
Notes on reading this manual:
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the H8/300H Series Software Manual.
• In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 19,
List of Registers.
Example: Bit order: The MSB is on the left and the LSB is on the right.
Notes:
When using the on-chip emulator (E7, E8) for H8/3664 program development and debugging, the
following restrictions must be noted.
1. The NMI pin is reserved for the E7 or E8, and cannot be used.
2. Pins P85, P86, and P87 cannot be us ed. In order to use these pins, additional hardware must be
provided on the user board.
3. Area H'7000 to H'7FFF is used by the E7 or E8, and is not available to the user.
4. Area H'F780 to H'FB7F must on no account be accessed.
Rev. 6.00 Mar. 24, 2006 Page vii of xxviii
5. When the E7 or E8 is used, address breaks can be set as either available to the user or for use
by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break
control registers must not be accessed.
6. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode), P85 and
P87 are input pins, and P86 is an output pin.
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
H8/3664 Group manuals:
Document Title Document No.
H8/3664 Group Hardware Manual This manual
H8/300H Series Software Manual REJ09B0213
User's manuals for development tools:
Document Title Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
REJ10B0058
H8S, H8/300 Series Simulator/Debugger User's Manual REJ10B0211
H8S, H8/300 Series High-Performance Embedded Workshop 3 Tutorial REJ10B0024
H8S, H8/300 Series High-performance Embedded Workshop 3 User's Manual REJ10B0026
Application n o t es:
Document Title Document No.
H8S, H8/300 Series C/C++ Compiler Package Application Note REJ05B0464
Single Power Supply F-ZTATTM On-Board Programming REJ05B0520
Rev. 6.00 Mar. 24, 2006 Page viii of xxviii
Rev. 6.00 Mar. 24, 2006 Page ix of xxviii
Contents
Section 1 Overview................................................................................................1
1.1 Features.................................................................................................................................1
1.2 Internal Block Diagram.........................................................................................................3
1.3 Pin Arrangeme nt................................................................................................................... 5
1.4 Pin Functions........................................................................................................................9
Section 2 CPU......................................................................................................13
2.1 Address Space and Memory Map.......................................................................................14
2.2 Register Configuration........................................................................................................17
2.2.1 General Registers................................................................................................18
2.2.2 Program Counter (PC) ........................................................................................ 19
2.2.3 Condition-Code Register (CCR).........................................................................19
2.3 Data Formats.......................................................................................................................21
2.3.1 General Register Data Formats...........................................................................21
2.3.2 Memor y Data Formats........................................................................................23
2.4 Instruction Set.....................................................................................................................24
2.4.1 Table of I nstructions Classifie d by Function......................................................24
2.4.2 Basic Instruction Formats...................................................................................34
2.5 Addressing Modes and Effective Address Calculation.......................................................35
2.5.1 Addressing Modes ..............................................................................................35
2.5.2 Effective Address Calculation ............................................................................39
2.6 Basic Bus Cycle..................................................................................................................41
2.6.1 Access to On-Chip Memory (RAM, ROM)........................................................41
2.6.2 On-Chip Peripheral Modules..............................................................................42
2.7 CPU States..........................................................................................................................43
2.8 Usage Notes........................................................................................................................44
2.8.1 Notes on Data Access to Empty Areas ...............................................................44
2.8.2 EEPMOV Instruction..........................................................................................44
2.8.3 Bit Manipulation Instruction...............................................................................45
Section 3 Exception Handling .............................................................................51
3.1 Exception Sources and Vector Address..............................................................................51
3.2 Register Descriptions..........................................................................................................53
3.2.1 Interrupt Edge Select Register 1 (IEGR1) ..........................................................53
3.2.2 Interrupt Edge Select Register 2 (IEGR2) ..........................................................54
3.2.3 Interrupt Enable Register 1 (IENR1)..................................................................55
Rev. 6.00 Mar. 24, 2006 Page x of xxviii
3.2.4 Inter r upt Flag Register 1 (IRR1).........................................................................56
3.2.5 Wake up Inter r upt Flag Register (IWPR)............................................................57
3.3 Reset Exception Handling .................................................................................................. 59
3.4 Interrupt Exception Handling ............................................................................................. 59
3.4.1 External Interrupts.............................................................................................. 59
3.4.2 Inter nal Interrupts ............................................................................................... 61
3.4.3 Interrupt Handling Sequence..................................................................... 61
3.4.4 Interrupt Response Time..................................................................................... 62
3.5 Usage Notes........................................................................................................................ 64
3.5.1 Interrupts after Reset........................................................................................... 64
3.5.2 Notes on Stack Area Use....................................................................................64
3.5.3 Notes on Rewriting Port Mode Registers ........................................................... 64
Section 4 Address Break .....................................................................................67
4.1 Register Descriptions.......................................................................................................... 68
4.1.1 Address Break Control Register (ABRKCR) ..................................................... 68
4.1.2 Address Break Status Register (ABRKSR) ........................................................ 70
4.1.3 Break Address Registers (BARH, BARL).......................................................... 70
4.1.4 Break Data Registers (BDR H, BDRL )...............................................................70
4.2 Operation............................................................................................................................ 71
4.3 Usage Notes........................................................................................................................ 73
Section 5 Clock Pulse Generators .......................................................................77
5.1 System Clock Generator..................................................................................................... 78
5.1.1 Connecting Crystal Resonator ............................................................................ 78
5.1.2 Connecting Ceramic Resonator.......................................................................... 79
5.1.3 External Clock Input Method.............................................................................. 79
5.2 Subclock Gene rator ............................................................................................................ 80
5.2.1 Connecting 32. 768-kHz Crystal Resonator ........................................................ 80
5.2.2 Pin Connection whe n Not Using Subclock.........................................................81
5.3 Prescalers............................................................................................................................ 81
5.3.1 Prescaler S .......................................................................................................... 81
5.3.2 Prescaler W......................................................................................................... 81
5.4 Usage Notes........................................................................................................................ 82
5.4.1 Note on Resonators............................................................................................. 82
5.4.2 Notes on Board Design.......................................................................................82
Section 6 Power-Down Modes............................................................................83
6.1 Register Descriptions.......................................................................................................... 84
6.1.1 System Control Register 1 (SYSCR1)................................................................84
Rev. 6.00 Mar. 24, 2006 Page xi of xxviii
6.1.2 System Control Register 2 (SYSCR2)................................................................86
6.1.3 Module Standby Control Register 1 (MSTCR1) ................................................87
6.2 Mode Transitions and States of LSI....................................................................................88
6.2.1 Sleep Mode.........................................................................................................91
6.2.2 Standby Mode.....................................................................................................91
6.2.3 Subsleep Mode....................................................................................................92
6.2.4 Subactive Mode ..................................................................................................92
6.3 Operating Frequency in Active Mode.................................................................................93
6.4 Direct Transition.................................................................................................................93
6.4.1 Direct Transition from Active Mode to Subactive Mode....................................93
6.4.2 Direct Transition from Subactive Mode to Active Mode....................................94
6.5 Module Standby Function................................................................................................... 94
6.6 Usage Note..........................................................................................................................94
Section 7 ROM ....................................................................................................95
7.1 Block Configuration ...........................................................................................................96
7.2 Register Descriptions..........................................................................................................97
7.2.1 Flash Memory Control Register 1 (FLMCR1)....................................................97
7.2.2 Flash Memory Control Register 2 (FLMCR2)....................................................98
7.2.3 Erase Block Register 1 (EBR1) .......................................................................... 99
7.2.4 Flash Memory Power Control Register (FLPWCR)...........................................99
7.2.5 Flash Memory Enable Register (FENR)...........................................................100
7.3 On-Board Programming Modes........................................................................................100
7.3.1 Boot Mode........................................................................................................101
7.3.2 Programming/Erasing in User Program Mode..................................................103
7.4 Flash Memory Programming/Erasing...............................................................................104
7.4.1 Program/Program-Verify..................................................................................104
7.4.2 Erase/Erase-Verify............................................................................................107
7.4.3 Inter rupt Handling when Programming/Erasing Flash Memory ....................... 107
7.5 Program/Erase Protection .................................................................................................109
7.5.1 Har d ware Pr otection ......................................................................................... 109
7.5.2 Software Protection...........................................................................................109
7.5.3 Error Protection.................................................................................................109
7.6 Programmer Mode............................................................................................................110
7.7 Power-Down States for Flash Memory............................................................................. 110
Section 8 RAM ..................................................................................................113
Section 9 I/O Ports.............................................................................................115
9.1 Port 1.................................................................................................................................115
Rev. 6.00 Mar. 24, 2006 Page xii of xxviii
9.1.1 Port Mode Register 1 (PMR1).......................................................................... 116
9.1.2 Port Control Register 1 (PCR1)........................................................................ 117
9.1.3 Port Data Register 1 (PDR1) ............................................................................ 118
9.1.4 Port Pull-Up Control Register 1 (PUCR1) ........................................................ 118
9.1.5 Pin Functions.................................................................................................... 119
9.2 Port 2................................................................................................................................. 121
9.2.1 Port Control Register 2 (PCR2)........................................................................ 121
9.2.2 Port Data Register 2 (PDR2) ............................................................................ 122
9.2.3 Pin Functions.................................................................................................... 122
9.3 Port 5................................................................................................................................. 124
9.3.1 Port Mode Register 5 (PMR5).......................................................................... 125
9.3.2 Port Control Register 5 (PCR5)........................................................................ 126
9.3.3 Port Data Register 5 (PDR5) ............................................................................ 127
9.3.4 Port Pull-Up Control Register 5 (PUCR5) ........................................................ 127
9.3.5 Pin Functions.................................................................................................... 128
9.4 Port 7................................................................................................................................. 130
9.4.1 Port Control Register 7 (PCR7)........................................................................ 131
9.4.2 Port Data Register 7 (PDR7) ............................................................................ 131
9.4.3 Pin Functions.................................................................................................... 132
9.5 Port 8................................................................................................................................. 133
9.5.1 Port Control Register 8 (PCR8)........................................................................ 134
9.5.2 Port Data Register 8 (PDR8) ............................................................................ 134
9.5.3 Pin Functions.................................................................................................... 135
9.6 Port B................................................................................................................................ 138
9.6.1 Port Data Register B (PDRB)........................................................................... 138
Section 10 Timer A ...........................................................................................139
10.1 Features............................................................................................................................. 139
10.2 Input/Output P i ns.............................................................................................................. 140
10.3 Register Descriptions........................................................................................................ 141
10.3.1 Timer Mode Register A (TMA)........................................................................ 141
10.3.2 Timer Counter A (TCA) ................................................................................... 142
10.4 Operation.......................................................................................................................... 143
10.4.1 Interval Timer Operation .................................................................................. 143
10.4.2 Clock Time Base Operation.............................................................................. 143
10.4.3 Clock Output..................................................................................................... 143
10.5 Usage Note ....................................................................................................................... 144
Section 11 Timer V ...........................................................................................145
11.1 Features............................................................................................................................. 145
Rev. 6.00 Mar. 24, 2006 Page xiii of xxviii
11.2 Input/Output P i ns..............................................................................................................147
11.3 Register Descriptions........................................................................................................147
11.3.1 Timer Counter V (TCNTV)..............................................................................147
11.3.2 Time Constant Registers A and B (TCORA, TCORB) .................................... 148
11.3.3 Timer Control Register V0 (TCRV0)............................................................... 148
11.3.4 Timer Control/Status Register V (TCSRV)......................................................150
11.3.5 Timer Control Register V1 (TCRV1)............................................................... 151
11.4 Operation ..........................................................................................................................152
11.4.1 Timer V Operation............................................................................................ 152
11.5 Timer V Application Examples........................................................................................155
11.5.1 Pulse Output with Arbitrary Duty C ycle...........................................................155
11.5.2 Pulse Output with Arbitrary Pulse Widt h a n d Delay fr om TRGV In put..........156
11.6 Usage Notes......................................................................................................................157
Section 12 Timer W...........................................................................................159
12.1 Features............................................................................................................................. 159
12.2 Input/Output P i ns..............................................................................................................162
12.3 Register Descriptions........................................................................................................162
12.3.1 Timer Mode Register W (TMRW) ................................................................... 163
12.3.2 Timer Control Register W (T CRW) ................................................................. 164
12.3.3 Timer Interrupt Enable Register W (TIERW) ..................................................165
12.3.4 Timer Status Register W (TS R W)....................................................................166
12.3.5 Timer I/O Control Register 0 (TIOR0).............................................................167
12.3.6 Timer I/O Control Register 1 (TIOR1).............................................................169
12.3.7 Timer Counter (TCNT).....................................................................................170
12.3.8 General Registers A to D (GRA to GRD).........................................................171
12.4 Operation ..........................................................................................................................172
12.4.1 Normal Operation.............................................................................................172
12.4.2 PWM Operation................................................................................................ 176
12.5 Operation Timing..............................................................................................................181
12.5.1 TCNT Count Timing ........................................................................................181
12.5.2 Output Compare Output Timing.......................................................................182
12.5.3 Input Capture Timing........................................................................................183
12.5.4 Timing of Counter Clearing by Compare Match..............................................183
12.5.5 Buffer Operation Timing ..................................................................................184
12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match..............................185
12.5.7 Timing of IMFA to IMFD Setting at Input Capture .........................................186
12.5.8 Timing of Status Flag Clearing.........................................................................186
12.6 Usage Notes......................................................................................................................187
Rev. 6.00 Mar. 24, 2006 Page xiv of xxviii
Section 13 Watchdog Timer..............................................................................191
13.1 Features............................................................................................................................. 191
13.2 Register Descriptions........................................................................................................ 191
13.2.1 Timer Control/Status Register WD (TCSRWD) .............................................. 192
13.2.2 Timer Counter WD (TCWD)............................................................................ 193
13.2.3 Timer Mode Register WD (T MWD)................................................................ 194
13.3 Operation.......................................................................................................................... 195
Section 14 Serial Communication Interface 3 (SCI3).......................................197
14.1 Features............................................................................................................................. 197
14.2 Input/Output P i ns.............................................................................................................. 198
14.3 Register Descriptions........................................................................................................ 199
14.3.1 Receive Shift Register (RSR) ........................................................................... 199
14.3.2 Receive Data Register (RDR)...........................................................................199
14.3.3 Transmit Shift Register (TSR).......................................................................... 199
14.3.4 Transmit Data Register (TDR).......................................................................... 200
14.3.5 Serial Mode Register (SMR) ............................................................................ 200
14.3.6 Serial Control Register 3 (SC R3) ..................................................................... 201
14.3.7 Serial Status Register (SSR) ............................................................................. 203
14.3.8 Bit Rate Register (BRR)................................................................................... 205
14.4 Operation in Asynchronous Mode.................................................................................... 210
14.4.1 Clock................................................................................................................. 210
14.4.2 SCI3 Initialization............................................................................................. 211
14.4.3 Data Transmission............................................................................................ 212
14.4.4 Serial Data Reception ....................................................................................... 214
14.5 Operation in Clocked Synchronous Mode........................................................................218
14.5.1 Clock................................................................................................................. 218
14.5.2 SCI3 Initialization............................................................................................. 218
14.5.3 Serial Data Transmission.................................................................................. 219
14.5.4 Serial Data Reception (Clocked Synchronous Mode) ...................................... 221
14.5.5 Simultaneous Serial Data Transmission and Reception.................................... 223
14.6 Multiprocessor Communication Function ........................................................................ 224
14.6.1 Multiprocessor Serial Data Transmission.........................................................226
14.6.2 Multiprocessor Serial Data Reception.............................................................. 227
14.7 Interrupts........................................................................................................................... 230
14.8 Usage Notes...................................................................................................................... 230
14.8.1 Break Detection and Processing....................................................................... 230
14.8.2 Mark State and Break Sending ......................................................................... 231
14.8.3 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mo de Only) ................................................................. 231
Rev. 6.00 Mar. 24, 2006 Page xv of xxviii
14.8.4 Receive Data Sampling Timing and Reception Margin
in Asynchronous Mode.....................................................................................231
Section 15 I2C Bus Interface (IIC).....................................................................233
15.1 Features............................................................................................................................. 233
15.2 Input/Output P i ns..............................................................................................................235
15.3 Register Descriptions........................................................................................................236
15.3.1 I2C Bus Data Register (ICDR) .......................................................................... 236
15.3.2 Slave Address Register (SAR)..........................................................................238
15.3.3 Second Slave Address Register (SARX)..........................................................238
15.3.4 I2C Bus Mode Register (ICMR)........................................................................239
15.3.5 I2C Bus Control Register (ICCR)......................................................................242
15.3.6 I2C Bus Status Register (ICSR).........................................................................245
15.3.7 Timer Serial Control Register (TSCR) .............................................................248
15.4 Operation ..........................................................................................................................249
15.4.1 I2C Bus Data Format.........................................................................................249
15.4.2 Master Transmit Operation...............................................................................251
15.4.3 Master Receive Operation.................................................................................253
15.4.4 Slave Receive Operation................................................................................... 255
15.4.5 Slave Transmit Operation.................................................................................258
15.4.6 Clock Synchronous Se rial Format ....................................................................259
15.4.7 IRIC Setting Timing and SCL Control.............................................................260
15.4.8 Noise Canceler..................................................................................................261
15.4.9 Sample Flowcharts............................................................................................262
15.5 Usage Notes......................................................................................................................266
Section 16 A/D Converter..................................................................................275
16.1 Features............................................................................................................................. 275
16.2 Input/Output P i ns..............................................................................................................277
16.3 Register Description .........................................................................................................278
16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ..........................................278
16.3.2 A/D Control/Status Register (ADCSR) ............................................................ 279
16.3.3 A/D Control Register (ADCR) .........................................................................280
16.4 Operation ..........................................................................................................................281
16.4.1 Single Mode......................................................................................................281
16.4.2 Scan Mode........................................................................................................281
16.4.3 Input Sampling and A/D Conversion Time ...................................................... 282
16.4.4 External Trigger Input Timing..........................................................................283
16.5 A/D Conversion Accurac y De finitions.............................................................................284
16.6 Usage Notes......................................................................................................................286
Rev. 6.00 Mar. 24, 2006 Page xvi of xxviii
16.6.1 Permissible Signal Source Impedance.............................................................. 286
16.6.2 Influences on Absolute Accuracy.....................................................................286
Section 17 EEPROM.........................................................................................287
17.1 Features............................................................................................................................. 287
17.2 Input/Output P i ns.............................................................................................................. 289
17.3 Register Description ......................................................................................................... 289
17.3.1 EEPROM Key Register (EKR)......................................................................... 289
17.4 Operation.......................................................................................................................... 290
17.4.1 EEPROM Interface........................................................................................... 290
17.4.2 Bus Format and Timing.................................................................................... 290
17.4.3 Start Condition.................................................................................................. 291
17.4.4 Stop Condition.................................................................................................. 291
17.4.5 Acknowledge.................................................................................................... 291
17.4.6 Slave Addressing.............................................................................................. 292
17.4.7 Write Operations............................................................................................... 293
17.4.8 Acknowledge Polling........................................................................................ 294
17.4.9 Read Operation................................................................................................. 295
17.5 Usage Notes...................................................................................................................... 297
17.5.1 Data Protection at VCC On/Off........................................................................... 297
17.5.2 Write/Erase Endurance..................................................................................... 297
17.5.3 Noise Suppression Time................................................................................... 298
Section 18 Power Supply Circuit ......................................................................299
18.1 When Using Internal Power Supply Step-Down Circuit .................................................. 299
18.2 When Not Using Internal Power Supply Step-Down Circuit ........................................... 300
Section 19 List of Registers...............................................................................301
19.1 Register Addresses (Address Or der )................................................................................. 302
19.2 Register Bits ..................................................................................................................... 305
19.3 Register States in Eac h Operating Mode.......................................................................... 308
Section 20 Electrical Characteristics.................................................................311
20.1 Absolute Maximum Ratings............................................................................................. 311
20.2 Electrical Characteristics (F-ZTAT™ Version, F-Z TAT ™ Version with EEPROM) ..... 311
20.2.1 Power Supply Voltage and Operating Ranges.................................................. 311
20.2.2 DC Characteristics............................................................................................ 314
20.2.3 AC Characteristics............................................................................................ 320
20.2.4 A/D Converter Characteristics.......................................................................... 324
20.2.5 Watchdog Timer Characteristics....................................................................... 325
Rev. 6.00 Mar. 24, 2006 Page xvii of xxviii
20.2.6 Memory Characteristics....................................................................................326
20.2.7 EEPROM Characteristics..................................................................................328
20.3 Electrical Characteristics (Mask ROM Version) ..............................................................329
20.3.1 Power Supply Voltage and Operating Ranges..................................................329
20.3.2 DC Characteristics............................................................................................ 331
20.3.3 AC Characteristics............................................................................................ 337
20.3.4 A/D Converter Characteristics..........................................................................341
20.3.5 Watchdog Timer Characteristics.......................................................................342
20.4 Operation Timing..............................................................................................................343
20.5 Output Loa d C ondition..................................................................................................... 346
Appendix A Instruction Set ...............................................................................347
A.1 Instruction List.................................................................................................................. 347
A.2 Operation Code Map ......................................................................................................... 362
A.3 Number of E x ecution States .............................................................................................365
A.4 Combinations of Instructions and Addressing Modes......................................................376
Appendix B I/O Port Block Diagrams...............................................................377
B.1 I/O Port Block...................................................................................................................377
B.2 Port States in Each Operating State ..................................................................................394
Appendix C Product Code Lineup.....................................................................395
Appendix D Package Dimensions .....................................................................397
Appendix E EEPROM Stacked-Structure Cross-Sectional View .....................401
Main Revisions and Additions in this Edition.....................................................403
Index ....................................................................................................................409
Rev. 6.00 Mar. 24, 2006 Page xviii of xxviii
Rev. 6.00 Mar. 24, 2006 Page xix of xxviii
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of H8/3664 of F-ZTATTM and Mask-ROM Versions ............. 3
Figure 1.2 Internal Block Diagram of H8/3664N of F-ZTATTM Version with EEPROM .............4
Figure 1.3 Pin Arrangement of H8/3664 of F-ZTATTM and Mask-ROM Versions
(FP-64E, FP-64A)......................................................................................................... 5
Figure 1.4 Pin Arrangement of H8/3664 of F-ZTATTM and Mask-ROM Versions
(FP-48F, FP-48B) .........................................................................................................6
Figure 1.5 Pin Arrangement of H8/3664 of F-ZTATTM and Mask-ROM Versions
(DS-42S).......................................................................................................................7
Figure 1.6 Pin Arrangement of H8/3664N of F-ZTATTM Version with EEPROM
(FP-64E) ....................................................................................................................... 8
Section 2 CPU
Figure 2.1 Memory Map (1) ......................................................................................................... 14
Figure 2.1 Memory Map (2) ......................................................................................................... 15
Figure 2.1 Memory Map (3) ......................................................................................................... 16
Figure 2.2 CPU Registers ............................................................................................................. 17
Figure 2.3 Usage of General Registers .........................................................................................18
Figure 2.4 Relationship between Stack Pointer and Stack Area................................................... 19
Figure 2.5 General Register Data Formats (1).............................................................................. 21
Figure 2.5 General Register Data Formats (2).............................................................................. 22
Figure 2.6 Memory Data Formats................................................................................................. 23
Figure 2.7 Instruction Formats...................................................................................................... 34
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 38
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 41
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 42
Figure 2.11 CPU Operation States................................................................................................ 43
Figure 2.12 State Transitions........................................................................................................ 44
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to
Same Address ........................................................................................................... 45
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................ 60
Figure 3.2 Stack Status after Exception Handling ........................................................................62
Figure 3.3 Interrupt Sequence....................................................................................................... 63
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure ..............65
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................ 67
Rev. 6.00 Mar. 24, 2006 Page xx of xxviii
Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 71
Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 72
Figure 4.3 Operation when Condition is not Satisfied in Branch Instruction ............................... 73
Figure 4.4 Operation when Another Interrupt is Accepted at
Address Break Setting Instruction ............................................................................... 74
Figure 4.5 Operation when the Instruction Set is not Executed
and does not Branch due to Conditions not Being Satisfied........................................ 75
Section 5 Clock Pulse Generators
Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 77
Figure 5.2 Block Diagram of System Clock Generator ................................................................ 78
Figure 5.3 Typical Connection to Crystal Resonator.................................................................... 78
Figure 5.4 Equivalent Circuit of Crystal Resonator...................................................................... 78
Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 79
Figure 5.6 Example of External Clock Input................................................................................ 79
Figure 5.7 Block Diagram of Subclock Generator ....................................................................... 80
Figure 5.8 Typical Connection to 32.768-kHz Crystal Resonator................................................ 80
Figure 5.9 Equivalent Circuit of 32.768-kHz Crystal Resonator.................................................. 80
Figure 5.10 Pin Connection when not Using Subclock ................................................................ 81
Figure 5.11 Example of Incorrect Board Design.......................................................................... 82
Section 6 Power-Down Modes
Figure 6.1 Mode Transition Diagram ........................................................................................... 88
Section 7 ROM
Figure 7.1 Flash Memory Block Configuration............................................................................ 96
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode.......................... 103
Figure 7.3 Program/Program-Verify Flowchart ......................................................................... 105
Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 108
Section 9 I/O Ports
Figure 9.1 Port 1 Pin Configuration............................................................................................ 115
Figure 9.2 Port 2 Pin Configuration............................................................................................ 121
Figure 9.3 Port 5 Pin Configuration............................................................................................ 124
Figure 9.4 Port 7 Pin Configuration............................................................................................ 130
Figure 9.5 Port 8 Pin Configuration............................................................................................ 133
Figure 9.6 Port B Pin Configuration...........................................................................................138
Section 10 Timer A
Figure 10.1 Block Diagram of Timer A ..................................................................................... 140
Section 11 Timer V
Figure 11.1 Block Diagram of Timer V ..................................................................................... 146
Rev. 6.00 Mar. 24, 2006 Page xxi of xxviii
Figure 11.2 Increment Timing with Internal Clock .................................................................... 153
Figure 11.3 Increment Timing with External Clock................................................................... 153
Figure 11.4 OVF Set Timing ...................................................................................................... 153
Figure 11.5 CMFA and CMFB Set Timing ................................................................................ 154
Figure 11.6 TMOV Output Timing ............................................................................................ 154
Figure 11.7 Clear Timing by Compare Match............................................................................ 154
Figure 11.8 Clear Timing by TMRIV Input ............................................................................... 155
Figure 11.9 Pulse Output Example ............................................................................................. 155
Figure 11.10 Example of Pulse Output Synchronized to TRGV Input....................................... 156
Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 157
Figure 11.12 Contention between TCORA Write and Compare Match ..................................... 158
Figure 11.13 Internal Clock Switching and TCNTV Operation................................................. 158
Section 12 Timer W
Figure 12.1 Timer W Block Diagram......................................................................................... 161
Figure 12.2 Free-Running Counter Operation ............................................................................ 172
Figure 12.3 Periodic Counter Operation..................................................................................... 173
Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)........................................................ 173
Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 174
Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................ 174
Figure 12.7 Input Capture Operating Example ........................................................................... 175
Figure 12.8 Buffer Operation Example (Input Capture)............................................................. 176
Figure 12.9 PWM Mode Example (1) ........................................................................................ 177
Figure 12.10 PWM Mode Example (2) ...................................................................................... 177
Figure 12.11 Buffer Operation Example (Output Compare) ...................................................... 178
Figure 12.12 PWM Mode Example
(TOB, TOC, and TOD = 0: initial output values are set to 0)............................... 179
Figure 12.13 PWM Mode Example
(TOB, TOC, and TOD = 1: initial output values are set to 1)............................... 180
Figure 12.14 Count Timing for Internal Clock Source............................................................... 181
Figure 12.15 Count Timing for External Clock Source.............................................................. 181
Figure 12.16 Output Compare Output Timing ........................................................................... 182
Figure 12.17 Input Capture Input Signal Timing........................................................................ 183
Figure 12.18 Timing of Counter Clearing by Compare Match................................................... 183
Figure 12.19 Buffer Operation Timing (Compare Match)..........................................................184
Figure 12.20 Buffer Operation Timing (Input Capture) ............................................................. 184
Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match .................................. 185
Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 186
Figure 12.23 Timing of Status Flag Clearing by CPU................................................................ 186
Figure 12.24 Contention between TCNT Write and Clear ......................................................... 187
Figure 12.25 Internal Clock Switching and TCNT Operation .................................................... 188
Rev. 6.00 Mar. 24, 2006 Page xxii of xxviii
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW
Occur at the Same Timing .................................................................................... 189
Section 13 Watchdog Timer
Figure 13.1 Block Diagram of Watchdog Timer........................................................................ 191
Figure 13.2 Watchdog Timer Operation Example...................................................................... 195
Section 14 Serial Communication Interface 3 (SCI3)
Figure 14.1 Block Diagram of SCI3........................................................................................... 198
Figure 14.2 Data Format in Asynchronous Communication ...................................................... 210
Figure 14.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............ 210
Figure 14.4 Sample SCI3 Initialization Flowchart ..................................................................... 211
Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit).......................................................................... 212
Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode) .............................. 213
Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit).......................................................................... 214
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous mode) (1)...................... 216
Figure 14.8 Sample Serial Reception Data Flowchart (2) .......................................................... 217
Figure 14.9 Data Format in Clocked Synchronous Communication .......................................... 218
Figure 14.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode...... 219
Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode) ................ 220
Figure 14.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode............... 221
Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)...................... 222
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode) .............................................................................. 223
Figure 14.15 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A).......................................... 225
Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart ........................................ 226
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 227
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 228
Figure 14.18 Example of SCI3 Operation in Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................. 229
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode ...................................... 232
Section 15 I2C Bus Interface (IIC)
Figure 15.1 Block Diagram of I2C Bus Interface ....................................................................... 234
Figure 15.2 I2C Bus Interface Connections (Example: This LSI as Master) .............................. 235
Figure 15.3 I2C Bus Data Formats (I2C Bus Formats)................................................................ 250
Figure 15.4 I2C Bus Timing........................................................................................................ 250
Figure 15.5 Master Transmit Mode Operation Timing Example (MLS = WAIT = 0).............. 252
Rev. 6.00 Mar. 24, 2006 Page xxiii of xxviii
Figure 15.6 Master Receive Mode Operation Timing Example (1)
(MLS = ACKB = 0, WAIT = 1) ............................................................................. 254
Figure 15.6 Master Receive Mode Operation Timing Example (2)
(MLS = ACKB = 0, WAIT = 1) ............................................................................. 255
Figure 15.7 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) ....... 256
Figure 15.8 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) ....... 257
Figure 15.9 Example of Slave Transmit Mode Operation Timing (MLS = 0) .......................... 259
Figure 15.10 I2C Bus Data Format (Serial Format) .................................................................... 259
Figure 15.11 IRIC Setting Timing and SCL Control.................................................................. 260
Figure 15.12 Block Diagram of Noise Canceler......................................................................... 261
Figure 15.13 Sample Flowchart for Master Transmit Mode.......................................................262
Figure 15.14 Sample Flowchart for Master Receive Mode ........................................................263
Figure 15.15 Sample Flowchart for Slave Receive Mode .......................................................... 264
Figure 15.16 Sample Flowchart for Slave Transmit Mode.........................................................265
Figure 15.17 Flowchart and Timing of Start Condition Instruction Issuance
for Retransmission ................................................................................................ 270
Figure 15.18 IRIC Flag Clear Timing on WAIT Operation ....................................................... 271
Figure 15.19 Notes on ICDR Reading with TRS = 1 Setting in Master Mode........................... 272
Figure 15.20 Notes on ICDR Writing with TRS = 0 Setting in Slave Mode..............................273
Section 16 A/D Converter
Figure 16.1 Block Diagram of A/D Converter ........................................................................... 276
Figure 16.2 A/D Conversion Timing..........................................................................................282
Figure 16.3 External Trigger Input Timing ................................................................................ 283
Figure 16.4 A/D Conversion Accuracy Definitions (1).............................................................. 285
Figure 16.5 A/D Conversion Accuracy Definitions (2).............................................................. 285
Figure 16.6 Analog Input Circuit Example................................................................................. 286
Section 17 EEPROM
Figure 17.1 Block Diagram of EEPROM................................................................................... 288
Figure 17.2 EEPROM Bus Format and Bus Timing .................................................................. 290
Figure 17.3 Byte Write Operation ..............................................................................................293
Figure 17.4 Page Write Operation ..............................................................................................294
Figure 17.5 Current Address Read Operation............................................................................. 295
Figure 17.6 Random Address Read Operation ........................................................................... 296
Figure 17.7 Sequential Read Operation (when current address read is used)............................. 297
Section 18 Power Supply Circuit
Figure 18.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 299
Figure 18.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 300
Rev. 6.00 Mar. 24, 2006 Page xxiv of xxviii
Section 20 Electrical Characteristics
Figure 20.1 System Clock Input Timing .................................................................................... 343
Figure 20.2 RES Low Width Timing.......................................................................................... 343
Figure 20.3 Input Timing............................................................................................................ 343
Figure 20.4 I2C Bus Interface Input/Output Timing ................................................................... 344
Figure 20.5 SCK3 Input Clock Timing ...................................................................................... 344
Figure 20.6 SCI3 Input/Output Timing in Clocked Synchronous Mode .................................... 345
Figure 20.7 EEPROM Bus Timing............................................................................................. 345
Figure 20.8 Output Load Circuit ................................................................................................ 346
Appendix B I/O Port Block Diagrams
Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 377
Figure B.2 Port 1 Block Diagram (P16 to P14).......................................................................... 378
Figure B.3 Port 1 Block Diagram (P12, P11) ............................................................................. 379
Figure B.4 Port 1 Block Diagram (P10) ..................................................................................... 380
Figure B.5 Port 2 Block Diagram (P22) ..................................................................................... 381
Figure B.6 Port 2 Block Diagram (P21) ..................................................................................... 382
Figure B.7 Port 2 Block Diagram (P20) ..................................................................................... 383
Figure B.8 Port 5 Block Diagram (P57, P56) ............................................................................. 384
Figure B.9 Port 5 Block Diagram (P55) ..................................................................................... 385
Figure B.10 Port 5 Block Diagram (P54 to P50)........................................................................ 386
Figure B.11 Port 7 Block Diagram (P76) ................................................................................... 387
Figure B.12 Port 7 Block Diagram (P75) ................................................................................... 388
Figure B.13 Port 7 Block Diagram (P74) ................................................................................... 389
Figure B.14 Port 8 Block Diagram (P87 to P85)........................................................................ 390
Figure B.15 Port 8 Block Diagram (P84 to P81)........................................................................ 391
Figure B.16 Port 8 Block Diagram (P80) ................................................................................... 392
Figure B.17 Port B Block Diagram (PB7 to PB0) ...................................................................... 393
Appendix D Package Dimensions
Figure D.1 FP-64E Package Dimensions ................................................................................... 397
Figure D.2 FP-64A Package Dimensions................................................................................... 398
Figure D.3 FP-48F Package Dimensions.................................................................................... 399
Figure D.4 FP-48B Package Dimensions ................................................................................... 400
Figure D.5 DP-42S Package Dimensions................................................................................... 400
Appendix E EEPROM Stacked-Structure Cross-Sectional View
Figure E.1 EEPROM Stacked-Structure Cross-Sectional View................................................. 401
Rev. 6.00 Mar. 24, 2006 Page xxv of xxviii
Tables
Section 1 Overview
Table 1.1 Pin Functions ............................................................................................................ 9
Section 2 CPU
Table 2.1 Operation Notation ................................................................................................. 24
Table 2.2 Data Transfer Instructions.......................................................................................25
Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 26
Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 27
Table 2.4 Logic Operations Instructions................................................................................. 28
Table 2.5 Shift Instructions..................................................................................................... 28
Table 2.6 Bit Manipulation Instructions (1)............................................................................ 29
Table 2.6 Bit Manipulation Instructions (2)............................................................................ 30
Table 2.7 Branch Instructions ................................................................................................. 31
Table 2.8 System Control Instructions.................................................................................... 32
Table 2.9 Block Data Transfer Instructions ............................................................................ 33
Table 2.10 Addressing Modes .................................................................................................. 35
Table 2.11 Absolute Address Access Ranges...........................................................................37
Table 2.12 Effective Address Calculation (1)........................................................................... 39
Table 2.12 Effective Address Calculation (2)........................................................................... 40
Section 3 Exception Handling
Table 3.1 Exception Sources and Vector Address..................................................................52
Table 3.2 Interrupt Wait States ...............................................................................................62
Section 4 Address Break
Table 4.1 Access and Data Bus Used .....................................................................................69
Section 5 Clock Pulse Generators
Table 5.1 Crystal Resonator Parameters .................................................................................79
Section 6 Power-Down Modes
Table 6.1 Operating Frequency and Waiting Time.................................................................85
Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling ........ 89
Table 6.3 Internal State in Each Operating Mode...................................................................90
Section 7 ROM
Table 7.1 Setting Programming Modes ................................................................................ 100
Table 7.2 Boot Mode Operation ........................................................................................... 102
Table 7.3 System Clock Frequencies for which Automatic Adjustment of
LSI Bit Rate is Possible ........................................................................................ 103
Rev. 6.00 Mar. 24, 2006 Page xxvi of xxviii
Table 7.4 Reprogram Data Computation Table .................................................................... 106
Table 7.5 Additional-Program Data Computation Table...................................................... 106
Table 7.6 Programming Time............................................................................................... 106
Table 7.7 Flash Memory Operating States............................................................................ 111
Section 10 Timer A
Table 10.1 Pin Configuration.................................................................................................. 140
Section 11 Timer V
Table 11.1 Pin Configuration.................................................................................................. 147
Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions ............................... 149
Section 12 Timer W
Table 12.1 Timer W Functions ............................................................................................... 160
Table 12.2 Pin Configuration.................................................................................................. 162
Section 14 Serial Communication Interface 3 (SCI3)
Table 14.1 Pin Configuration.................................................................................................. 198
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ...... 206
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ...... 207
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ...... 208
Table 14.3 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 208
Table 14.4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)..................... 209
Table 14.5 SSR Status Flags and Receive Data Handling ...................................................... 215
Table 14.6 SCI3 Interrupt Requests........................................................................................ 230
Section 15 I2C Bus Interface (IIC)
Table 15.1 I2C Bus Interface Pins........................................................................................... 235
Table 15.2 Communication Format ........................................................................................ 239
Table 15.3 I2C Transfer Rate .................................................................................................. 241
Table 15.4 Flags and Transfer States...................................................................................... 249
Table 15.5 I2C Bus Timing (SCL and SDA Output) .............................................................. 266
Table 15.6 Permissible SCL Rise Time (tsr) Values ............................................................... 267
Table 15.7 I2C Bus Timing (with Maximum Influence of tsr/tsf) ............................................ 268
Section 16 A/D Converter
Table 16.1 Pin Configuration.................................................................................................. 277
Table 16.2 Analog Input Channels and Corresponding ADDR Registers.............................. 278
Table 16.3 A/D Conversion Time (Single Mode)................................................................... 283
Section 17 EEPROM
Table 17.1 Pin Configuration.................................................................................................. 289
Table 17.2 Slave Addresses.................................................................................................... 292
Rev. 6.00 Mar. 24, 2006 Page xxvii of xxviii
Section 20 Electrical Characteristics
Table 20.1 Absolute Maximum Ratings ................................................................................. 311
Table 20.2 DC Characteristics (1)...........................................................................................314
Table 20.2 DC Characteristics (2)...........................................................................................318
Table 20.2 DC Characteristics (3)...........................................................................................319
Table 20.3 AC Characteristics ................................................................................................ 320
Table 20.4 I2C Bus Interface Timing ...................................................................................... 322
Table 20.5 Serial Interface (SCI3) Timing ............................................................................. 323
Table 20.6 A/D Converter Characteristics .............................................................................. 324
Table 20.7 Watchdog Timer Characteristics........................................................................... 325
Table 20.8 Flash Memory Characteristics .............................................................................. 326
Table 20.9 EEPROM Characteristics...................................................................................... 328
Table 20.10 DC Characteristics (1).......................................................................................331
Table 20.10 DC Characteristics (2).......................................................................................336
Table 20.11 AC Characteristics ............................................................................................ 337
Table 20.12 I2C Bus Interface Timing .................................................................................. 339
Table 20.13 Serial Interface (SCI3) Timing ......................................................................... 340
Table 20.14 A/D Converter Characteristics .......................................................................... 341
Table 20.15 Watchdog Timer Characteristics....................................................................... 342
Appendix A Instruction Set
Table A.1 Instruction Set....................................................................................................... 349
Table A.2 Operation Code Map (1) ....................................................................................... 362
Table A.2 Operation Code Map (2) ....................................................................................... 363
Table A.2 Operation Code Map (3) ....................................................................................... 364
Table A.3 Number of Cycles in Each Instruction.................................................................. 366
Table A.4 Number of Cycles in Each Instruction.................................................................. 367
Table A.5 Combinations of Instructions and Addressing Modes .......................................... 376
Rev. 6.00 Mar. 24, 2006 Page xxviii of xxviii
Section 1 Overview
Rev. 6.00 Mar. 24, 2006 Page 1 of 412
REJ09B0142-0600
Section 1 Overview
1.1 Features
• High-speed H8/300H central processing unit with an internal 16-bit arch itectur e
Upward-compatible with H8/300 CPU on an object level
Sixteen 16-bit general regist ers
62 basic instructions
• Various peripheral functions
Timer A (can be used as a time base for a clock)
Timer V (8-bit timer)
Timer W (16-bit timer)
Watchdog timer
SCI3 (Asynchronous or clocked synchronous serial communication interface)
I2C Bus Interface (conforms to the I2C bus interface format that is advocated by Philips
Electronics)
10-bit A/D converter
• On-chip memory
Product Classification Model EEPROM ROM RAM
Flash memory version H8/3664N HD64N3664 512 bytes 32 kbytes 2,048 bytes
(F-ZTATTM version) H8/3664F HD64F3664 32 kbytes 2,048 bytes
Mask ROM version H8/3664 HD6433664 32 kbytes 1,024 bytes
H8/3663 HD6433663 24 kbytes 1,024 bytes
H8/3662 HD6433662 16 kbytes 512 bytes
H8/3661 HD6433661 12 kbytes 512 bytes
H8/3660 HD6433660 8 kbytes 512 bytes
• General I/O ports
I/O pins: 29 I/O pins (H8/3664N has 27 I/O pins), including 8 large current ports (IOL = 20
mA, @VOL = 1.5 V)
Input-only pins: 8 input pins (also used for analog input)
• EEPROM interface (only for H8/3664N)
I2C Bus Interface (conforms to the I2C bus interface format that is advocated by Philips
Electronics)
Section 1 Overview
Rev. 6.00 Mar. 24, 2006 Page 2 of 412
REJ09B0142-0600
• Supports various power-down modes
Note: F-ZTATTM is a trademark of Renesas Technology Co rp.
• Compact package
Package Code Body Size Pin Pitch
LQFP-64 FP-64E 10.0
× 10.0 mm 0.5 mm
QFP-64 FP-64A 14.0 × 14.0 mm 0.8 mm
LQFP-48 FP-48F 10.0 × 10.0 mm 0.65 mm
LQFP-48 FP-48B 7.0 × 7.0 mm 0.5 mm
SDIP-42 DP-42S 14.0 × 37.3 mm 1.78 mm
Only LQFP-64 (FP-64E) for H8/3664N package
Section 1 Overview
Rev. 6.00 Mar. 24, 2006 Page 3 of 412
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1.2 Internal Block Diagram
P10/TMOW
P11
P12
P14/IRQ0
P15/IRQ1
P16/IRQ2
P17/IRQ3/TRGV
P50/WKP0
P51/WKP1
P52/WKP2
P53/WKP3
P54/WKP4
P55/WKP5/ADTR
G
P56/SDA
P57/SCL
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
V
CC
V
SS
V
CL
RES
TEST
NMI
AV
CC
P20/SCK3
P21/RXD
P22/TXD
P80/FTCI
P81/FTIOA
P82/FTIOB
P83/FTIOC
P84/FTIOD
P85
P86
P87
P74/TMRIV
P75/TMCIV
P76/TMOV
OSC1
OSC2
X1
X2
CPU
H8/300H
ROM RAM
SCI3
Port 1
Timer W
I
2
C bus
interface
Timer A Watchdog
timer
Timer V A/D
converter
Subclock
generator
System
clock
generator
Port 2
Port B Port 5 Port 7 Port 8
Data bus (upper)
Address bus
Data bus (lower)
Figure 1.1 Internal Block Diagra m of H 8/ 3 664 o f F-Z T ATTM and Mask-ROM Versions
Section 1 Overview
Rev. 6.00 Mar. 24, 2006 Page 4 of 412
REJ09B0142-0600
P10/TMOW
P11
P12
P14/IRQ0
P15/IRQ1
P16/IRQ2
P17/IRQ3/TRGV
P50/WKP0
P51/WKP1
P52/WKP2
P53/WKP3
P54/WKP4
P55/WKP5/ADTR
G
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
V
CC
V
SS
V
CL
RES
TEST
NMI
AV
CC
P20/SCK3
P21/RXD
P22/TXD
SDA
SCL
P80/FTCI
P81/FTIOA
P82/FTIOB
P83/FTIOC
P84/FTIOD
P85
P86
P87
P74/TMRIV
P75/TMCIV
P76/TMOV
OSC1
OSC2
X1
X2
CPU
H8/300H
ROM RAM
EEPROM
SCI3
Timer W
I
2
C bus
interface
I
2
C bus
Timer A Watchdog
timer
Timer V A/D
converter
Port 1
Subclock
generator
System
clock
generator
Port 2
Port 5
Port B Port 7 Port 8
Data bus (upper)
Address bus
Note : The H8/3664N is a stacked-structure product in which an EEPROM chip is mounted on the
H8/3664F-ZTAT
TM
version.
Data bus (lower)
Figure 1.2 Internal Block Diagram of H8/3664N of F-ZT ATTM Version with EEPROM
Section 1 Overview
Rev. 6.00 Mar. 24, 2006 Page 5 of 412
REJ09B0142-0600
1.3 Pin Arrangement
NC
NC
AVCC
X2
X1
VCL
RES
TEST
VSS
OSC2
OSC1
VCC
P50/WKP0
P51/WKP1
NC
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
NC
NC
P22/TXD
P21/RXD
P20/SCK3
P87
P86
P85
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
NMI
NC
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
NC
P14/IRQ0
P15/IRQ1
P16/IRQ2
P17/IRQ3/TRGV
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
NC
NC
NC
NC
P76/TMOV
P75/TMCIV
P74/TMRIV
P57/SCL
P56/SDA
P12
P11
P10/TMOW
P55/WKP5/ADTR
G
P54/WKP4
P53/WKP3
P52/WKP2
NC
NC
H8/3664
Top view
Note: Do not connect NC pins (* these pins are not connected to the internal circuitry).
Figure 1.3 Pin Arrangement of H8/3664 of F-ZTATTM and Mask-ROM Versions
(FP-64E, FP-64A)
Section 1 Overview
Rev. 6.00 Mar. 24, 2006 Page 6 of 412
REJ09B0142-0600
AVcc
X2
X1
V
CL
RES
TEST
V
SS
OSC2
OSC1
Vcc
P50/WKP0
P51/WKP1
123456789101112
37
38
39
40
41
42
43
44
45
46
47
48
36 35 34 33 32 31 30 29 28 27 26 25
P22/TXD
P21/RXD
P20/SCK3
P87
P86
P85
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
NMI
24
23
22
21
20
19
18
17
16
15
14
13
P14/IRQ0
P15/IRQ1
P16/IRQ2
P17/IRQ3/TRGV
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
P76/TMOV
P75/TMCIV
P74/TMRIV
P57/SCL
P56/SDA
P12
P11
P10/TMOW
P55/WKP5/ADTR
G
P54/WKP4
P53/WKP3
P52/WKP2
H8/3664
Top View
Figure 1.4 Pin Arrangement of H8/3664 of F-ZTATTM and Mask-ROM Versions
(FP-48F, FP-48B)
Section 1 Overview
Rev. 6.00 Mar. 24, 2006 Page 7 of 412
REJ09B0142-0600
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
AVCC
X2
X1
VCL
RES
TEST
VSS
OSC2
OSC1
VCC
P50/WKP0
P51/WKP1
P52/WKP2
P53/WKP3
P54/WKP4
P55/WKP5/ADTRG
P10/TMOW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
P17/IRQ3/TRGV
P16/IRQ2
P15/IRQ1
P14/IRQ0
P22/TXD
P21/RXD
P20/SCK3
P87
P86
P85
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
NMI
P76/TMOV
P75/TMCIV
P74/TMRIV
P57/SCL
P56/SDA
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
H8/3664
Top view
Note: DP-42S has no P11, P12, PB4/AN4, PB5/AN5, PB6/AN6, and PB7/AN7 pins.
Figure 1.5 Pin Arrangement of H8/3664 of F-ZTATTM and Mask-ROM Versions
(DS-42S)
Section 1 Overview
Rev. 6.00 Mar. 24, 2006 Page 8 of 412
REJ09B0142-0600
NC
NC
AVcc
X2
X1
VCL
RES
TEST
VSS
OSC2
OSC1
Vcc
P50/WKP0
P51/WKP1
NC
NC
1 2 3 4 5 6 7 8 9 10111213141516
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
NC
NC
P22/TXD
P21/RXD
P20/SCK3
P87
P86
P85
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
NMI
NC
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
NC
P14/IRQ0
P15/IRQ1
P16/IRQ2
P17/IRQ3/TRGV
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
NC
NC
NC
NC
P76/TMOV
P75/TMCIV
P74/TMRIV
SCL*
SDA*
P12
P11
P10/TMOW
P55/WKP5/ADTR
G
P54/WKP4
P53/WKP3
P52/WKP2
NC
NC
H8/3664N
Top View
Note: Do not connect NC pins.
* These pins are only available for the I
2
C bus interface in the F-ZAT
TM
version with EEPROM.
Figure 1.6 Pin Arrangement of H8/3664N of F-ZTATTM Version with EEPROM
(FP-64E)
Section 1 Overview
Rev. 6.00 Mar. 24, 2006 Page 9 of 412
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1.4 Pin Functions
Table 1.1 Pin Functions
Pin No.
H8/3664 H8/3664N
Type Symbol
FP-64E,
FP-64A FP-48F,
FP-48B DP-42S FP-64E I/O Functions
Power source
pins
VCC 12 10 14 12 Input Power supply pin. Connect this pin to the
system power supply.
V
SS 9 7 11 9 Input Ground pin. Connect all these pins to the
system power supply (0V).
AVCC 3 1 5 3 Input Analog power supply pin for the A/D
converter. When the A/D converter is not
used, connect this pin to the system
power supply.
V
CL 6 4 8 6 Input Internal step-down power supply pin.
Connect a capacitor of around 0.1 µF
between this pin and the Vss pin for
stabilization.
Clock pins OSC1 11 9 13 11 Input
OSC2 10 8 12 10 Output
These pins connect to a crystal or ceramic
resonator for system clocks, or can be
used to input an external clock.
These pins can be used to input an
external clock.
See section 5, Clock Pulse Generators,
for a typical connection.
X1 5 3 7 5 Input For connection to a 32.768 kHz crystal
resonator for subclocks.
See section 5, Clock Pulse Generators,
for a typical connection.
X2 4 2 6 4 Output
System control RES 7 5 9 7 Input Reset pin. When this driven low, the chip
is reset.
TEST 8 6 10 8 Input Test pin. Connect this pin to Vss.
Section 1 Overview
Rev. 6.00 Mar. 24, 2006 Page 10 of 412
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Pin No.
H8/3664 H8/3664N
Type Symbol
FP-64E,
FP-64A FP-48F,
FP-48B DP-42S FP-64E I/O Functions
Interrupt pins NMI 35 25 27 35 Input Non-maskable interrupt request input pin.
Be sure to pull-up by a pull-up resistor.
IRQ0 to
IRQ3
51 to 54 37 to 40 39 to 42 51 to 54 Input External interrupt request input pins. Can
select the rising or falling edge.
WKP0 to
WKP5
13, 14,
19 to 22
11 to 16 15 to 20
13, 14,
19 to 22
Input External interrupt request input pins. Can
select the rising or falling edge.
Timer A TMOW 23 17 21 23 Output This is an output pin for divided clocks
Timer V TMOV 30 24 26 30 Output This is an output pin for waveforms
generated by the output compare function
TMCIV 29 23 25 29 Input External event input pin
TMRIV 28 22 24 28 Input Counter reset input pin
TRGV 54 40 42 54 Input Counter start trigger input pin
Timer W FTCI 36 26 28 36 Input External event input pin
FTIOA to
FTIOD
37 to 40 27 to 30 29 to 32 37 to 40 I/O Output compare output/ input capture
input/ PWM output pin
I2C bus
inerface
SDA 26*2 20 22 26*1 I/O IIC data I/O pin. Can directly drive a bus
by NMOS open-drain output. When using
this pin, external pull-up resistance is
required.
SCL 27*2 21 23 27*1 I/O
(EEPROM:
input)
IIC clock I/O pin. Can directly drive a bus
by NMOS open-drain output. When using
this pin, external pull-up resistance is
required.
Serial commu-
nication
TXD 46 36 38 46 Output Transmit data output pin
interface (SCI) RXD 45 35 37 45 Input Receive data input pin
SCK3 44 34 36 44 I/O Clock I/O pin
A/D converter AN7 to
AN0
55 to 62 41 to 48 1 to 4*2 55 to 62 Input Analog input pin
ADTRG 22 16 20 22 Input A/D converter trigger input pin
Section 1 Overview
Rev. 6.00 Mar. 24, 2006 Page 11 of 412
REJ09B0142-0600
Pin No.
H8/3664 H8/3664N
Type Symbol
FP-64E,
FP-64A FP-48F,
FP-48B DP-42S FP-64E I/O Functions
I/O ports PB7 to PB0 55 to 62 41 to 48 1 to 4*2 55 to 62 Input 8-bit input port
P17 to P14,
P12 to P10
51 to 54
23 to 25
37 to 40
17 to 19
39 to 42,
21*2
51 to 54,
23 to 25
I/O 7-bit I/O port
P22 to P20 44 to 46 34 to 36 36 to 38 44 to 46 I/O 3-bit I/O port
P57 to P50
(P55 to P50
for
H8/3664N)
13,14,
19 to 22
26, 27
21, 20,
16 to 11
15 to 20,
22, 23
13, 14,
19 to 22
I/O 8-bit I/O port
(6-bit I/O port for H8/3664N)
P76 to P74 28 to 30 22 to 24 24 to 26 28 to 30 I/O 3-bit I/O port
P87 to P80 36 to 43 26 to 33 28 to 35 36 to 43 I/O 8-bit I/O port
Notes: 1. These pins are only available for the I2C bus interface in the F-ZATTM version with EEPROM. Since
the I2C bus is disabled after canceling a reset, the ICE bit in ICCR must be set to 1 by using the
program.
2. The DP-42S does not have the P11, P12, PB4/AN4, PB5/AN5, PB6/AN6, and PB7/AN7 pins.
Section 1 Overview
Rev. 6.00 Mar. 24, 2006 Page 12 of 412
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Section 2 CPU
Rev. 6.00 Mar. 24, 2006 Page 13 of 412
REJ09B0142-0600
Section 2 CPU
This LSI has an H8/300H CPU with an internal 32-bit arch itecture that is upward-compatible with
the H8/300CPU, and supports only normal mode, which has a 64-kby te address space.
• Upward-compatible with H8/300 CPUs
Can execute H8/300 CPUs object programs
Additional eight 16-bit extended registers
32-bit transfer and arithmetic and logic instructions are added
Signed multiply and divide instructions are added.
• General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
• Sixty-two basic instructions
8/16/32-bit data transfer and arithmetic and logic in structions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displ a cement [@(d: 16 ,ER n ) or @( d:24,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24]
Immediate [#xx:8, #xx :16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 64-kbyte address space
• High-speed operation
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract : 2 state
8 × 8-bit register-register multiply : 14 states
16 ÷ 8-bit register-register divide : 14 states
16 × 16-bit register-register multiply : 22 states
32 ÷ 16-bit register-register divide : 22 states
• Power-down state
Transition to power-down state by SLEEP instruction
Section 2 CPU
Rev. 6.00 Mar. 24, 2006 Page 14 of 412
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2.1 Address Space and Memory Map
The address space of this LSI is 64 kbytes, which includes the program area and the data area.
Figures 2.1 show the memo ry map.
Interrupt vector
On-chip ROM
(32 kbytes)
Not used
(1-kbyte work area
for flash memory
programming)
Internal I/O register
H'0000
H'0033
H'0034
H'7FFF
H'F780
H'FB7F
H'FF7F
H'FF80
H'FB80
H'FFFF
HD64F3664
(Flash memory version)
HD6433660
(Mask ROM version) HD6433661
(Mask ROM version)
Interrupt vector
On-chip ROM
(8 kbytes)
Not used
On-chip RAM
(512 bytes)
Internal I/O register
H'0000
H'0033
H'0034
H'FD80
H'FF7F
H'FF80
H'FFFF
H'1FFF
Interrupt vector
On-chip ROM
(12 kbytes)
Not used
On-chip RAM
(512 bytes)
Internal I/O register
H'0000
H'0033
H'0034
H'FD80
H'FF7F
H'FF80
H'FFFF
H'2FFF
(1-kbyte user area)
On-chip RAM
(2 kbytes)
Figure 2.1 Memory Map (1 )
Section 2 CPU
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REJ09B0142-0600
Interrupt vector
On-chip ROM
(16 kbytes)
On-chip RAM
(512 bytes)
Internal I/O register
H'0000
H'0033
H'0034
H'3FFF
H'FF7F
H'FF80
H'FFFF
HD6433664
(Mask ROM version)
HD6433663
(Mask ROM version)
HD6433662
(Mask ROM version)
H'FD80
Interrupt vector
On-chip ROM
(24 kbytes)
Not used
Not used
On-chip RAM
(1 kbyte)
Internal I/O register
H'0000
H'0033
H'0034
H'5FFF
H'FB80
H'FF7F
H'FF80
H'FFFF
Interrupt vector
On-chip ROM
(32 kbytes)
Not used
On-chip RAM
(1 kbyte)
Internal I/O register
H'0000
H'0033
H'0034
H'7FFF
H'FB80
H'FF7F
H'FF80
H'FFFF
Figure 2.1 Memory Map (2 )
Section 2 CPU
Rev. 6.00 Mar. 24, 2006 Page 16 of 412
REJ09B0142-0600
HD64N3664
(On-chip EEPROM module)
User area
(512 bytes)
Not used
Slave address
register
Not used
H'0000
H'01FF
H'FF09
Figure 2.1 Memory Map (3 )
Section 2 CPU
Rev. 6.00 Mar. 24, 2006 Page 17 of 412
REJ09B0142-0600
2.2 Register Configuration
The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers;
general registers and control registers. The control registers are a 24-bit program counter (PC), and
an 8-bit condition code register (CCR).
PC
23 0
15 0 7 0 7 0
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
SP:
PC:
CCR:
I:
UI:
Stack pointer
Program counter
Condition-code register
Interrupt mask bit
User bit
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)
IUIHUNZVC
CCR
76543210
H:
U:
N:
Z:
V:
C:
General Registers
Control Registers (CR)
[Legend]
Figure 2.2 CPU Registers
Section 2 CPU
Rev. 6.00 Mar. 24, 2006 Page 18 of 412
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2.2.1 General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
identical and can be used as both address registers and data regi st ers . When a general register is
used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates
the usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum of sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit registers designated by the letters RH (R0H to R7H) and RL (R0L
to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8-bit
registers.
The usage of each register can be selected inde pendently.
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the
stack.
• Address registers
• 32-bit registers
• 16-bit registers • 8-bit registers
ER registers
(ER0 to ER7)
E registers (extended registers)
(E0 to E7)
R registers
(R0 to R7)
RH registers
(R0H to R7H)
RL registers
(R0L to R7L)
Figure 2.3 Usage of General Regi ster s
Section 2 CPU
Rev. 6.00 Mar. 24, 2006 Page 19 of 412
REJ09B0142-0600
SP (ER7)
Free area
Stack area
Figure 2.4 Relationship between Stack Pointer and Stack Area
2.2.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched , the least significant PC bit is regarded as 0). The PC is initialized when the
start address is loaded by the vector address generated during reset exception-handling sequence.
2.2.3 Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized to 1
by reset exception-handling sequence, but other bits are not initialized.
Some instructions leav e flag bits unchanged. Operations can be performed on the CCR bits by the
LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching
conditions for conditional branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List.
Section 2 CPU
Rev. 6.00 Mar. 24, 2006 Page 20 of 412
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Bit Bit Name Initial
Value R/W Description
7 I 1 R/W Interrupt Mask Bit
Masks interrupts other than NMI when set to 1. NMI is
accepted regardless of the I bit setting. The I bit is set
to 1 at the start of an exception-handling sequence.
6 UI Undefined R/W User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
5 H Undefined R/W Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B,
or NEG.B instruction is executed, this flag is set to 1 if
there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or
NEG.W instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 11, and cleared to 0
otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 27, and cleared to 0 otherwise.
4 U Undefined R/W User Bit
Can be written and read by software using the LDC,
STC, ANDC, ORC, and XORC instructions.
3 N Undefined R/W Negative Flag
Stores the value of the most significant bit of data as a
sign bit.
2 Z Undefined R/W Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1 V Undefined R/W Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
0 C Undefined R/W Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to indicate a carry
The carry flag is also used as a bit accumulator by bit
manipulation instructions.
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2.3 Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data . The DAA a n d D AS decimal -adjust instructio n s treat byte dat a as two
digits of 4-bi t B C D data.
2.3.1 General Register Data Format s
Figure 2.5 shows the data formats in general registers.
7 0
70
MSB LSB
MSB LSB
704 3
Don't care
Don't care
Don't care
7 04 3
70
Don't care
6543271
0
70
Don't care 65432710
Don't care
RnH
RnL
RnH
RnL
RnH
RnL
Data Type General Register Data Format
Byte data
Byte data
4-bit BCD data
4-bit BCD data
1-bit data
1-bit data
Upper Lower
Upper Lower
Figure 2.5 General Register Data Formats (1)
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15 0
MSB LSB
15 0
MSB LSB
31 16
MSB
15 0
LSB
ERn:
En:
Rn:
RnH:
RnL:
MSB:
LSB:
General register ER
General register E
General register R
General register RH
General register RL
Most significant bit
Least significant bit
Data Type Data FormatGeneral
Register
Word data
Word data
Rn
En
Longword
data
[Legend]
ERn
Figure 2.5 General Register Data Formats (2)
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2.3.2 Memory Data Formats
Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and
longword data in memory, however word or longword data must begin at an even address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding address. This also applies to instruction fetches.
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
or longword.
70
76 543210
MSB LSB
MSB
MSB
LSB
LSB
Data Type Address
1-bit data
Byte data
Word data
Address L
Address L
Address 2M
Address 2M+1
Longword data Address 2N
Address 2N+1
Address 2N+2
Address 2N+3
Data Format
Figure 2.6 Memory Data Formats
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2.4 Instruction Set
2.4.1 Table of Instructions Classifi ed by Func ti on
The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each
functional category. The notation used in tables 2.2 to 2.9 is defined below.
Table 2.1 Operation Notation
Symbol Description
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register or address register)
(EAd) Destination operand
(EAs) Source operand
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ Logical AND
∨ Logical OR
⊕ Logical XOR
→ Move
¬ NOT (logical complement)
:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length
Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers
(R0 to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7).
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Table 2.2 Data Transfer Instructions
Instruction Size* Function
MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE B (EAs) → Rd, Cannot be used in this LSI.
MOVTPE B Rs → (EAs) Cannot be used in this LSI.
POP W/L @SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH W/L Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.3 Arithmetic Operations Instructions (1)
Instruction Size* Function
ADD
SUB
B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register (immediate byte data
cannot be subtracted from byte data in a general register. Use the
SUBX or ADD instruction.)
ADDX
SUBX
B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte data in two general
registers, or on immediate data and data in a general register.
INC
DEC
B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
ADDS
SUBS
L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAA
DAS
B Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.3 Arithmetic Operations Instructions (2)
Instruction Size* Function
DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits
÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets CCR bits according to the
result.
NEG B/W/L 0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU W/L Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS W/L Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.4 Logic Operations Instructions
Instruction Size* Function
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT B/W/L ¬ (Rd) → (Rd)
Takes the one's complement of general register contents.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.5 Shift Instructions
Instruction Size* Function
SHAL
SHAR
B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
SHLL
SHLR
B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
ROTL
ROTR
B/W/L Rd (rotate) → Rd
Rotates general register contents.
ROTXL
ROTXR
B/W/L Rd (rotate) → Rd
Rotates general register contents through the carry flag.
Note: * Refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.6 Bit Manipulation Instructions (1)
Instruction Size* Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST B ¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets
or clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
BIAND
B
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR
BIOR
B
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Note: * Refers to the operand size.
B: Byte
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Table 2.6 Bit Manipulation Instructions (2)
Instruction Size* Function
BXOR
BIXOR
B
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
C ⊕ ¬ (<bit-No.> of <EAd>) → C
XORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BLD
BILD
B
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
BIST
B
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: * Refers to the operand size.
B: Byte
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Table 2.7 Branch Instructions
Instruction Size Function
Bcc* — Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic Description Condition
BRA (BT) Always (true) Always
BRN (BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
BCC (BHS) Carry clear
(high or same)
C = 0
BCS (BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z∨(N ⊕ V) = 0
BLE Less or equal Z∨(N ⊕ V) = 1
JMP — Branches unconditionally to a specified address.
BSR — Branches to a subroutine at a specified address.
JSR — Branches to a subroutine at a specified address.
RTS — Returns from a subroutine
Note: * Bcc is the general name for conditional branch instructions.
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Table 2.8 System Control Instructions
Instruction Size* Function
TRAPA — Starts trap-instruction exception handling.
RTE — Returns from an exception-handling routine.
SLEEP — Causes a transition to a power-down state.
LDC B/W (EAs) → CCR
Moves the source operand contents to the CCR. The CCR size is one
byte, but in transfer from memory, data is read by word access.
STC B/W CCR → (EAd), EXR → (EAd)
Transfers the CCR contents to a destination location. The condition
code register size is one byte, but in transfer to memory, data is written
by word access.
ANDC B CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR with immediate data.
ORC B CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR with immediate data.
XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically XORs the CCR with immediate data.
NOP — PC + 2 → PC
Only increments the program counter.
Note: * Refers to the operand size.
B: Byte
W: Word
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Table 2.9 Block Data Transfer Instructions
Instruction Size Function
EEPMOV.B — if R4L ≠ 0 then
Repeat @ER5+ → @ER6+,
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W — if R4 ≠ 0 then
Repeat @ER5+ → @ER6+,
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
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2.4.2 Basic Instruction Formats
H8/300H CPU instru ctions consist of 2-byte (1-wor d) units. An instruction con sists of an
operation field (o p fi el d) , a re gi st er fi el d (r fiel d), an effective address extension (EA field), and a
condition field (cc).
Figure 2.7 shows examples of instruction formats.
• Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fiel ds.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instr uct i o ns ha ve tw o register fields. S ome have no register fiel d.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A24-bit
address or displacement is treated as a 32-bit data in which the first 8 bits are 0 (H'00).
• Condition Field
Specifies the branching condition of Bcc instructions.
op
op rn rm
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm
rn rm
op
EA(disp)
op cc EA(disp) BRA d:8
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
Figure 2.7 Instruction Formats
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2.5 Addressing Modes and Effective Address Calculation
The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the
generated 24-bit address, so the effective add ress is 16 bits.
2.5.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses
a subset of these addressing mode s. A ddressing modes that can be used di f fer de pen di ng on the
instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing
Modes.
Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer
instructions can use all addressing modes except program-counter relative and memory indirect.
Bit manipulation instructions use register direct, register indirect, or the absolute addressing mode
to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or
immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.10 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn)/@(d:24,ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5 Absolute address @aa:8/@aa:16/@aa:24
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8,PC)/@(d:16,PC)
8 Memory indirect @@aa:8
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(1) Register Direct—Rn
The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7
can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
(2) Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn), the lower 24 bits of
which contain the address of the operand on memory.
(3) Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn)
A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction, and the lower 24 bits of the sum the address of a
memory operand. A 16-bit displacemen t is sign-extended when added.
(4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
(a) Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits of
which contains the address of a memor y oper and . Aft er the operand is accessed, 1, 2, or 4 is ad ded
to the address register contents (32 bits) and the sum is stored in the address register. The value
added is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword
access, the register value should be even.
(b) Register indirect with pre-decrement—@-ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in
the instruction code, and the lower 24 bits of the result is the address of a memory operand. The
result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word
access, or 4 for longword access. For the word or longword access, the register value should be
even.
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(5) Absolute Address—@aa:8, @aa:16, @aa:24
The instruction code contains the absolute address of a memory op erand. The absolu te address
may be 8 bits long (@aa: 8) , 1 6 bit s lo ng (@ aa: 16 ), 2 4 bi t s long (@aa: 2 4 )
For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit
absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the
entire address space.
The access ranges of absolute addresses for the group of this LSI are those shown in table 2.11,
because the upper 8 bits are ignored.
Table 2.11 Absolute Address Access Ranges
Absolute Address Access Range
8 bits (@aa:8) H'FF00 to H'FFFF
16 bits (@aa:16) H'0000 to H'FFFF
24 bits (@aa:24) H'0000 to H'FFFF
(6) Immediate—#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
(7) Program-Counter Rela tive—@(d:8, PC) or @(d:1 6, P C)
This mode is used in the BSR instruction. An 8-bit or 16-bit displacement contained in the
instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 by tes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.
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(8) Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The memory operand is accessed by longword access. The first byte of the memory operand is
ignored, generating a 24-bit branch address. Figure 2.8 shows how to specify branch address for in
memory indirect mode. The upper bits of th e absolute address are all assumed to be 0, so the
address range is 0 to 255 (H '0000 to H'00FF).
Note that the first part of the address range is also the exception vector area.
Specified
by @aa:8
Branch address
Dummy
Figure 2.8 Branch Address Specification in Memory Indirect Mode
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2.5.2 Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI
the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address.
Table 2.12 Effective Address Calculation (1)
No
1
r
op
31 0
23
2
3Register indirect with displacement
@(d:16,ERn) or @(d:24,ERn)
4
r
opdisp
r
op
rm
op rn
310
0
r
op
230
31 0
disp
31 0
31 0
23 0
23 0
Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
Register direct(Rn)
General register contents
General register contents
General register contents
General register contents
Sign extension
Register indirect(@ERn)
Register indirect with post-increment or
pre-decrement
•Register indirect with post-increment @ERn+
•Register indirect with pre-decrement @-ERn
1, 2, or 4
1, 2, or 4
Operand is general register contents.
The value to be added or subtracted is 1 when the
operand is byte size, 2 for word size, and 4 for
longword size.
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Table 2.12 Effective Address Calculation (2)
No
5
op
23 0
abs
@aa:8 7
H'FFFF
op
23 0
@aa:16
@aa:24
abs
15
16
23 0
op
abs
6
opIMM
#xx:8/#xx:16/#xx:32
8
Addressing Mode and Instruction Format
Absolute address
Immediate
Effective Address Calculation Effective Address (EA)
Sign extension
Operand is immediate data.
7
Program-counter relative
@(d:8,PC) @(d:16,PC)
Memory indirect @@aa:8
23 0
disp
0
23 0
disp
op
23
op
8
abs 23 0
abs
H'0000
7
8
0
1523 0
15
H'00
16
[Legend]
r, rm,rn :
op :
disp :
IMM :
abs :
Register field
Operation field
Displacement
Immediate data
Absolute address
PC contents
Sign
extension
Memory contents
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2.6 Basic Bus Cycle
CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising
edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or
three states. The cycle differs depending on whether access is to on-chip memory or to on-chip
peripheral modules.
2.6.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.9 shows the on-chip memory access cycle.
T1 state
Bus cycle
T2 state
Internal address bus
φ or φ
SUB
Internal read signal
Internal data bus
(read access)
Internal write signal
Read data
Address
Write data
Internal data bus
(write access)
Figure 2.9 On-Chip Memory Access Cycle
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2.6.2 On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits
or 16 bits depending on the register. For description on the data bus width and number of
accessing states of each register, refer to section 19.1, Register Addresses (Address Order).
Registers with 16- bi t data bus width can be accessed by word size only. Regist ers wi t h 8- bi t data
bus width can be accessed by byte or word size. When a register with 8-bit data bus width is
accessed by word size, access is completed in two cycles. In two-state access, the operation timing
is the same as that for on-chip memory.
Figure 2.10 shows the operation timing in the case of three-state access to an on-chip peripheral
module.
T
1
state
Bus cycle
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Read data
Address
Internal
data bus
(write access)
T
2
state T
3
state
Write data
φ or φ
SUB
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
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2.7 CPU States
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active mode and subactive mode.
In the program halt state there are a sleep mode, standby mode, and sub-sleep mode. These states
are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution
state and program halt state, refer to section 6, Power-Down Modes. For details on exception
processing, refer to section 3, Exception Handling.
CPU state Reset state
Program
execution state
Program halt state
Exception-
handling state
Active
(high speed) mode
Subactive mode
Sleep mode
Subsleep mode
Power-down
modes
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock
A state in which some
or all of the chip
functions are stopped
to conserve power
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
The CPU is initialized
Standby mode
Figure 2.11 CPU Operation States
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Reset state
Program halt state
Exception-handling state
Program execution state
Reset cleared
SLEEP instruction executed
Reset
occurs
Interrupt
source
Reset
occurs
Interrupt
source
Exception-
handling
complete
Reset occurs
Figure 2.12 State Transitions
2.8 Usage Notes
2.8.1 Notes on Data Access to Empty Areas
The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip
I/O registers areas available to the user. When data is transferred from CPU to empty areas, the
transferred data will be lost. This action may also cause the CPU to malfunction. When data is
transferred from an empty area to CPU, the contents of the data cannot be guaranteed.
2.8.2 EEPMOV Instruction
EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L,
which starts from the address indicated by R5, to the address indicated by R6. Set R4L and R6 so
that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the
value of R6 must not change from H'FFFF to H'0000 during execution).
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2.8.3 Bit Manipulation Instruction
The BSET, BCLR, BNOT, BST, and BIST instructions read d ata from the specified address in
byte units, manipulate the data of the target bit, and write data to the same address again in byte
units. Special care is required when using these instructions in cases where two registers are
assigned to the same address or when a bit is directly manipulated for a port, because this may
rewrite data of a bit other than the bit to be manipulated.
(1) Bit manipulation for two registers assigned to the same address
Example 1: Bit manipulation for the timer load register and timer counter
(Applicable for timer B and timer C, not for the group of this LSI.)
Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same
address. When a bit manipulation instruction accesses the timer load register and timer counter of
a reloadable timer, since these two registers share the same address, the following operations takes
place.
1. Data is read in byte units.
2. The CPU sets or resets the bit to be manipulated with the bit manipulatio n instruction.
3. The written data is written again in byte units to the timer load register.
The timer is counting, so th e value read is not necessarily the same as the value in the timer load
register. As a result, bits other than the intended bit in the timer counter may be modified and the
modified value may be written to the timer load register.
Read
Write
Count clock Timer counter
Timer load register
Reload
Internal bus
Figure 2.13 Example of Timer Con fi gur ation with Two Registers Allocated to Same
Address
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Example 2: The BSET instruction is executed for port 5.
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level
signal at P50 with a BSET instruction is shown below.
Prior to executing BSET
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
BSET instruction executed
BSET #0, @PDR5 The BSET instruction is executed for port 5.
After executing BSET
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5 0 0 1 1 1 1 1 1
PDR5 0 1 0 0 0 0 0 1
Description on operation
When the BSET instruction is executed, first the CPU reads port 5.
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a
value of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41.
Finally, the CPU writes H'41 to PDR5, completing execution of BSET.
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As a result of the BSET instruction, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal.
However, bits 7 and 6 of PDR5 end up with different values. To prevent this problem, store a copy
of the PDR5 data in a work area in memory. Perform the bit manipulatio n on th e data in the work
area, then write this data to PDR5.
Prior to executing BSET
MOV.B #80, R0L
MOV.B R0L, @RAM0
MOV.B R0L, @PDR5
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
RAM0 1 0 0 0 0 0 0 0
BSET instruction executed
BSET #0, @RAM0 The BSET instruction is executed designating the PDR5
work area (RAM0).
After executing BSET
MOV.B @RAM0, R0L
MOV.B R0L, @PDR5 The work area (RAM0) value is written to PDR5.
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 1
RAM0 1 0 0 0 0 0 0 1
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(2) Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: BC LR instr uct io n e xecut e d designating port 5 control register PCR 5
P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at
P56. P55 to P50 are output pins that output low-level signals. An example of setting the P50 pin as
an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be
input to this input pin.
Prior to executing BCLR
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
BCLR instruction executed
BCLR #0, @PCR5 The BCLR instruction is executed for PCR5.
After executing BCLR
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Output Output Output Output Output Output Output Input
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5 1 1 1 1 1 1 1 0
PDR5 1 0 0 0 0 0 0 0
Description on operation
When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only
register, the CPU reads a value of H'FF, even though the PCR5 value is act ual ly H'3F.
Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.
Finally, H'FE is written to PCR5 and BCLR instruction execution ends.
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As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7
and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins. To prevent
this problem, stor e a copy of the PDR5 data in a work area in memory and manipulate data of the
bit in the work area, then write this data to PDR5.
Prior to executing BCLR
MOV.B #3F, R0L
MOV.B R0L, @RAM0
MOV.B R0L, @PCR5
The PCR5 value (H'3F) is written to a work area in
memory (RAM0) as well as to PCR5.
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5 0 0 1 1 1 1 1 1
PDR5 1 0 0 0 0 0 0 0
RAM0 0 0 1 1 1 1 1 1
BCLR instruction executed
BCLR #0, @RAM0 The BCLR instructions executed for the PCR5 work area
(RAM0).
After executing BCLR
MOV.B @RAM0, R0L
MOV.B R0L, @PCR5 The work area (RAM0) value is written to PCR5.
P57 P56 P55 P54 P53 P52 P51 P50
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR5 0 0 1 1 1 1 1 0
PDR5 1 0 0 0 0 0 0 0
RAM0 0 0 1 1 1 1 1 0
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Section 3 Exception Handling
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Section 3 Exception Handling
Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts.
• Reset
A reset has the highest excep tion priority. Exception hand ling starts as soon as the reset is cleared
by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling
starts. Exception handling is the same as exception handling by the RES pin.
• Trap Instruction
Exception handlin g starts when a trap instruction (TRAPA) is executed. The TRAPA instruction
generates a vector address corresponding to a vector number from 0 to 3, as specified in the
instruction code. Exception handling can be executed at all times in the program execution state.
• Interrupts
External interrupts other than NMI and internal interrupts other than address break are masked by
the I bit in CCR, and kept masked while th e I bit is set to 1. Exception handling starts when the
current instruction or exception handling ends, if an interrupt request has been issued.
3.1 Exception Sources and Vector Address
Table 3.1 shows the vector addresses and prio rity of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest pr iority.
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Table 3.1 Exception Sources and Vector Address
Relative Module
Exception Sources Vector
Number
Vector Address
Priority
RES pin
Watchdog timer
Reset 0 H'0000 to H'0001 High
Reserved for system use 1 to 6 H'0002 to H'000D
External interrupt
pin
NMI 7 H'000E to H'000F
Trap instruction (#0) 8 H'0010 to H'0011
(#1) 9 H'0012 to H'0013
(#2) 10 H'0014 to H'0015
CPU
(#3) 11 H'0016 to H'0017
Address break Break conditions satisfied 12 H'0018 to H'0019
CPU Direct transition by executing the
SLEEP instruction
13 H'001A to H'001B
IRQ0 14 H'001C to H'001D
IRQ1 15 H'001E to H'001F
IRQ2 16 H'0020 to H'0021
IRQ3 17 H'0022 to H'0023
External interrupt
pin
WKP 18 H'0024 to H'0025
Timer A Overflow 19 H'0026 to H'0027
Reserved for system use 20 H'0028 to H'0029
Timer W Input capture A/compare match A
Input capture B/compare match B
Input capture C/compare match C
Input capture D/compare match D
Timer W overflow
21 H'002A to H'002B
Timer V Timer V compare match A
Timer V compare match B
Timer V overflow
22 H'002C to H'002D
SCI3 SCI3 receive data full
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
23 H'002E to H'002F
IIC Data transfer end
Address inequality
Stop conditions detected
24 H'0030 to H'0031
A/D converter A/D conversion end 25 H'0032 to H'0033 Low
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3.2 Register Descriptions
Interrupts are controlled by the following registers.
• Interrupt edge select register 1 (IE GR 1 )
• Interrupt edge select register 2 (IE GR 2 )
• Interrupt enable register 1 (IENR1)
• Interrupt flag register 1 (IRR1)
• Wakeup interrupt flag register (IWPR)
3.2.1 Interrupt Edge Select Register 1 (IEGR1)
IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to
IRQ0.
Bit Bit Name
Initial
Value R/W Description
7 NMIEG 0 R/W NMI Edge Select
0: Falling edge of NMI pin input is detected
1: Rising edge of NMI pin input is detected
6
5
4
1
1
1
Reserved
These bits are always read as 1.
3 IEG3 0 R/W IRQ3 Edge Select
0: Falling edge of IRQ3 pin input is detected
1: Rising edge of IRQ3 pin input is detected
2 IEG2 0 R/W IRQ2 Edge Select
0: Falling edge of IRQ2 pin input is detected
1: Rising edge of IRQ2 pin input is detected
1 IEG1 0 R/W IRQ1 Edge Select
0: Falling edge of IRQ1 pin input is detected
1: Rising edge of IRQ1 pin input is detected
0 IEG0 0 R/W IRQ0 Edge Select
0: Falling edge of IRQ0 pin input is detected
1: Rising edge of IRQ0 pin input is detected
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3.2.2 Interrupt Edge Select Register 2 (IEGR2)
IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and
WKP5 to WKP0.
Bit Bit Name
Initial
Value R/W Description
7
6
1
1
Reserved
These bits are always read as 1.
5 WPEG5 0 R/W WKP5 Edge Select
0: Falling edge of WKP5 (ADTRG) pin input is detected
1: Rising edge of WKP5 (ADTRG) pin input is detected
4 WPEG4 0 R/W WKP4 Edge Select
0: Falling edge of WKP4 pin input is detected
1: Rising edge of WKP4 pin input is detected
3 WPEG3 0 R/W WKP3 Edge Select
0: Falling edge of WKP3 pin input is detected
1: Rising edge of WKP3 pin input is detected
2 WPEG2 0 R/W WKP2 Edge Select
0: Falling edge of WKP2 pin input is detected
1: Rising edge of WKP2 pin input is detected
1 WPEG1 0 R/W WKP1Edge Select
0: Falling edge of WKP1 pin input is detected
1: Rising edge of WKP1 pin input is detected
0 WPEG0 0 R/W WKP0 Edge Select
0: Falling edge of WKP0 pin input is detected
1: Rising edge of WKP0 pin input is detected
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3.2.3 Interrupt Enable Register 1 (IENR1)
IENR1 enables direct tran sition interrupts, timer A overflow interrupts, and external pin interrupts.
Bit Bit Name
Initial
Value R/W Description
7 IENDT 0 R/W Direct Transfer Interrupt Enable
When this bit is set to 1, direct transition interrupt
requests are enabled.
6 IENTA 0 R/W Timer A Interrupt Enable
When this bit is set to 1, timer A overflow interrupt
requests are enabled.
5 IENWP 0 R/W Wakeup Interrupt Enable
This bit is an enable bit, which is common to the pins
WKP5 to WKP0. When the bit is set to 1, interrupt
requests are enabled.
4 1 Reserved
This bit is always read as 1.
3 IEN3 0 R/W IRQ3 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ3
pin are enabled.
2 IEN2 0 R/W IRQ2 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ2
pin are enabled.
1 IEN1 0 R/W IRQ1 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ1
pin are enabled.
0 IEN0 0 R/W IRQ0 Interrupt Enable
When this bit is set to 1, interrupt requests of the IRQ0
pin are enabled.
When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in
an interrupt flag register, always d o so whil e interrupts are masked (I = 1). If the above clear
operations are performed while I = 0, and as a result a conflict arises between the clear instruction
and an interrupt request, exception handlin g for the interrupt will be executed after the clear
instruction has been executed.
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3.2.4 Interrupt Flag Register 1 (IRR1)
IRR1 is a status flag register for direct transition interrupts, timer A overflow interrupts, and IRQ3
to IRQ0 interrupt requests.
Bit Bit Name
Initial
Value R/W Description
7 IRRDT 0 R/W Direct Transfer Interrupt Request Flag
[Setting condition]
When a direct transfer is made by executing a SLEEP
instruction while DTON in SYSCR2 is set to 1.
[Clearing condition]
When IRRDT is cleared by writing 0
6 IRRTA 0 R/W Timer A Interrupt Request Flag
[Setting condition]
When the timer A counter value overflows
[Clearing condition]
When IRRTA is cleared by writing 0
5
4
1
1
Reserved
These bits are always read as 1.
3 IRRI3 0 R/W IRQ3 Interrupt Request Flag
[Setting condition]
When IRQ3 pin is designated for interrupt input and
the designated signal edge is detected.
[Clearing condition]
When IRRI3 is cleared by writing 0
2 IRRI2 0 R/W IRQ2 Interrupt Request Flag
[Setting condition]
When IRQ2 pin is designated for interrupt input and
the designated signal edge is detected.
[Clearing condition]
When IRRI2 is cleared by writing 0
1 IRRI1 0 R/W IRQ1 Interrupt Request Flag
[Setting condition]
When IRQ1 pin is designated for interrupt input and
the designated signal edge is detected.
[Clearing condition]
When IRRI1 is cleared by writing 0
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Bit Bit Name
Initial
Value R/W Description
0 IRRl0 0 R/W IRQ0 Interrupt Request Flag
[Setting condition]
When IRQ0 pin is designated for interrupt input and
the designated signal edge is detected.
[Clearing condition]
When IRRI0 is cleared by writing 0
3.2.5 Wakeup Interrupt Flag Register (IWPR)
IWPR is a status flag register for WKP5 to WKP0 interrupt requests.
Bit Bit Name
Initial
Value R/W Description
7
6
1
1
Reserved
These bits are always read as 1.
5 IWPF5 0 R/W WKP5 Interrupt Request Flag
[Setting condition]
When WKP5 pin is designated for interrupt input and
the designated signal edge is detected.
[Clearing condition]
When IWPF5 is cleared by writing 0.
4 IWPF4 0 R/W WKP4 Interrupt Request Flag
[Setting condition]
When WKP4 pin is designated for interrupt input and
the designated signal edge is detected.
[Clearing condition]
When IWPF4 is cleared by writing 0.
3 IWPF3 0 R/W WKP3 Interrupt Request Flag
[Setting condition]
When WKP3 pin is designated for interrupt input and
the designated signal edge is detected.
[Clearing condition]
When IWPF3 is cleared by writing 0.
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Bit Bit Name
Initial
Value R/W Description
2 IWPF2 0 R/W WKP2 Interrupt Request Flag
[Setting condition]
When WKP2 pin is designated for interrupt input and
the designated signal edge is detected.
[Clearing condition]
When IWPF2 is cleared by writing 0.
1 IWPF1 0 R/W WKP1 Interrupt Request Flag
[Setting condition]
When WKP1 pin is designated for interrupt input and
the designated signal edge is detected.
[Clearing condition]
When IWPF1 is cleared by writing 0.
0 IWPF0 0 R/W WKP0 Interrupt Request Flag
[Setting condition]
When WKP0 pin is designated for interrupt input and
the designated signal edge is detected.
[Clearing condition]
When IWPF0 is cleared by writing 0.
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3.3 Reset Exception Handling
When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of
the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure
that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output
stabilizes. To reset the chip during operation, hold th e RES pin low for at least 10 system clock
cycles. When the RES pin goes high after being held low for the necessary time, this LSI starts
reset exception handling. The reset exception handling sequence is shown in figure 3.1.
The reset exception handling sequence is as follows:
1. Set the I bit in the condition cod e register (CCR) to 1.
2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the
data in that address is sent to the program counter (PC) as the start address, and program
execution starts from that address.
3.4 Interrupt Exception Handling
3.4.1 External Interrupts
There are external interrupts, NMI, IRQ3 to IRQ0, and WKP5 to WKP0.
(1) NMI Interrupt
NMI interrupt is requested by input signal edge to pin NMI. This interrupt is detected by either
rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1.
NMI is the highest-priority interrupt, and can always be accepted without depending on the I bit
value in CCR.
(2) IRQ3 to IRQ0 Interrupts
IRQ3 to IRQ0 interrupts are requested by input signals to pins IRQ3 to IRQ0. These four
interrupts are given di f ferent vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in IEGR1.
When pins IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal
edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt. When
IRQ3 to IRQ0 interrupt is accepted, the I bit is set to 1 in CCR. These interrupts can be masked by
setting bits IEN3 to IEN0 in IENR1.
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(3) WKP5 to WKP0 Interrupts
WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six
interrupts have the same vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in IEGR2.
When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated signal
edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an interrupt. These
interrupts can be masked by setting bit IENWP in IENR1.
Vector fetch
φ
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
RES
Internal
processing
Initial program
instruction prefetch
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
(2) (3)
(2)(1)
Reset cleared
Figure 3.1 Reset Sequence
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3.4.2 Internal Interrupts
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to
enable or disable the interrupt. For timer A interrupt requests and direct transfer interrupt requests
generated by execution of a SLEEP instruction, this function is included in IRR1 and IENR1.
When an on-chip peripheral module requests an in terrupt, the corresponding interrupt request
status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit
is set to 1 in CCR. These interrupts can be masked by writing 0 to clear the corresponding enable
bit.
3.4.3 Interrupt Handling Sequence
Interrupts are controlled by an interrupt controller.
Interrupt operation is described as follows.
1. If an interrupt occurs while the NMI or interrupt enab le bit is set to 1, an interrupt request
signal is sent to the interrupt controller.
2. When multiple interrup t requests are generated, the interrupt contro ller requests to the CPU for
the interrupt handling with the highest priority at that time according to table 3.1 . Other
interrupt re quests are held pendi ng .
3. The CPU accepts the NMI and address break without depending on the I bit value. Other
interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the
interrupt request is held pending.
4. If the CPU accepts the interrupt after processing of the current instruction is completed,
interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The
state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the
address of the first instruction to be executed upon ret ur n fr o m int errupt handli n g.
5. Then, the I bit of CCR is set to 1, masking further interrupts excluding the NMI and address
break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be
restored and returned to the values prior to the start of interrupt exception handling.
6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and
transfers the address to PC as a start address of the interrupt handling-routine. Then a program
starts executing from the address indicated in PC.
Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
Section 3 Exception Handling
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PC and CCR
saved to stack
SP (R7)
SP – 1
SP – 2
SP – 3
SP – 4
Stack area
SP + 4
SP + 3
SP + 2
SP + 1
SP (R7)
Even address
Prior to start of interrupt
exception handling
After completion of interrupt
exception handling
[Legend]
PC
H
:
PC
L
:
CCR:
SP:
Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
Condition code register
Stack pointer
Notes:
CCR
CCR*3
PCH
PCL
1.
2.
PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
Register contents must always be saved and restored by word length, starting from
an even-numbered address.
3. Ignored when returning from the interrupt handling routine.
Figure 3.2 Stack Status aft er Excep ti on Han dl i ng
3.4.4 Interrupt Response Time
Table 3.2 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handling-routine is executed.
Table 3.2 Interrupt Wait States
Item States Total
Waiting time for completion of executing instruction* 1 to 23 15 to 37
Saving of PC and CCR to stack 4
Vector fetch 2
Instruction fetch 4
Internal processing 4
Note: * Not including EEPMOV instruction.
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Vector fetch
φ
Internal
address bus
Internal read
signal
Internal write
signal
(2)
Internal data bus
(16 bits)
Interrupt
request signal
(9)
(1)
Internal
processing
Prefetch instruction of
interrupt-handling routine
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)
(2)(4) Instruction code (not executed)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP – 2
(6) SP – 4
(7) CCR
(8) Vector address
(9) Starting address of interrupt-handling routine (contents of vector)
(10) First instruction of interrupt-handling routine
(3) (9)(8)(6)(5)
(4) (1) (7) (10)
Stack access
Internal
processing
Instruction
prefetch
Interrupt level
decision and wait for
end of instruction
Interrupt is
accepted
Figure 3.3 Interrupt Sequence
Section 3 Exception Handling
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3.5 Usage Notes
3.5.1 Interrupts after Reset
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a progr am is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.W #xx: 16, SP).
3.5.2 Notes on Stack Area Use
When word data is accessed the least significant bit of the address is regarded as 0. Access to the
stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd
address. U se PUSH Rn (MOV.W Rn, @–SP ) or POP Rn (MOV.W @SP+, Rn) to save or restore
register values.
3.5.3 Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, IRQ3 to
IRQ0, and WKP5 to WKP0, the interrupt request flag may be set to 1.
Figure 3.4 shows a port mode register setting and interrupt request flag clearing procedure.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0.
Section 3 Exception Handling
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CCR I bit 1
Set port mode register bit
Execute NOP instruction
Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)
After setting the port mode register bit,
first execute at least one instruction
(e.g., NOP), then clear the interrupt
request flag to 0
Interrupt mask cleared
Clear interrupt request flag to 0
←
CCR I bit 0
←
Figure 3.4 Port Mode Register Setting and Interrupt Reque st Flag Clearing Procedure
Section 3 Exception Handling
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Section 4 Address Break
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Section 4 Address Break
The address break simplifies on-board program debugging. It requests an address break interrupt
when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR.
Break conditions that can be set include instruction execution at a specific address and a
combination of access and data at a specific address. With the address break function, the
execution start point of a program containing a bug is detected and execution is branched to the
correcting program. Figure 4.1 shows a block diagram of the address break.
BARH BARL
BDRH BDRL
ABRKCR
ABRKSR
Internal address bus
Comparator
Interrupt
generation
control circuit
Internal data bus
Comparator
Interrupt
[Legend]
BARH, BARL: Break address register
BDRH, BDRL: Break data register
ABRKCR: Address break control register
ABRKSR: Address break status register
Figure 4.1 Block Diagram of Address Break
Section 4 Address Break
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4.1 Register Descriptions
Address break has the following registers.
• Address break control register (ABR KC R )
• Address break status register (ABRKSR)
• Break address register (BARH, BARL)
• Break data register (BDRH, BDRL)
4.1.1 Address Break Control Register (ABRKCR)
ABRKCR sets address break conditions.
Bit Bit Name
Initial
Value R/W Description
7 RTINTE 1 R/W RTE Interrupt Enable
When this bit is 0, the interrupt immediately after
executing RTE is masked and then one instruction must
be executed. When this bit is 1, the interrupt is not
masked.
6
5
CSEL1
CSEL0
0
0
R/W
R/W
Condition Select 1 and 0
These bits set address break conditions.
00: Instruction execution cycle
01: CPU data read cycle
10: CPU data write cycle
11: CPU data read/write cycle
4
3
2
ACMP2
ACMP1
ACMP0
0
0
0
R/W
R/W
R/W
Address Compare Condition Select 2 to 0
These bits comparison condition between the address
set in BAR and the internal address bus.
000: Compares 16-bit addresses
001: Compares upper 12-bit addresses
010: Compares upper 8-bit addresses
011: Compares upper 4-bit addresses
1XX: Reserved (setting prohibited)
Section 4 Address Break
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Bit Bit Name
Initial
Value R/W Description
1
0
DCMP1
DCMP0
0
0
R/W
R/W
Data Compare Condition Select 1 and 0
These bits set the comparison condition between the
data set in BDR and the internal data bus.
00: No data comparison
01: Compares lower 8-bit data between BDRL and data
bus
10: Compares upper 8-bit data between BDRH and
data bus
11: Compares 16-bit data between BDR and data bus
[Legend]
X: Don't care.
When an address break is s et in the da ta read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4.1 shows the access and
data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a
byte access is generated twice. For details on data widths of each register, see section 19.1,
Register Addresses (Address Order).
Table 4.1 Access and Data Bus Used
Word Access Byte Access
Even Address Odd Address Even Address Odd Address
ROM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits
RAM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits
I/O register with 8-bit
data bus width
Upper 8 bits Upper 8 bits Upper 8 bits Upper 8 bits
I/O register with 16-
bit data bus width
Upper 8 bits Lower 8 bits — —
Section 4 Address Break
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4.1.2 Address Break Status Register (ABRKSR)
ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit.
Bit Bit Name
Initial
Value R/W Description
7 ABIF 0 R/W Address Break Interrupt Flag
[Setting condition]
When the condition set in ABRKCR is satisfied
[Clearing condition]
When 0 is written after ABIF=1 is read
6 ABIE 0 R/W Address Break Interrupt Enable
When this bit is 1, an address break interrupt request is
enabled.
5 to 0 — All 1 — Reserved
These bits are always read as 1.
4.1.3 Break Address Registers (BARH, BARL)
BARH and BARL are 16-bit read/write registers that set the address for generating an address
break interrupt. When setting the address break conditio n to the instruction execution cycle, set
the first byte address of the instru ction. The initial value of this register is H'FFFF.
4.1.4 Break Data Registers (BDRH, BDRL)
BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break
interrupt. BDRH is compared with the upper 8-b it data bus. BDRL is compared with the lower 8-
bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is used for
even and odd addresses in the data transmission. Therefore, compar ison data must be set in
BDRH for byte access. For word access, the data bus used depends on the address. See section
4.1.1, Address Break Control Register (ABRKCR), for details. The initial value of this register is
undefined.
Section 4 Address Break
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4.2 Operation
When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an
interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the
address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt
request is accepted, interrupt exception handling starts after the instruction being executed ends.
The address break interrupt is not masked because of the I bit in CCR of the CPU.
Figures 4.2 show the operation examples of the address break interrupt setting.
NOP
instruc-
tion
prefetch
Register setting
• ABRKCR = H'80
• BAR = H'025A
Program
0258
025A
025C
0260
0262
:
*NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
:
0258
Address
bus
φ
Interrupt
request
025A 025C 025E SP-2 SP-4
NOP
instruc-
tion
prefetch
MOV
instruc-
tion 1
prefetch
MOV
instruc-
tion 2
prefetch
Internal
processing
Stack save
Interrupt acceptance
Underline indicates the address
to be stacked.
When the address break is specified in instruction execution cycle
Figure 4.2 Address Break Interrupt Operation Example (1)
Section 4 Address Break
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MOV
instruc-
tion 1
prefetch
Register setting
• ABRKCR = H'A0
• BAR = H'025A
Program
0258
025A
025C
0260
0262
:
*
NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
:
025C
Address
bus
φ
Interrupt
request
025E 0260 025A 0262 0264 SP-2
MOV
instruc-
tion 2
prefetch
NOP
instruc-
tion
prefetch
MOV
instruc-
tion
execution
Next
instru-
ction
prefetch
Internal
processing
Stack
save
NOP
instruc-
tion
prefetch
Interrupt acceptance
Underline indicates the address
to be stacked.
When the address break is specified in the data read cycle
Figure 4.2 Address Break Interrupt Operation Example (2)
Section 4 Address Break
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4.3 Usage Notes
When an address break is s et to an instruction after a conditional branch ins truction, and the
instruction set when the condition of the branch instruction is not satisfied is executed (see figure
4.3), note that an address break interrupt request is not generated. Therefore an address break must
not be set to the instruction after a co nditional branch instruction.
0134
Address bus
φ
Address break
interrupt request
0136 102A 0138
[Register setting]
BNE
instruction
prefetch
NOP
instruction
prefetch
MOV
instruction
prefetch
NOP
instruction
prefetch
ABRKCR = H'80
BAR = H'0136
012A MOV.B . . .
: :
0134 BNE
*0136 NOP
0138 NOP
: :
[Program]
Figure 4.3 Operation when Condition is not Satisfied in Branch Instruction
Section 4 Address Break
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When another interrupt re quest is accepted before an instruction to which an address break is set is
executed, exception handling of an address break interrupt is not executed. However, the ABIF bit
is set to 1 (see figure 4.4). Therefore the ABIF bit must be read during exception handling of an
address break interrupt.
0142
0144
0146
*
MOV.B #H'23,R1H
MOV.B #H'45,R1H
MOV.B #H'67,R1H
0142 0144 0146 SP-2 SP-4 001C 0900
ABIF
[Register setting]
External interrupt Underlined indicates the address to be stacked.
ABRKCR = H'80
BAR = H'0144
001C 0900
: :
[Program]
MOV
instruction
prefetch
MOV
instruction
prefetch
MOV
instruction
prefetch Stack save
Vector
fetch
Internal
processing
External interrupt
acceptance
Internal
processing
Address bus
φ
External interrupt acceptance
Address break
interrupt request
Figure 4.4 Operation when Another Interrupt is Accepted at Address Break Setting
Instruction
Section 4 Address Break
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When an address break is s et to an instruction as a branch destination of a conditional branch
instruction, the instruction set when the condition of th e branch instruction is not satisfied is not
executed, and an address break is generated. Therefore an address break must not be set to the
instruction as a branch destination of a conditional branch instruction.
BNE
instruction
prefetch
NOP
instruction
prefetch
MOV
instruction
prefetch
NOP
instruction
prefetch
[Register setting]
• ADBRKCR = H'80
• BAR = H'0150
[Program]
0134
0136
0138
0150
*
BNE
NOP
NOP
MOV.B
0134
Address bus
φ
Address break
interrupt request
0136 0150 0138
Interrupt acceptance
. . .
Figure 4.5 Operation when the Instruction Set is not Executed and does not Branch due to
Conditions not Being Satisfied
Section 4 Address Break
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Section 5 Clock Pulse Generators
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Section 5 Clock Pulse Generators
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. T he system c lock p uls e gene rat or
consists of a system clock oscillator, a duty correction circuit, and system clo c k dividers. The
subclock pulse gene rator consists of a subclock oscillator circuit and a subclock divider.
Figure 5.1 shows a block diagram of the clock pulse generators.
System
clock
oscillator
Subclock
oscillator Subclock
divider
Duty
correction
circuit
System
clock
divider
Prescaler S
(13 bits)
Prescaler W
(5 bits)
OSC1
OSC2
X1
X2
System clock pulse generator
φOSC
(fOSC)
φOSC
(fOSC)
φW
(fW)
φW/2
φW/4 φSUB
φ/2
to
φ/8192
φW/8
φ
φOSC/8
φOSC
φOSC/16
φOSC/32
φOSC/64
φW/8
to
φW/128
Subclock pulse generator
Figure 5.1 Block Diagram of Clock Pulse Generators
The basic clock signals that drive the CPU and on-chip peripheral modules are φ and φSUB. The
system clock is divided by prescaler S to become a clock signal from φ/8192 to φ/2, and the
subclock is divided by prescaler W to become a clock signal from φw/128 to φw/8. Both the
system clock and subclock signals are provi ded to the on-chip peripheral modules.
Section 5 Clock Pulse Generators
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5.1 System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system
clock generato r.
LPM
LPM: Low-power mode (standby mode, subactive mode, subsleep mode)
2
1
OSC
OSC
Figure 5.2 Block Diagram of System Clock Generator
5.1.1 Connecting Crystal Resonator
Figure 5.3 shows a typical method of connecting a crystal resonator. An AT-cut parallel-resonance
crystal resonator should be used. Figure 5.4 shows the equivalent circuit of a cr ystal resonator. A
resonator having the characteristics given in table 5.1 should be used.
1
2
C
1
C
2
OSC
OSC C
1
= C
2
= 12 pF ±20%
Note: Capacitances are reference values.
Figure 5.3 Typical Connection to Crystal Resonator
C
S
C
0
R
S
OSC
1
OSC
2
L
S
Figure 5.4 Equivalent Circuit of Crystal Res on at or
Section 5 Clock Pulse Generators
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Table 5.1 Crystal Resonator Parameters
Frequency (MHz) 2 4 8 10 16
RS (max) 500 Ω 120 Ω 80 Ω 60 Ω 50 Ω
C0 (max) 7 pF 7 pF 7 pF 7 pF 7 pF
5.1.2 Connecting Ceramic Resonator
Figure 5.5 shows a typical method of connecting a ceramic resonator.
OSC
1
OSC
2
C
1
C
2
C
1
= 30 pF ±10%
C
2
= 30 pF ±10%
Note: Capacitances are reference values.
Figure 5.5 Typical Connection to Ceramic Resonator
5.1.3 External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 5.6 shows a typical
connection. The duty cycle of the external clock signal must be 45 to 55%.
OSC1External clock input
OSC 2 Open
Figure 5.6 Example of External Clock Input
Section 5 Clock Pulse Generators
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5.2 Subclock Generator
Figure 5.7 shows a block diagram of the subclock generator.
Note : Resistance is a reference value.
2
8MΩ
1
x
x
Figure 5.7 Block Diagram of Subclock Ge nera tor
5.2.1 Connecting 32.768-kHz Crystal Resonator
Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal
resonator, as shown in figure 5.8. Figure 5.9 shows the equivalent circuit of the 32.768-kHz
crystal resonator .
Note: Capacitances are reference values.
X
X
C1
C2
1
2C1 = C2 = 15 pF (typ.)
Figure 5.8 Typical Connecti on to 32 .7 68- kHz Cry st al Res on at or
X
1
X
2
L
S
C
S
C
O
C
O
= 1.5 pF (typ.)
R
S
= 14 kΩ (typ.)
f
W
= 32.768 kHz
R
S
Note: Constants are reference values.
Figure 5.9 Equivalent Circ ui t of 3 2. 768 -k Hz Cr ys tal Resonator
Section 5 Clock Pulse Generators
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5.2.2 Pin Connection when Not Using Subclock
When the subclock is not used, connect pin X1 to VCL or VSS and leave pin X2 open, as shown in
figure 5.10.
X
1
V
CL
or V
SS
X
2
Open
Figure 5.10 Pin Connection when not Using Subclock
5.3 Prescalers
5.3.1 Prescaler S
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once
per clock period. Prescaler S is initialized to H'000 0 by a reset, and starts counting on ex it from
the reset state. In standby mode, subactive mode, and subsleep mode, the system clock pulse
generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write
prescaler S. The output from prescaler S is shared by the on- chip peripheral modules. The divider
ratio can be set separately for each on-chip peripheral function. In active mode and sleep mode,
the clock input to prescaler S is determined by the division factor designated by MA2 to MA0 in
SYSCR2.
5.3.2 Prescaler W
Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (φW/4) as its input clock. The
divided outp ut i s used fo r cloc k ti me base o p erat i on of time r A. Prescal er W is i nit i al i zed to H'00
by a reset, and starts counting on exit from the reset state. Even in standby mode, su bact iv e mode,
or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins
X1 and X2. Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register
A (TMA).
Section 5 Clock Pulse Generators
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5.4 Usage Notes
5.4.1 Note on Resonators
Resonator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Resonator circuit constants will differ
depending on the resonator element, stray capacitance in its interconnecting circuit, and other
factors. Suitable constants should be determined in consultation with the resonator element
manufacturer. Design the circuit so that the resonator element never receives voltages exceeding
its maximum rating.
5.4.2 Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as
close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the
resonator circuit to prevent induction from interfering with correct oscillation (see figure 5.11).
OSC1
OSC2
C1
C2
Signal A Signal BAvoid
Figure 5.11 Example of Incorrect Board Design
Section 6 Power-Down Modes
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Section 6 Power-Down Modes
This LSI has six modes of operation after a reset. These include a normal active mode and four
power-down modes, in which power consumption is significantly reduced. Module standby mode
reduces power consumption by selectively halting on-chip module functions.
• Ac tive mode
The CPU and all on-chip peripheral modules are operable on the system clock. The system
clock frequency can be selected from φosc, φosc/8, φosc/16, φosc/32, and φosc/64.
• Subactive mode
The CPU and all on-chip peripheral modules are operable on the subclock. The subclock
frequency can be selected from φw/2, φw/4, and φw/8.
• Sleep mode
The CPU halts. On-chip peripheral modules are operable on the system clock.
• Subsleep mode
The CPU halts. On-chi p peri p heral mod ul es are operable on the subclock.
• Standby mode
The CPU and all on-chip peripheral modules halt. When the clock time-base function is
selected, timer A is operable.
• Module standby mode
Independent of the above modes, power consumption can be reduced by halting on-chip
peripheral modules that are not used in module units.
Section 6 Power-Down Modes
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6.1 Register Descriptions
The registers related to power-down modes are listed below.
• System control register 1 (SYSCR1)
• System control register 2 (SYSCR2)
• Module standby control register 1 (MSTCR1)
6.1.1 System Control Register 1 (SYSCR1)
SYSCR1 controls the power-down modes, as well as SYSCR2.
Bit Bit Name
Initial
Value R/W Description
7 SSBY 0 R/W Software Standby
This bit selects the mode to transit after the execution
of the SLEEP instruction.
0: a transition is made to sleep mode or subsleep
mode.
1: a transition is made to standby mode.
For details, see table 6.2.
6
5
4
STS2
STS1
STS0
0
0
0
R/W
R/W
R/W
Standby Timer Select 2 to 0
These bits designate the time the CPU and peripheral
modules wait for stable clock operation after exiting
from standby mode, subactive mode, or subsleep mode
to active mode or sleep mode due to an interrupt. The
designation should be made according to the clock
frequency so that the waiting time is at least 6.5 ms.
The relationship between the specified value and the
number of wait states is shown in table 6.1. When an
external clock is to be used, the minimum value (STS2
= STS1 = STS0 = 1) is recommended.
Section 6 Power-Down Modes
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Bit Bit Name
Initial
Value R/W Description
3 NESEL 0 R/W Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch
clock signal (φW) and the system clock pulse generator
generates the oscillator clock (φOSC). This bit selects the
sampling frequency of the oscillator clock when the
watch clock signal (φW) is sampled. When φOSC = 4 to 16
MHz, clear NESEL to 0.
0: Sampling rate is φOSC/16
1: Sampling rate is φOSC/4
2
1
0
0
0
0
Reserved
These bits are always read as 0.
Table 6.1 Operating Frequency and Wai tin g Ti me
STS2 STS1 STS0 Waiting Time 16 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz
0 0 0 8,192 states 0.5 0.8 1.0 2.0 4.1 8.1 16.4
1 16,384 states 1.0 1.6 2.0 4.1 8.2 16.4 32.8
1 0 32,768 states 2.0 3.3 4.1 8.2 16.4 32.8 65.5
1 65,536 states 4.1 6.6 8.2 16.4 32.8 65.5 131.1
1 0 0 131,072 states 8.2 13.1 16.4 32.8 65.5 131.1 262.1
1 1,024 states 0.06 0.10 0.13 0.26 0.51 1.02 2.05
1 0 128 states 0.00 0.01 0.02 0.03 0.06 0.13 0.26
1 16 states 0.00 0.00 0.00 0.00 0.01 0.02 0.03
Note: Time unit is ms.
Section 6 Power-Down Modes
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6.1.2 System Control Register 2 (SYSCR2)
SYSCR2 controls the power-down modes, as well as SYSCR1.
Bit Bit Name
Initial
Value R/W Description
7
6
5
SMSEL
LSON
DTON
0
0
0
R/W
R/W
R/W
Sleep Mode Selection
Low Speed on Flag
Direct Transfer on Flag
These bits select the mode to transit after the execution
of a SLEEP instruction, as well as bit SSBY of
SYSCR1.
For details, see table 6.2.
4
3
2
MA2
MA1
MA0
0
0
0
R/W
R/W
R/W
Active Mode Clock Select 2 to 0
These bits select the operating clock frequency in
active and sleep modes. The operating clock frequency
changes to the set frequency after the SLEEP
instruction is executed.
0XX: φOSC
100: φOSC/8
101: φOSC/16
110: φOSC/32
111: φOSC/64
1
0
SA1
SA0
0
0
R/W
R/W
Subactive Mode Clock Select 1 and 0
These bits select the operating clock frequency in
subactive and subsleep modes. The operating clock
frequency changes to the set frequency after the
SLEEP instruction is executed.
00: φW/8
01: φW/4
1X: φW/2
[Legend]
X: Don't care.
Section 6 Power-Down Modes
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6.1.3 Module Standby Control Regi ster 1 (MSTCR1)
MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units.
Bit Bit Name
Initial
Value R/W Description
7 0 Reserved
This bit is always read as 0.
6 MSTIIC 0 R/W IIC Module Standby
IIC enters standby mode when this bit is set to 1
5 MSTS3 0 R/W SCI3 Module Standby
SCI3 enters standby mode when this bit is set to 1
4 MSTAD 0 R/W A/D Converter Module Standby
A/D converter enters standby mode when this bit is set
to 1
3 MSTWD 0 R/W Watchdog Timer Module Standby
Watchdog timer enters standby mode when this bit is
set to 1.When the internal oscillator is selected for the
watchdog timer clock, the watchdog timer operates
regardless of the setting of this bit
2 MSTTW 0 R/W Timer W Module Standby
Timer W enters standby mode when this bit is set to 1
1 MSTTV 0 R/W Timer V Module Standby
Timer V enters standby mode when this bit is set to 1
0 MSTTA 0 R/W Timer A Module Standby
Timer A enters standby mode when this bit is set to 1
Section 6 Power-Down Modes
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6.2 Mode Transitions and States of LSI
Figure 6.1 shows the possible transitions among these operating modes. A transition is made from
the program execution state to the prog ram halt state of the program by executing a SLEEP
instruction. Interrupts allow for returning from the program halt state to the program execution
state of the program. A direct transition between active mode and subactive mode, which are both
program execution states, can be made without halting the program. The operating frequency can
also be changed in the same modes by making a transition directly from active mode to active
mode, and from subactive mode to subactive mode. RES input enables transitions from a mode to
the reset state. Table 6.2 shows the transition conditions of each mode after the SLEEP instruction
is executed and a mode to return by an interrupt. Table 6.3 shows the internal states of the LSI in
each mode.
Reset state
Standby mode Active mode Sleep mode
Subsleep mode
Subactive
mode
Program halt state Program execution state Program halt state
SLEEP
instruction
SLEEP
instruction
Interrupt
Direct transition
interrupt
Direct transition
interrupt
Notes: 1. To make a transition to another mode by an interrupt, make sure interrupt handling is after the interrupt
is accepted.
2. Details on the mode transition conditions are given in table 6.2.
SLEEP
instruction
Direct
transition
interrupt
Direct
transition
interrupt
Interrupt
SLEEP
instruction
Interrupt
Interrupt
SLEEP
instruction
Interrupt
SLEEP
instruction
Figure 6.1 Mode Transiti o n Di agram
Section 6 Power-Down Modes
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Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling
DTON
SSBY
SMSEL
LSON
Transition Mode after
SLEEP Instruction
Execution
Transition Mode due
to Interrupt
0 0 0 0 Sleep mode Active mode
1 Subactive mode
1 0 Subsleep mode Active mode
1 Subactive mode
1 X X Standby mode Active mode
1 X 0* 0 Active mode (direct
transition)
—
X X 1 Subactive mode (direct
transition)
—
[Legend]
X: Don't care.
Note: * When a state transition is performed while SMSEL is 1, timer V, SCI3, and the A/D
converter are reset, and all registers are set to their initial values. To use these
functions after entering active mode, reset the registers.
Section 6 Power-Down Modes
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Table 6.3 Internal State in Each Operating Mode
Function
Active Mode
Sleep Mode Subactive
Mode Subsleep
Mode Standby
Mode
System clock oscillator Functioning Functioning Halted Halted Halted
Subclock oscillator Functioning Functioning Functioning Functioning Functioning
Instructions Functioning Halted Functioning Halted Halted CPU
operations Registers Functioning Retained Functioning Retained Retained
RAM Functioning Retained Functioning Retained Retained
IO ports Functioning Retained Functioning Retained Register
contents are
retained, but
output is the
high-
impedance
state.
IRQ3 to IRQ0 Functioning Functioning Functioning Functioning Functioning External
interrupts WKP5 to
WKP0
Functioning Functioning Functioning Functioning Functioning
Timer A Functioning Functioning Functioning if the timekeeping time-base
function is selected, and retained if not selected
Timer V Functioning Functioning Reset Reset Reset
Timer W Functioning Functioning Retained (if internal clock φ is
selected as a count clock, the
counter is incremented by a
subclock*)
Retained
Watchdog
timer
Functioning Functioning Retained (functioning if the internal oscillator is
selected as a count clock*)
SCI3 Functioning Functioning Reset Reset Reset
IIC Functioning Functioning Retained* Retained Retained
Peripheral
functions
A/D converter Functioning Functioning Reset Reset Reset
Note: * Registers can be read or written in subactive mode.
Section 6 Power-Down Modes
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6.2.1 Sleep Mode
In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock
frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained.
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the
requested interrupt is disabled in the interrupt enable register. After sleep mode is cleared, a
transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to
subactive mode when the bit is 1.
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
6.2.2 Standby Mode
In standby mode, the clock pulse generator stops, so the CPU and on-chip peripheral modules stop
functioning. However, as long as the rated voltage is supplied, the contents of CPU registers, on-
chip RAM, and some on-chip peripheral module registers are retained. On-chip RAM contents
will be retained as long as the voltage set by the RAM data retention voltage is provided. The I/O
ports go to the high-impedance state.
Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse
generator starts. After the time set in bits STS2–STS0 in SYSCR1 has elapsed, and in terrupt
exception handling starts. Standby mode is not cleared if the I bit of CCR is set to 1 or the
requested interrupt is disabled in the interrupt enable register.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generator st art s functi o ning, the
RES pin must be kept low until the pu lse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
Section 6 Power-Down Modes
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6.2.3 Subsleep Mode
In subsleep mode, operation of the CPU and on-chip peripheral modules other than timer A is
halted. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM,
and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states
as before the transition.
Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared
and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1
or the requested interrupt is disabled in the interrupt enable register. After subsleep mode is
cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is
made to subactive mode when th e bit is 1.
When the RES pin goes low, the system clock pulse generator starts. Since system clock signals
are supplied to the entire chip as soon as the system clock pulse generat o r st arts functi o ning, the
RES pin must be kept low until the pulse generator output stabilizes. After the pulse generator
output has stabilized, the CPU starts reset exception handling if the RES pin is driven high.
6.2.4 Subactive Mode
The operating frequency of subactive mode is selected fro m φW/2, φW/4, and φW/8 by the SA1 and
SA0 bits in SYSCR2. After the SLEEP instruction is execute d, the operating frequency changes to
the frequency which is set before the execution. When the SLEEP instruction is executed in
subactive mode, a transition to sleep mode, subsleep mode, standby mode, active mode, or
subactive mode is made, depending on the combination of SYSCR1 and SYSCR2. When the RES
pin goes low, the system clock pulse generator starts. Since system clock signals ar e supplied to
the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be
kept low until the pulse generator output stabilizes. After the pulse generator output has stabilized,
the CPU starts reset exception handling if the RES pin is driven high.
Section 6 Power-Down Modes
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6.3 Operating Frequency in Active Mode
Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits
in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction
execution.
6.4 Direct Transition
The CPU can execute programs in two modes: active and subactive mode. A direct transition is a
transition between these two modes withou t stopping program execution. A direct transition can
be made by executing a SLEEP in struction while the DTON bit in SYSCR2 is set to 1. The direct
transition also enables operating frequency modification in active or subactive mode. After th e
mode transition, direct transition interrupt exception handling starts.
If the direct transition interrupt is disabled in interrupt enable register 1, a transition is made
instead to sleep or subsleep mode. Note that if a direct transition is attempted while the I bit in
CCR is set to 1, sleep or subsleep mode will be entered, and the resulting mode cannot be cleared
by means of an interrupt.
6.4.1 Direct Transition from Active Mode to Subactive Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by equation (1).
Direct transition time = {(number of SLEEP instruction execution states) +
(number of internal processing states)}× (tcyc before transition) +
(number of interrupt exception handling states) × (tsubcyc after transition).………………(1)
Example:
Direct transition time = (2 + 1) × tosc + 14 × 8tw = 3tosc + 112tw
(when the CPU operating clock of φosc → φw/8 is selected)
[Legend]
tosc: OSC clock cycle time
tw: watch clock cycle time
tcyc: system clock (φ) cycle time
tsubcyc: subclock (φSUB) cycle time
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6.4.2 Direct Transition from Subactive Mode to Active Mode
The time from the start of SLEEP instruction execution to the end of interrupt exception handling
(the direct transition time) is calculated by eq uation (2).
Direct transition time = {(number of SLEEP instruction execution states) +
(number of internal processing states)} × (tsubcyc before transition) +
{(waiting time set in bits STS2 to STS0) + (number of interrupt exception handling states)} ×
(tcyc after transition)…………………………………………………………………………(2)
Example
Direct transition time = (2 + 1) × 8 tw + (8192 + 14) × tosc = 24tw + 8206 tosc
(when the CPU operating clock of φw/8 → φosc and a waiting time of 8192 states are selected)
[Legend]
tosc: OSC clock cycle time
tw: watch clock cycle time
tcyc: system clock (φ) cycle time
tsubcyc: subclock (φSUB) cycle time
6.5 Module Standby Function
The module-stand b y fu nct io n can be set to any peri p heral mo dule. In module standby m ode, the
clock supply to modules stops to enter the power-down mode. Module standby mode enables each
on-chip peripheral module to enter the standby state by setting a bit that corresponds to each
module to 1 and cancels the mode by clearin g the bit to 0.
6.6 Usage Note
When subsleep mode is entered by setting the SMSEL bit to 1 while the subclock is not used (the
X1 pin is fixed), note that active mode cannot be re-entered by using an interrupt. To use a power-
down mode while a port is retained, connect the subclock to th e X1 and X2 pins.
Section 7 ROM
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Section 7 ROM
The features of the 32-kbyte flash memory built into the flash memory version are summarized
below.
• Programming/erase methods
The flash memory is programmed 128 bytes at a time. Erase is performed in single-b lock
units. The flash memory is configured as follows: 1 kbyte × 4 blocks and 28 kbytes × 1
block. To erase the entire flash memory, each block must be erased in turn.
• Reprogramming capability
The flash memory can be reprogrammed up to 1,000 times.
• On-board programming
On-board programming/erasing can be done in boot mode, in which the boot program built
into the chip is started to erase or program of the entire flash memory. In normal user
program mode, individual blocks can be erased or programmed.
• Programmer mode
Flash memory can be programmed/erased in pro gram mer mo de usi n g a PR OM
programmer, as well as in on-board programming mode.
• Automatic bit rate adjustment
For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match
the transfer bit rate of the host.
• Programming/erasing pr ot ect i on
Sets software protection against fl ash memory programming/erasing.
• Power-down mode
Operation of the power supply circuit can be partly halted in subactive mode. As a result,
flash memory can be read with low power consumption.
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7.1 Block Configuration
Figure 7.1 shows the block configuration of 32-kbyte flash memory. The thick lines indicate
erasing units, the narrow lines indicate programming units, and the values are addresses. The
flash memory is divided into 1 kbyte × 4 blocks and 28 kbytes × 1 block. Erasing is performed in
these units. Programming is performed in 128-byte units starting from an address with lower eight
bits H'00 or H' 80 .
H'007F
H'0000 H'0001 H'0002
H'00FF
H'0080 H'0081 H'0082
H'03FF
H'0380 H'0381 H'0382
H'047F
H'0400 H'0401 H'0402
H'04FF
H'0480 H'0481 H'0481
H'07FF
H'0780 H'0781 H'0782
H'087F
H'0800 H'0801 H'0802
H'08FF
H'0880 H'0881 H'0882
H'0BFF
H'0B80 H'0B81 H'0B82
H'0C7F
H'0C00 H'0C01 H'0C02
H'0CFF
H'0C80 H'0C81 H'0C82
H'0FFF
H'0F80 H'0F81 H'0F82
H'107F
H'1000 H'1001 H'1002
H'10FF
H'1080 H'1081 H'1082
H'7FFF
H'7F80 H'7F81 H'7F82
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
1kbyte
Erase unit
1kbyte
Erase unit
1kbyte
Erase unit
1kbyte
Erase unit
28 kbytes
Erase unit
Figure 7.1 Flash Memory Bl ock Co nfi g u r ation
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7.2 Register Descriptions
The flash memory has the following registers.
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1)
• Flash memory power control regi st er (FLP WC R )
• Flash memory enable register (FENR)
7.2.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash
Memory Programming/Erasing.
Bit Bit
Name Initial
Value R/W Description
7 — 0 — Reserved
This bit is always read as 0.
6 SWE 0 R/W Software Write Enable
When this bit is set to 1, flash memory
programming/erasing is enabled. When this bit is
cleared to 0, other FLMCR1 register bits and all EBR1
bits cannot be set.
5 ESU 0 R/W Erase Setup
When this bit is set to 1, the flash memory changes to
the erase setup state. When it is cleared to 0, the
erase setup state is cancelled. Set this bit to 1 before
setting the E bit to 1 in FLMCR1.
4 PSU 0 R/W Program Setup
When this bit is set to 1, the flash memory changes to
the program setup state. When it is cleared to 0, the
program setup state is cancelled. Set this bit to 1
before setting the P bit in FLMCR1.
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Bit Bit
Name Initial
Value R/W Description
3 EV 0 R/W Erase-Verify
When this bit is set to 1, the flash memory changes to
erase-verify mode. When it is cleared to 0, erase-verify
mode is cancelled.
2 PV 0 R/W Program-Verify
When this bit is set to 1, the flash memory changes to
program-verify mode. When it is cleared to 0,
program-verify mode is cancelled.
1 E 0 R/W Erase
When this bit is set to 1, and while the SWE=1 and
ESU=1 bits are 1, the flash memory changes to erase
mode. When it is cleared to 0, erase mode is
cancelled.
0 P 0 R/W Program
When this bit is set to 1, and while the SWE=1 and
PSU=1 bits are 1, the flash memory changes to
program mode. When it is cleared to 0, program mode
is cancelled.
7.2.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Bit Bit
Name Initial
Value R/W Description
7 FLER 0 R Flash Memory Error
Indicates that an error has occurred during an
operation on flash memory (programming or erasing).
When FLER is set to 1, flash memory goes to the error-
protection state.
See section 7.5.3, Error Protection, for details.
6 to 0 — All 0 — Reserved
These bits are always read as 0.
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7.2.3 Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to
be automatically cleared to 0.
Bit Bit
Name Initial
Value R/W Description
7 to 5 — All 0 — Reserved
These bits are always read as 0.
4 EB4 0 R/W When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF
will be erased.
3 EB3 0 R/W When this bit is set to 1, 1 kbyte of H'0C00 to H'0FFF
will be erased.
2 EB2 0 R/W When this bit is set to 1, 1 kbyte of H'0800 to H'0BFF
will be erased.
1 EB1 0 R/W When this bit is set to 1, 1 kbyte of H'0400 to H'07FF
will be erased.
0 EB0 0 R/W When this bit is set to 1, 1 kbyte of H'0000 to H'03FF
will be erased.
7.2.4 Flash Memory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. There are two modes: mode in which operation of the power supply
circuit of flash memory is partly halted in power-down mo de and flash memory can be read, and
mode in which even if a transition is made to subactive mode, operation of the power supply
circuit of flash memory is retained and flash memory can be read.
Bit Bit
Name Initial
Value R/W Description
7 PDWND 0 R/W Power-Down Disable
When this bit is 0 and a transition is made to subactive
mode, the flash memory enters the power-down mode.
When this bit is 1, the flash memory remains in the
normal mode even after a transition is made to
subactive mode.
6 to 0 — All 0 — Reserved
These bits are always read as 0.
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7.2.5 Flash Memory Enable Register (FEN R)
Bit 7 (FLSHE) in FENR enables or disables the CPU access to the flash memory control registers,
FLMCR1, FLMCR2, EBR1, and FLPWCR.
Bit Bit
Name Initial
Value R/W Description
7 FLSHE 0 R/W Flash Memory Control Register Enable
Flash memory control registers can be accessed when
this bit is set to 1. Flash memory control registers
cannot be accessed when this bit is set to 0.
6 to 0 — All 0 — Reserved
These bits are always read as 0.
7.3 On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables on-
board programming/erasing, and programmer mode, in which programming/erasing is performed
with a PROM programmer. On-board programming/erasing can also be performed in user
program mode. At reset-start in reset mode, the series of HD64F3664 changes to a mode
depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in
table 7.1. The input level of each pin must be defined four states before the reset ends.
When chang ing to boot mode, the boot program built into this LSI is initiated. The boot program
transfers the programming control program from the externally-connected host to on-chip RAM
via SCI3. After erasing th e entire flash memory, the programming control program is executed.
This can be used for programming initial values in th e on-board state or for a forcible return when
programming/erasing can no longer be done in user program mode. In user program mode,
individual blocks can be erased and programmed by branching to the user program/erase control
program prepared by the user.
Table 7.1 Setting Programming Modes
TEST NMI P85 PB0 PB1 PB2 LSI State after Reset End
0 1 X X X X User Mode
0 0 1 X X X Boot Mode
1 X X 0 0 0 Programmer Mode
[Legend]
X: Don't care.
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7.3.1 Boot Mode
Table 7.2 shows the boot mode operations between reset end and branching to the programming
control pro gram.
1. When boot mode is use d, t he fl ash mem or y pr o gram mi n g c ontrol program must be prepared in
the host beforehand. Prepare a programming control program in accordance with the
description in s ecti on 7.4, Flash Memor y Pr o gra mmi n g/ Erasing.
2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop
bit, and no parity.
3. When the boot program is initiated, the chip measures the low-level period of asynchronous
SCI communication data (H'00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that
of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be
pulled up on the board if necessary. After the reset is complete, it take s approximately 100
states before the chip is ready to measur e the low-level period.
4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
completion of bit rate adjustment. The host should confirm that this adjustment end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate th e SCI properly, set the host's transfer bit
rate and system clock frequency of this LSI within the ranges listed in table 7.3.
5. In boot mode, a part of th e on-chip RAM area is used by the boot program. The area H'F780 to
H'FEEF is the area to which the programming control program is transferred from the host.
The boot program area cannot be used until the execution state in boot mode switches to the
programming control program.
6. Before bran ching to the programming control program, the chip terminates transfer operations
by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer
of write data or verify data with the host. The TxD pin is high (PCR22 = 1, P22 = 1). The
contents of the CPU ge neral r e gi sters a re un defined immediat ely after branching to the
programming control program. These registers must be initialized at the beginning of the
programming control program, as the stack pointer (SP), in particular, is used implicitly in
subroutine calls, etc.
7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at
least 20 states, and then setting the TEST pin and NMI pin. Boot mode is also cleared when a
WDT overflow occurs.
8. Do not change the TEST pin and NMI pin input levels in boot mode.
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Table 7.2 Boot Mode Operation
Communication Contents
Processing Contents
Host Operation LSI Operation
Processing Contents
Continuously transmits data H'00
at specified bit rate.
Branches to boot program at reset-start.
Boot program initiation
H'00, H'00 . . . H'00
H'00
H'55 H'55 reception.
Transmits data H'55 when data H'00
is received error-free.
H'XX
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data
(low-order byte following high-order
byte)
Transmits 1-byte of programming
control program (repeated for N times)
H'AA reception
H'AA reception
Upper bytes, lower bytes
Echoback
Echoback
H'AA
H'AA
Branches to programming control program
transferred to on-chip RAM and starts
execution.
Transmits data H'AA to host when data H'55
is received.
Checks flash memory data, erases all flash
memory blocks in case of written data
existing, and transmits data H'AA to host.
(If erase could not be done, transmits data
H'FF to host and aborts operation.)
H'FF
Boot program
erase error
Item
Boot mode initiation
• Measures low-level period of receive data
H'00.
• Calculates bit rate and sets BRR in SCI3.
• Transmits data H'00 to host as adjustment
end indication.
Bit rate adjustment
Echobacks the 2-byte data
received to host.
Echobacks received data to host and also
transfers it to RAM.
(repeated for N times)
Transfer of number of bytes of
programming control program Flash memory erase
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Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is
Possible
Host Bit Rate System Clock Frequency Range of LSI
19,200 bps 16 MHz
9,600 bps 8 to 16 MHz
4,800 bps 4 to 16 MHz
2,400 bps 2 to 16 MHz
7.3.2 Programming/Erasing in User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user
program mode by branching to a user program/erase control program. The user must set branching
conditions and provide on-board means of supplying programming data. The flash memory must
contain the user program/erase control program or a program that provides the user p rogram/e rase
control program from external memory. As the flash memory itself cannot be read during
programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot
mode. Figure 7.2 shows a sample procedure fo r programming/erasing in user program mode.
Prepare a user program/erase control program in accordance with the description in section 7.4,
Flash Memory Programming/Erasing.
Ye s
No
Program/erase?
Transfer user program/erase control
program to RAM
Reset-start
Branch to user program/erase control
program in RAM
Execute user program/erase control
program (flash memory rewrite)
Branch to flash memory application
program
Branch to flash memory application
program
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode
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7.4 Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the on-
board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one
of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify
mode. The programming control program in boot mode and the user program/erase control
program in user program mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 7.4.1, Program/Progra m-Verify and section 7.4.2,
Erase/Erase-Verify, respectively.
7.4.1 Program/Program-Verify
When writing dat a or programs to the flash memor y, t he pr og ram/program- veri f y fl o wchart shown
in figure 7.3 sh ould be followed. Pe rf or mi n g pr o gramming operat i o ns ac cor di n g t o this fl o wchart
will enable data or programs to be written to the flash memory without sub jecting the chip to
voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128-
byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation according to table 7.4, and additional programming data
computation according to table 7.5.
4. Consecutiv ely transfer 128 bytes of data in byte units fro m the reprogramming data area or
additional-pro gra mmi n g data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80 .
5. The time during which the P bit is set to 1 is the programming time. Table 7.6 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
An overflow cycle of approximately 6.6 ms is allowed.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits
are B'00. Verify data can be read in words or in longwords from the address to which a
dummy write was per f ormed.
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8. The maximum number of repetitions of the program/program-verify sequen ce of th e same bit
is 1,000.
START
End of programming
Note: *The RTS instruction must not be used during the following 1. and 2. periods.
1. A period between 128-byte data programming to flash memory and the P bit clearing
2. A period between dummy writing of H'FF to a verify address and verify data reading
Set SWE bit in FLMCR1
Write pulse application subroutine
Wait 1 µs
Apply Write Pulse
*
End Sub
Set PSU bit in FLMCR1
WDT enable
Disable WDT
Wait 50 µs
Set P bit in FLMCR1
Wait (Wait time=programming time)
Clear P bit in FLMCR1
Wait 5 µs
Clear PSU bit in FLMCR1
Wait 5 µs
n= 1
m= 0
No
No
No Yes
Yes
Yes
Yes
Wait 4 µs
Wait 2 µs
Wait 2 µs
Apply
Write pulse
Set PV bit in FLMCR1
Set block start address as
verify address
H'FF dummy write to verify address
Read verify data
Verify data =
write data?
Reprogram data computation
Additional-programming data computation
Clear PV bit in FLMCR1
Clear SWE bit in FLMCR1
m = 1
m= 0 ?
Increment address
Programming failure
No
Clear SWE bit in FLMCR1
Wait 100 µs
No
Yes
n
≤
6?
No
Yes
n
≤
6 ?
Wait 100 µs
n ≤ 1000 ?
n ← n + 1
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Store 128-byte program data in program
data area and reprogram data area
Apply Write Pulse
Sub-Routine-Call
128-byte
data verification completed?
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
*
Figure 7.3 Program/Program-Verify Flowchart
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Table 7.4 Reprogram Dat a C ompu t at i on Tabl e
Program Data Verify Data Reprogram Data Comments
0 0 1 Programming completed
0 1 0 Reprogram bit
1 0 1 —
1 1 1 Remains in erased state
Table 7.5 Additional -Program Data C omp ut ation Table
Reprogram Data
Verify Data Additional-Program
Data
Comments
0 0 0 Additional-program bit
0 1 1 No additional programming
1 0 1 No additional programming
1 1 1 No additional programming
Table 7.6 Programming Time
n
(Number of Writes) Programming
Time In Additional
Programming
Comments
1 to 6 30 10
7 to 1,000 200 —
Note: Time shown in µs.
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7.4.2 Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
register (EBR1). To erase multiple blocks, each block must be erased in turn.
3. The time during which th e E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An
overflow cycle of approximately 19.8 ms is allowed.
5. For a dummy write to a verify address, write 1-byte data H'FF to an addr ess whose lower two
bits are B'00. Verify data can be read in longwords from the address to whic h a dumm y wri t e
was performed.
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase-
verify sequence as before. The maximum number of repetitions of the erase/erase-verify
sequence is 100.
7.4.3 Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed
or erased, or while the boot program is executing, for the following three reasons:
1. Interrupt d urin g pr o gramming/erasin g may cause a vi ol at i on of the pr og r a mmi n g or era si ng
algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handling starts before the vector address is written or during
programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
carried out.
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Erase start
Set EBR1
Enable WDT
Wait 1 µs
Wait 100 µs
SWE bit ← 1
n ← 1
ESU bit ← 1
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 µs
ESU bit ← 10
10 µs
Disable WDT
Read verify data
Increment address Verify data + all 1s ?
Last address of block ?
All erase block erased ?
Set block start address as verify address
H'FF dummy write to verify address
Wait 20 µs
Wait 2 µs
EV bit ← 1
Wait 100 µs
End of erasing
Note: *The RTS instruction must not be used during a period between dummy writing of H'FF to a verify address and verify data reading.
SWE bit ← 0
Wait 4 µs
EV bit ← 0
n ≤100 ?
Wait 100 µs
Erase failure
SWE bit ← 0
Wait 4µs
EV bit ← 0
n ← n + 1
Ye s
No
Ye s
Ye s
Ye s
No
No
No
*
Figure 7.4 Erase/Erase-Verify Flowchart
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7.5 Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
7.5.1 Hardware Protection
Hardware protect i on refe rs to a state in which pr o gram mi n g/ erasi ng o f fla s h mem or y is forcibly
disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby
mode. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2),
and erase block register 1 (EBR1) are initialized. In a reset via the RES pin, the reset state is not
entered unless the RES pin is held low until oscillatio n stabilizes after powering on. In the case of
a reset during operation, hold the RES pin low for the RES pulse width specified in the AC
Characteristics section.
7.5.2 Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase
block register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to
H'00, erase protection is set for all blocks.
7.5.3 Error Protection
In error protection, an error is detected whe n CPU runa way occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the progr am/ erase operation
prevents d amag e to the flash memory due to overprogramming or overerasing.
When the follow ing errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and th e error pro tection state is entered.
• When the flash memory of the re levant address area is read during programming/er asing
(including vector read and instruction fetch)
• Immediately after exception handling excluding a reset during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
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The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode
is aborted at the point at wh ich the error occurred. Program mode or erase mode cannot be re-
entered by re-setting the P or E bit. H owever, PV and EV bit setting is enab led, and a transition
can be made to verify mode. Error protection can be cleared only by a power-on reset.
7.6 Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU
device type with the on-chip 64-kbyte flash memory (FZTAT64V5).
7.7 Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read and written to at high speed.
• Powe r-down operating mode
The power supply circui t of flash memory can be partly halted. As a result, flash memory can
be read with low power consumption.
• Standby mode
All flash memory circuits are ha lted.
Table 7.7 shows the correspondence between the operating modes of this LSI and the flash
memory. In subactive mode, the flash memory can be set to operate in power-down mode with the
PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from
power-down mode or standby mode, a period to stabilize operation of the power supply circuits
that were stopped is needed. When the flash memory returns to its normal operating state, bits
STS2 to STS0 in SYSCR1 must be set to pro vide a wait time of at least 20 µs, even when the
external clock is being used .
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Table 7.7 Flash Memory Operating States
Flash Memory Operating State
LSI Operating State PDWND = 0 (Initial value) PDWND = 1
Active mode Normal operating mode Normal operating mode
Subactive mode Power-down mode Normal operating mode
Sleep mode Normal operating mode Normal operating mode
Subsleep mode Standby mode Standby mode
Standby mode Standby mode Standby mode
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Section 8 RAM
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Section 8 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit
data bus, enabling two-state access by the CPU to both byte data and word data.
Product Classification RAM Size RAM Address
Flash memory version H8/3664N 2 kbytes H'F780 to H'FF7F*
(F-ZTATTM version) H8/3664F 2 kbytes H'F780 to H'FF7F*
Mask ROM version H8/3664 1 kbyte H'FB80 to H'FF7F
H8/3663 1 kbyte H'FB80 to H'FF7F
H8/3662 512 bytes H'FD80 to H'FF7F
H8/3661 512 bytes H'FD80 to H'FF7F
H8/3660 512 bytes H'FD80 to H'FF7F
Note: * Area H'F780 to H'FB7F must not be accessed.
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Section 9 I/O Ports
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Section 9 I/O Ports
The group of this LSI has twenty-nine gen eral I/O ports (twenty-seven ports for H8/3664N) and
eight general input-only ports. Port 8 is a large current port, which can drive 20 mA (@VOL = 1.5
V) when a low level signal is output. Any of these ports can become an input port immediately
after a reset. They can also be used as I/O pins of the on-c h i p pe rip heral m od ule s or exte r nal
interrupt input pins, and these functions can be switched depending on the register settings. The
registers for selecting these functions can be divided into two types: those included in I/O ports
and those included in each on-chip peripheral module. General I/O ports are comprised of the port
control register for controllin g inputs/outputs and the port data register for storing output data and
can select inputs/outputs in bit units. For functions in each port, see appendix B.1, I/O Port Block.
For the execution of bit manipulation in structions to the port control register and port data register,
see section 2.8.3, Bit Manipulation Instruction.
9.1 Port 1
Port 1 is a general I/O port also functioning as IRQ interrupt input pins, a timer A output pin, and
a timer V input pin. Figure 9.1 shows its pin configuration.
P17/IRQ3/TRGV
P16/IRQ2
P15/IRQ1
P14/IRQ0
P12
P11
P10/TMOW
Port 1
Figure 9.1 Port 1 Pin Configuration
Port 1 has the following registers.
• Port mode register 1 (PMR1)
• Port control register 1 (PCR1)
• Port data register 1 (PDR1)
• Port pull-up control register 1 (PUCR1)
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9.1.1 Port Mode Register 1 (PMR1)
PMR1 switches the functions of pins in port 1 and port 2.
Bit Bit Name
Initial
Value R/W Description
7 IRQ3 0 R/W P17/IRQ3/TRGV Pin Function Switch
This bit selects whether pin P17/IRQ3/TRGV is used as
P17 or as IRQ3/TRGV.
0: General I/O port
1: IRQ3/TRGV input pin
6 IRQ2 0 R/W P16/IRQ2 Pin Function Switch
This bit selects whether pin P16/IRQ2 is used as P16 or
as IRQ2.
0: General I/O port
1: IRQ2 input pin
5 IRQ1 0 R/W P15/IRQ1 Pin Function Switch
This bit selects whether pin P15/IRQ1 is used as P15 or
as IRQ1.
0: General I/O port
1: IRQ1 input pin
4 IRQ0 0 R/W P14/IRQ0 Pin Function Switch
This bit selects whether pin P14/IRQ0 is used as P14 or
as IRQ0.
0: General I/O port
1: IRQ0 input pin
3
2
1
1
Reserved
These bits are always read as 1.
1 TXD 0 R/W P22/TXD Pin Function Switch
This bit selects whether pin P22/TXD is used as P22 or
as TXD.
0: General I/O port
1: TXD output pin
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Bit Bit Name
Initial
Value R/W Description
0 TMOW 0 R/W P10/TMOW Pin Function Switch
This bit selects whether pin P10/TMOW is used as P10
or as TMOW.
0: General I/O port
1: TMOW output pin
9.1.2 Port Control Register 1 (PCR1 )
PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PCR17
PCR16
PCR15
PCR14
PCR12
PCR11
PCR10
0
0
0
0
0
0
0
W
W
W
W
W
W
W
When the corresponding pin is designated in PMR1 as
a general I/O pin, setting a PCR1 bit to 1 makes the
corresponding pin an output port, while clearing the bit
to 0 makes the pin an input port.
Bit 3 is a reserved bit.
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9.1.3 Port Data Register 1 (PDR1)
PDR1 is a general I/O port data register of port 1.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P12
P11
P10
0
0
0
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR1 stores output data for port 1 pins.
If PDR1 is read while PCR1 bits are set to 1, the value
stored in PDR1 are read. If PDR1 is read while PCR1
bits are cleared to 0, the pin states are read regardless
of the value stored in PDR1.
Bit 3 is a reserved bit. This bit is always read as 1.
9.1.4 Port Pull-Up Control Register 1 (PUC R1 )
PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PUCR17
PUCR16
PUCR15
PUCR14
PUCR12
PUCR11
PUCR10
0
0
0
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Only bits for which PCR1 is cleared are valid. The pull-
up MOS of P17 to P14 and P12 to P10 pins enter the
on-state when these bits are set to 1, while they enter
the off-state when these bits are cleared to 0.
Bit 3 is a reserved bit. This bit is always read as 1.
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9.1.5 Pin Functions
The correspondence between the register specification and the port functions is shown below.
• P17/IRQ3/TRGV Pin
Register PMR1 PCR1
Bit Name IRQ3 PCR17 Pin Function
Setting value 0 0 P17 input pin
1 P17 output pin
1 X IRQ3 input/TRGV input pin
[Legend]
X: Don't care.
• P16/IRQ2 Pin
Register PMR1 PCR1
Bit Name IRQ2 PCR16 Pin Function
Setting value 0 0 P16 input pin
1 P16 output pin
1 X IRQ2 input pin
[Legend]
X: Don't care.
• P15/IRQ1 Pin
Register PMR1 PCR1
Bit Name IRQ1 PCR15 Pin Function
Setting value 0 0 P15 input pin
1 P15 output pin
1 X IRQ1 input pin
[Legend]
X: Don't care.
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• P14/IRQ0 Pin
Register PMR1 PCR1
Bit Name IRQ0 PCR14 Pin Function
Setting value 0 0 P14 input pin
1 P14 output pin
1 X IRQ0 input pin
[Legend]
X: Don't care.
• P12 Pin
Register PCR1
Bit Name PCR12 Pin Function
0 P12 input pin Setting value
1 P12 output pin
• P11 Pin
Register PCR1
Bit Name PCR11 Pin Function
0 P11 input pin Setting value
1 P11 output pin
• P10/TMOW Pin
Register PMR1 PCR1
Bit Name TMOW PCR10 Pin Function
Setting value 0 0 P10 input pin
1 P10 output pin
1 X TMOW output pin
[Legend]
X: Don't care.
Section 9 I/O Ports
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9.2 Port 2
Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in
figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the p ins for both
uses.
P22/TXD
P21/RXD
P20/SCK3
Port 2
Figure 9.2 Port 2 Pin Configuration
Port 2 has the following registers.
• Port control register 2 (PCR2)
• Port data register 2 (PDR2)
9.2.1 Port Control Register 2 (PCR2 )
PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
Reserved
2
1
0
PCR22
PCR21
PCR20
0
0
0
W
W
W
When each of the port 2 pins P22 to P20 functions as
an general I/O port, setting a PCR2 bit to 1 makes the
corresponding pin an output port, while clearing the bit
to 0 makes the pin an input port.
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9.2.2 Port Data Register 2 (PDR2)
PDR2 is a general I/O port data register of port 2.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
1
1
1
1
1
Reserved
These bits are always read as 1.
2
1
0
P22
P21
P20
0
0
0
R/W
R/W
R/W
PDR2 stores output data for port 2 pins.
PDR2 is read while PCR2 bits are set to 1, the value
stored in PDR2 is read. If PDR2 is read while PCR2 bits
are cleared to 0, the pin states are read regardless of
the value stored in PDR2.
9.2.3 Pin Functions
The correspondence between the register specification and the port functions is shown below.
• P22/TXD Pin
Register PMR1 PCR2
Bit Name TXD PCR22 Pin Function
Setting Value 0 0 P22 input pin
1 P22 output pin
1 X TXD output pin
[Legend]
X: Don't care.
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• P21/RXD Pin
Register SCR3 PCR2
Bit Name RE PCR21 Pin Function
Setting Value 0 0 P21 input pin
1 P21 output pin
1 X RXD input pin
[Legend]
X: Don't care.
• P20/SCK3 Pin
Register SCR3 SMR PCR2
Bit Name CKE1 CKE0 COM PCR20 Pin Function
Setting Value 0 0 0 0 P20 input pin
1 P20 output pin
0 0 1 X SCK3 output pin
0 1 X X SCK3 output pin
1 X X X SCK3 input pin
[Legend]
X: Don't care.
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9.3 Port 5
Port 5 is a general I/O port also functioning as an I2C bus interface I/O pin, an A/D trigger input
pin, wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting
of the I2C bus interface register has priority for functions of the pins P57/SCL and P56/SDA. Since
the output buffer for pins P56 and P57 has the NMOS push-pull structure, it differs from an output
buffer with the CMOS structure in the high-level output characteristics (see section 20, Electrical
Characteristics). The H8/3664 N doe s not have P57 and P56.
P57/SCL
P56/SDA
P55/WKP5/ADTRG
P54/WKP4
P53/WKP3
P52/WKP2
P51/WKP1
P50/WKP0
Port 5
SCL
SDA
P55/WKP5/ADTR
G
P54/WKP4
P53/WKP3
P52/WKP2
P51/WKP1
P50/WKP0
Port 5
H8/3664 H8/3664N
Figure 9.3 Port 5 Pin Configuration
Port 5 has the following registers.
• Port mode register 5 (PMR5)
• Port control register 5 (PCR5)
• Port data register 5 (PDR5)
• Port pull-up control register 5 (PUCR5)
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9.3.1 Port Mode Register 5 (PMR5)
PMR5 switches the functions of pins in port 5.
Bit Bit Name
Initial
Value R/W Description
7
6
0
0
Reserved
These bits are always read as 0.
5 WKP5 0 R/W P55/WKP5/ADTRG Pin Function Switch
Selects whether pin P55/WKP5/ADTRG is used as P55
or as WKP5/ADTRG input.
0: General I/O port
1: WKP5/ADTRG input pin
4 WKP4 0 R/W P54/WKP4 Pin Function Switch
Selects whether pin P54/WKP4 is used as P54 or as
WKP4.
0: General I/O port
1: WKP4 input pin
3 WKP3 0 R/W P53/WKP3 Pin Function Switch
Selects whether pin P53/WKP3 is used as P53 or as
WKP3.
0: General I/O port
1: WKP3 input pin
2 WKP2 0 R/W P52/WKP2 Pin Function Switch
Selects whether pin P52/WKP2 is used as P52 or as
WKP2.
0: General I/O port
1: WKP2 input pin
1 WKP1 0 R/W P51/WKP1 Pin Function Switch
Selects whether pin P51/WKP1 is used as P51 or as
WKP1.
0: General I/O port
1: WKP1 input pin
Section 9 I/O Ports
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Bit Bit Name
Initial
Value R/W Description
0 WKP0 0 R/W P50/WKP0 Pin Function Switch
Selects whether pin P50/WKP0 is used as P50 or as
WKP0.
0: General I/O port
1: WKP0 input pin
9.3.2 Port Control Register 5 (PCR5 )
PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
When each of the port 5 pins P57 to P50 functions as
an general I/O port, setting a PCR5 bit to 1 makes the
corresponding pin an output port, while clearing the bit
to 0 makes the pin an input port.
Note: Do not set PCR57 and PCR56 to 1 for H8/3664N.
Section 9 I/O Ports
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9.3.3 Port Data Register 5 (PDR5)
PDR5 is a general I/O port data register of port 5.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
P57
P56
P55
P54
P53
P52
P51
P50
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Stores output data for port 5 pins.
If PDR5 is read while PCR5 bits are set to 1, the value
stored in PDR5 are read. If PDR5 is read while PCR5
bits are cleared to 0, the pin states are read regardless
of the value stored in PDR5.
Note: Do not set P57 and P56 to 1 for H8/3664N.
9.3.4 Port Pull-Up Control Register 5 (PUC R5 )
PUCR5 controls the pull-up MOS in bit units o f the pins set as the input ports.
Bit Bit Name
Initial
Value R/W Description
7
6
0
0
Reserved
These bits are always read as 0.
5
4
3
2
1
0
PUCR55
PUCR54
PUCR53
PUCR52
PUCR51
PUCR50
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Only bits for which PCR5 is cleared are valid. The pull-
up MOS of the corresponding pins enter the on-state
when these bits are set to 1, while they enter the off-
state when these bits are cleared to 0.
Section 9 I/O Ports
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9.3.5 Pin Functions
The correspondence between the register specification and the port functions is shown below.
• P57/SCL Pin
Register ICCR PCR5
Bit Name ICE PCR57 Pin Function
Setting Value 0 0 P57 input pin
1 P57 output pin
1 X SCL I/O pin
[Legend]
X: Don't care.
SCL performs the NMOS open-drain output, that enables a direct bus drive.
• P56/SDA Pin
Register ICCR PCR5
Bit Name ICE PCR56 Pin Function
Setting Value 0 0 P56 input pin
1 P56 output pin
1 X SDA I/O pin
[Legend]
X: Don't care.
SDA performs the NMOS open-drain output, that enables a direct bus drive.
• P55/WKP5/ADTRG Pin
Register PMR5 PCR5
Bit Name WKP5 PCR55 Pin Function
Setting Value 0 0 P55 input pin
1 P55 output pin
1 X WKP5/ADTRG input pin
[Legend]
X: Don't care.
Section 9 I/O Ports
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• P54/WKP4 Pin
Register PMR5 PCR5
Bit Name WKP4 PCR54 Pin Function
Setting Value 0 0 P54 input pin
1 P54 output pin
1 X WKP4 input pin
[Legend]
X: Don't care.
• P53/WKP3 Pin
Register PMR5 PCR5
Bit Name WKP3 PCR53 Pin Function
Setting Value 0 0 P53 input pin
1 P53 output pin
1 X WKP3 input pin
[Legend]
X: Don't care.
• P52/WKP2 Pin
Register PMR5 PCR5
Bit Name WKP2 PCR52 Pin Function
Setting Value 0 0 P52 input pin
1 P52 output pin
1 X WKP2 input pin
[Legend]
X: Don't care.
Section 9 I/O Ports
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• P51/WKP1 Pin
Register PMR5 PCR5
Bit Name WKP1 PCR51 Pin Function
Setting Value 0 0 P51 input pin
1 P51 output pin
1 X WKP1 input pin
[Legend]
X: Don't care.
• P50/WKP0 Pin
Register PMR5 PCR5
Bit Name WKP0 PCR50 Pin Function
Setting Value 0 0 P50 input pin
1 P50 output pin
1 X WKP0 input pin
[Legend]
X: Don't care.
9.4 Port 7
Port 7 is a general I/O port also fu nct i o nin g as a timer V I/O pin. Each pin of the port 7 i s show n
in figure 9.4. The register setting of TCSRV in timer V has priority for functions of p in
P76/TMOV. The pins, P75/TMCIV and P74/TMRIV, are also functioning as timer V input ports
that are connected to the timer V regardless of the register setting of port 7.
P76/TMOV
P75/TMCIV
P74/TMRIV
Port 7
Figure 9.4 Port 7 Pin Configuration
Section 9 I/O Ports
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Port 7 has the following registers.
• Port control register 7 (PCR7)
• Port data register 7 (PDR7)
9.4.1 Port Control Register 7 (PCR7 )
PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7.
Bit Bit Name
Initial
Value R/W Description
7 Reserved
6
5
4
PCR76
PCR75
PCR74
0
0
0
W
W
W
Setting a PCR7 bit to 1 makes the corresponding pin an
output port, while clearing the bit to 0 makes the pin an
input port. Note that the TCSRV setting of the timer V
has priority for deciding input/output direction of the
P76/TMOV pin.
3
2
1
0
Reserved
9.4.2 Port Data Register 7 (PDR7)
PDR7 is a general I/O port data register of port 7.
Bit Bit Name
Initial
Value R/W Description
7 1 Reserved
This bit is always read as 1.
6
5
4
P76
P75
P74
0
0
0
R/W
R/W
R/W
PDR7 stores output data for port 7 pins.
PDR7 is read while PCR7 bits are set to 1, the value
stored in PDR7 is read. If PDR7 is read while PCR7 bits
are cleared to 0, the pin states are read regardless of
the value stored in PDR7.
3
2
1
0
1
1
1
1
Reserved
These bits are always read as 1.
Section 9 I/O Ports
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9.4.3 Pin Functions
The correspondence between the register specification and the port functions is shown below.
• P76/TMOV Pin
Register TCSRV PCR7
Bit Name OS3 to OS0 PCR76 Pin Function
Setting Value 0000 0 P76 input pin
1 P76 output pin
Other than
the above
values
X TMOV output pin
[Legend]
X: Don't care.
• P75/TMCIV Pin
Register PCR7
Bit Name PCR75 Pin Function
Setting Value 0 P75 input/TMCIV input pin
1 P75 output/TMCIV input pin
• P74/TMRIV Pin
Register PCR7
Bit Name PCR74 Pin Function
Setting Value 0 P74 input/TMRIV input pin
1 P74 output/TMRIV input pin
Section 9 I/O Ports
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9.5 Port 8
Port 8 is a general I/O port also fu ncti o ni n g as a timer W I/O pin. Each pin of the p ort 8 i s show n
in figure 9.5. The register setting of the timer W has priority for functions of the pins P84 /FTIOD,
P83/FTIOC, P82/FTIOB, and P81/FTIOA. P80/FTCI also functions as a timer W input port that is
connected to the timer W regardless of the register setting of port 8.
P87
P86
P85
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
Port 8
Figure 9.5 Port 8 Pin Configuration
Port 8 has the following registers.
• Port control register 8 (PCR8)
• Port data register 8 (PDR8)
Section 9 I/O Ports
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9.5.1 Port Control Register 8 (PCR8 )
PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PCR87
PCR86
PCR85
PCR84
PCR83
PCR82
PCR81
PCR80
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
When each of the port 8 pins P87 to P80 functions as
an general I/O port, setting a PCR8 bit to 1 makes the
corresponding pin an output port, while clearing the bit
to 0 makes the pin an input port.
9.5.2 Port Data Register 8 (PDR8)
PDR8 is a general I/O port data register of port 8.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
P87
P86
P85
P84
P83
P82
P81
P80
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR8 stores output data for port 8 pins.
PDR8 is read while PCR8 bits are set to 1, the value
stored in PDR8 is read. If PDR8 is read while PCR8
bits are cleared to 0, the pin states are read
regardless of the value stored in PDR8.
Section 9 I/O Ports
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9.5.3 Pin Functions
The correspondence between the register specification and the port functions is shown below.
• P87 Pin
Register PCR8
Bit Name PCR87 Pin Function
Setting Value 0 P87 input pin
1 P87 output pin
• P86 Pin
Register PCR8
Bit Name PCR86 Pin Function
Setting Value 0 P86 input pin
1 P86 output pin
• P85 Pin
Register PCR8
Bit Name PCR85 Pin Function
Setting Value 0 P85 input pin
1 P85 output pin
Section 9 I/O Ports
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• P84/FTIOD Pin
Register TMRW TIOR1 PCR8
Bit Name PWMD IOD2 IOD1 IOD0 PCR84 Pin Function
Setting Value 0 0 0 0 0 P84 input/FTIOD input pin
1 P84 output/FTIOD input pin
0 0 1 X FTIOD output pin
0 1 X X FTIOD output pin
1 X X 0 P84 input/FTIOD input pin
1 P84 output/FTIOD input pin
1 X X X X PWM output pin
[Legend]
X: Don't care.
• P83/FTIOC Pin
Register TMRW TIOR1 PCR8
Bit Name PWMC IOC2 IOC1 IOC0 PCR83 Pin Function
Setting Value 0 0 0 0 0 P83 input/FTIOC input pin
1 P83 output/FTIOC input pin
0 0 1 X FTIOC output pin
0 1 X X FTIOC output pin
1 X X 0 P83 input/FTIOC input pin
1 P83 output/FTIOC input pin
1 X X X X PWM output pin
[Legend]
X: Don't care.
Section 9 I/O Ports
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• P82/FTIOB Pin
Register TMRW TIOR0 PCR8
Bit Name PWMB IOB2 IOB1 IOB0 PCR82 Pin Function
Setting Value 0 0 0 0 0 P82 input/FTIOB input pin
1 P82 output/FTIOB input pin
0 0 1 X FTIOB output pin
0 1 X X FTIOB output pin
1 X X 0 P82 input/FTIOB input pin
1 P82 output/FTIOB input pin
1 X X X X PWM output pin
[Legend]
X: Don't care.
• P81/FTIOA Pin
Register TIOR0 PCR8
Bit Name IOA2 IOA1 IOA0 PCR81 Pin Function
Setting Value 0 0 0 0 P81 input/FTIOA input pin
0 1 P81 output/FTIOA input pin
0 0 1 X FTIOA output pin
0 1 X X FTIOA output pin
1 X X 0 P81 input/FTIOA input pin
1 P81 output/FTIOA input pin
[Legend]
X: Don't care.
• P80/FTCI Pin
Register PCR8
Bit Name PCR80 Pin Function
Setting Value 0 P80 input/FTCI input pin
1 P80 output/FTCI input pin
Section 9 I/O Ports
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9.6 Port B
Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port
B is shown in figure 9.6.
PB7/AN7
PB6/AN6
PB5/AN5
PB4/AN4
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
Port B
Figure 9.6 Port B Pin Configuration
Port B has the following register.
• Port data register B (PDRB)
9.6.1 Port Data Register B (PDRB)
PDRB is a general input-only port data register of port B.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
R
R
R
R
R
R
R
R
The input value of each pin is read by reading this
register.
However, if a port B pin is designated as an analog
input channel by ADCSR in A/D converter, 0 is read.
Section 10 Timer A
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Section 10 Timer A
Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock
time-base function is available when a 32.768kHz crystal oscillator is connected. Figure 10.1
shows a block diag ram of ti mer A.
10.1 Features
• Timer A can be used as an interval timer or a clock time base.
• An interrupt is requested when the counter overflow s.
• Any of eight clock signals can be output from pin TMOW: 32.768 kHz divided by 32, 16, 8, or
4 (1 kHz, 2 kHz, 4 kHz, 8 kHz), or the system clock divided by 32 , 16, 8, or 4.
Interval Timer:
• Choice of eight internal clock sources (φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128, φ/32, φ8)
Clock Time Base:
• Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock
time base (using a 32.768 kHz crystal o scillator).
Section 10 Timer A
Rev. 6.00 Mar. 24, 2006 Page 140 of 412
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φ
W
TMOW
φ
φ
W
/32
φ
W
/16
φ
W
/8
φ
W
/4
φ
W
/32
φ
W
/16
φ
W
/8
φ
W
/4
φ/8192, φ/4096,
φ/2048, φ/512,
φ/256, φ/128,
φ/32, φ/8
φ
W
/128
φ
W
/4
1/4 PSW
PSS
TMA
TCA
IRRTA
÷8*
÷64*
÷128*
÷256*
[Legend]
TMA: Timer mode register A
TCA: Timer counter A
IRRTA: Timer A overflow interrupt request flag
PSW: Prescaler W
PSS: Prescaler S
Note: * Can be selected only when the prescaler W output (øW/128) is used as the TCA input clock.
Internal data bus
Figure 10.1 Block Diagram of Timer A
10.2 Input/Output Pins
Table 10.1 shows the timer A input/output pin.
Table 10.1 Pin Configuration
Name Abbreviation I/O Function
Clock output TMOW Output Output of waveform generated by
timer A output circuit
Section 10 Timer A
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10.3 Register Descriptions
Timer A has the following registers.
• Timer mode register A (TMA)
• Timer counter A (TCA)
10.3.1 Timer Mode Register A (TMA)
TMA selects the operating mode, the divided clock output, and the input clock.
Bit Bit
Name Initial
Value R/W Description
7
6
5
TMA7
TMA6
TMA5
0
0
0
R/W
R/W
R/W
Clock Output Select 7 to 5
These bits select the clock output at the TMOW pin.
000: φ/32
001: φ/16
010: φ/8
011: φ/4
100: φw/32
101: φw/16
110: φw/8
111: φw/4
For details on clock outputs, see section 10.4.3, Clock
Output.
4 1 Reserved
This bit is always read as 1.
3 TMA3 0 R/W Internal Clock Select 3
This bit selects the operating mode of the timer A.
0: Functions as an interval timer to count the outputs of
prescaler S.
1: Functions as a clock-time base to count the outputs
of prescaler W.
Section 10 Timer A
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Bit Bit
Name Initial
Value R/W Description
2
1
0
TMA2
TMA1
TMA0
0
0
0
R/W
R/W
R/W
Internal Clock Select 2 to 0
These bits select the clock input to TCA when TMA3 =
0.
000: φ/8192
001: φ/4096
010: φ/2048
011: φ/512
100: φ/256
101: φ/128
110: φ/32
111: φ/8
These bits select the overflow period when TMA3 = 1
(when a 32.768 kHz crystal oscillator with is used as
φW).
000: 1s
001: 0.5 s
010: 0.25 s
011: 0.03125 s
1XX: Both PSW and TCA are reset
[Legend]
X: Don't care.
10.3.2 Timer Counter A (TCA)
TCA is an 8-bit readable up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in TMA. TCA values can be
read by the CPU in active mode, but cannot be read in subactive mode. When TCA overflows, the
IRRTA bit in interrupt request register 1 (IRR1) is set to 1. TCA is cleared by setting bits TMA 3
and TMA2 in TMA to B’11. TCA is initialized to H'00.
Section 10 Timer A
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10.4 Operation
10.4.1 Interval Timer Operation
When bit TMA3 in TMA is cleared to 0, timer A functions as an 8-bit interval timer.
Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-co unting of timer A
resume immediately as an interval timer. The clock input to timer A is selected by bits TMA2 to
TMA0 in TMA; any of eight inte r nal cloc k si gnal s o ut p ut by prescaler S can be selected.
After the count value in TCA reaches H'FF, the next clock signal input causes timer A to
overflow, setting bit IRRTA to 1 in interrupt Flag Register 1 (IRR1). If IENTA = 1 in interrupt
enable register 1 (IENR1), a CPU interrupt is requested. At overflow, TCA returns to H'00 and
starts counting up again. In this mode timer A functions as an interval timer that generates an
overflow output at intervals of 256 input clock pulses.
10.4.2 Clock Time Base Operation
When bit TMA3 in TMA is set to 1, timer A functions as a clock-timer base by counting clock
signals output by prescaler W. When a clock signal is input after the TCA counter value has
become H'FF, timer A overflows and IRRTA in IRR1 is set to 1. At that time, an interrupt request
is generated to the CPU if IENTA in the interrupt enable register 1 (IENR1) is 1. The overflow
period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available.
In clock time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W
to H'00.
10.4.3 Clock Output
Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin
TMOW. Eight different clock output signals can be selected by means of bits TMA7 to TMA5 in
TMA. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A
32.768 kHz signal di vi ded by 32, 16, 8, or 4 can be output in active mode, sl eep m o de, an d
subactive mode.
Section 10 Timer A
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10.5 Usage Note
When the clock time base function is selected as the internal clock of TCA in active mode or sleep
mode, the internal clock is not synchronous with the system clock, so it is synchronized by a
synchronizing circuit. This may result in a maximum error of 1/φ (s) in the count cycle.
Section 11 Timer V
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Section 11 Timer V
Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Compare-
match signals with two registers can also be used to reset the counter, request an interrupt, or
output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at
the TRGV pin, enabling pulse output control to b e synchronized to the trigger, with an arbitrary
delay from the trigger input. Figure 11.1 shows a block diagram of timer V.
11.1 Features
• Choice of seven clock signals is available.
Choice of six internal clock sources (φ/128, φ/64, φ/32, φ/16, φ/8, φ/4) or an external clock.
• Counter can be cleared by compare match A or B, or by an external reset signal. If the count
stop function is selected, the counter can be halted when cleared.
• Timer output is controlled by two independent compare match signals, enabling pulse output
with an arbitrary duty cycle, PWM output, and other applications.
• Three interrupt sources: compare match A, compare match B, timer overflow
• Counting can be initiated by trigger input at the TRGV pin. The rising edge, falling edge, or
both edges of the TRGV input can be selected.
Section 11 Timer V
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TRGV
TMCIV
TMRIV
TMOV
φ
Trigger
control
Clock select
Clear
control
Output
control
PSS
TCRV1
TCORB
Comparator
TCNTV
Comparator
TCORA
TCRV0
Interrupt
request
control
TCSRV
CMIA
CMIB
OVI
Internal data bus
[Legend]
TCORA: Time constant register A
TCORB: Time constant register B
TCNTV: Timer counter V
TCSRV: Timer control/status register V
TCRV0: Timer control register V0
TCRV1: Timer control register V1
PSS: Prescaler S
CMIA: Compare-match interrupt A
CMIB: Compare-match interrupt B
OVI: Overflow interupt
Figure 11.1 Block Diagram of Timer V
Section 11 Timer V
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11.2 Input/Output Pins
Table 11.1 shows the timer V pin configuration.
Table 11.1 Pin Configuration
Name Abbreviation I/O Function
Timer V output TMOV Output Timer V waveform output
Timer V clock input TMCIV Input Clock input to TCNTV
Timer V reset input TMRIV Input External input to reset TCNTV
Trigger input TRGV Input Trigger input to initiate counting
11.3 Register Descriptions
Time V has the following registers.
• Timer counter V (TCNTV)
• Timer constant register A (TCORA)
• Timer constant register B (TCORB)
• Timer control register V0 (TCRV0)
• Timer control/status register V (TCSRV)
• Timer control register V1 (TCRV1)
11.3.1 Timer Counter V (TCNTV)
TCNTV is an 8-bit up-counter. The clock source is selected by bits CKS2 to CKS0 in timer
control register V0 (TCR V 0) . The TCNTV value can be read and written by the CPU at any time.
TCNTV can be cleared by an external reset input signal, or by compare match A or B. The
clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0.
When TCNTV overflow s, OVF is set to 1 in timer control/status register V (TCSRV).
TCNTV is initialized to H'00 .
Section 11 Timer V
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11.3.2 Time Constant Registers A and B (TCORA, TCORB)
TCORA and TCORB have the same function.
TCORA and TCORB are 8-bit read/write registers.
TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents ma tch,
CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested.
Note that they must not be compared during the T3 state of a TCORA write cycle.
Timer output from the TMOV pin can be controlled by the identifying signal (compare match A)
and the settings of bits OS3 to OS0 in TCSRV.
TCORA and TCORB are initialized to H'FF.
11.3.3 Timer Control Register V0 (TCRV0)
TCRV0 selects the input clock signals of TCNTV, specifies the clearing con ditions of TCNTV,
and controls each interrupt request.
Bit Bit Name
Initial
Value R/W Description
7 CMIEB 0 R/W Compare Match Interrupt Enable B
When this bit is set to 1, interrupt request from the
CMFB bit in TCSRV is enabled.
6 CMIEA 0 R/W Compare Match Interrupt Enable A
When this bit is set to 1, interrupt request from the
CMFA bit in TCSRV is enabled.
5 OVIE 0 R/W Timer Overflow Interrupt Enable
When this bit is set to 1, interrupt request from the OVF
bit in TCSRV is enabled.
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Bit Bit Name
Initial
Value R/W Description
4
3
CCLR1
CCLR0
0
0
R/W
R/W
Counter Clear 1 and 0
These bits specify the clearing conditions of TCNTV.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared on the rising edge of the TMRIV pin. The
operation of TCNTV after clearing depends on
TRGE in TCRV1.
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
These bits select clock signals to input to TCNTV and
the counting condition in combination with ICKS0 in
TCRV1.
Refer to table 11.2.
Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions
TCRV0 TCRV1
Bit 2 Bit 1 Bit 0 Bit 0
CKS2 CKS1 CKS0 ICKS0 Description
0 0 0 Clock input prohibited
1 0 Internal clock: counts on φ/4, falling edge
1 Internal clock: counts on φ/8, falling edge
1 0 0 Internal clock: counts on φ/16, falling edge
1 Internal clock: counts on φ/32, falling edge
1 0 Internal clock: counts on φ/64, falling edge
1 Internal clock: counts on φ/128, falling edge
1 0 0 Clock input prohibited
1 External clock: counts on rising edge
1 0 External clock: counts on falling edge
1 External clock: counts on rising and falling
edge
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11.3.4 Timer Control/Status Register V (TCSRV)
TCSRV indicates the status flag and controls outputs by using a compare match.
Bit Bit Name
Initial
Value R/W Description
7 CMFB 0 R/W Compare Match Flag B
Setting condition:
When the TCNTV value matches the TCORB value
Clearing condition:
After reading CMFB = 1, cleared by writing 0 to CMFB
6 CMFA 0 R/W Compare Match Flag A
Setting condition:
When the TCNTV value matches the TCORA value
Clearing condition:
After reading CMFA = 1, cleared by writing 0 to CMFA
5 OVF 0 R/W Timer Overflow Flag
Setting condition:
When TCNTV overflows from H'FF to H'00
Clearing condition:
After reading OVF = 1, cleared by writing 0 to OVF
4 1 Reserved
This bit is always read as 1.
3
2
OS3
OS2
0
0
R/W
R/W
Output Select 3 and 2
These bits select an output method for the TMOV pin
by the compare match of TCORB and TCNTV.
00: No change
01: 0 output
10: 1 output
11: Output toggles
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Bit Bit Name
Initial
Value R/W Description
1
0
OS1
OS0
0
0
R/W
R/W
Output Select 1 and 0
These bits select an output method for the TMOV pin
by the compare match of TCORA and TCNTV.
00: No change
01: 0 output
10: 1 output
11: Output toggles
OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level
for compare match A. The two output levels can be controlled independently. After a reset, the
timer output is 0 until the first compare match.
11.3.5 Timer Control Register V1 (TCRV1)
TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to
TCNTV.
Bit Bit Name
Initial
Value R/W Description
7 to 5 All 1 Reserved
These bits are always read as 1.
4
3
TVEG1
TVEG0
0
0
R/W
R/W
TRGV Input Edge Select
These bits select the TRGV input edge.
00: TRGV trigger input is prohibited
01: Rising edge is selected
10: Falling edge is selected
11: Rising and falling edges are both selected
2 TRGE 0 R/W TCNTV starts counting up by the input of the edge
which is selected by TVEG1 and TVEG0.
0: Disables starting counting-up TCNTV by the input of
the TRGV pin and halting counting-up TCNTV when
TCNTV is cleared by a compare match.
1: Enables starting counting-up TCNTV by the input of
the TRGV pin and halting counting-up TCNTV when
TCNTV is cleared by a compare match.
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Bit Bit Name
Initial
Value R/W Description
1 1 Reserved
This bit is always read as 1.
0 ICKS0 0 R/W Internal Clock Select 0
This bit selects clock signals to input to TCNTV in
combination with CKS2 to CKS0 in TCRV0.
Refer to table 11.2.
11.4 Operation
11.4.1 Timer V Operation
1. According to table 11.2, six internal/external clock signals output by prescaler S can be
selected as the timer V operating clock signals. When the operating clock signal is selected,
TCNTV starts counting-up. Figure 11.2 shows the count timing with an internal clock signal
selected, and figure 11.3 shows the count timing with both edges of an external clock signal
selected.
2. When TCNTV overflows (changes from H'FF to H'00), the overflow flag (OVF) in TCRV0
will be set. The timing at this time is shown in figure 11.4. An interrupt request is sent to the
CPU when OVIE in TCRV0 is 1.
3. TCNTV is constantly compared with TCORA and TCORB. Compar e match flag A or B
(CMFA or CMFB) is set to 1 when TCNTV matches TC ORA or TCORB, respectively. The
compare-match signal is generated in the last state in which the values match. Figure 11.5
shows the timing. An interrupt request is generated for the CPU when CMIEA or CMIEB in
TCRV0 is 1.
4. When a compare match A or B is generated, the TMOV responds with the output value
selected by bits OS3 to OS0 in TCSRV. Figure 11.6 shows the timing when the output is
toggled by compare match A.
5. When CCLR1 or CCLR0 in TCRV0 is 01 or 10, TCNTV can be cleared by the corresponding
compare match. Figure 11.7 shows the timing.
6. When CCLR1 or CCLR0 in TCRV0 is 11, TCNTV can be cleared by the rising edge of the
input of TMRIV pin. A TMRIV input pulse-width of at least 1.5 system clocks is necessary.
Figure 11.8 shows the timing.
7. When a counter-clearing source is generated with TRGE in TCRV1 set to 1, the counting-up is
halted as soon as TCNTV is cleared. TCNTV resumes counting-up when the edge selected by
TVEG1 or TVEG0 in TCRV1 is inpu t from the TGRV pin.
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N – 1 N + 1N
φ
Internal clock
TCNTV input
clock
TCNTV
Figure 11.2 Increment Timing with Internal Clock
N – 1 N + 1N
φ
TMCIV
(External clock
input pin)
TCNTV input
clock
TCNTV
Figure 11.3 Increment Timing with External Clock
H'FF H'00
φ
TCNTV
Overflow signal
OVF
Figure 11.4 OVF Set Timing
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N
N
N+1
φ
TCNTV
TCORA or
TCORB
Compare match
signal
CMFA or
CMFB
Figure 11.5 CMFA and CMFB Set Timing
φ
Compare match
A signal
Timer V output
pin
Figure 11.6 TMOV Output Timing
N H'00
φ
Compare match
A signal
TCNTV
Figure 11.7 Clear Timing by Compare Match
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φ
TMRIV(External
counter reset
input pin )
TCNTV reset
signal
TCNTV N – 1 N H'00
Figure 11.8 Clear Timing by TMRIV Input
11.5 Timer V Application Examples
11.5.1 Pulse Output with Arbitrary Duty Cycle
Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle.
1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with
TCORA.
2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at co mpare match with TCORA
and to 0 at compare match with TCORB.
3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
4. With these settings, a waveform is output without further software intervention, with a period
determined by TCORA and a pulse width determined by TCORB.
Counter cleared
Time
TCNTV value
H'FF
TCORA
TCORB
H'00
TMOV
Figure 11.9 Pulse Output Example
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11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input
The trigger function can be used to output a pulse with an ar bitrary pulse width at an arbitrary
delay from the TRGV input, as shown in figure 11.10. To set up this output:
1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with
TCORB.
2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA
and to 0 at compare match with TCORB.
3. Set bits TVEG1 and TV EG0 in TCRV1 and set TRGE to select the falling edge of the TRGV
input.
4. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
5. After these setting s, a pulse wave form will be output without further software intervention,
with a delay determined by TCORA from the TRGV input, and a pulse width determined by
(TCORB – TCORA).
Counter cleared
H'FF
TCORA
TCORB
H'00
TRGV
TMOV
Compare match A
Compare match B
clears TCNTV and
halts count-up
Compare match B
clears TCNTV and
halts count-up
Compare match A
TCNTV value
Time
Figure 11.10 Example of Pulse Output Synchronized to TRGV Input
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11.6 Usage Notes
The following types of contention or operation can occur in timer V operation.
1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear
signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing
takes precedence and the write to the counter is not carried out. If counting-up is generated in
the T3 state of a TCNTV write cycle, writing takes precedence.
2. If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write
to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure
11.12 shows the timing.
3. If compare matches A and B occur simultaneously, any conflict between the output selections
for co mpare match A and compare ma tch B is resolved by the following priority: toggle
output > output 1 > output 0.
4. Depending on the timing, TCNTV may be incremented by a switch between different internal
clock sources. When TCNTV is internally clocked, an increment pulse is generated from the
falling edge of an internal clock signal, that is divided system clock ( φ). Therefore, as shown
in figure 11.3 the switch is from a high clock signal to a low clock signal, the switchover is
seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a
switch between internal and external clocks.
φ
Address TCNTV address
TCNTV write cycle by CPU
Internal
write signal
Counter clear
signal
TCNTV N H'00
T1T2T3
Figure 11.11 Contention between TCNTV Write and Clear
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φ
Address TCORA address
Internal
write signal
TCNTV
TCORA
N
N
N+1
M
TCORA write data
Inhibited
T
1
T
2
T
3
TCORA write cycle by CPU
Compare match
signal
Figure 11.12 Contention between TCORA Write and Compare Match
Clock before
switching
Clock after
switching
Count clock
TCNTV N N+1 N+2
Write to CKS1 and CKS0
Figure 11.13 Internal Clock Switching and TCNTV Operation
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Section 12 Timer W
The timer W has a 16-bit timer having output compare and input capture functions. The timer W
can count external events and output pulses with an arbitrary duty c ycle by compare match
between the timer counter and four general registers. Thus, it can be applied to various systems.
12.1 Features
• Selection of five counter clock sources: four internal clocks (φ, φ/2, φ/4, and φ/8) and an
external clock (external events can be counted)
• Capability to process up to four pulse outputs or four pulse inputs
• Four general registers:
Independently assignable output compare or input capture functions
Usable as two pairs of registers; one register of each pair operates as a buffer for the output
compare or input capture register
• Four selectable operating modes :
Waveform output by compare match
Selection of 0 output, 1 output, or toggle output
Input capture function
Rising edge, falling edge, or both edges
Counter clearing function
Counters can be cleared by compare match
PWM mode
Up to three-phase PWM output can be provided with desired duty ratio.
• Any initial timer output value can be set
• Five interrupt sources
Four compare match/input capture interrupts and an overflow interrupt.
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Table 12.1 summarizes the timer W functions, and figure 12.1 shows a block diagram of the timer
W.
Table 12.1 Timer W Functions
Input/Output Pins
Item Counter FTIOA FTIOB FTIOC FTIOD
Count clock Internal clocks: φ, φ/2, φ/4, φ/8
External clock: FTCI
General registers
(output compare/input
capture registers)
Period
specified in
GRA
GRA GRB GRC (buffer
register for
GRA in
buffer mode)
GRD (buffer
register for
GRB in
buffer mode)
Counter clearing function GRA
compare
match
GRA
compare
match
— — —
Initial output value
setting function
— Yes Yes Yes Yes
Buffer function — Yes Yes — —
Compare 0 — Yes Yes Yes Yes
match output 1 — Yes Yes Yes Yes
Toggle — Yes Yes Yes Yes
Input capture function — Yes Yes Yes Yes
PWM mode — — Yes Yes
Yes
Interrupt sources Overflow Compare
match/input
capture
Compare
match/input
capture
Compare
match/input
capture
Compare
match/input
capture
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Internal clock:
External clock: FTCI
FTIOA
FTIOB
FTIOC
FTIOD
IRRTW
Control logic
Clock
selector
Comparator
TCNT
Internal
data bus
Bus interface
[Legend]
TMRW: Timer mode register W (8 bits)
TCRW: Timer control register W (8 bits)
TIERW: Timer interrupt enable register W (8 bits)
TSRW: Timer status register W (8 bits)
TIOR: Timer I/O control register (8 bits)
TCNT: Timer counter (16 bits)
GRA: General register A (input capture/output compare register: 16 bits)
GRB: General register B (input capture/output compare register: 16 bits)
GRC: General register C (input capture/output compare register: 16 bits)
GRD: General register D (input capture/output compare register: 16 bits)
IRRTW: Timer W interrupt request
GRA
GRB
GRC
GRD
TMRW
TCRW
TIERW
TSRW
TIOR
φ
φ/2
φ/4
φ/8
Figure 12.1 Timer W Block Diagram
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12.2 Input/Output Pins
Table 12.2 summarizes the timer W pins.
Table 12.2 Pin Configuration
Name Abbreviation Input/Output Function
External clock input FTCI Input External clock input pin
Input capture/output
compare A
FTIOA Input/output Output pin for GRA output compare
or input pin for GRA input capture
Input capture/output
compare B
FTIOB Input/output Output pin for GRB output compare,
input pin for GRB input capture, or
PWM output pin in PWM mode
Input capture/output
compare C
FTIOC Input/output Output pin for GRC output compare,
input pin for GRC input capture, or
PWM output pin in PWM mode
Input capture/output
compare D
FTIOD Input/output Output pin for GRD output compare,
input pin for GRD input capture, or
PWM output pin in PWM mode
12.3 Register Descriptions
The timer W has the following registers.
• Timer mode register W (TMRW)
• Timer control register W (TCRW)
• Timer interrupt enable register W (TIERW)
• Timer status register W (TSRW)
• Timer I/O control register 0 (TIOR0)
• Timer I/O control register 1 (TIOR1)
• Timer counter (TCNT)
• General register A (GRA)
• General register B (GRB)
• General register C (GRC)
• General register D (GRD)
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12.3.1 Timer Mode Register W (TMRW)
TMRW selects the general register functions and the timer output mode.
Bit Bit Name
Initial
Value R/W Description
7 CTS 0 R/W Counter Start
The counter operation is halted when this bit is 0, while
it can be performed when this bit is 1.
6 1 Reserved
This bit is always read as 1.
5 BUFEB 0 R/W Buffer Operation B
Selects the GRD function.
0: GRD operates as an input capture/output compare
register
1: GRD operates as the buffer register for GRB
4 BUFEA 0 R/W Buffer Operation A
Selects the GRC function.
0: GRC operates as an input capture/output compare
register
1: GRC operates as the buffer register for GRA
3 1 Reserved
This bit is always read as 1.
2 PWMD 0 R/W PWM Mode D
Selects the output mode of the FTIOD pin.
0: FTIOD operates normally (output compare output)
1: PWM output
1 PWMC 0 R/W PWM Mode C
Selects the output mode of the FTIOC pin.
0: FTIOC operates normally (output compare output)
1: PWM output
0 PWMB 0 R/W PWM Mode B
Selects the output mode of the FTIOB pin.
0: FTIOB operates normally (output compare output)
1: PWM output
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12.3.2 Timer Control Register W (TCRW)
TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer
output levels.
Bit Bit Name
Initial
Value R/W Description
7 CCLR 0 R/W Counter Clear
The TCNT value is cleared by compare match A when
this bit is 1. When it is 0, TCNT operates as a free-
running counter.
6
5
4
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
Select the TCNT clock source.
000: Internal clock: counts on φ
001: Internal clock: counts on φ/2
010: Internal clock: counts on φ/4
011: Internal clock: counts on φ/8
1XX: Counts on rising edges of the external event (FTCI)
When the internal clock source (φ) is selected, subclock
sources are counted in subactive and subsleep modes.
3 TOD 0 R/W Timer Output Level Setting D
Sets the output value of the FTIOD pin until the first
compare match D is generated.
0: Output value is 0*
1: Output value is 1*
2 TOC 0 R/W Timer Output Level Setting C
Sets the output value of the FTIOC pin until the first
compare match C is generated.
0: Output value is 0*
1: Output value is 1*
1 TOB 0 R/W Timer Output Level Setting B
Sets the output value of the FTIOB pin until the first
compare match B is generated.
0: Output value is 0*
1: Output value is 1*
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Bit Bit Name
Initial
Value R/W Description
0 TOA 0 R/W Timer Output Level Setting A
Sets the output value of the FTIOA pin until the first
compare match A is generated.
0: Output value is 0*
1: Output value is 1*
[Legend]
X: Don't care.
Note: * The change of the setting is immediately reflected in the output value.
12.3.3 Timer Interrupt Enable Register W (TIERW)
TIERW controls the timer W interrupt request.
Bit Bit Name
Initial
Value R/W Description
7 OVIE 0 R/W Timer Overflow Interrupt Enable
When this bit is set to 1, FOVI interrupt requested by
OVF flag in TSRW is enabled.
6
5
4
1
1
1
Reserved
These bits are always read as 1.
3 IMIED 0 R/W Input Capture/Compare Match Interrupt Enable D
When this bit is set to 1, IMID interrupt requested by
IMFD flag in TSRW is enabled.
2 IMIEC 0 R/W Input Capture/Compare Match Interrupt Enable C
When this bit is set to 1, IMIC interrupt requested by
IMFC flag in TSRW is enabled.
1 IMIEB 0 R/W Input Capture/Compare Match Interrupt Enable B
When this bit is set to 1, IMIB interrupt requested by
IMFB flag in TSRW is enabled.
0 IMIEA 0 R/W Input Capture/Compare Match Interrupt Enable A
When this bit is set to 1, IMIA interrupt requested by
IMFA flag in TSRW is enabled.
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12.3.4 Timer Status Register W (TSRW)
TSRW shows the status of interrupt requests.
Bit Bit Name
Initial
Value R/W Description
7 OVF 0 R/W Timer Overflow Flag
[Setting condition]
When TCNT overflows from H'FFFF to H'0000
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
6
5
4
1
1
1
Reserved
These bits are always read as 1.
3 IMFD 0 R/W Input Capture/Compare Match Flag D
[Setting conditions]
• TCNT = GRD when GRD functions as an output
compare register
• The TCNT value is transferred to GRD by an input
capture signal when GRD functions as an input
capture register
[Clearing condition]
Read IMFD when IMFD = 1, then write 0 in IMFD
2 IMFC 0 R/W Input Capture/Compare Match Flag C
[Setting conditions]
• TCNT = GRC when GRC functions as an output
compare register
• The TCNT value is transferred to GRC by an input
capture signal when GRC functions as an input
capture register
[Clearing condition]
Read IMFC when IMFC = 1, then write 0 in IMFC
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Bit Bit Name
Initial
Value R/W Description
1 IMFB 0 R/W Input Capture/Compare Match Flag B
[Setting conditions]
• TCNT = GRB when GRB functions as an output
compare register
• The TCNT value is transferred to GRB by an input
capture signal when GRB functions as an input
capture register
[Clearing condition]
Read IMFB when IMFB = 1, then write 0 in IMFB
0 IMFA 0 R/W Input Capture/Compare Match Flag A
[Setting conditions]
• TCNT = GRA when GRA functions as an output
compare register
• The TCNT value is transferred to GRA by an input
capture signal when GRA functions as an input
capture register
[Clearing condition]
Read IMFA when IMFA = 1, then write 0 in IMFA
12.3.5 Timer I/O Control Register 0 (TIOR0)
TIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and
FTIOB pins.
Bit Bit Name
Initial
Value R/W Description
7 1 Reserved
This bit is always read as 1.
6 IOB2 0 R/W I/O Control B2
Selects the GRB function.
0: GRB functions as an output compare register
1: GRB functions as an input capture register
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Bit Bit Name
Initial
Value R/W Description
5
4
IOB1
IOB0
0
0
R/W
R/W
I/O Control B1 and B0
When IOB2 = 0,
00: No output at compare match
01: 0 output to the FTIOB pin at GRB compare match
10: 1 output to the FTIOB pin at GRB compare match
11: Output toggles to the FTIOB pin at GRB compare
match
When IOB2 = 1,
00: Input capture at rising edge at the FTIOB pin
01: Input capture at falling edge at the FTIOB pin
1X: Input capture at rising and falling edges of the
FTIOB pin
3 1 Reserved
This bit is always read as 1.
2 IOA2 0 R/W I/O Control A2
Selects the GRA function.
0: GRA functions as an output compare register
1: GRA functions as an input capture register
1
0
IOA1
IOA0
0
0
R/W
R/W
I/O Control A1 and A0
When IOA2 = 0,
00: No output at compare match
01: 0 output to the FTIOA pin at GRA compare match
10: 1 output to the FTIOA pin at GRA compare match
11: Output toggles to the FTIOA pin at GRA compare
match
When IOA2 = 1,
00: Input capture at rising edge of the FTIOA pin
01: Input capture at falling edge of the FTIOA pin
1X: Input capture at rising and falling edges of the
FTIOA pin
[Legend]
X: Don't care.
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12.3.6 Timer I/O Control Register 1 (TIOR1)
TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and
FTIOD pins.
Bit Bit Name
Initial
Value R/W Description
7 1 Reserved
This bit is always read as 1.
6 IOD2 0 R/W I/O Control D2
Selects the GRD function.
0: GRD functions as an output compare register
1: GRD functions as an input capture register
5
4
IOD1
IOD0
0
0
R/W
R/W
I/O Control D1 and D0
When IOD2 = 0,
00: No output at compare match
01: 0 output to the FTIOD pin at GRD compare match
10: 1 output to the FTIOD pin at GRD compare match
11: Output toggles to the FTIOD pin at GRD compare
match
When IOD2 = 1,
00: Input capture at rising edge at the FTIOD pin
01: Input capture at falling edge at the FTIOD pin
1X: Input capture at rising and falling edges at the
FTIOD pin
3 1 Reserved
This bit is always read as 1.
2 IOC2 0 R/W I/O Control C2
Selects the GRC function.
0: GRC functions as an output compare register
1: GRC functions as an input capture register
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Bit Bit Name
Initial
Value R/W Description
1
0
IOC1
IOC0
0
0
R/W
R/W
I/O Control C1 and C0
When IOC2 = 0,
00: No output at compare match
01: 0 output to the FTIOC pin at GRC compare match
10: 1 output to the FTIOC pin at GRC compare match
11: Output toggles to the FTIOC pin at GRC compare
match
When IOC2 = 1,
00: Input capture to GRC at rising edge of the FTIOC
pin
01: Input capture to GRC at falling edge of the FTIOC
pin
1X: Input capture to GRC at rising and falling edges of
the FTIOC pin
[Legend]
X: Don't care.
12.3.7 Timer Counter (TCNT)
TCNT is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS2 to
CKS0 in TCRW. TCNT can be cleared to H'0000 through a compare match with GRA by setting
the CCLR in TCRW to 1. When TCNT overflows (changes from H'FFFF to H'0000), the OVF
flag in TSRW is set to 1. If OVIE in TIERW is set to 1 at this time, an interrupt request is
generated. TCNT must always be read or written in 16-bit units; 8-bit access is not allowed.
TCNT is initialized to H'0000 by a reset.
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12.3.8 General Registers A to D (GRA to GRD)
Each general register is a 16-bit readable/writable register that can function as either an output-
compare register or an input-capture register. The function is selected by settings in TIOR0 and
TIOR1.
When a general register is used as an input-compare register, its value is constantly compared with
the TCNT value. When the two values match (a compare match), the corresponding flag (IMF A,
IMFB, IMFC, or IMFD) in TSRW is set to 1. An interrupt request is generated at this time, when
IMIEA, IMIEB, IMIEC, or IMIED is set to 1. Compare match output can be selected in TIOR.
When a general register is used as an input-capture register, an external input-capture signal is
detected and the current TCNT value is stored in the general register. The corresponding flag
(IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1. If the corres po n di n g i nt e rr upt-enable bit
(IMIEA, IMIEB, IMIEC, or IMIED) in TSRW is set to 1 at this time, an interrupt request is
generated. The edge of the input-capture signal is selected in TIOR.
GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA
and BUFEB in TMRW.
For example, when GRA is set as an output-compare register and GRC is set as the buffer register
for GRA, the value in the buffer register GRC is sent to GRA w henever compare match A is
generated.
When GRA is set as an input-capture register and GRC is set as the buffer register for GRA, the
value in TCNT is transferred to GRA and the value in the buffer register GRC is transferred to
GRA whenever an input capture is generated.
GRA to GRD must be written or read in 16-bit units; 8-bit access is not allowed. GRA to GRD are
initialized to H'FFFF by a reset.
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12.4 Operation
The timer W has the following operating modes.
• Normal Operation
• PWM Operation
12.4.1 Normal Operation
TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a free-
running counter. When the CTS bit in TMRW is set to 1, TCNT starts in crementing the count.
When the count overflows from H'FFFF to H'0000, the OV F flag in TSRW is set to 1. If the OVIE
in TIERW is set to 1, an interrup t request is generated. Figure 12.2 shows free-running co unting.
TCNT value
H'FFFF
H'0000
CTS bit
OVF
Time
Flag cleared
by software
Figure 12.2 Free-Running Counter Operation
Periodic counting operation can be pe rformed when GRA is set as an output compare register and
bit CCLR in TCRW is set to 1. When the cou nt matches GRA, TCNT is cleared to H'0000, the
IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt
request is generated. TCNT continues countin g from H'0000. Figure 12.3 show s periodic
counting.
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TCNT value
GRA
H'0000
CTS bit
IMFA
Time
Flag cleared
by software
Figure 12.3 Periodic Counter Operation
By setting a general register as an output compare register, compare match A, B, C, or D can
cause the output at the FTIOA, FTIOB, FTIOC, or FTIOD pin to output 0, output 1, or toggle.
Figure 12.4 sho ws an example of 0 and 1 output when TCNT operates as a free-running counter, 1
output is selected for compare match A, and 0 output is selected for compare match B. When
signal is already at the selected output level, the signal level does not change at compare match.
TCNT value
H'FFFF
H'0000
FTIOA
FTIOB
Time
GRA
GRB
No change No change
No change No change
Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)
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Figure 12.5 sho ws an example of toggle output when TCNT operates as a free-running counter,
and toggle output is selected for both compare match A and B.
TCNT value
H'FFFF
H'0000
FTIOA
FTIOB
Time
GRA
GRB
Toggle output
Toggle output
Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1)
Figure 12.6 shows another example of toggle output when TCNT operates as a periodic counter,
cleared by compare match A. Toggle o utp ut i s selected for both compare match A a nd B .
TCNT value
H'FFFF
H'0000
FTIOA
FTIOB
Time
GRA
GRB
Toggle
output
Toggle
output
Counter cleared by compare match with GRA
Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1)
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The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a
signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can
take place on the rising edge, falling edge, or both edges. By using the input-capture function, the
pulse width and periods can be measured. Figure 12.7 shows an example of input capture when
both edges of FTIOA and the fallin g edge of FTIOB are selected as capture edges. TCN T operates
as a free-running counter.
TCNT value
H'FFFF
H'1000
H'0000
FTIOA
GRA
Time
H'AA55
H'55AA
H'F000
H'1000 H'F000 H'55AA
GRB H'AA55
FTIOB
Figure 12.7 Input Capture Operating Example
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Figure 12.8 shows an example of buffer operation when the GRA is set as an input-capture
register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter,
and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation,
the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA.
TCNT value
H'DA91
H'0245
H'0000
GRC
Time
H'0245
FTIOA
GRA H'5480H'0245
H'FFFF
H'5480
H'5480
H'DA91
Figure 12.8 Buffer Operation Example (Input Capture)
12.4.2 PWM Operation
In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB,
GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and
FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register
functions as an output compare register automatically. The output level of each pin depends on the
corresponding timer output level set bit (TOB, TOC, and TOD) in TCRW. When TOB is 1, the
FTIOB output goes to 1 at compare match A and to 0 at compare match B. When TOB is 0, the
FTIOB output goes to 0 at compare match A and to 1 at compare match B. Thus the compare
match output level settings in TIOR0 and TIOR1 are ignored for the output pin set to PWM mode.
If the same value is set in the cycle register and the duty register, the output does not change when
a compare match occurs.
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Figure 12.9 shows an example of operation in PWM mode. The output signals go to 1 and TCNT
is cleared at compare match A, and the output signals go to 0 at compare match B, C, and D
(TOB, TOC, and TOD = 1: initial output values are set to 1).
TCNT value
GRA
GRB
GRC
H'0000
FTIOB
FTIOC
FTIOD
Time
GRD
Counter cleared by compare match A
Figure 12.9 PWM Mode Example (1)
Figure 12.10 shows another example of operation in PWM mode. The output signals go to 0 and
TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and
D (TOB, TOC, and TOD = 0: initial output values are set to 1).
TCNT value
GRA
GRB
GRC
H'0000
FTIOB
FTIOC
FTIOD
Time
GRD
Counter cleared by compare match A
Figure 12.10 PWM Mode Example (2)
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Figure 12.11 sh ows an example of buffer operation when the FTIOB pin is set to PWM mode and
GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB
outputs 1 at compare match B and 0 at compare match A.
Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD
is transferred to GRB whenever compare match B occurs. This procedure is repeated every time
compare match B occurs.
TCNT value
GRA
H'0000
GRD
Time
GRB
H'0200 H'0520
FTIOB
H'0200
H'0450 H'0520
H'0450
GRB H'0450 H'0520
H'0200
Figure 12.11 Buffer Operation Example (Output Compare)
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Figures 12.12 and 12.13 show examples of the output of PWM waveforms with duty cycles of 0%
and 100%.
TCNT value
GRA
H'0000
FTIOB
Time
GRB
Duty 0%
Write to GRB
Write to GRB
TCNT value
GRA
H'0000
FTIOB
Time
GRB
Duty 100%
Write to GRB
Write to GRB
Output does not change when cycle register
and duty register compare matches occur
simultaneously.
TCNT value
GRA
H'0000
FTIOB
Time
GRB
Duty 100%
Write to GRB
Write to GRB
Write to GRB
Output does not change when cycle register
and duty register compare matches occur
simultaneously.
Duty 0%
Write to GRB
Figure 12.12 PWM Mode Example
(TOB, TOC, and TOD = 0: initial output values are set to 0)
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TCNT value
GRA
H'0000
FTIOB
Time
GRB
Duty 100%
Write to GRB
TCNT value
GRA
H'0000
FTIOB
Time
GRB
Duty 0%
Write to GRB
Write to GRB
Output does not change when cycle register
and duty register compare matches occur
simultaneously.
TCNT value
GRA
H'0000
FTIOB
Time
GRB
Duty 0%
Write to GRB
Write to GRB
Output does not change when cycle register
and duty register compare matches occur
simultaneously.
Duty 100%
Write to GRB
Write to GRB
Write to GRB
Figure 12.13 PWM Mode Example
(TOB, TOC, and TOD = 1: initial output values are set to 1)
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12.5 Operation Timing
12.5.1 TCNT Count Timing
Figure 12.14 show s the TCNT count timing when the internal clock source is selected. Figure
12.15 shows the timing when the external clock source is selected. The pulse width of the external
clock signal must be at least two system clock (φ) cycles; shorter pulses will not be counted
correctly.
TCNT
TCNT input
clock
Internal
clock
φ
NN+1 N+2
Rising edge
Figure 12.14 Count Timing for Internal Clock Source
TCNT
TCNT input
clock
External
clock
φ
NN+1N+2
Rising edge Rising edge
Figure 12.15 Count Timing for External Clock Source
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12.5.2 Output Compare Output Timing
The compare match signal is generated in the last state in which TCNT and GR match (when
TCNT changes from the matching value to the next value). When the compare match signal is
generated, the output value selected in TIOR is output at the compare match output pin (FTIOA,
FTIOB, FTIOC, or FTIOD).
When TCNT matches GR, the compare match signal is generated only after the next counter clock
pulse is input.
Figure 12.16 sh ows the output compare timing.
GRA to GRD
TCNT
TCNT input
clock
φ
N
NN+1
Compare
match signal
FTIOA to FTIOD
Figure 12.16 Output Compare Output Timing
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12.5.3 Input Capture Timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR0 and TIOR1. Figure 12.17 shows the timing when the falling edge is selected. The pulse
width of the input capture signal must be at least two system clock (φ) cycles; shorter pulses will
not be detected correctly.
TCNT
Input capture
input
φ
N–1 N N+1 N+2
N
GRA to GRD
Input capture
signal
Figure 12.17 Input Capture Input Signal Timing
12.5.4 Timing of Counter Clearing by Compare Match
Figure 12.18 sh ows the timing when th e counter is cleared by compare match A. When the GRA
value is N, the counter coun ts from 0 to N, and its cycle is N + 1.
TCNT
Compare
match signal
φ
GRA N
N H'0000
Figure 12.18 Timing of Counter Clearing by Compare Match
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12.5.5 Buffer Operation Timing
Figures 12.19 and 12.20 show the buffer operation timing.
GRC, GRD
Compare
match signal
TCNT
φ
GRA, GRB
NN+1
M
M
Figure 12.19 Buffer Operation Timing (Compare Match)
GRA, GRB
TCNT
Input capture
signal
φ
GRC, GRD
N
M
MN+1
N
NN+1
Figure 12.20 Buffer Operation Timing (Input Capture)
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12.5.6 Timing of IMFA to IMFD Fl ag Setti n g a t Compare Match
If a gener al register (GRA, GRB, GRC, or GRD) is used as an output compare register, th e
correspondin g IMFA, IMFB, IMFC, or IMF D fl ag is set to 1 when TC NT matches the general
register.
The compare match signal is generated in the last state in which the values match (when TCNT is
updated from the matching count to the next count). Therefore, when TCNT matches a general
register, the compare match signal is generated only after the next TCNT clock pulse is input.
Figure 12.21 sh ows the timing of the IMFA to IMFD flag setting at compare match.
GRA to GRD
TCNT
TCNT input
clock
φ
N
NN+1
Compare
match signal
IMFA to IMFD
IRRTW
Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match
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12.5.7 Timing of IMFA to IMFD Setting at Input Captu re
If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the
corresponding IM FA, IM FB, IM FC, or IMF D flag is set to 1 when an input capture occu r s. Fi gure
12.22 shows the timing of the IMFA to IMFD flag setting at input capture.
GRA to GRD
TCNT
Input capture
signal
φ
N
N
IMFA to IMFD
IRRTW
Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture
12.5.8 Timing of Status Flag Clearing
When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag
is cleared. Figure 12.23 shows the status flag clearing timing.
IMFA to IMFD
Write signal
Address
φ
TSRW address
IRRTW
TSRW write cycle
T1 T2
Figure 12.23 Timing of Status Flag Clearing by CPU
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12.6 Usage Notes
The following types of contention or operation can occur in timer W operation.
1. The pulse width of the input clock signal and the input capture signal must be at least two
system clock (φ) cycles; shorter pulses will not be detected correctly.
2. Writing to registers is performed in the T2 state of a TCNT write cycle.
If counter clear signal occurs in the T2 state of a TCNT write cycle, clearing of the counter
takes priority and the write is not performed, as shown in figure 12.24. If counting-up is
generated in the TCNT write cycle to contend with the TCNT counting-up, writing takes
precedence.
3. Depending on t he timi ng , TC NT may be inc remented by a switch between differe nt internal
clock sources. When TCNT is internally clocked, an increment pulse is generated from the
rising edge of an internal clock signal, that is divided system clock (φ). Therefore, as shown in
figure 12.25 the switch is fr om a low clock signal to a high clock signal, the switchover is seen
as a rising edge, causing TCNT to increment.
4. If timer W enters module standby mode while an interrupt request is generated, the interrupt
request cannot be cleared. Before entering module standby mode, disable interrupt requests.
Counter clear
signal
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1 T2
NH'0000
Figure 12.24 Contention between TCNT Write and Clear
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TCNT
Previous clock
NN+1 N+2 N+3
New clock
Count clock
The change in signal level at clock switching is
assumed to be a rising edge, and TCNT
increments the count.
Figure 12.25 Internal Clock Switching and TCNT Operation
5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the
first compare match occurs. Once a compare match occurs and this compare match changes the
values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the
values read from the TOA to TOD bits may differ. Moreover, when the writing to TCRW and
the generation of the compare match A to D occur at the same timing, the writing to TCRW
has the priority. Thus, output change due to the compare match is not reflected to the FTIOA
to FTIOD pins. Therefore, when bit manipulation instruction is used to write to TCRW, the
values of the FTIOA to FTIOD pin output may result in an unexpected result. When TCRW is
to be written to while compare match is operating, stop the counter once before accessing to
TCRW, read the port 8 state to reflect the values of FTIOA to FTIOD output, to TOA to TOD,
and then restart the counter. Figure 12.26 shows an example when the compare match and the
bit manipulation instruction to TCRW occur at the same timing.
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Compare match B
signal
φ
FTIOB pin
TCRW
write signal
Set value
Bit
TRCCR1
0
CCLR
0
CKS2
0
CKS1
0
CKS0
0
TOD
1
TOC
1
TOB
0
76543210
TOA
Expected
output
Remains high because the writing 1
to TOB has priority
TCRW has been set to H'06. Compare match B and compare match C are used. The FTIOB pin is the 1 output state,
and is set to the toggle output or the 0 output on compare match B.
When BCLR#2, @TCRW is executed to clear the TOC bit (the FTIOC signal is low) and compare match B occurs
at the same timing as shown below, the H'02 writing to TCRW has priority and compare match B does not drive the
FTIOB signal low; the FTIOB signal remains high.
BCLR#2, @TCRW
(1) TCRW read operation: Read H'06
(2) Modify operation: Modify H'06 to H'02
(3) Write operation to TCRW: Write H'02
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW
Occur at the Same Timing
Section 12 Timer W
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Section 13 Watchdog Timer
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Section 13 Watchdog Timer
The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
The block diagram of the watchdog timer is shown in figure 13.1.
φ
Internal reset
signal
PSS TCWD
TMWD
TCSRWD
Internal data bus
[Legend]
TCSRWD: Timer control/status register WD
TCWD: Timer counter WD
PSS: Prescaler S
TMWD: Timer mode register WD
Internal
oscillator
CLK
Figure 13.1 Block Diagram of Watchdog Timer
13.1 Features
• Selectable from nine counter input clocks.
Eight clock sources (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, and φ/8192 ) or the
internal oscillator can be selected as the timer-counter clock. When the internal oscillator is
selected, it can operate as the watchdog timer in any operating mo de.
• Reset signal generated on counte r o verfl o w
An overflow period of 1 to 256 times the selected clock can be set.
13.2 Register Descriptions
The watchdog timer has the following registers.
• Timer control/status register WD (TCSRWD)
• Timer counter WD (TCWD)
• Timer mode register WD (TMWD)
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13.2.1 Timer Control/Status Register WD (TCSRWD)
TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the
watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using
the MOV instruction. The bit manipulation instruction cannot be used to change the setting value.
Bit Bit Name
Initial
Value R/W Description
7 B6WI 1 R/W Bit 6 Write Inhibit
The TCWE bit can be written only when the write value
of the B6WI bit is 0.
This bit is always read as 1.
6 TCWE 0 R/W Timer Counter WD Write Enable
TCWD can be written when the TCWE bit is set to 1.
When writing data to this bit, the value for bit 7 must be
0.
5 B4WI 1 R/W Bit 4 Write Inhibit
The TCSRWE bit can be written only when the write
value of the B4WI bit is 0. This bit is always read as 1.
4 TCSRWE 0 R/W Timer Control/Status Register WD Write Enable
The WDON and WRST bits can be written when the
TCSRWE bit is set to 1.
When writing data to this bit, the value for bit 5 must be
0.
3 B2WI 1 R/W Bit 2 Write Inhibit
This bit can be written to the WDON bit only when the
write value of the B2WI bit is 0.
This bit is always read as 1.
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Bit Bit Name
Initial
Value R/W Description
2 WDON 0 R/W Watchdog Timer On
TCWD starts counting up when WDON is set to 1 and
halts when WDON is cleared to 0.
[Setting condition]
When 1 is written to the WDON bit while writing 0 to the
B2WI bit when the TCSRWE bit=1
[Clearing conditions]
• Reset by RES pin
• When 0 is written to the WDON bit while writing 0 to
the B2WI when the TCSRWE bit=1
1 B0WI 1 R/W Bit 0 Write Inhibit
This bit can be written to the WRST bit only when the
write value of the B0WI bit is 0. This bit is always read
as 1.
0 WRST 0 R/W Watchdog Timer Reset
[Setting condition]
When TCWD overflows and an internal reset signal is
generated
[Clearing conditions]
• Reset by RES pin
• When 0 is written to the WRST bit while writing 0 to
the B0WI bit when the TCSRWE bit=1
13.2.2 Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the
internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to
H'00.
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13.2.3 Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Bit Bit Name
Initial
Value R/W Description
7 to 4 All 1 Reserved
These bits are always read as 1.
3
2
1
0
CKS3
CKS2
CKS1
CKS0
1
1
1
1
R/W
R/W
R/W
R/W
Clock Select 3 to 0
Select the clock to be input to TCWD.
1000: Internal clock: counts on φ/64
1001: Internal clock: counts on φ/128
1010: Internal clock: counts on φ/256
1011: Internal clock: counts on φ/512
1100: Internal clock: counts on φ/1024
1101: Internal clock: counts on φ/2048
1110: Internal clock: counts on φ/4096
1111: Internal clock: counts on φ8192
0XXX: Internal oscillator
For the internal oscillator overflow periods, see section
20, Electrical Characteristics.
[Legend]
X: Don't care.
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13.3 Operation
The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to
B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate
the watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input
after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset
signal is generated. The internal reset signal is output for a period of 256 φosc clock cycles. TCWD
is a writable counter, and when a value is set in TCWD, the count-up starts from that value. An
overflow period in the range of 1 to 256 input clock cycles can therefore be set, according to the
TCWD set value.
Figure 13.2 shows an example of watchdog timer operation.
Example: With 30ms overflow period when φ = 4 MHz
4 × 10
6
× 30 × 10
–3
= 14.6
8192
TCWD overflow
H'FF
H'00
Internal reset
signal
H'F1
TCWD
count value
H'F1 written
to TCWD
H'F1 written to TCWD Reset generated
Start
256 φ
osc
clock cycles
Therefore, 256 – 15 = 241 (H'F1) is set in TCW.
Figure 13.2 Watchdog Timer Operation Example
Section 13 Watchdog Timer
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Section 14 Serial Communication Interface 3 (SCI3)
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Section 14 Serial Communication Interface 3 (SCI3)
Serial Communication Interface 3 (SCI3) can handle both asynchronous and clocked synchronous
serial communication. In the asynchronous method, serial data communication can be carried out
using standard asynchronous communication chips such as a Universal Asynchronous
Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA). A
function is also provided for serial communication betwee n proces so rs (multiprocess or
communication fu ncti o n).
Figure 14.1 sh ow s a bloc k diagram of the SCI3.
14.1 Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
• External clock or on-chip baud rate generator can be selected as a transfer clock source.
• Six interrupt sources
Transmit-end, transmit-data-empty, receive-data-full, overrun error, framing error, and parity
error.
Asynchro no us mode
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin leve l directly in the case of a
framing error
Clocked synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Section 14 Serial Communication Interface 3 (SCI3)
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Clock
TXD
RXD
SCK3
BRR
SMR
SCR3
SSR
TDR
RDR
TSR
RSR
Transmit/receive
control circuit
Internal data bus
[Legend]
RSR:
RDR:
TSR:
TDR:
SMR:
SCR3:
SSR:
BRR:
BRC:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register 3
Serial status register
Bit rate register
Bit rate counter
Interrupt request
(TEI, TXI, RXI, ERI)
Internal clock (φ/64, φ/16, φ/4, φ)
External
clock
BRC
Baud rate generator
Figure 14.1 Block Diagram of SCI3
14.2 Input/Output Pins
Table 14.1 shows the SCI3 pin configuration.
Table 14.1 Pin Configuration
Pin Name Abbreviation I/O Function
SCI3 clock SCK3 I/O SCI3 clock input/output
SCI3 receive data input RXD Input SCI3 receive data input
SCI3 transmit data output TXD Output SCI3 transmit data output
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14.3 Register Descriptions
The SCI3 has the followin g registers.
• Receive shift register (RSR)
• Receive data register (RDR)
• Transmit shift register (TSR)
• Transmit data register (TDR)
• Serial mode register (SMR)
• Serial control register 3 (SCR3)
• Serial status register (SSR)
• Bit rate register (BRR)
14.3.1 Receive Shift Register (RSR)
RSR is a shift register that is used to receive serial data input from the RxD pin and convert it into
parallel data. When one byte of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
14.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores received data. When the SCI3 has received one byte of serial
data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is
receive-enabled. As RSR and RDR function as a double buffer in this way, continuous receive
operations are possible. After confirming that the RDRF bit in SSR is set to 1, read RDR only
once. RDR cannot be written to by the CPU. RDR is initialized to H'00.
14.3.3 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first
transfers transmit data from TDR to TSR auto matically, then sends the data that starts from the
LSB to the TXD pin. TSR cannot be directly accessed by the CPU.
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14.3.4 Transmit Da t a Regi s ter (T DR )
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is
empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-
buffered structure of TD R and TSR enables continuous serial transmission. If the next transmit
data has already been written to TDR during transmission of one-frame data, the SCI3 transfers
the written data to TSR to con tinue transmission. To achieve reliable serial transmission, write
transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is
initialized to H'FF.
14.3.5 Serial Mode Regis ter (S M R)
SMR is used to set the SCI3’s serial transfer format and select the on-chip baud rate generator
clock source.
Bit Bit Name
Initial
Value R/W Description
7 COM 0 R/W Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6 CHR 0 R/W Character Length (enabled only in asynchronous
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length.
5 PE 0 R/W Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception.
4 PM 0 R/W Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
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Bit Bit Name
Initial
Value R/W Description
3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
For reception, only the first stop bit is checked,
regardless of the value in the bit. If the second stop bit
is 0, it is treated as the start bit of the next transmit
character.
2 MP 0 R/W Multiprocessor Mode
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit and
PM bit settings are invalid. In clocked synchronous
mode, this bit should be cleared to 0.
1
0
CKS1
CKS0
0
0
R/W
R/W
Clock Select 0 and 1
These bits select the clock source for the on-chip
baud rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register
setting and the baud rate, see section 14.3.8, Bit Rate
Register (BRR). n is the decimal representation of the
value of n in BRR (see section 14.3.8, Bit Rate
Register (BRR)).
14.3.6 Serial Control Register 3 (SCR3)
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is
also used to select the transfer clock source. For details on interrupt requests, refer to section 14.7,
Interrupts.
Bit Bit Name
Initial
Value R/W Description
7 TIE 0 R/W Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
Section 14 Serial Communication Interface 3 (SCI3)
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Bit Bit Name
Initial
Value R/W Description
6 RIE 0 R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
5 TE 0 R/W Transmit Enable
When this bit is set to 1, transmission is enabled.
4 RE 0 R/W Receive Enable
When this bit is set to 1, reception is enabled.
3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when
the MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and OER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically cleared
and normal reception is resumed. For details, refer to
section 14.6, Multiprocessor Communication
Function.
2 TEIE 0 R/W Transmit End Interrupt Enable
When this bit is set to 1, the TEI interrupt request is
enabled.
1
0
CKE1
CKE0
0
0
R/W
R/W
Clock Enable 0 and 1
Selects the clock source.
Asynchronous mode:
00: Internal baud rate generator
01: Internal baud rate generator
Outputs a clock of the same frequency as the bit
rate from the SCK3 pin.
10: External clock
Inputs a clock with a frequency 16 times the bit
rate from the SCK3 pin.
11:Reserved
Clocked synchronous mode:
00: Internal clock (SCK3 pin functions as clock output)
01: Reserved
10: External clock (SCK3 pin functions as clock input)
11: Reserved
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14.3.7 Serial Status Regi s ter (SS R )
SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared.
Bit Bit Name
Initial
Value R/W Description
7 TDRE 1 R/W Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
• When the TE bit in SCR3 is 0
• When data is transferred from TDR to TSR
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the transmit data is written to TDR
6 RDRF 0 R/W Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
When serial reception ends normally and receive data
is transferred from RSR to RDR
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF =
1
• When data is read from RDR
5 OER 0 R/W Overrun Error
[Setting condition]
When an overrun error occurs in reception
[Clearing condition]
When 0 is written to OER after reading OER = 1
4 FER 0 R/W Framing Error
[Setting condition]
When a framing error occurs in reception
[Clearing condition]
When 0 is written to FER after reading FER = 1
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Bit Bit Name
Initial
Value R/W Description
3 PER 0 R/W Parity Error
[Setting condition]
When a parity error is generated during reception
[Clearing condition]
When 0 is written to PER after reading PER = 1
2 TEND 1 R Transmit End
[Setting conditions]
• When the TE bit in SCR3 is 0
• When TDRE = 1 at transmission of the last bit of a
1-byte serial transmit character
[Clearing conditions]
• When 0 is written to TEND after reading TEND = 1
• When the transmit data is written to TDR
1 MPBR 0 R Multiprocessor Bit Receive
MPBR stores the multiprocessor bit in the receive
character data. When the RE bit in SCR3 is cleared to
0, its previous state is retained.
0 MPBT 0 R/W Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit character data.
Section 14 Serial Communication Interface 3 (SCI3)
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14.3.8 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. The in itial value of BRR is H'FF. Table 14.2
shows the relationship b etween the N setting in BRR and the n setting in bits CKS1 and CKS0 of
SMR in asynchronous mode. Table 14.3 shows the maximum bit rate for each freque nc y in
asynchronous mode. The values shown in both tables 14.2 and 14.3 are values in active (high-
speed) mode. Table 14.4 shows the relationship between the N setting in BRR and the n setting in
bits CKS1 and CKS0 in SMR in clocked synchronous mode. The values shown in table 14.4 are
values in active (high -speed) mode. The N setting in BRR and error for other operating
frequencie s an d bi t rates ca n be obt ai ned by the followi n g formul as:
[Asynchronous Mode]
N = φ
64 × 2
2n–1
× B × 10
6
– 1
Error (%) = – 1 × 100
φ × 106
(N + 1) × B × 64 × 22n–1
[Clocked Synchronous Mode]
N = φ
8 × 2
2n–1
× B × 10
6
– 1
[Legend]
B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n: CKS1 and CKS0 setting for SMR (0 ≤ N ≤ 3)
Section 14 Serial Communication Interface 3 (SCI3)
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Table 14.2 Examples of BRR Settings for Various Bit Rates (Asyn chronous Mode) (1)
Operating Frequency φ (MHz)
2 2.097152 2.4576 3
Bit Rate
(bits/s)
n
N Error
(%)
n
N Error
(%)
n
N Error
(%)
n
N Error
(%)
110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03
150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16
300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16
600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16
1200 0 51 0.16 0 54 –0.70 0 63 0.00 0 77 0.16
2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16
4800 0 12 0.16 0 13 –2.48 0 15 0.00 0 19 –2.34
9600 0 6 –6.99 0 6 –2.48 0 7 0.00 0 9 –2.34
19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 –2.34
31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00
38400 0 1 –18.62 0 1 –14.67 0 1 0.00 — — —
[Legend]
: A setting is available but error occurs
Operating Frequency φ (MHz)
3.6864 4 4.9152 5
Bit Rate
(bits/s)
n
N Error
(%)
n
N Error
(%)
n
N Error
(%)
n
N Error
(%)
110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25
150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16
300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16
600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16
1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16
2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16
4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 –1.36
9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73
19200 0 5 0.00 0 6 –6.99 0 7 0.00 0 7 1.73
31250 — — — 0 3 0.00 0 4 –1.70 0 4 0.00
38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73
Section 14 Serial Communication Interface 3 (SCI3)
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Table 14.2 Examples of BRR Settings for Various Bit Rates (Asyn chronous Mode) (2)
Operating Frequency φ (MHz)
6 6.144 7.3728 8
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03
150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16
300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16
600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16
1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16
2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16
4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16
9600 0 19 –2.34 0 19 0.00 0 23 0.00 0 25 0.16
19200 0 9 –2.34 0 9 0.00 0 11 0.00 0 12 0.16
31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00
38400 0 4 –2.34 0 4 0.00 0 5 0.00 0 6 -6.99
Operating Frequency φ (MHz)
9.8304 10 12 12.888
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 174 –0.26 2 177 –0.25 2 212 0.03 2 217 0.08
150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00
300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00
600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00
1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00
2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00
4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00
9600 0 31 0.00 0 32 –1.36 0 38 0.16 0 39 0.00
19200 0 15 0.00 0 15 1.73 0 19 –2.34 0 19 0.00
31250 0 9 –1.70 0 9 0.00 0 11 0.00 0 11 2.40
38400 0 7 0.00 0 7 1.73 0 9 –2.34 0 9 0.00
Section 14 Serial Communication Interface 3 (SCI3)
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Table 14.2 Examples of BRR Settings for Various Bit Rates (Asyn chronous Mode) (3)
Operating Frequency φ (MHz)
14 14.7456 16
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 248 –0.17 3 64 0.70 3 70 0.03
150 2 181 0.16 2 191 0.00 2 207 0.16
300 2 90 0.16 2 95 0.00 2 103 0.16
600 1 181 0.16 1 191 0.00 1 207 0.16
1200 1 90 0.16 1 95 0.00 1 103 0.16
2400 0 181 0.16 0 191 0.00 0 207 0.16
4800 0 90 0.16 0 95 0.00 0 103 0.16
9600 0 45 –0.93 0 47 0.00 0 51 0.16
19200 0 22 –0.93 0 23 0.00 0 25 0.16
31250 0 13 0.00 0 14 –1.70 0 15 0.00
38400 — — — 0 11 0.00 0 12 0.16
[Legend]
—: A setting is available but error occurs.
Table 14.3 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz) Maximum Bit
Rate (bit/s) n N φ (MHz) Maximum Bit
Rate (bit/s) n N
2 62500 0 0 7.3728 230400 0 0
2.097152 65536 0 0 8 250000 0 0
2.4576 76800 0 0 9.8304 307200 0 0
3 93750 0 0 10 312500 0 0
3.6864 115200 0 0 12 375000 0 0
4 125000 0 0 12.288 384000 0 0
4.9152 153600 0 0 14 437500 0 0
5 156250 0 0 14.7456 460800 0 0
6 187500 0 0 16 500000 0 0
6.144 192000 0 0
Section 14 Serial Communication Interface 3 (SCI3)
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Table 14.4 BRR Setting s for Various Bit Rates (Clocked Synchronous Mode)
Operating Frequency φ (MHz)
2 4 8 10 16
Bit Rate
(bit/s) n N n N n N n N n N
110 3 70 — — — — — —
250 2 124 2 249 3 124 — — 3 249
500 1 249 2 124 2 249 — — 3 124
1k 1 124 1 249 2 124 — — 2 249
2.5k 0 199 1 99 1 199 1 249 2 99
5k 0 99 0 199 1 99 1 124 1 199
10k 0 49 0 99 0 199 0 249 1 99
25k 0 19 0 39 0 79 0 99 0 159
50k 0 9 0 19 0 39 0 49 0 79
100k 0 4 0 9 0 19 0 24 0 39
250k 0 1 0 3 0 7 0 9 0 15
500k 0 0* 0 1 0 3 0 4 0 7
1M 0 0* 0 1 — — 0 3
2M 0 0* — — 0 1
2.5M 0 0* — —
4M 0 0*
[Legend]
Blank: No setting is available.
—: A setting is available but error occurs.
*: Continuous transfer is not possible.
Section 14 Serial Communication Interface 3 (SCI3)
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14.4 Operation in Asynchronous Mode
Figure 14.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and
finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units,
enabling full duplex. Both the transmitter and the receiver also have a double-buffered structure,
so data can be read or written during transmission or reception, enabling continuous data t ransfer.
LSB
Start
bit
MSB
Mark state
Stop bit
Transmit/receive data
1
Serial
data
Parity
bit
1 bit 1 or
2 bits
7 or 8 bits 1 bit,
or none
One unit of transfer data (character or frame)
Figure 14.2 Data Format in Asynchronous Communication
14.4.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK3 pin can be selected as the SCI3’s serial clock source, according to the setti ng o f the
COM bit in SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the
SCK3 pin, the clock fre q uency should be 16 t i mes the bi t ra t e used.
When the SCI3 is operated on an internal clock, the clock can be output from the SCK3 pin. The
frequency of the clock output in th is case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 14.3.
0
1 character (frame)
D0 D1 D2 D3 D4 D5 D6 D7 0/1 11
Clock
Serial data
Figure 14.3 Relationshi p bet ween Out p ut Cl ock and Transfer Data Phase
(Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
Section 14 Serial Communication Interface 3 (SCI3)
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14.4.2 SCI3 Initialization
Follow the flowchart as shown in figure 14.4 to initialize the SCI3. When the TE bit is cleared to
0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of
the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in
asynchronous mode, the clock must be supplied even during initialization.
Wait
<Initialization completion>
Start initialization
Set data transfer format in SMR
[1]
Set CKE1 and CKE0 bits in SCR3
No
Yes
Set value in BRR
Clear TE and RE bits in SCR3 to 0
[2]
[3]
Set TE and RE bits in
SCR3 to 1, and set RIE, TIE, TEIE,
and MPIE bits. For transmit (TE=1),
also set the TxD bit in PMR1.
[4]
1-bit interval elapsed?
[1] Set the clock selection in SCR3.
Be sure to clear bits RIE, TIE, TEIE,
and MPIE, and bits TE and RE, to 0.
When the clock output is selected in
asynchronous mode, clock is output
immediately after CKE1 and CKE0
settings are made. When the clock
output is selected at reception in
clocked synchronous mode, clock is
output immediately after CKE1, CKE0,
and RE are set to 1.
[2] Set the data transfer format in SMR.
[3] Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4] Wait at least one bit interval, then set
the TE bit or RE bit in SCR3 to 1. RE
settings enable the RXD pin to be
used. For transmission, set the TXD bit
in PMR1 to 1 to enable the TXD output
pin to be used. Also set the RIE, TIE,
TEIE, and MPIE bits, depending on
whether interrupts are required. In
asynchronous mode, the bits are
marked at transmission and idled at
reception to wait for the start bit.
Figure 14.4 Sample SCI3 Initi ali zation Flowchart
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14.4.3 Data Transmission
Figure 14.5 sho ws an example of opera tion for transmission in asynchronous mode. In
transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a TXI interrupt request is generated.
Continuous transmission is possible because the TXI interrupt routine writes next transmit data
to TDR before transmission of the curren t transmit data has been completed.
3. The SCI3 checks the TDRE flag at the timing for sending the stop bit.
4. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
5. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
state” is entered, in which 1 is output. If the TEIE bit in SCR3 is set to 1 at this time, a TEI
interrupt request is generated.
6. Figure 14.6 shows a sample flowchart for transmission in asynchronous mode.
1 frame
Start
bit
Start
bit
Transmit
data
Transmit
data
Parity
bit
Stop
bit
Parity
bit
Stop
bit
Mark
state
1 frame
01D0D1D70/11 110D0D1 D70/1
Serial
data
TDRE
TEND
LSI
operation
TXI interrupt
request
generated
TDRE flag
cleared to 0
User
processing
Data written
to TDR
TXI interrupt request generated TEI interrupt request
generated
Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Section 14 Serial Communication Interface 3 (SCI3)
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No
<End>
Yes
Start transmission
Read TDRE flag in SSR[1]
Write transmit data to TDR
Yes
No
No
Yes
Read TEND flag in SSR
[2]
No
Yes
[3]
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR3 to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
[1] Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR. When data is written to
TDR, the TDRE flag is automaticaly
cleared to 0.
[2] To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR. When data is
written to TDR, the TDRE flag is
automaticaly cleared to 0.
[3] To output a break in serial
transmission, after setting PCR to 1
and PDR to 0, clear TxD in PMR1 to
0, then clear the TE bit in SCR3 to
0.
Figure 14.6 Sample Serial Transmi ssion Flowchart (Asynchronous Mo de)
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 214 of 412
REJ09B0142-0600
14.4.4 Serial Data Reception
Figure 14.7 sho ws an example of opera tion for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI3 monitors the commun ication line. If a start bit is detected, the SCI3 performs
internal synchronization, receives data in RSR, and checks the parity bit and stop bit.
2. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated. Continuous reception is possible because the RXI interrupt routine reads the receive
data transferred to RDR before reception of the next receive data has been completed.
1 frame
Start
bit
Start
bit
Receive
data
Receive
data
Parity
bit
Stop
bit
Parity
bit
Stop
bit
Mark state
(idle state)
1 frame
01D0D1D70/11 010D0D1 D70/1
Serial
data
RDRF
FER
LSI
operation
User
processing
RDRF
cleared to 0
RDR data read Framing error
processing
RXI request 0 stop bit
detected
ERI request in
response to
framing error
Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 215 of 412
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Table 14.5 shows the states of the SSR status flags and receive data handling when a receive error
is detected. If a receive error is detected, the RDRF flag retains its state before receiving data.
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.8 shows a sample flowchart
for serial data reception.
Table 14.5 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF* OER FER PER Receive Data Receive Error Type
1 1 0 0 Lost Overrun error
0 0 1 0 Transferred to RDR Framing error
0 0 0 1 Transferred to RDR Parity error
1 1 1 0 Lost Overrun error + framing error
1 1 0 1 Lost Overrun error + parity error
0 0 1 1 Transferred to RDR Framing error + parity error
1 1 1 1 Lost Overrun error + framing error
+ parity error
Note: * The RDRF flag retains the state it had before data reception.
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 216 of 412
REJ09B0142-0600
Yes
<End>
No
Start reception
[1]
No
Yes
Read RDRF flag in SSR [2]
[3]
Clear RE bit in SCR3 to 0
Read OER, PER, and
FER flags in SSR
Error processing
(Continued on next page)
[4]
Read receive data in RDR
Yes
No
OER+PER+FER = 1
RDRF = 1
All data received?
[1] Read the OER, PER, and FER flags in
SSR to identify the error. If a receive
error occurs, performs the appropriate
error processing.
[2] Read SSR and check that RDRF = 1,
then read the receive data in RDR. The
RDRF flag is cleared automatically.
[3] To continue serial reception, before the
stop bit for the current frame is received,
read the RDRF flag and read RDR.
The RDRF flag is cleared automatically.
[4] If a receive error occurs, read the OER,
PER, and FER flags in SSR to identify
the error. After performing the
appropriate error processing, ensure that
the OER, PER, and FER flags are all
cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a break
can be detected by reading the value of
the input port corresponding to the RxD
pin.
(A)
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous mode) (1)
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 217 of 412
REJ09B0142-0600
<End>
(A)
Error processing
Parity error processing
Yes
No
Clear OER, PER, and
FER flags in SSR to 0
No
Yes
No
Yes
Framing error processing
No
Yes
Overrun error processing
OER = 1
FER = 1
Break?
PER = 1
[4]
Figure 14.8 Sample Serial Reception Data Flowchart (2)
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 218 of 412
REJ09B0142-0600
14.5 Operation in Clocked Synchronous Mode
Figure 14.9 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received synchronous with clock pulses. A single
character in the transmit data consists of the 8-bit data starting from the LSB. In clocked
synchronous serial communication, data on the tran smission line is output from one falling edge of
the serial clock to the next. In clocked synchronous mode, the SCI3 receives data in synchronous
with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the
MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the
SCI3, the transmitter and receiver ar e independent units, enabling full-duplex communication
through the use of a common clock. Both the transmitter and the receiver also have a double-
buffered structure, so data can be read or written during transmission or reception, enabling
continuous data transfer.
Don't
care
Don't
care
One unit of transfer data (character or frame)
8-bit
Bit 0
Serial data
Synchronization
clock
Bit 1 Bit 3 Bit 4 Bit 5
LSB MSB
Bit 2 Bit 6 Bit 7
*
*
Note: * High except in continuous transfer
Figure 14.9 Data Format in Clocked Synchronous Communication
14.5.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK3 pin can be selected, according to the setting of the COM
bit in SMR and CKE0 an d CKE1 bits in SCR3. When the SCI3 is operated on an in ternal clock,
the serial clock is output from the SCK3 pin . Eight serial clock pulses are output in the transfer of
one character, and when no transfer is performed the clock is fixed high.
14.5.2 SCI3 Initialization
Before transmitting and receiving data, the SCI3 should be initialized as described in a sample
flowchart in figure 14.4.
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 219 of 412
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14.5.3 Serial Data Transmission
Figure 14.10 shows an example of SCI3 operation for transmission in clocked synchronous mode.
In serial transmission, the SCI3 operates as described below.
1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has
been written to TDR, and transfers the data from TDR to TSR.
2. The SCI3 sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR3 is set to 1 at
this time, a transmit data empty interrupt (TXI) is generated.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified, and synchronized with the input clock when use of an external clock
has been specified. Serial d a ta is transmitted sequentially from the LSB (bit 0), from th e TXD
pin.
4. The SCI checks the TDRE flag at the timin g for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains
the output state of the last bit. If the TEIE bit in SCR3 is set to 1 at this time, a TEI interrupt
request is generated.
7. The SCK3 pin is fixe d high.
Figure 14.11 sh ows a sample flowchart for serial data tran smission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (OER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission.
Serial
clock
Serial
data Bit 1Bit 0 Bit 7 Bit 0
1 frame 1 frame
Bit 1 Bit 6 Bit 7
TDRE
TEND
LSI
operation
User
processing
TXI interrupt request generated
Data written
to TDR
TDRE flag
cleared to 0
TXI interrupt
request
generated
TEI interrupt request
generated
Figure 14.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 220 of 412
REJ09B0142-0600
No
<End>
Yes
Start transmission
Read TDRE flag in SSR[1]
Write transmit data to TDR
No
Yes
No
Yes
Read TEND flag in SSR
[2]
Clear TE bit in SCR3 to 0
TDRE = 1
All data transmitted?
TEND = 1
[1] Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR. When data is written to TDR,
the TDRE flag is automatically cleared
to 0 and clocks are output to start the
data transmission.
[2] To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR.
When data is written to TDR, the TDRE
Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 221 of 412
REJ09B0142-0600
14.5.4 Serial Data Reception (Clocked Synchronous Mode)
Figure 14.12 sh ows an example of SCI3 operation for reception in clocked synchronous mode. In
serial reception, the SCI3 operates as described below.
1. The SCI3 performs internal initialization synchronous with a synchronous clock input or
output, starts receiving data.
2. The SCI3 stores the received data in RSR.
3. If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.
4. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated.
Serial
clock
Serial
data
1 frame 1 frame
Bit 0Bit 7 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
RDRF
OER
LSI
operation
User
processing
RXI interrupt request generated
RDR data read
RDRF flag
cleared
to 0
RXI interrupt
request
generated
ERI interrupt request
generated by
overrun error
Overrun error
processing
RDR data has
not been read
(RDRF = 1)
Figure 14.12 Example of SCI3 Reception Operation in Clocke d Sync hronous Mode
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 222 of 412
REJ09B0142-0600
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming recep tion. Figure 14.13 show s a sample flowchart
for serial data reception.
Yes
<End>
No
Start reception
[1]
[4]
No
Yes
Read RDRF flag in SSR [2]
[3]
Clear RE bit in SCR3 to 0
Error processing
(Continued below)
Read receive data in RDR
Yes
No
OER = 1
RDRF = 1
All data received?
Read OER flag in SSR
<End>
Error processing
Overrun error processing
Clear OER flag in SSR to 0
[4]
[1] Read the OER flag in SSR to determine
if there is an error. If an overrun error
has occurred, execute overrun error
processing.
[2] Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR. When data is read from
RDR, the RDRF flag is automatically
cleared to 0.
[3] To continue serial reception, before the
MSB (bit 7) of the current frame is
received, reading the RDRF flag and
reading RDR should be finished. When
data is read from RDR, the RDRF flag
is automatically cleared to 0.
[4] If an overrun error occurs, read the
OER flag in SSR, and after performing
the appropriate error processing, clear
the OER flag to 0. Reception cannot be
Figure 14.13 Sample Serial Reception Flowchart (Clo cked Synchronous Mode)
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 223 of 412
REJ09B0142-0600
14.5.5 Simultaneous Serial Data Transmission and Reception
Figure 14.14 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations. To switch from transmit mode to simultaneous transmit and receive mod e, after
checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear
TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive
mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished
reception, clear RE to 0. Then after checking that the RDRF and receive error flags (OER, FER,
and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
Yes
<End>
No
Start transmission/reception
[3]
Error processing
[4]
Read receive data in RDR
Yes
No
OER = 1
All data received?
[1]
Read TDRE flag in SSR
No
Yes
TDRE = 1
Write transmit data to TDR
No
Yes
RDRF = 1
Read OER flag in SSR
[2]
Read RDRF flag in SSR
Clear TE and RE bits in SCR to 0
[1] Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR.
When data is written to TDR, the
TDRE flag is automatically cleared
to 0.
[2] Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR.
When data is read from RDR, the
RDRF flag is automatically cleared
to 0.
[3] To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR. Also, before the MSB (bit 7)
of the current frame is transmitted,
read 1 from the TDRE flag to confirm
that writing is possible. Then write
data to TDR.
When data is written to TDR, the
TDRE flag is automatically cleared
to 0. When data is read from RDR,
the RDRF flag is automatically
cleared to 0.
[4] If an overrun error occurs, read the
OER flag in SSR, and after
performing the appropriate error
processing, clear the OER flag to 0.
Transmission/reception cannot be
resumed if the OER flag is set to 1.
For overrun error processing, see
figure 14.13.
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
(Clocked Synchronous Mode)
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 224 of 412
REJ09B0142-0600
14.6 Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer between a number of
processors sharing communication lines by asynchronous serial communication using the
multiprocessor format, in which a multiprocessor bit is added to the transfer data. When
multiprocessor communication is performed, each receiving station is addressed by a unique ID
code. The serial communication cycle consists of two component cycles; an ID transmission cycle
that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to
differentiate between the ID transmission cycle and the data transmission cycle. If the
multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the
cycle is a data transmission cycle. Figure 14.15 shows an example of inter-processor
communication using the multiprocessor format. The transmitting station first sends the ID code
of the receiving station with which it wants to perform serial communication as data with a 1
multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not
match continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI3 uses the MPIE bit in SCR3 to implement this function. When the MPIE b it is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and OER to 1, are inhibited until data with a 1 multiprocessor bit is received. On
reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and
the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR3 is
set to 1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit
settings are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode .
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 225 of 412
REJ09B0142-0600
Transmitting
station
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01) (ID = 02) (ID = 03) (ID = 04)
Serial transmission line
Serial
data
ID transmission cycle =
receiving station
specification
Data transmission cycle =
Data transmission to
receiving station specified by ID
(MPB = 1) (MPB = 0)
H'01 H'AA
[Legend]
MPB: Multiprocessor bit
Figure 14.15 Example of Communication Using Multiprocessor For mat
(Transmission of Data H'AA to Receiving Station A)
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 226 of 412
REJ09B0142-0600
14.6.1 Multiprocessor Serial Data Transmission
Figure 14.16 sh ows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 befo re transmi ssion. All other SCI3 operations are the same
as those in asynchronous mode.
No
<End>
Yes
Start transmission
Read TDRE flag in SSR[1]
Set MPBT bit in SSR
Yes
No
No
Yes
Read TEND flag in SSR
[2]
No
Yes
[3]
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR3 to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
Write transmit data to TDR
[1] Read SSR and check that the TDRE
flag is set to 1, set the MPBT bit in
SSR to 0 or 1, then write transmit
data to TDR. When data is written to
TDR, the TDRE flag is automatically
cleared to 0.
[2] To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR. When data is
written to TDR, the TDRE flag is
automatically cleared to 0.
[3] To output a break in serial
transmission, set the port PCR to 1,
clear PDR to 0, then clear the TE bit
in SCR3 to 0.
Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 227 of 412
REJ09B0142-0600
14.6.2 Multiprocessor Serial Data Reception
Figure 14.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving
data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request
is generated at this time. All other SCI3 operations are the same as in asynchronous mode. Figure
14.18 shows an example of SCI3 operation for multiprocessor format reception.
Yes
<End>
No
Start reception
No
Yes
[4]
Clear RE bit in SCR3 to 0
Error processing
(Continued on
next page)
[5]
Yes
No
FER+OER = 1
RDRF = 1
All data received?
Set MPIE bit in SCR3 to 1 [1]
[2]
Read OER and FER flags in SSR
Read RDRF flag in SSR [3]
Read receive data in RDR
No
Yes
[A]
This station's ID?
Read OER and FER flags in SSR
Yes
No
Read RDRF flag in SSR
No
Yes
FER+OER = 1
Read receive data in RDR
RDRF = 1
[1] Set the MPIE bit in SCR3 to 1.
[2] Read OER and FER in SSR to check for
errors. Receive error processing is
performed in cases where a receive error
occurs.
[3] Read SSR and check that the RDRF flag
is set to 1, then read the receive data in
RDR and compare it with this station’s
ID.
If the data is not this station’s ID, set the
MPIE bit to 1 again.
When data is read from RDR, the RDRF
flag is automatically cleared to 0.
[4] Read SSR and check that the RDRF flag
is set to 1, then read the data in RDR.
[5] If a receive error occurs, read the OER
and FER flags in SSR to identify the
error. After performing the appropriate
error processing, ensure that the OER
and FER flags are all cleared to 0.
Reception cannot be resumed if either of
these flags is set to 1.
In the case of a framing error, a break
can be detected by reading the RxD pin
value.
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 228 of 412
REJ09B0142-0600
<End>
Error processing
Yes
No
Clear OER, and
FER flags in SSR to 0
No
Yes
No
Yes
Framing error processing
Overrun error processing
OER = 1
FER = 1
Break?
[5]
[A]
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 229 of 412
REJ09B0142-0600
1 frame
Start
bit
Start
bit
Receive
data (ID1)
Receive data
(Data1)
MPB MPB
Stop
bit
Stop
bit
Mark state
(idle state)
1 frame
01D0D1D711 110D0D1 D7
ID1
0
Serial
data
MPIE
RDRF
RDR
value
RDR
value
LSI
operation
RXI interrupt
request
MPIE cleared
to 0
User
processing
RDRF flag
cleared
to 0
RXI interrupt request
is not generated, and
RDR retains its state
RDR data read When data is not
this station's ID,
MPIE is set to 1
again
1 frame
Start
bit
Start
bit
Receive
data (ID2)
Receive data
(Data2)
MPB MPB
Stop
bit
Stop
bit
Mark state
(idle state)
1 frame
01D0D1D711 110
(a) When data does not match this receiver's ID
(b) When data matches this receiver's ID
D0 D1 D7
ID2 Data2ID1
0
Serial
data
MPIE
RDRF
LSI
operation
RXI interrupt
request
MPIE cleared
to 0
User
processing
RDRF flag
cleared
to 0
RXI interrupt
request
RDRF flag
cleared
to 0
RDR data read When data is
this station's
ID, reception
is continued
RDR data read
MPIE set to 1
again
Figure 14.18 Example of SCI3 Operation in Reception Using Multiprocessor Format
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 230 of 412
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14.7 Interrupts
The SCI3 creates the following six interrupt requests: transmission end, transmit data empty ,
receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.6
shows the interrupt sources.
Table 14.6 SCI3 Interrupt Requests
Interrupt Requests Abbreviation Interrupt Sources
Receive Data Full RXI Setting RDRF in SSR
Transmit Data Empty TXI Setting TDRE in SSR
Transmission End TEI Setting TEND in SSR
Receive Error ERI Setting OER, FER, and PER in SSR
The initial value of the TDRE flag in SSR is 1. Thus, when the TIE bit in SCR3 is set to 1 before
transferring the transmit d ata to TDR, a TXI interrupt request is generated even if the transmit d a ta
is not ready. The initial v alue of the TEND flag in SSR is 1. Thus, when the TEIE bit in SCR3 is
set to 1 before transferring the transmit data to TDR, a TEI interrupt request is generated even if
the transmit data has not been sen t. It is possible to make use of the most of these interrupt
requests efficiently by transferring the transmit data to TDR in the interrupt routine. To preven t
the generation of these interrupt requests (TXI and TEI), set the enable bits (T IE and TEIE) that
correspond to these interrupt requests to 1, after transferring the transmit data to TDR.
14.8 Usage Notes
14.8.1 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0, setting the FER flag, and possibly
the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if
the FER flag is cleared to 0, it will be set to 1 again.
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 231 of 412
REJ09B0142-0600
14.8.2 Mark State and Break Sending
When TE is 0, the TxD pi n is used as an I/O port whose di r ect i on (i n put o r output) and level are
determined by PCR and PDR. This can be used to set the TxD pin to mark state (high level) or
send a break during serial data transmission. To maintain the communication line at mark state
until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TxD pin
becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission,
first set PCR to 1 and PDR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is
initialized regardless of the current transmissio n state, the TxD pin becomes an I/O port, and 0 is
output from the TxD pin.
14.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the
transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock,
and performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the basic clock as shown in figure 14.19.
Thus, the reception margin in asynchronous mode is given by formula (1) below.
M = (0.5 – ) – – (L – 0.5) F × 100(%)
1
2N
D – 0.5
N
... Formula (1)
Where N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
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Assuming values of F (absolute value of clock rate deviation) = 0 and D (clock duty) = 0.5 in
formula (1), the reception margin can be given by the formula.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the co mputed value, and a margin of 20% to 30% shou ld be allowed for in
system design.
Internal basic
clock
16 clocks
8 clocks
Receive data
(RxD)
Synchronization
sampling timing
Start bit D0 D1
Data sampling
timing
15 0 7 15 00 7
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode
Section 15 I2C Bus Interface (IIC)
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Section 15 I2C Bus Interface (IIC)
The I2C bus interface conforms to and provides a subset of the Philips I2C bus (i nt er- IC b us)
interface functions. The register configuration that controls the I2C bus differs partly from the
Philips configuration, however.
15.1 Features
• Selection of I2C format or clocked synchronous serial format
I2C bus format: addressing format with acknowledge bit, for master/slave operation
Cloc ked synchronous serial format: non-addressing format with out acknowledge bit, for
master operation only
• I2C bus format
• Two ways of setting slave address
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Wait function in master mode
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
• Wait function in slave mode
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer bec o mes pos si bl e.
• Three interrupt sources
Data transfer end (including transmission mode transition with I2C bus format and address
reception after loss of master arbitration)
Address match: when any slave address matches or the general call address is received in
slave receive mode
Stop condition detection
• Selection of 16 internal clocks (in master mode)
• Direct bus drive
Two pins, SCL and SDA pins function as NMOS open-drain outputs when the bus drive
function is selected.
Section 15 I2C Bus Interface (IIC)
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Figure 15.1 show s a block diagram of t he I2C bus interface.
Figure 15.2 shows an example of I/O pin connections to external circuits. The I/O pins are NMOS
open drains. Set the upper limit of voltage applied to the power supply (VCC) voltage range +
0.3 V, i.e. 5. 8 V.
φPS
Noise
canceler
Noise
canceler
Clock
control
Bus state
decision
circuit
Arbitration
decision
circuit
Output data
control
circuit
Address
comparator
SAR, SARX
Interrupt
generator
ICDRS
ICDRR
ICDRT
ICSR
ICMR
ICCR
Internal data bus
Interrupt
request
SCL
SDA
[Legend]
ICCR:
ICMR:
ICSR:
ICDR:
SAR:
SARX:
PS:
I2C bus control register
I2C bus mode register
I2C bus status register
I2C bus data register
Slave address register
Slave address register X
Prescaler
Figure 15.1 Block Diagram of I2C Bus Interface
Section 15 I2C Bus Interface (IIC)
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SCL in
SCL out
SDA in
SDA out
(Slave 1)
SCL
SDA
SCL in
SCL out
SDA in
SDA out
(Slave 2)
SCL
SDA
SCL in
SCL out
SDA in
SDA out
(Master)
This LSI
SCL
SDA
VDD
VCC
SCL
SDA
Figure 15.2 I2C Bus Interface Connections (Example: This LSI as Master)
15.2 Input/Output Pins
Table 15.1 summarizes the input/output pins used by the I2C bus interface.
Table 15.1 I2C Bus Interface Pins
Name Abbreviation I/O Function
Serial clock SCL I/O IIC serial clock input/output
Serial data SDA I/O IIC serial data input/output
Section 15 I2C Bus Interface (IIC)
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15.3 Register Descriptions
The I2C bus interface has the following registers. ICDR, SARX, ICMR, and SAR are allocated to
one address, and registers that can be accessed depend on the ICE bit in ICCR. When ICE = 0.
SAR and SARX can be accessed. When ICE = 1, ICMR and ICDR can be accessed.
• I2C bus control register (ICCR)
• I2C bus status register (ICSR)
• I2C bus data register (ICDR)
• I2C bus mode register (ICMR)
• Slave address register (SAR)
• Second slave address register (SARX)
• Timer serial control register (TSCR)
15.3.1 I2C Bus Data Register (ICDR)
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among the
three registers are performed automatically in coordination with changes in the bus state, and
affect the status of internal flags such as TDRE and RDRF. When TDRE is 1 and the transmit
buffer is empty, TDRE shows that the next transmit data can be written from the CPU. When
RDRF is 1, it shows that the valid receive data is stored in the receive buffer.
If I2C is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following
transmission/reception of one frame of data using ICDRS, data is transferred automatically from
ICDRT to ICDRS. If I2C is in receive mode and no previous data remains in ICDRR (the RDRF
flag is 0) following transmission / reception of one frame of data using IC D R S, dat a is tra n sfer red
automatically from ICDRS to ICDRR.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
ICDR can be written and read only when the ICE bit is set to 1 in ICCR.
The value of ICDR is undefined after a reset.
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The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the
TDRE and RDRF flags affects the status of the interrupt flags.
Bit Bit Name
Initial
Value R/W Description
TDRE Transmit Data Register Empty
[Setting conditions]
• In transmit mode, when a start condition is detected
in the bus line state after a start condition is issued
in master mode with the I2C bus format or serial
format selected
• When transmit mode (TRS = 1) is set without a
format
• When data is transferred from ICDRT to ICDRS
• When a switch is made from receive mode to
transmit mode after detection of a start condition
[Clearing conditions]
• When transmit data is written in ICDR in transmit
mode
• When a stop condition is detected in the bus line
state after a stop condition is issued with the I2C
bus format or serial format selected
• When a stop condition is detected with the I2C bus
format selected
• In receive mode
RDRF Receive Data Register Full
[Setting condition]
When data is transferred from ICDRS to ICDRR
[Clearing condition]
When ICDR (ICDRR) receive data is read in receive
mode
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15.3.2 Slave Address Register (SAR)
SAR selects the slave address and selects the communication format. SAR can be written and read
only when the ICE bit is cleared to 0 in ICCR.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Slave Address 6 to 0
Sets a slave address
0 FS 0 R/W Selects the communication format together with the
FSX bit in SARX. Refer to table 15.2.
15.3.3 Second Slave Address Register (SARX)
SARX stores the second slave address and selects the communication format. SARX can be
written and read only when the ICE bit is cleared to 0 in ICCR.
Bit Bit Name
Initial
Value R/W Description
7
6
5
4
3
2
1
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Slave Address 6 to 0
Sets the second slave address
0 FSX 0 R/W Selects the communication format together with the FS
bit in SAR. Refer to table 15.2.
Section 15 I2C Bus Interface (IIC)
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Table 15.2 Communication Format
SAR SARX
FS FSX I2C Transfer Format
0 0 SAR and SARX are used as the slave addresses with the I2C bus
format.
0 1 Only SAR is used as the slave address with the I2C bus format.
1 0 Only SARX is used as the slave address with the I2C bus format.
1 1 Clock synchronous serial format (SAR and SARX are invalid)
15.3.4 I2C Bus Mode Register (ICMR)
The I2C bus mode register (ICMR) sets the transfer format and tra ns fer rate. It can only be
accessed when the ICE bit in ICCR is 1.
Bit Bit Name
Initial
Value R/W Description
7 MLS 0 R/W MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I2C bus format is used.
6 WAIT 0 R/W Wait Insertion Bit
This bit is valid only in master mode with the I2C bus
format.
When WAIT is set to 1, after the fall of the clock for the
final data bit, the IRIC flag is set to 1 in ICCR, and a
wait state begins (with SCL at the low level). When the
IRIC flag is cleared to 0 in ICCR, the wait ends and the
acknowledge bit is transferred. If WAIT is cleared to 0,
data and acknowledge bits are transferred
consecutively with no wait inserted. The IRIC flag in
ICCR is set to 1 on completion of the acknowledge bit
transfer, regardless of the WAIT setting.
5
4
3
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Serial Clock Select 2 to 0
This bit is valid only in master mode.
These bits select the required transfer rate, together
with the IICX bit in TSCR. Refer table 15.3.
Section 15 I2C Bus Interface (IIC)
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Bit Bit Name
Initial
Value R/W Description
2
1
0
BC2
BC1
BC0
0
0
0
R/W
R/W
R/W
Bit Counter 2 to 0
These bits specify the number of bits to be transferred
next. With the I2C bus format, the data is transferred
with one addition acknowledge bit. Bit BC2 to BC0
settings should be made during an interval between
transfer frames. If bits BC2 to BC0 are set to a value
other than 000, the setting should be made while the
SCL line is low. The value returns to 000 at the end of a
data transfer, including the acknowledge bit.
I2C Bus Format Clocked Synchronous Mode
000: 9 000: 8
001: 2 001: 1
010: 3 010: 2
011: 4 011: 3
100: 5 100: 4
101: 6 101: 5
110: 7 110: 6
111: 8 111: 7
Section 15 I2C Bus Interface (IIC)
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Table 15.3 I2C Transfer Rate
TSCR ICMR
Bit 0 Bit 5 Bit 4 Bit 3 Transfer Rate
IICX CKS2 CKS1 CKS0 Clock φ = 5 M Hz φ = 8 MHz φ = 10 MHz φ = 16 MHz
0 0 0 0 φ/28 179MHz 286kHz 357kHz 571kHz
0 0 0 1 φ/40 125kHz 200kHz 250kHz 400kHz
0 0 1 0 φ/48 104kHz 167kHz 208kHz 333kHz
0 0 1 1 φ/64 78.1kHz 125kHz 156kHz 250kHz
0 1 0 0 φ/80 62.5kHz 100kHz 125kHz 200kHz
0 1 0 1 φ/100 50.0kHz 80.0kHz 100kHz 160kHz
0 1 1 0 φ/112 44.6kHz 71.4kHz 89.3kHz 143kHz
0 1 1 1 φ/128 39.1kHz 62.5kHz 78.1kHz 125kHz
1 0 0 0 φ/56 89.3kHz 143kHz 179kHz 286kHz
1 0 0 1 φ/80 62.5kHz 100kHz 125kHz 200kHz
1 0 1 0 φ/96 52.1kHz 83.3kHz 104kHz 167kHz
1 0 1 1 φ/128 39.1kHz 62.5kHz 78.1kHz 125kHz
1 1 0 0 φ/160 31.3kHz 50.0kHz 62.5kHz 100kHz
1 1 0 1 φ/200 25.0kHz 40.0kHz 50.0kHz 80.0kHz
1 1 1 0 φ/224 22.3kHz 35.7kHz 44.6kHz 71.4kHz
1 1 1 1 φ/256 19.5kHz 31.3kHz 39.1kHz 62.5kHz
Section 15 I2C Bus Interface (IIC)
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15.3.5 I2C Bus Control Register (ICCR)
I2C bus control register (ICCR) consists of the control bits and interrupt request flags of I2C bus
interface.
Bit Bit Name
Initial
Value R/W Description
7 ICE 0 R/W I2C Bus Interface Enable
When this bit is set to 1, the I2C bus interface module is
enabled to send/receive data and drive the bus since it
is connected to the SCL and SDA pins. ICMR and
ICDR can be accessed.
When this bit is cleared, the module is halted and
separated from the SCL and SDA pins. SAR and SARX
can be accessed.
6 IEIC 0 R/W I2C Bus Interface Interrupt Enable
When this bit is 1, Interrupts are enabled by IRIC.
5
4
MST
TRS
0
0
R/W
R/W
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode of the I2C bus
format. In slave receive mode, the R/W bit in the first
frame immediately after the start automatically sets
these bits in receive mode or transmit mode by using
hardware. The settings can be made again for the bits
that were set/cleared by hardware, by reading these
bits. When the TRS bit is intended to change during a
transfer, the bit will not be switched until the frame
transfer is completed, including acknowledgement.
Section 15 I2C Bus Interface (IIC)
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Bit Bit Name
Initial
Value R/W Description
3 ACKE 0 R/W Acknowledge Bit Judgement Selection
0: The value of the acknowledge bit is ignored, and
continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the
ACKB bit, which is always 0.
1: If the acknowledge bit is 1, continuous transfer is
interrupted.
2 BBSY 0 R/W Bus Busy
In slave mode, reading the BBSY flag enables to
confirm whether the I2C bus is occupied or released.
The BBSY flag is set to 0 when the SDA level changes
from high to low under the condition of SCl = high,
assuming that the start condition has been issued. The
BBSY flag is cleared to 0 when the SDA level changes
from low to high under the condition of SCl = high,
assuming that the start condition has been issued.
Writing to the BBSY flag in slave mode is disabled.
In master mode, the BBSY flag is used to issue start
and stop conditions. Write 1 to BBSY and 0 to SCP to
issue a start condition. Follow this procedure when also
re-transmitting a start condition. To issue a start/stop
condition, use the MOV instruction. The I2C bus
interface must be set in master transmit mode before
the issue of a start condition.
Section 15 I2C Bus Interface (IIC)
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Bit Bit Name
Initial
Value R/W Description
1 IRIC 0 R/W I2C Bus Interface Interrupt Request Flag
Also see table 15.4.
[Setting conditions]
In master mode with I2C bus format
• When a start condition is detected in the bus line
state after a start condition is issued
• When a wait is inserted between the data and
acknowledge bit when WAIT = 1
• At the rising edge of the ninth transfer/receive clock,
and at the falling edge of the eighth transfer/receive
clock when a wait is inseted
• When a slave address is received after bus
arbitration is lost (when the AL flag is set to1)
• When 1 is received as the acknowledge bit when
the ACKE bit is 1 (when the ACKB bit is set to 1)
I2C bus format slave mode
• When the slave address (SVA, SVAX) matches
(when the AAS and AASX flags are set to 1) and at
the end of data transfer up to the subsequent
retransmission start condition or stop condition
detection (FS = 0 and when the TDRE or RDRF flag
is set to 1)
• When the general call address is detected (when
the ADZ flag is set to 1) and at the end of data
transfer up to the subsequent retransmission start
condition or stop condition detection (when the
TDRE or RDRF flag is set to 1)
• When 1 is received as the acknowledge bit when
the ACKE bit is 1 (when the ACKB bit is set to 1)
• When a stop condition is detected (when the STOP
or ESTP flag is set to 1)
Clocked synchronous serial format
• At the end of data transfer (when the TDRE or
RDRF flag is set to 1)
• When a start condition is detected with serial format
selected
[Clearing condition]
When 0 is written in IRIC after reading IRIC = 1
Section 15 I2C Bus Interface (IIC)
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Bit Bit Name
Initial
Value R/W Description
0 SCP 1 W Start Condition/Stop Condition Prohibit
The SCP bit controls the issue of start/stop conditions
in master mode.
To issue a start condition, write 1 in BBSY and 0 in
SCP. A retransmit start condition is issued in the same
way. To issue a stop condition, write 0 in BBSY and 0 in
SCP. This bit is always read as 1. If 1 is written, the
data is not stored.
15.3.6 I2C Bus Status Register (ICSR)
The I2C bus status register (ICSR) consists of status flags. Also see table 15.4.
Bit Bit Name
Initial
Value R/W Description
7 ESTP 0 R/W
Error Stop Condition Detection Flag
This bit is valid in I2C bus format slave mode.
[Setting condition]
When a stop condition is detected during frame
transfer.
[Clearing conditions]
• When 0 is written in ESTP after reading ESTP = 1
• When the IRIC flag is cleared to 0
6 STOP 0 R/W Normal Stop Condition Detection Flag
This bit is valid in I2C bus format slave mode.
[Setting condition]
When a stop condition is detected during frame
transfer.
[Clearing conditions]
• When 0 is written in STOP after reading STOP = 1
• When the IRIC flag is cleared to 0
Section 15 I2C Bus Interface (IIC)
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Bit Bit Name
Initial
Value R/W Description
5 IRTR 0 R/W I2C Bus Interface Continuous Transmission/Reception
Interrupt Request Flag
[Setting conditions]
In I2C bus interface slave mode
• When the TDRE or RDRF flag is set to 1 when
AASX = 1
In I2C bus interface other modes
• When the TDRE or RDRF flag is set to 1
[Clearing conditions]
• When 0 is written in IRTR after reading IRTR = 1
• When the IRIC flag is cleared to 0
4 AASX 0 R/W Second Slave Address Recognition Flag
[Setting condition]
When the second slave address is detected in slave
receive mode and FSX = 0
[Clearing conditions]
• When 0 is written in AASX after reading AASX = 1
• When a start condition is detected
• In master mode
3 AL 0 R/W Arbitration Lost
[Setting condition]
When bus arbitration was lost in master mode.
[Clearing conditions]
• When 0 is written in AL after reading AL = 1
• When ICDR data is written (transmit mode) or read
(receive mode)
Section 15 I2C Bus Interface (IIC)
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Bit Bit Name
Initial
Value R/W Description
2 AAS 0 R/W Slave Address Recognition Flag
[Setting condition]
When the slave address or general call address is
detected in slave receive mode and FS = 0.
[Clearing conditions]
• When ICDR data is written (transmit mode) or read
(receive mode)
• When 0 is written in AAS after reading AAS = 1
• In master mode
1 ADZ 0 R/W General Call Address Recognition Flag
This bit is valid in I2C bus format slave receive mode.
[Setting condition]
When the general call address is detected in slave
receive mode and FSX = 0 or FS = 0.
[Clearing conditions]
• When ICDR data is written (transmit mode) or read
(receive mode)
• When 0 is written in ADZ after reading ADZ = 1
• In master mode
0 ACKB 0 R/W Acknowledge Bit
In transmit mode, the acknowledge data that are
returned by the receive device is loaded. In receive
mode, the acknowledge data originally specified to this
bit is sent to the transmit device, after receiving data.
When this bit is read, the loaded value (return value
from the receive device) is read at transmission and the
specified value is read at reception.
Section 15 I2C Bus Interface (IIC)
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15.3.7 Timer Serial Control Register (TSCR)
The timer serial control register (TSCR) is an 8-bit readable/writable register that controls the
operating modes.
Bit Bit Name
Initial
Value R/W Description
7 to 2 − All 1 − Reserved
This bit is always read as 1 and cannot be modified.
1 IICRST 0 R/W I2C Control Unit Reset
Resets the control unit except for the I2C registers.
When a hang up occurs due to illegal communication
during I2C operation, setting IICRST to 1 can set a port
or reset the I2C control unit without initializing registers.
0 IICX 0 R/W I2C Transfer Rate Select
Selects the transfer rate in master mode, together with
bits CKS2 to CKS0 in ICMR. Refer to table 15.3.
When, with the I2C bus format selected, IRIC is set to 1 and an interr upt is generated, other flags
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer. When the TDRE or RDRF internal
flag is set, the readable IRTR flag may or may not be set . Even when the IRIC flag and IRTR flag
are set, the TDRE or RDRF internal flag may not be set. Table 15.4 shows the relationship
between the flags and the transfer states.
Section 15 I2C Bus Interface (IIC)
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Table 15.4 Flags and Transfer States
MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB State
1/0 1/0 0 0 0 0 0 0 0 0 0 Idle state (flag clearing required)
1 1 0 0 0 0 0 0 0 0 0 Start condition issuance
1 1 1 0 0 1 0 0 0 0 0 Start condition established
1 1/0 1 0 0 0 0 0 0 0 0/1 Master mode wait
1 1/0 1 0 0 1 0 0 0 0 0/1 Master mode transmit/receive end
0 0 1 0 0 0 1/0 1 1/0 1/0 0 Arbitration lost
0 0 1 0 0 0 0 0 1 0 0 SAR match by first frame in slave
mode
0 0 1 0 0 0 0 0 1 1 0 General call address match
0 0 1 0 0 0 1 0 0 0 0 SARX match
0 1/0 1 0 0 0 0 0 0 0 0/1 Slave mode transmit/receive end
(except after SARX match)
0
0
1/0
1
1
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
Slave mode transmit/receive end
(after SARX match)
0 1/0 0 1/0 1/0 0 0 0 0 0 0/1 Stop condition detected
15.4 Operation
The I2C bus interface has serial and I2C bus formats.
15.4.1 I2C Bus Data Format
The I2C bus formats are addressing formats and an acknowledge bit is inserted. These are shown
in figures 15.3. Figure 15.5 shows the I2C bus timing. The first frame following a start condition
always consists of 8 bits.
Section 15 I2C Bus Interface (IIC)
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S SLA R/WA DATA A A/AP
1111n7
1 m
(a) I
2
C bus format (FS = 0 or FSX = 0)
(b) I
2
C bus format (start condition retransmission, FS = 0 or FSX = 0)
n: transfer bit count
(n = 1 to 8)
m: transfer frame count
(m ≥ 1)
S SLA R/WA DATA
11
1 n17
1 m1
S SLA R/WA DATA A/AP
11
1 n27
1 m2
111
A/A
n1 and n2: transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: transfer frame count (m1 and m2 ≥ 1)
11
Figure 15.3 I2C Bus Data Formats (I2C Bus Formats)
SDA
SCL
S
1-7
SLA
8
R/W
9
A
1-7
DATA
89 1-7 89
A DATA P
A/A
Figure 15.4 I2C Bus Timing
[Legend]
S: Start condition. The master device drives SDA from high to low while SCL is high
SLA: Slave address
R/W: Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0
A: Acknowledge. The receiving device drives SDA
DATA: Transferred data
P: Stop condition. The master device drives SDA from low to high while SCL is high
Section 15 I2C Bus Interface (IIC)
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15.4.2 Master Transmit Operation
When data is set to ICDR during the period between the execution of an instructio n to issue a start
condition and the creation of the start con dition, the data may not be output normally, because
there will be a contention between a generation of a start condition and an output of data.
Although data H'FF is to be sent to the ICDR register by a dummy wri t e o peration before an issue
of a stop condition, the H'FF data may be output by the dummy write operation if the execution of
the instruction to issue a stop cond ition is delayed. To prevent these prob lems, follow the
flowchart shown below during the master transmit operation.
In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal. The transmission procedure and
operations synchronize w ith the ICDR writing are described below.
1. Set the ICE bit in ICCR to 1. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX
in TSCR, according to the operating mode.
2. Read the BBSY flag in ICCR to confirm that the bus is free.
3. Set bits MST and TRS to 1 in ICCR to select master transmit mode.
4. Write 1 to BBSY and 0 to SCP. This changes SD A from high to low when SCL is high, and
generates the start condition.
5. Then IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt
request is sent to the CPU.
6. Write the data (slave address + R/W) to ICDR. With the I2C bus format (when the FS bit in
SAR or the FSX bit in SARX is 0), the first frame data following the start condition indicates
the 7-bit slave address and transmit/receive direction. As indicating the end of the transfer, and
so the IRIC flag is cleared to 0. After writing ICDR, clear IRIC continuously not to execute
other interr upt han dl i n g ro ut i n e. If one frame of data has been transmitted before the IRIC
clearing, it can not be determine the end of transmission. The master device sequentially sends
the transmission clock and the data written to ICDR using the timing shown in figure 15.5. The
selected slave device (i.e. the slave device with the matching slave address) drives SDA low at
the 9th transmit clock pulse and returns an acknowledge signal.
7. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
8. Read the ACKB bit in ICSR to confirm th at AC KB is cleared to 0. When the slave device has
not acknowledged (ACKB bit is 1), operate the step [12] to end transmission, and retry the
transmit operation.
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 252 of 412
REJ09B0142-0600
9. Write the transmit data to ICDR. As indicating the end of the transfer, and so the IRIC flag is
cleared to 0. Perform the ICDR write and the IRIC flag clearing sequentially, just as in the step
[6]. Transmission of the next frame is performed in synchronization with the internal clock.
10. When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted SCL is automatically fixed low in
synchronization with th e internal clock until the next transmit data is written.
11. Read the ACKB bit in ICSR. Confirm that the slave device has been acknowledged (ACKB bit
is 0). When there is data to be transmitted, go to the step [9] to continue next transmission.
When the slave device has not acknowledged (ACKB bit is set to 1), operate the step [12] to
end transmission.
12. Clear the IRIC flag to 0. And write 0 to BBSY and SCP in ICCR. This changes SDA from low
to high when SCL is high, and generates the stop condition.
SDA
(master output)
SDA
(slave output)
21 214365879
Bit 7
Slave address
Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
IRTR
ICDR
SCL
(master output)
Start condition generation
Data 1
Address + R/W
[4] Write BBSY = 1
and SCP = 0
(start condition
issuance)
[9] IRIC clearance
[9] ICDR write
[6] IRIC clearance
User processing
Slave address Data 1
R/W[7]
[5] A
[6] ICDR write
Normal
operation
ICDR writing
prohibited
Note: * Data write timing in ICDR
*
Figure 15.5 Master Transmit Mode Operation Timing Example
(MLS = WAIT = 0)
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 253 of 412
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15.4.3 Master Receive Operation
The data buffer of the I2C module can receive data consecutively since it consists of ICDRR and
ICDRS. However, if the completion of receiving the last data is delayed, there will be a contention
between the instruction to issue a stop condition and the SCl clock output to receive the next data,
and may generate unnecessary clocks or fix the output level of the SDA line as low. The switch
timing of the ACKB bit in the ICSR register should be controlled because the acknowledge bit
does not return ackno wl ed gement after recei ving the last data in master mode. These problems can
be avoided by using the WAIT function. Follow the flowchart shown below.
In master receive mode, the master device outputs the receive clock, receives data, and returns an
acknowledge signal. The slave device transmits data. The reception procedure and operations with
the wait function synchronized with the ICDR read operation to receive data in sequence are
shown below.
1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode, and set the
WAIT bit in ICMR to 1. Also clear the bit in ICSR to ACKB 0 (acknowledge data setting).
2. When ICDR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. In order to detect wait operation,
set the IRIC flag in ICCR must be cleared to 0. After reading ICDR, clear IRIC continuously
not to execute other interrupt handling routine. If one frame of data has been received before
the IRIC clearing, it can not be determine the end of reception.
3. The IRIC flag is set to 1 at the fall of the 8th receive clock pulse. If the IEIC bit in ICCR has
been set to 1, an interrupt request is sent to the CPU. SCL is automatically fixed low in
synchronization with the internal clock until the IRIC flag clearing. If the first frame is the last
receive data, execute the step [10] to halt reception.
4. Clear the IRIC flag to release from the Wait State. The master device outputs the 9th clock and
drives SDA at the 9th receive clock pulse to return an acknowledge signal.
5. When one frame of data has been received, the IRIC flag in ICCR and the IRTR flag in ICSR
are set to 1 at the rise of the 9th receive clock pulse. The master device outputs SCL clock to
receive next data.
6. Read ICDR.
7. Clear the IRIC flag to detect next wait operation. Data reception process from the step [5] to
[7] should be execut ed during one byte reception period after IRIC flag clearing in the step [4]
or [9] to release wait status.
8. The IRIC flags set to 1 at the fall of 8th receive clock pulse. SCL is automatically fixed low in
synchronization with th e internal clock until the IRIC flag clearing. If this frame is the last
receive data, execute the step [10] to halt reception.
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 254 of 412
REJ09B0142-0600
9. Clear the IRIC flag in ICCR to cancel wait operation. The master device outputs the 9th clock
and drives SDA at the 9th receive clock pulse to return an ackowledge signal. Data can be
received continuously by repeating the step [5] to [9].
10. Set the ACKB bit in ICSR to 1 so as to return “N o acknowledge” data. Also set the TRS bit in
ICCR to 1 to switch from receive mode to transmit mode.
11. Clear IRIC flag to 0 to release from the Wait State.
12. When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th
receive clock pulse.
13. Clear the WAIT bit to 0 to switch from wait mode to no wait mode. Read ICDR and the IRIC
flag to 0. Clearing of the IRIC flag should be after the WAIT = 0. If the WAIT bit is cleared to
0 after clearing the IRIC flag and then an instruction to issue a stop condition is executed, the
stop condition cannot be issued because the output level of the SDA line is fixed as low.
14. Clear the BBSY bit and SCP bit to 0. This changes SDA from low to high when SCL is high,
and generates the stop condition.
SDA
(master output)
SDA
(slave output)
21 214365879
Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
IRTR
ICDR
SCL
(master output)
Data 1
[1] TRS cleared to 0
WAIT set to 1
ACKB cleared to 0
[7] IRIC clearance
[6] ICDR read
(Data 1)
[4] IRIC clearance
[2] IRIC clearance
User processing
Bit 5 Bit 4 Bit 3
5439
Data 1 Data 2
[3] [5]
A
[2] ICDR read
(dummy read)
Master tansmit mode Master receive mode
A
Figure 15.6 Master Receive Mode Operation Timing Example (1)
(MLS = ACKB = 0, WAIT = 1)
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 255 of 412
REJ09B0142-0600
SDA
(master output)
SDA
(slave output)
21 214365879
Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
IRTR
ICDR
SCL
(master output)
Data 3
[9] IRIC clearance [7] IRIC clearance
[9] IRIC clearance
[6] ICDR read
(Data 3)
[7] IRIC clearance
User processing
98
Data 3 Data 4
[8] [5]
[8] [5]
AA
[6] ICDR read
(Data 2)
Bit 0
Data 2
Data 2Data 1
Figure 15.6 Master Receive Mode Operation Timing Example (2)
(MLS = ACKB = 0, WAIT = 1)
15.4.4 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The reception procedure and operations in slave
receive mode are described below.
1. Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR
according to the operating mode.
2. When the start condition outpu t by the master device is detected, the BBSY flag in ICCR is set
to 1.
3. When the slave address matches in the first frame following the start condition, the device
operates as the slave device specified by the master devi ce. If t he 8t h dat a bi t (R/ W) is 0, the
TRS bit in ICCR remains cleared to 0, and slave receive operation is performed.
4. At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an
acknowledge signal. At th e same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in
ICCR has been set to 1, an interrupt requ est is sen t to th e CPU. If th e RDRF internal flag has
been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag
has been set to 1 and ninth clock is received for the following data receival, the slave device
drives SCL low from the falling edge of the receive clock until data is read into ICDR.
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 256 of 412
REJ09B0142-0600
5. Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0.
Receive operations can be performed continuously by repeat ing steps [4] an d [5]. When SDA is
changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in
ICCR is cleared to 0.
SDA
(master output)
SDA
(slave output)
21 214365879
Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IRIC
ICDRS
ICDRR
RDRF
SCL
(master output)
Start condition issuance
SCL
(slave output)
Interrupt
request
generation
Address + R/W
Address + R/W
[5] ICDR read [5] IRIC clearance
User processing
Slave address
Data 1
[4]
A
R/W
High
Figure 15.7 Example of Slave Receive Mode Operation Timing (1)
(MLS = ACKB = 0)
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 257 of 412
REJ09B0142-0600
SDA
(master output)
SDA
(slave output)
214365879879
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 1 Bit 0
IRIC
ICDRS
ICDRR
RDRF
SCL
(master output)
SCL
(slave output)
Interrupt
request
generation
Interrupt
request
generation
Data
2
Data
2
Data
1
Data
1
[5] ICDR read [5] IRIC clearance
User processing
Data
2
Data
1[4] [4]
A
Figure 15.8 Example of Slave Receive Mode Operation Timing (2)
(MLS = ACKB = 0)
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 258 of 412
REJ09B0142-0600
15.4.5 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. The transmission procedure and operations
in slave transmit mode are described below.
1. Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR
according to the operating mode.
2. When the slave address matches in the first frame following detection of the start condition,
the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. At
the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an
interrupt request is sent to the CPU. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to
1, and the mode changes to slave transmit mode automatically. The TDRE internal flag is set
to 1. The slave device drives SCL low from the fall of the transmit clock until ICDR data is
written.
3. After clearing the IRIC flag to 0, write data to ICDR. The TDRE internal flag is cleared to 0.
The written data is transferred to ICDRS, and the TDRE internal flag and the IRIC and IRTR
flags are set to 1 again. After clearing the IRIC flag to 0, write the next data to ICDR. The
slave device sequentially sends the data written into ICDR in accordance with th e clock output
by the master device at the timing shown in figure 15.9.
4. When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of
the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, this slave device
drives SCL low from the fall of the transmit clock until data is written to ICDR. The master
device drives SDA low at the 9th clock pulse, and returns an acknowledg e signal. As this
acknowledge signa l is stor ed in the ACKB bit in ICSR, this bit can be used to determine
whether the transfer operation was performed normally. When the TDRE internal flag is 0, the
data written into ICDR is transferred to ICDRS, transmission is started, and the TDRE internal
flag and the IRIC and IRTR flags are set to 1 again.
5. To continue transmission, clear the IRIC flag to 0, then write the next data to be transmitted
into ICDR. The TDRE flag is cleared to 0.
Transmit operations can be performed continuously by repeating steps [4] and [5]. To end
transmission, write H'FF to ICDR. When SDA is changed from low to high when SCL is high, and
the stop condition is de tected, the BBSY flag in ICCR is cleared to 0.
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 259 of 412
REJ09B0142-0600
SDA
(slave output)
SDA
(master output)
SCL
(slave output)
21 21436587998
Bit
7
Bit
6
Bit
5
Bit
7
Bit
6
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
IRIC
ICDRS
ICDRT
TDRE
SCL
(master output)
Interrupt
request
generation
Interrupt
request
generation
Interrupt
request
generation
Slave receive mode Slave transmit mode
Data 1 Data 2
[3] IRIC
clearance
[5] IRIC
clearance
[3] ICDR
write
[3] ICDR
write
[5] ICDR
write
User processing
Data 1
Data 1 Data 2
Data 2
A
R/W
A
[3]
[2]
Figure 15.9 Example of Slave Tra nsmi t Mode Opera tion Timing
(MLS = 0)
S DATA DATA P
11n8
1 m
FS = 1 and FSX = 1
n: transfer bit count
(n = 1 to 8)
m: transfer frame count
(m ≥ 1)
Figure 15.10 I2C Bus Data Format (Serial Format)
15.4.6 Clock Synchronous Serial Format
Serial format is a non-addressing format that has no acknow ledge bit. Figure 15.10 shows this
format.
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 260 of 412
REJ09B0142-0600
15.4.7 IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figure 15.11 shows th e IRIC set timing and SCL control.
(a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait)
SCL
SDA
IRIC
User processing Clear IRIC Write to ICDR (transmit)
or read ICDR (receive)
1A
8
1
1
A
7
1897
(b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted)
SCL
SDA
IRIC
User processing Clear
IRIC
Clear
IRIC
Write to ICDR (transmit)
or read ICDR (receive)
SCL
SDA
IRIC
User processing
(c) When FS = 1 and FSX = 1 (synchronous serial format)
Clear IRIC Write to ICDR (transmit)
or read ICDR (receive)
8
89
8
71
8
71
Figure 15.11 IRIC Setting Timing and SCL Control
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 261 of 412
REJ09B0142-0600
15.4.8 Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latche d
internally. Figure 15.12 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
System clock
period
Sampling clock
C
DQ
Latch
C
DQ
Latch
SCL or
SDA input
signal Match
detector
Internal
SCL or
SDA
signal
Sampling
clock
Figure 15.12 Block Diagram of Noise Canceler
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 262 of 412
REJ09B0142-0600
15.4.9 Sample Flowcharts
Figures 15.13 to 15.16 show sample flowcharts for using the I2C bus interface in each mode.
Start
Initialize
Set MST = 1 and
TRS = 1 in ICCR
Write BBSY =1 and
SCP = 0 in ICCR
Write transmit data in ICDR
Clear IRIC in ICCR
No
No
Yes
Yes
Yes
Yes
No
No
[1] Initialization
[3] Select master transmit mode.
[4] Start condition issuance
[6] Set transmit data for the first byte
(slave address + R/W).
(After writing ICDR, clear IRIC
continuously)
[9] Set transmit data for the second and
subsequent bytes.
(After writing ICDR, clear IRIC
immediately)
[2] Test the status of the SCL and SDA lines.
[7] Wait for 1 byte to be transmitted.
[10] Wait for 1 byte to be transmitted.
[11] Test for end of tranfer
[12] Stop condition issuance
[8] Test the acknowledge bit,
transferred from slave device.
[5] Wait for a start condition
Read IRIC in ICCR
Read ACKB in ICSR
IRIC = 1?
ACKB = 0?
Transmit mode?
Write transmit data in ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
Read ACKB in ICSR
Clear IRIC in ICCR
End of transmission?
or ACKB = 1?
Write BBSY = 0 and
SCP = 0 in ICCR
End
Read BBSY in ICCR
BBSY = 0?
Yes
No
Read IRIC in ICCR
IRIC = 1?
Yes
No
Yes
No IRIC = 1?
Master receive mode
Figure 15.13 Sample Flowchart for Master Transmit Mode
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 263 of 412
REJ09B0142-0600
Master receive operation
Clear IRIC in ICCR
Yes
No
Yes
Yes
No
Yes
No
[1] Select receive mode.
[3] Wait for 1 byte to be received.
[4] Clear IRIC.
(to end the wait insertion)
[6] Read the receive data.
[9] Clear IRIC.
(to end the wait insertion)
[2] Start receiving. The first read
is a dummy read. After reading
ICDR, please clear IRIC immediately.
[7] Clear IRIC.
[10] Set acknowledge data for
the last reception.
[11] Clear IRIC.
(to end the wait insertion)
[12] Wait for 1 byte to be received.
[13] Clear wait mode.
Read receive data.
Clear IRIC.
(Note: After setting WAIT = 0,
IRIC should be cleared to 0.)
[14] Stop condition issuance.
[8] Wait for the next data to be
received.
[5] Wait for 1 byte to be received.
Read IRIC in ICCR
Read ICDR
Clear IRIC in ICCR
IRIC = 1?
IRIC = 1?
Yes
Last receive?
Last receive?
Set ACKB = 1 in ICSR
Set TRS = 1 in ICCR
Clear IRIC in ICCR
Read IRIC in ICCR
Set Wait = 0 in ICMR
Read ICDR
Clear IRIC in ICCR
Write BBSY = 0 and
SCP = 0 in ICCR
End
Set TRS = 0 in ICCR
Set ACKB = 0 in ICSR
Read IRIC in ICCR
IRIC = 1?
Yes
No
No
Read IRIC in ICCR
Clear IRIC in ICCR
No IRIC = 1?
Set WAIT = 1 in ICMR
Clear IRIC in ICCR
Read ICDR
Figure 15.14 Sample Flowchart for Master Receive Mode
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 264 of 412
REJ09B0142-0600
Start
Initialize
Set MST = 0
and TRS = 0 in ICCR
Set ACKB = 0 in ICSR
Read IRIC in ICCR
IRIC = 1?
Yes
No
Clear IRIC in ICCR
Read AAS and ADZ in ICSR
AAS = 1
and ADZ = 0?
Read TRS in ICCR
TRS = 0?
No
Yes
No
Yes
Yes
No
Yes
Yes
No
No
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Last receive?
Read ICDR
Read IRIC in ICCR
IRIC = 1?
Clear IRIC in ICCR
Set ACKB = 1 in ICSR
Read ICDR
Read IRIC in ICCR
Read ICDR
IRIC = 1?
Clear IRIC in ICCR
End
General call address processing
* Description omitted
Slave transmit mode
[1] Select slave receive mode.
[2] Wait for the first byte to be received (slave
address).
[3] Start receiving. The first read is a dummy read.
[4] Wait for the transfer to end.
[5] Set acknowledge data for the last reception.
[6] Start the last reception.
[7] Wait for the transfer to end.
[8] Read the last receive data.
Figure 15.15 Sample Flowchart for Slave Receive Mode
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 265 of 412
REJ09B0142-0600
Slave transmit mode
Write transmit data in ICDR
Read IRIC in ICCR
IRIC = 1?
Clear IRIC in ICCR
Clear IRIC in ICCR
Clear IRIC in ICCR
Read ACKB in ICSR
Set TRS = 0 in ICCR
End
of transmission
(ACKB = 1)?
Yes
No
No
Yes
End
[1]
[2]
[3]
Read ICDR [5]
[4]
[1] Set transmit data for the second and
subsequent bytes.
[2] Wait for 1 byte to be transmitted.
[3] Test for end of transfer.
[4] Set slave receive mode.
[5] Dummy read (to release the SCL line).
Figure 15.16 Sample Flowchart for Slave Transmit Mode
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 266 of 412
REJ09B0142-0600
15.5 Usage Notes
1. In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition. Note that SCL may not yet have gone low when
BBSY is cleared to 0.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when reading or writing to ICDR.
Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
ICDRT to ICDRS)
Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
ICDRS to ICDRR)
3. Table 15.5 shows the timing of SCL and SDA output in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Table 15.5 I2C Bus Timing (SCL and SDA Output)
Item Symbol Output Timing Unit Notes
SCL output cycle time tSCLO 28tcyc to 256tcyc ns
SCL output high pulse width tSCLHO 0.5tSCLO ns
SCL output low pulse width tSCLLO 0.5tSCLO ns
SDA output bus free time tBUFO 0.5tSCLO – 1tcyc ns
Start condition output hold time tSTAHO 0.5tSCLO – 1tcyc ns
Retransmission start condition output
setup time
tSTASO 1tSCLO ns
Stop condition output setup time tSTOSO 0.5tSCLO + 2tcyc ns
Data output setup time (master) tSDASO 1tSCLLO – 3tcyc ns
Data output setup time (slave) 1tSCLL – 3tcyc ns
Data output hold time tSDAHO 3tcyc ns
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle tcyc, as shown in table 20-4 in section 20, Electrical
Characteristics. Note that the I2C bus interface AC timing specifications will not be met with a
system clock frequency of less than 5 MHz.
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 267 of 412
REJ09B0142-0600
5. The I2C bus interface specification for the SCL rise time tsr is under 10 0 0 ns (3 0 0 ns fo r hi g h-
speed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds
the time determined by the input clock of the I2C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table in
table 15.6.
Table 15.6 Permissible SCL Rise Time (tsr) Values
Time Indication
IICX tcyc
Indication
I2C Bus
Specification
(Max.) φ =
5 MHz φ =
8 MHz φ =
10 MHz φ = 16
MHz
0 7.5tcyc Normal mode 1000 ns 1000 ns 937 ns 750 ns 468 ns
High-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns
1 17.5tcyc Normal mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns
High-speed mode 300 ns 300 ns 300 ns 300 ns 300 ns
6. The I2C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I2C bus interface SCL and SDA output timing is prescribed by tScyc and tcyc, as
shown in table 15.5. However, because of the rise and fall times, the I2C bus interface
specifications may not be satisfied at the maximum transfer rate. Table 15.7 shows output
timing calculations for different operating frequencies, including the worst-case influence of
rise and fall times. The values in the above table will v ary depending on the settings of the
IICX bit and bits CKS0 to CKS2. Depending on the frequency it may not be possible to
achieve the maximum transfer rate; therefore, whether or not the I2C bus interface
specifications are met must be determined in accordance with the actual setting conditions.
tBUFO fails to meet the I2C bus interface specifications at any frequency. The solution is either (a)
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I2C bus.
tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I2C bus interface
specifications for worst-case calculations of tSr/tSf. Possible solutions that should be
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose input timing permits this output timing for use as slave devices connected to the I2C
bus.
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 268 of 412
REJ09B0142-0600
Table 15.7 I2C Bus Timing (with Maximum Influence of tsr/tsf)
Time Indication (at Maximum Transfer Rate) [ns]
Item tcyc Indication
tsr/tsf
Influence
(Max.)
I2C Bus
Specifi-
cation
(Min.) φ =
5 MHz φ =
8 MHz φ =
10 MHz φ =
16 MHz
tSCLHO 0.5tSCLO (–tSr) Standard mode –1000 4000 4000 4000 4000 4000
High-speed mode –300 600 950 950 950 950
tSCLLO 0.5tSCLO (–tSf ) Standard mode –250 4700 4750 4750 4750 4750
High-speed mode –250 1300 1000*1 1000*1 1000*1 1000*1
tBUFO 0.5tSCLO –1tcyc Standard mode –1000 4700 3800*1 3875*1 3900*1 3938*1
( –tSr ) High-speed mode –300 1300 750*1 825*1 850*1 888*1
tSTAHO 0.5tSCLO –1tcyc Standard mode –250 4000 4550 4625 4650 4688
(–tSf ) High-speed mode –250 600 800 875 900 938
tSTASO 1tSCLO (–tSr ) Standard mode –1000 4700 9000 9000 9000 9000
High-speed mode –300 600 2200 2200 2200 2200
tSTOSO 0.5tSCLO + 2tcyc Standard mode –1000 4000 4400 4250 4200 4125
(–tSr ) High-speed mode –300 600 1350 1200 1150 1075
tSDASO 1tSCLLO*2 –3tcyc Standard mode –1000 250 3100 3325 3400 3513
(master) (–tSr ) High-speed mode –300 100 400 625 700 813
tSDASO 1tSCLL*2 –3tcyc Standard mode –1000 250 3100 3325 3400 3513
(slave) (–tSr ) High-speed mode –300 100 400 625 700 813
tSDAHO 3tcyc Standard mode 0 0 600 375 300 188
High-speed mode 0 0 600 375 300 188
Notes: 1. Does not meet the I2C bus interface specification
2. Calculated using the I2C bus specification values (standard mode: 4700 ns min.; high-
speed mode: 1300 ns min.).
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 269 of 412
REJ09B0142-0600
7. Note on ICDR Read at end of Master Reception
To halt reception after completion of a receive operation in master receive mode, set the TRS
bit to 1 and write 0 to BBSY and SCP in ICCR. This changes the SDA pin from low to high
when the SCL pin is high, and generates the stop condition. After this, receive data can be read
by means of an ICDR read, but if data remains in the buffer the ICDRS receive data will not be
transferred to ICDR, and so it will not be possible to read the second byte of data. If it is
necessary to read the second byte of data, issue the stop condition in master receive mode (i.e.
with the TRS bit cleared to 0). When reading the receive data, first confirm that the BBSY bit
in ICCR is cleared to 0, the stop condition has be en generated, and the bus has b e en released,
then read ICDR with TRS cleared to 0. Note that if the receive data (ICDR data) is read in the
interval between execution of the instruction for issuance of the stop condition (writing of 0 to
BBSY and SCP in ICCR) and the actual generation of the stop conditio n, the clock may not be
output correctly in subsequent master transmission.
8. Notes on Start Condition Issuance for Retransmission
Depending on the timing combination with the start condition issuance and the subsequently
writing data to ICDR, it may no t be possible to issue the retransmission and the data
transmission after retransmission condition issuance.
After start condition issuance is done and determined th e start condition, write the transmit
data to ICDR, as shown below. Figure 15.17 shows the timing of start co ndition issuance for
retransmission, and the timing for subsequently writing data to ICDR, together with the
corresponding flowchart.
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 270 of 412
REJ09B0142-0600
SDA
IRIC
SCL
ACK Bit 7
Data output
[3] (Restart) Start condition instruction issuance
[4] IRIC determination
[5] ICDR write (next transmit data)
[2] Detemination of SCL = Low
[1] IRIC determination
Start condition
(retransmission)
IRIC = 1?
Yes
Clear IRIC in ICSR
Read SCL pin
Write transmit data to ICDR
Write BBSY = 1,
SCP = 0 (ICSR)
[1]
[1] Wait for end of 1-byte transfer
[2] Determine whether SCL is low
[3] Issue restart condition instruction for transmission
[4] Determine whether start condition is generated or not
[5] Set transmit data (slave address + R/W)
[2]
[3]
[4]
[5]
Yes
Yes
No
No
IRIC = 1?
Yes
SCL = Low?
Start condition
issuance?
No
No
Other processing
Note: Program so that processing from [3] to [5]
is executed continuously.
9
Figure 15.17 Flowchart and Timing of Start Condition Instruction Issuance for
Retransmission
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 271 of 412
REJ09B0142-0600
• Notes on WAIT Function
Conditions to cause this phenomenon
When both of the following conditions are satisfied, the clock pulse of the 9th clock could
be outputted continuously in master mode using the WAIT function due to the failure of
the WAIT insertion after the 8th clock fall.
(1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode
(2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock
and the fall of the 8th clock.
Er ror phenomenon
Normally, WAIT state will be cancelled by clearing the IRIC flag bit from 1 to 0 after the
fall of the 8th clock in WAIT state. In this case, if the IRIC flag bit is cleared between the
7th clock fall and the 8th clock fall, the IRIC flag clear- data will be retained internally.
Therefore, the WAIT state will be cancelled right after WAIT insertion on 8th clock fall.
Restrictions
Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2
through BC0 shou ld be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th
clock.
If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC
counter is turned to 1 or 0, please confirm the SCL pins are in the low state after the
counter value of BC2 through BC0 is turn ed to 0, and clear the IRIC flag. (See figure
15.18.)
SCL
BC2 to BC0
19
A Transmit/receive data Transmit/receive
data
A
23 19
SCL =
'L' confirm
IRIC clear
IRIC flag clear availableIRIC flag clear available
IRIC flag clear unavailable
When BC2 to BC0 ≥ 2
clear IRIC
2345678
SDA
7065 7654321 0
IRIC
(operation
example)
Figure 15.18 IRIC Flag Clear Timing on WAIT Operation
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 272 of 412
REJ09B0142-0600
• Notes on TRS Bit Setting and ICDR Register Access
Conditions to cause this failure
Low-fixation of the SCL pins is cancelled incorrectly when the following conditions are
satisfied.
Master mode:
Figure 15.19 show s the notes on ICDR reading (TRS = 1) in master mode.
(a) When previously received 2-byte data remains in ICDR unread (ICDRS are full).
(b) Reads ICDR register after switching to transmit mode (TRS = 1). (RDRF = 0 state)
(c) Sets to receive mode (TRS = 0), after transmitting the first frame of issued start
condition by master mode.
Slave mode:
Figure 15.20 shows the notes on ICDR writing (TRS = 0) in slave mode.
(a) Writes ICDR register in receive mode (TRS = 0), after entering the start cond ition by
slave mode (TDRE = 0 state).
(b) Address match with the first frame, receive 1 by R/W bit, and switches to transmit
mode (TRS = 1).
When these conditions are satisfied, the low fixation of the SCL pins is cancelled without
ICDR register access after the first frame is transferred.
SDA
SCL
TRS bit
RDRF bit
ICDRS data full
(c) TRS = 0
(b) RDRF = 0
(a) ICDRS data full
ICDR read TRS = 0 setting
Stop condition Start condition
DataAAddressA
89 123456789 123
Cancel condition of SCL =
Low fixation is set.
Along with ICDRS → ICDRR transfer
Detection of 9th clock rise
(TRS = 1)
Figure 15.19 Notes on ICDR Reading with TRS = 1 Setting in Master Mode
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 273 of 412
REJ09B0142-0600
SDA
SCL
TRS bit
TDRE bit
(b) TRS = 1
(a) TDRE = 0
TRS = 0 setting ICDR write Automatic TRS = 1 setting by
receiving R/W = 1
Start conditionStop condition
DataAAddressA
89 1234567891234
Cancel condition of SCL =
Low fixation is set.
Along with ICDRT → ICDRR transfer
Figure 15.20 Notes on ICDR Writing with TRS = 0 Setting in Slave Mode
Restriction
Please carry out the following countermeasures when transmitting/receiving via the IIC bus
interface module.
(1) Please read the ICDR registers in receive mode, and write them in transmit mode.
(2) In receiving operation with master mode, please issue the start condition after clearing
the internal flag of the IIC bus interface module, using CLR3 to CLR0 bit of the
DDCSWR register on bus-free state (BBSY = 0).
Section 15 I2C Bus Interface (IIC)
Rev. 6.00 Mar. 24, 2006 Page 274 of 412
REJ09B0142-0600
Section 16 A/D Converter
Rev. 6.00 Mar. 24, 2006 Page 275 of 412
REJ09B0142-0600
Section 16 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight
analog input channels to be selected. The block diagram of the A/D converter is shown in figure
16.1.
16.1 Features
• 10-bit resolution
• Eight input channels (four channels for the 42-pin version)
• Conversion time: at least 4.4 µs per channel (at 16 MHz operation)
• Two operating modes
Single mode: Single-channel A/ D c o nversion
Scan mode : Continuous A/D conversion on 1 to 4 channels
• Four data registers
Conversion results are held in a 16-bit data register for each channel
• Sample and hold function
• Two conversion start methods
Software
External trigger signal
• Interrupt request
An A/D conversion en d interrupt request (ADI) can be generated
Section 16 A/D Converter
Rev. 6.00 Mar. 24, 2006 Page 276 of 412
REJ09B0142-0600
Module data bus
Control circuit
Internal data bus
10-bit D/A
Comparator
+
Sample-and-
hold circuit ADI
interrupt
Bus interface
Successive approximations
register
Analog multiplexer
A
D
C
S
R
A
D
C
R
A
D
D
R
D
A
D
D
R
C
A
D
D
R
B
A
D
D
R
A
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
[Legend]
ADCR: A/D control register
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
ADDRD: A/D data register D
Note: AN4, AN5, AN6, and AN7 do not exist in the 42-pin version.
ADTRG
φ/4
φ/8
AVCC
*
Figure 16.1 Block Diagram of A/D Converter
Section 16 A/D Converter
Rev. 6.00 Mar. 24, 2006 Page 277 of 412
REJ09B0142-0600
16.2 Input/Output Pins
Table 16.1 summarizes the input pins used by the A/D converter. The eight analog input pins are
divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input
pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc pin is the power supply pin for the
analog block in the A/D converter.
Table 16.1 Pin Configuration
Pin Name Symbol I/O Function
Analog power supply pin AVCC Input Analog block power supply pin
Analog input pin 0 AN0 Input
Analog input pin 1 AN1 Input
Analog input pin 2 AN2 Input
Analog input pin 3 AN3 Input
Group 0 analog input pins
Analog input pin 4 AN4 Input
Analog input pin 5 AN5 Input
Analog input pin 6 AN6 Input
Analog input pin 7 AN7 Input
Group 1 analog input pins
A/D external trigger input pin ADTRG Input External trigger input pin for starting A/D
conversion
Section 16 A/D Converter
Rev. 6.00 Mar. 24, 2006 Page 278 of 412
REJ09B0142-0600
16.3 Register Description
The A/D converter has the following registers.
• A/D data register A (ADDRA )
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD )
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
16.3.1 A/D Data Registers A to D (ADDRA to ADDRD)
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are
shown in table 16.2.
The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.
The data bus between the CPU a nd the A/D con verter is 8 bits wide. The up per byte can be read
directly from the CPU, however the lower byte shou ld be read via a temporary register. The
temporary register contents are transferred from the ADDR when the up per byte data is read.
Therefore, byte access to ADDR should be done by readin g the upper byte first then the lower
one. Word access is also possible. ADDR is initialized to H'0000.
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Group 0 Group 1 A/D Data Register to be Stored Results of A/D Conversion
AN0 AN4 ADDRA
AN1 AN5 ADDRB
AN2 AN6 ADDRC
AN3 AN7 ADDRD
Section 16 A/D Converter
Rev. 6.00 Mar. 24, 2006 Page 279 of 412
REJ09B0142-0600
16.3.2 A/D Control/Status Register (ADCSR)
ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Bit Bit Name
Initial
Value R/W Description
7 ADF 0 R/W A/D End Flag
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all the channels
selected in scan mode
[Clearing condition]
When 0 is written after reading ADF = 1
6 ADIE 0 R/W A/D Interrupt Enable
A/D conversion end interrupt (ADI) request enabled by
ADF when 1 is set
5 ADST 0 R/W A/D Start
Setting this bit to 1 starts A/D conversion. In single
mode, this bit is cleared to 0 automatically when
conversion on the specified channel is complete. In
scan mode, conversion continues sequentially on the
specified channels until this bit is cleared to 0 by
software, a reset, or a transition to standby mode.
4 SCAN 0 R/W Scan Mode
Selects single mode or scan mode as the A/D
conversion operating mode.
0: Single mode
1: Scan mode
3 CKS 0 R/W Clock Select
Selects the A/D conversions time
0: Conversion time = 134 states (max.)
1: Conversion time = 70 states (max.)
Clear the ADST bit to 0 before switching the
conversion time.
Section 16 A/D Converter
Rev. 6.00 Mar. 24, 2006 Page 280 of 412
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Bit Bit Name
Initial
Value R/W Description
2
1
0
CH2
CH1
CH0
0
0
0
R/W
R/W
R/W
Channel Select 0 to 2
Select analog input channels.
When SCAN = 0 When SCAN = 1
000: AN0 000: AN0
001: AN1 001: AN0 to AN1
010: AN2 010: AN0 to AN2
011: AN3 011: AN0 to AN3
100: AN4 100: AN4
101: AN5 101: AN4 to AN5
110: AN6 110: AN4 to AN6
111: AN7 111: AN4 to AN7
AN4, AN5, AN6, and AN7 do not exist in the 42-pin
version.
16.3.3 A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit Bit Name
Initial
Value R/W Description
7 TRGE 0 R/W Trigger Enable
A/D conversion is started at the falling edge and the
rising edge of the external trigger signal (ADTRG)
when this bit is set to 1.
The selection between the falling edge and rising edge
of the external trigger pin (ADTRG) conforms to the
WPEG5 bit in the interrupt edge select register 2
(IEGR2).
6 to 1 — All 1 — Reserved
These bits are always read as 1.
0 — 0 R/W Reserved
Do not set this bit to 1, though the bit is
readable/writable.
Section 16 A/D Converter
Rev. 6.00 Mar. 24, 2006 Page 281 of 412
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16.4 Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes; single mode and scan mode. When changing the operating mode or analog input
channel, in order to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The
ADST bit can be set at the same time as the operating mode or analog input chann e l is changed.
16.4.1 Single Mode
In single mode, A/D conversion is performed once for the analog input on the specified single
channel as follows:
1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to software or
external trigger inpu t.
2. When A/D conversion is completed, the result is transferred to the corresponding A/D data
register to the channel.
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion. When A/D conversion ends, the ADST
bit is automatically cleared to 0 and th e A/D converter enters the wait state.
16.4.2 Scan Mode
In scan mode, A/D conversion is performed sequentially for the analog input on the specified
channels (four channels maximum) as follows:
1. When the ADST bit is set to 1 by software, or external trigger input, A/D conversion starts on
the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1).
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the A/D data register corresponding to each channel.
3. When conversion of all the selected channels is completed, the ADF flag in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first
channel in the group starts again.
4. The ADST bit is not automatically cleared to 0. Steps [2] to [3] are repeated as long as the
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops.
Section 16 A/D Converter
Rev. 6.00 Mar. 24, 2006 Page 282 of 412
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16.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold cir cuit. The A/D converter samples the analog
input when th e A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then
starts conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 shows th e A/D
conversion time.
As indicated in figure 16.2, the A/D conversion time includes tD and the input sampling time. The
length of tD varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 16.3.
In scan mode, the values given in table 16.3 apply to the first conversion time. In the second and
subsequent conversions, the conversion time is 128 states (fixed) when CKS = 0 and 66 states
(fixed) when CKS = 1.
(1)
(2)
φ
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
t
D
: A/D conversion start delay
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 16.2 A/D Conversion Timing
Section 16 A/D Converter
Rev. 6.00 Mar. 24, 2006 Page 283 of 412
REJ09B0142-0600
Table 16.3 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Item Symbol Min Typ Max Min Typ Max
A/D conversion start delay tD 6 — 9 4 — 5
Input sampling time tSPL — 31 — — 15 —
A/D conversion time tCONV 131 — 134 69 — 70
Note: All values represent the number of states.
16.4.4 External Trigger Input Timing
The A/D conversion can also b e started by an external trigger input. When the TRGE bit is set to 1
in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG
input pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both
single and scan modes, are the same as when the bit ADST has been set to 1 by software. Figure
16.3 shows the timing.
φ
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 16.3 External Trigger Input Timing
Section 16 A/D Converter
Rev. 6.00 Mar. 24, 2006 Page 284 of 412
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16.5 A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitio ns are given below.
• Resolution
The number of A/D converter digital output codes
• Q uantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes fro m th e minimum voltage value 000 0000000 to 0000000001
(see figure 16.5).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from 1111111110 to 1111111111 (see figure 16.5).
• Nonlinearity error
The error with respect to the ideal A/D conversion character istics between zero voltage and
full-scale voltage. Does not include offset error, full-scale error, or quantization error.
• Absolute accuracy
The deviation between the digital value and the analog input value. Includes offset error, full-
scale error, quantization error, and nonlinearity error.
Section 16 A/D Converter
Rev. 6.00 Mar. 24, 2006 Page 285 of 412
REJ09B0142-0600
111
110
101
100
011
010
001
000
1
8
2
8
6
8
7
8
FS
Quantization error
Digital output
Ideal A/D conversion
characteristic
Analog
input voltage
3
8
4
8
5
8
Figure 16.4 A/D Conversion Accuracy Definitions (1)
FS
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Analog
input voltage
Offset error
Actual A/D conversion
characteristic
Full-scale error
Figure 16.5 A/D Conversion Accuracy Definitions (2)
Section 16 A/D Converter
Rev. 6.00 Mar. 24, 2006 Page 286 of 412
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16.6 Usage Notes
16.6.1 Permissible Signal Source Impedance
This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal
for which the signal source impedance is 5 kΩ or less. This specification is provided to enable the
A/D converter's sample-and-hold circuit input cap acitance to be charged within the sampling time;
if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it may not be
possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with
a large capacitance provided extern ally, the input load will essentially comprise on ly the internal
input resistance of 10 kΩ, and the signal source impedance is ignored. However, as a low-pass
filter effect is obtained in this case, it may not be possible to follow an analog signal with a large
differential coefficient (e.g., 5 mV/µs or greater) (see fig ure 16.6 ). Whe n conve rting a high-speed
analog signal or converting in scan mode, a lo w-impedance buffer should be inserted.
16.6.2 Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute accuracy. Be sure to make the connection to an electrically stable GND.
Care is also required to ensure that filter circuits do not interfere with digital signals or act as
antennas on the mounting board.
20 pF
10 kΩ
C
in
=
15 pF
Sensor output
impedance
to 5 kΩ
This LSI
Low-pass
filter
C to 0.1 µF
Sensor input
A/D converter
equivalent circuit
Figure 16.6 Analog Input Circuit Example
Section 17 EEPROM
Rev. 6.00 Mar. 24, 2006 Page 287 of 412
REJ09B0142-0600
Section 17 EEPROM
This LSI has an on-chip 512-byt e EEPROM. The block di agram of the EEPROM is sho wn in
figure 17.1.
17.1 Features
• Two writing methods:
1-byte write
Page write: Page size 8 bytes
• Three reading methods:
Current address read
Random address read
Sequential read
• Acknowledge polli n g po ssi ble
• Write cycle time:
10 ms (power supply voltage Vcc = 2.7 V or more)
• Write/Erase Endurance:
104 cycles/byte (byte write mode), 105 cycles/page (page write mode)
• Data retention:
10 years after the write cycle of 10 4 cycles (page write mode)
• Interface with the CPU
I2C bus interface (complies with the standard of Philips Corporation)
Device code 1010
Sleep address code can be changed (initial value: 000))
The I2C bus is open to the outside, so the EEPROM can be directly accessed from the outside.
Section 17 EEPROM
Rev. 6.00 Mar. 24, 2006 Page 288 of 412
REJ09B0142-0600
H'0000
H'01FF
H'FF09
H'FF10
ESAR
SDA
EEPROM Data bus
EEPROM Key
register (EKR)
Key control circuit
I
2
C bus interface
control circuit
Address bus
Y decoder
Y-select/
Sense amp.
Memory
array
User area
(512 bytes)
Slave address
register
Power-on reset Booster circuit
EEPROM module
ESAR: Register for referring the slave address
(specifies the slave address of the memory array)
[Legend]
X decoder
SCL
Figure 17.1 Block Diagram of EEPROM
Section 17 EEPROM
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17.2 Input/Output Pins
Pins used in the EEPROM are listed in tab le 17.1.
Table 17.1 Pin Configuration
Pin name Symbol Input/
Output Function
Serial clock
pin
SCL Input The SCL pin is used to control serial input/output data timing.
The data is input at the rising edge of the clock and output at
the falling edge of the clock. The SCL pin needs to be pulled
up by resistor as that pin is open-drain driven structure of the
I2C pin. Use proper resistor value for your system by
considering VOL, IOL, and the CIN pin capacitance in section
20.2.2, DC Characteristics and in section 20.2.3, AC
Characteristics. Maximum clock frequency is 400 kHz.
Serial data
pin
SDA Input/
Output
The SDA pin is bidirectional for serial data transfer. The SDA
pin needs to be pulled up by resistor as that pin is open-drain
driven structure. Use proper resistor value for your system by
considering VOL, IOL, and the CIN pin capacitance in section
20.2.2, DC Characteristics and in section 20.2.3, AC
Characteristics. Except for a start condition and a stop
condition which will be discussed later, the high-to-low and
low-to-high change of SDA input should be done during SCL
low periods.
17.3 Register Description
The EEPROM has a following register.
• EEPROM key register (EKR)
17.3.1 EEPROM Key Register (EKR)
EKR is an 8-bit readable/writable reg ister, which changes the slave address code written in the
EEPROM. The slave address code is changed by writing H'5F in EKR and then writing either of
H'00 to H'07 as an address code to the H'FF09 address in the EEPROM by the by te write method.
EKR is initialized to H'FF.
Section 17 EEPROM
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17.4 Operation
17.4.1 EEPROM Interface
This LSI has a multi-chip structure with two internal chips of F-ZTAT™ HD64F3664 and 512-
byte EEPROM.
The EEPROM interface is the I2C bus interface. This I2C bus is open to the outside, so the
communication with the external devices connected to the I2C bus ca n be made.
17.4.2 Bus Format and Timing
The I2C bus format and the I2C bus timing follow section 15.4.1, I2C Bus Data Format. The bus
formats specific for the EEPROM are the following two.
1. The EEPROM address is configured of two bytes, the write data is transferred in the order of
upper address and lower address from each MSB side.
2. The write data is transmitted from the MSB side.
The bus format and bus timi ng of the EEPROM are shown in figure 17.2.
R/WACK
SCL
SDA
Start
condition
Slave address Upper memory
address
lower memory
address Data Data
Stop
conditon
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read),
ACK: acknowledge
ACK ACKACK ACK
112345678
A15 A8 A7 A0 D7 D0 D7 D0
9189 189 189 8 9
Figure 17.2 EEPROM Bus Format and Bus Timing
Section 17 EEPROM
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17.4.3 Start Condition
A high-to-low transition of the SDA input with the SCL input high is needed to generate the start
condition for starting read, write operation.
17.4.4 Stop Condition
A low-to-high transition of the SDA input with the SCL input high is needed to generate the stop
condition for stopping read, write operation.
The standby operation starts after a read sequence by a stop condition. In the case of write
operation, a stop condition terminates the write data inputs and place the device in an internally-
timed write cycle to the memories. After the internally-timed write cycle (tWC) which is specified
as tWC, the device enters a standby mode.
17.4.5 Acknowledge
All address data and serial data such as read data and write data are transmitted to and from in 8-
bit unit. The acknowledgement is the signal that in dicates that this 8-bit data is normally
transmitted to and from.
In the write operation, EEPROM sends "0" to acknowledge in the ninth cycle after receiving the
data. In the read operation, EEPROM sends a read data following the acknowledgement after
receiving the data. After sending read data, the EEPROM enters the bus open state. If the
EEPROM receives "0" as an acknowledgement, it sends read data of the next address. If the
EEPROM does not receive acknowledgement "0" and receives a following stop condition, it stops
the read operation and enters a standby mode. If the EEPROM receives neither acknowledgement
"0" nor a stop condition, the EEPROM keeps bus open without sending read data.
Section 17 EEPROM
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17.4.6 Slave Addressing
The EEPROM device receives a 7-bit slave address and a 1-bit R/W code followin g the generation
of the start condition s. Th e EEPROM enables the chip for a read or a write operation with this
operation.
The slave address consists of a former 4-bit device code and latter 3-bit slave address as shown in
table 17.2. The device code is used to distinguish device type and this LSI uses "1010" fixed code
in the same manner as in a general-purpose EEPROM. The slave address code selects one device
out of all devices with device code 1010 (8 devices in maximum) which are connected to the I2C
bus. This means that the device is selected if the inputted slave address code received in the order
of A2, A1, A0 is equal to the corresponding slave address reference register (ESAR).
The slave address code is stored in the address H'FF09 in the EEPROM. It is transferred to ESAR
from the slave address register in the memory array during 10 ms after the reset is released. An
access to the EEPROM is not allowed during transfer.
The initial value of the slave address code written in the EEPROM is H'00. It can be written in the
range of H'00 to H'07. Be sure to write the data by the byte write method.
The next one bit of the slave address is the R/W code. 0 is for a write and 1 is for a read.
The EEPROM turns to a standby state if the device code is not "1010" or slave address code
doesn’t coincide.
Table 17.2 Slave Addresses
Bit
Bit name Initial
Value Setting
Value
Remarks
7 Device code D3 1
6 Device code D2 0
5 Device code D1 1
4 Device code D0 0
3 Slave address code A2 0 A2 The initial value can be changed
2 Slave address code A1 0 A1 The initial value can be changed
1 Slave address code A0 0 A0 The initial value can be changed
Section 17 EEPROM
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17.4.7 Write Operations
There are two types write operations; byte write operation and page write operation. To initiate
the write operation, input 0 to R/W code following the slave address.
1. Byte Write
A write operation requires an 8-bit data of a 7-bit slave address with R/W code = "0". Then
the EEPROM sends acknowledgement "0" at the ninth bit. This enters the write mode. Then,
two bytes of the memory address are received from the MSB side in the order of upper and
lower. Upon receipt of one-byte memory address, the EEPROM sends acknowledgement "0"
and receives a following a one-byte write data. After receipt of write data, the EEPROM sends
acknowledgement "0". If the EEPROM receives a stop condition, the EEPROM enters an
internally controlled write cycle and terminates receipt of SCL and SDA inputs until
completion of the write cycle. The EEPROM returns to a standby mode after completion of
the write cycle.
The byte write operation is shown in figure 17.3.
R/WACK
SCL
SDA
ACK ACKACK
112345678
A15 A8 A7 A0 D7 D0
9189 189 89
Start
condition
Upper memory
address
lower memory
address Write DataSlave address
Stop
conditon
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read)
ACK: acknowledge
Figure 17.3 Byte Write Operation
2. Page Write
This LSI is capable of the page write operation which allows any number of bytes up to 8
bytes to be written in a single write cy cle. The write data is input in the same sequence as the
byte write in the order of a start condition, slave address + R/W code, memory address (n), and
write data (Dn) with every ninth bit acknowledgement "0" output. The EEPROM enters the
page write operation if the EEPROM receives more write data (Dn+1) is input instead of
receiving a stop condition after receiving the write data (Dn). LSB 3 bits (A2 to A0) in the
EEPROM address are automatically incremented to be the (n+1) address upon receiving write
data (Dn+1). Thus the write data can be received sequentially.
Section 17 EEPROM
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Addresses in the page are incremented at each receipt of the write data and the write data can
be input up to 8 bytes. If the LSB 3 bits (A2 to A0) in the EEPROM address reach the last
address of the page, the address w ill roll over to the first address of the same page. When the
address is rolled over, write data is received twice or more to the same address, however, the
last received data is valid. At the receipt of the stop condition, write data reception is
terminated and the write operation is en tered.
The page write operati o n is shown in figure 17.4.
SCL
SDA
112345678
A15 A8 A7 A0 D7 D0 D7 D0
9189 189 89
R/WACK ACK ACKACK ACK
Start
condition
Upper memory
address
lower memory
address Write Data Write Data
Stop
conditon
[Legend]
Slave address
R/W: R/W code (0 is for a write and 1 is for a read),
ACK: acknowledge
Figure 17.4 Page Write Operation
17.4.8 Acknowledge Polling
Acknowledge polling feature is used to show if the EEPROM is in an internally-timed write cycle
or not. This feature is initiated by the input of the 8-bit slave add ress + R/W code following the
start condition during an internally-timed write cycle. Acknowledge polling will operate R/W
code = "0". The ninth acknowledgement judges if the EEPROM is an internally-timed write cycle
or not. Acknowledgement "1" shows the EEPROM is in a internally-timed write cycle and
acknowledgement "0" shows the internally-timed write cycle has been completed. The
acknowledge polling starts to function after a write d ata is input, i.e., when the stop condition is
input.
Section 17 EEPROM
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17.4.9 Read Operation
There a re three read operations; current addre ss read, random address read, and sequential read.
Read operations are initiated in the same way as write operations with the exception of R/W = 1.
1. Current Address Read
The internal address coun ter maintains the (n+1) address that is made by the last address (n)
accessed during the last read or write operation, with incremented by one. Current address
read accesses the (n+1) address kept by the internal address counter.
After receiving in the order of a start condition and the slave address + R/W code (R/W = 1),
the EEPROM outputs the 1-byte data of the (n+1) address from the most significant bit
following acknowledgement "0". If the EEPROM receives in the order of acknowledgement
"1" and a following stop condition, the EEPROM stops the read operation and is turned to a
standby state.
In case the EEPROM has accessed the last address H'01FF at pre vio us read operation, t he
current address will roll over and returns to zero address. In case the EEPROM has accessed
the last address of the page at previous write operation, the current address will roll over within
page addressing and returns to the first address in the same page.
The current addr ess is va lid while power is on. The current address after power on will be
undefined. After power is turned on, define the address by the random address read operation
described below is necessary.
The current address read operation is shown in figure 17.5.
R/WACK
SCL
SDA D7 D0
ACK
1123456789 89
Start
condition Stop
conditon
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read)
ACK: acknowledge
Read Data
Slave address
Figure 17.5 Current Address Read Operation
Section 17 EEPROM
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2. Random Address Read
This is a read operation with defined read address. A random address read requires a dummy
write to set read address. The EEPROM receives a start condition, slave address + R/W code
(R/W = 0), memory address (upper) and memory address (lower) sequentially. The EEPROM
outputs acknowledgement "0" after receiving memory address (lower) then enters a current
address read with receiving a start condition again. The EEPROM outputs the read data of the
address which was defined in the dummy write operation. After receiving acknowledgement
"1" and a following stop condition, the EEPROM stops th e random read operation and returns
to a standby state.
The random address read operation is shown in figure 17.6.
SDA
A15 A8 A7 A0 D7 D0
R/WACK
SCL
ACK ACK
1123456789 189 89 1123456789 89
RACK ACK
Start
condition Start
condition
Upper memory
address
lower memory
address
Stop
conditon
[Legend]
Slave address Slave address Read Data
R/W: R/W code (0 is for a write and 1 is for a read),
ACK: acknowledge
Figure 17.6 Random Address Read Operation
3. Sequential Read
This is a mode to read the data sequentially. Data is sequential read by either a current address
read or a random address read. If th e EEPROM receives acknowledgement "0" after 1-byte
read data is output, the read address is incremented and the next 1-byte read data are coming
out. Data is output sequentially by incrementing addresses as long as the EEPROM receives
acknowledgement "0 " after the data is output. The address will roll over and returns address
zero if it reaches the last address H'01FF. The sequential read can be continued after roll over.
The sequential read is terminated if the EEPROM receives acknowledgement "1" and a
following stop condition as the same manner as in the random address read.
The condition of a sequential read when the current address read is used is shown in figure
17.7.
Section 17 EEPROM
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SCL
SDA
112345678
D7 D0 D7 D0
98918
9
R/WACK ACK ACK
Start
condition Stop
conditon
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read)
ACK: acknowledge
Read DataRead DataSlave address
····
Figure 17.7 Sequential Read Operation (when current address read is used)
17.5 Usage Notes
17.5.1 Data Protection at VCC On/Off
When VCC is turned o n or o ff, t he data mig ht be dest r oye d b y mal fu ncti o n. Be careful of the
notices describe d bel o w to pr event t he data to be destr oyed.
1. SCL and SDA should be fixed to VCC or VSS during VCC on/off.
2. VCC should be turned off after the EEPROM is placed in a standby state.
3. When VCC is turned on from the intermediate level, malfunction is caused, so VCC should be
turned on from the ground level (VSS).
4. VCC turn on speed should be longer than 10 us.
17.5.2 Write/Erase Endurance
The endurance is 105 cycles/page (1% cumulative failure rate) in case of page programming and
104 cycles/byte in case of byte programming. The data retention time is more than 10 years when a
device is page-programmed less than 104 cycles.
Section 17 EEPROM
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17.5.3 Noise Suppression Time
This EEPROM has a noise suppression function at SCL and SDA inputs, that cuts noise of width
less than 50 ns. Be careful not to allow noise of width more than 50 ns because the noise of with
more than 50 ms is recognized as an active pulse.
Section 18 Power Supply Circuit
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Section 18 Power Supply Circuit
This LSI incorporates an internal power supply step- d ow n ci rcui t . Use of t hi s circuit e na ble s the
internal power supply to be fixed at a constant level of approximately 3.0 V, independently of th e
voltage of the power supply connected to the external VCC pin. As a result, the current consumed
when an external power supply is used at 3.0 V or above can be held down to virtually the same
low level as when used at approximately 3.0 V. If the external power supply is 3.0 V or below, the
internal voltage will be practically the same as the external voltage. It is, of course, also possible
to use the same level of external power supply voltage and internal power supply voltage without
using the internal pow er supply step-down circuit.
18.1 When Using Internal Power Supply Step-Down Circuit
Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0 .1
µF between VCL and VSS, as shown in figure 18.1. The internal step-down circuit is made effective
simply by adding this external circuit. In the external circuit interface, the external power supply
voltage connected to VCC and the GND potential connected to VSS are the reference levels. For
example, for port input/output levels, the VCC level is the reference for the high level, and the VSS
level is that for the low lev e l. The A/D conver ter analog power supply is not affected by the
internal step-down circuit.
V
CL
V
SS
Internal
logic
Step-down circuit
Internal
power
supply
Stabilization
capacitance
(approx. 0.1 µF)
V
CC
V
CC
= 3.0 to 5.5 V
Figure 18.1 Power Supply Connection when Internal Step-Down Circuit is Used
Section 18 Power Supply Circuit
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18.2 When Not Using Internal Power Supply Step-Down Circuit
When the internal power supply step-down circu it is not used, connect the external power supply
to the VCL pin and VCC pin, as shown in f igur e 18.2. The external power supply is then input directly
to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V.
Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V)
is input.
V
CL
V
SS
Internal
logic
Step-down circuit
Internal
power
supply
V
CC
V
CC
= 3.0 to 3.6 V
Figure 18.2 Power Supply Connection when Internal Step-Down Circuit is Not Used
Section 19 List of Registers
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Section 19 List of Registers
The register list gives information on the on-chip I/O register ad dresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1. Register addresses (address order)
• Registers are listed from the lower allocation addresses.
• Registers are classified by functional modules.
• The data bus width is indicated.
• The number of access states is indicated.
2. Register bits
• Bit configurations of the registers are described in the same order as the register addresses.
• Reserved bits are indicated by in the bit name column.
• When registers consist of 16 bits, bits are described from the MSB side.
3. Register states in each operating mode
• Register states are described in the same order as the register addresses.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
Section 19 List of Registers
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19.1 Register Addresses (Address Order)
The data bus width indicat es t he numbers of bits by which the regist er is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Abbre-
viation
Bit No.
Address
Module
Name
Data
Bus
Width
Access
State
Timer mode register W TMRW 8 H'FF80 Timer W 8 2
Timer control register W TCRW 8 H'FF81 Timer W 8 2
Timer interrupt enable register W TIERW 8 H'FF82 Timer W 8 2
Timer status register W TSRW 8 H'FF83 Timer W 8 2
Timer I/O control register 0 TIOR0 8 H'FF84 Timer W 8 2
Timer I/O control register 1 TIOR1 8 H'FF85 Timer W 8 2
Timer counter TCNT 16 H'FF86 Timer W 16*1 2
General register A GRA 16 H'FF88 Timer W 16*1 2
General register B GRB 16 H'FF8A Timer W 16*1 2
General register C GRC 16 H'FF8C Timer W 16*1 2
General register D GRD 16 H'FF8E Timer W 16*1 2
Flash memory control register 1 FLMCR1 8 H'FF90 ROM 8 2
Flash memory control register 2 FLMCR2 8 H'FF91 ROM 8 2
Flash memory power control register FLPWCR 8 H'FF92 ROM 8 2
Erase block register 1 EBR1 8 H'FF93 ROM 8 2
Flash memory enable register FENR 8 H'FF9B ROM 8 2
Timer control register V0 TCRV0 8 H'FFA0 Timer V 8 3
Timer control/status register V TCSRV 8 H'FFA1 Timer V 8 3
Timer constant register A TCORA 8 H'FFA2 Timer V 8 3
Timer constant register B TCORB 8 H'FFA3 Timer V 8 3
Timer counter V TCNTV 8 H'FFA4 Timer V 8 3
Timer control register V1 TCRV1 8 H'FFA5 Timer V 8 3
Timer mode register A TMA 8 H'FFA6 Timer A 8 2
Timer counter A TCA 8 H'FFA7 Timer A 8 2
Serial mode register SMR 8 H'FFA8 SCI3 8 3
Bit rate register BRR 8 H'FFA9 SCI3 8 3
Serial control register 3 SCR3 8 H'FFAA SCI3 8 3
Section 19 List of Registers
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Register Name
Abbre-
viation
Bit No.
Address
Module
Name
Data
Bus
Width
Access
State
Transmit data register TDR 8 H'FFAB SCI3 8 3
Serial status register SSR 8 H'FFAC SCI3 8 3
Receive data register RDR 8 H'FFAD SCI3 8 3
A/D data register A ADDRA 16 H'FFB0 A/D converter 8 3
A/D data register B ADDRB 16 H'FFB2 A/D converter 8 3
A/D data register C ADDRC 16 H'FFB4 A/D converter 8 3
A/D data register D ADDRD 16 H'FFB6 A/D converter 8 3
A/D control/status register ADCSR 8 H'FFB8 A/D converter 8 3
A/D control register ADCR 8 H'FFB9 A/D converter 8 3
Timer control/status register WD TCSRWD 8 H'FFC0 WDT*2 8 2
Timer counter WD TCWD 8 H'FFC1 WDT*2 8 2
Timer mode register WD TMWD 8 H'FFC2 WDT*2 8 2
I2C bus control register ICCR 8 H'FFC4 IIC 8 2
I2C bus status register ICSR 8 H'FFC5 IIC 8 2
I2C bus data register ICDR 8 H'FFC6 IIC 8 2
Second slave address register SARX 8 H'FFC6 IIC 8 2
I2C bus mode register ICMR 8 H'FFC7 IIC 8 2
Slave address register SAR 8 H'FFC7 IIC 8 2
Address break control register ABRKCR 8 H'FFC8 Address break 8 2
Address break status register ABRKSR 8 H'FFC9 Address break 8 2
Break address register H BARH 8 H'FFCA Address break 8 2
Break address register L BARL 8 H'FFCB Address break 8 2
Break data register H BDRH 8 H'FFCC Address break 8 2
Break data register L BDRL 8 H'FFCD Address break 8 2
Port pull-up control register 1 PUCR1 8 H'FFD0 I/O port 8 2
Port pull-up control register 5 PUCR5 8 H'FFD1 I/O port 8 2
Port data register 1 PDR1 8 H'FFD4 I/O port 8 2
Port data register 2 PDR2 8 H'FFD5 I/O port 8 2
Port data register 5 PDR5 8 H'FFD8 I/O port 8 2
Port data register 7 PDR7 8 H'FFDA I/O port 8 2
Port data register 8 PDR8 8 H'FFDB I/O port 8 2
Section 19 List of Registers
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Register Name
Abbre-
viation
Bit No.
Address
Module
Name
Data
Bus
Width
Access
State
Port data register B PDRB 8 H'FFDD I/O port 8 2
Port mode register 1 PMR1 8 H'FFE0 I/O port 8 2
Port mode register 5 PMR5 8 H'FFE1 I/O port 8 2
Port control register 1 PCR1 8 H'FFE4 I/O port 8 2
Port control register 2 PCR2 8 H'FFE5 I/O port 8 2
Port control register 5 PCR5 8*3 H'FFE8 I/O port 8 2
Port control register 7 PCR7 8 H'FFEA I/O port 8 2
Port control register 8 PCR8 8 H'FFEB I/O port 8 2
System control register 1 SYSCR1 8 H'FFF0 Power-down 8 2
System control register 2 SYSCR2 8 H'FFF1 Power-down 8 2
Interrupt edge select register 1 IEGR1 8 H'FFF2 Interrupts 8 2
Interrupt edge select register 2 IEGR2 8 H'FFF3 Interrupts 8 2
Interrupt enable register 1 IENR1 8 H'FFF4 Interrupts 8 2
Interrupt flag register 1 IRR1 8 H'FFF6 Interrupts 8 2
Wake-up interrupt flag register IWPR 8 H'FFF8 Interrupts 8 2
Module standby control register 1 MSTCR1 8 H'FFF9 Power-down 8 2
Timer serial control register TSCR 8 H'FFFC IIC 8 2
Notes: 1. Only word access can be used.
2. WDT: Watchdog timer.
3. The number of bits is six for H8/3664N.
• EEPROM
Register Name
Abbre-
viation
Bit No.
Address
Module
Name
Data
Bus
Width
Access
State
EEPROM key register EKR 8 H'FF10 IEEPROM 8 2
Section 19 List of Registers
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19.2 Register Bits
Register bit names of the on-chip peripheral modules are described below.
Each line covers eight bits, and 16-bit registers are shown as 2 lines.
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Module
Name
TMRW CTS — BUFEB BUFEA — PWMD PWMC PWMB Timer W
TCRW CCLR CKS2 CKS1 CKS0 TOD TOC TOB TOA
TIERW OVIE — — — IMIED IMIEC IMIEB IMIEA
TSRW OVF — — — IMFD IMFC IMFB IMFA
TIOR0 — IOB2 IOB1 IOB0 — IOA2 IOA1 IOA0
TIOR1 — IOD2 IOD1 IOD0 — IOC2 IOC1 IOC0
TCNT TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 TCNT9 TCNT8
TCNT7 TCNT6 TCNT5 TCNT4 TCNT3 TCNT2 TCNT1 TCNT0
GRA GRA15 GRA14 GRA13 GRA12 GRA11 GRA10 GRA9 GRA8
GRA7 GRA6 GRA5 GRA4 GRA3 GRA2 GRA1 GRA0
GRB GRB15 GRB14 GRB13 GRB12 GRB11 GRB10 GRB9 GRB8
GRB7 GRB6 GRB5 GRB4 GRB3 GRB2 GRB1 GRB0
GRC GRC15 GRC14 GRC13 GRC12 GRC11 GRC10 GRC9 GRC8
GRC7 GRC6 GRC5 GRC4 GRC3 GRC2 GRC1 GRC0
GRD GRD15 GRD14 GRD13 GRD12 GRD11 GRD10 GRD9 GRD8
GRD7 GRD6 GRD5 GRD4 GRD3 GRD2 GRD1 GRD0
FLMCR1 — SWE ESU PSU EV PV E P ROM
FLMCR2 FLER — — — — — — —
FLPWCR PDWND — — — — — — —
EBR1 — — — EB4 EB3 EB2 EB1 EB0
FENR FLSHE — — — — — — —
TCRV0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Timer V
TCSRV CMFB CMFA OVF — OS3 OS2 OS1 OS0
TCORA TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0
TCORB TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0
TCNTV TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0
TCRV1 — — — TVEG1 TVEG0 TRGE — ICKS0
TMA TMA7 TMA6 TMA5 — TMA3 TMA2 TMA1 TMA0 Timer A
TCA TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0
Section 19 List of Registers
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Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Module
Name
SMR COM CHR PE PM STOP MP CKS1 CKS0 SCI3
BRR BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0
SCR3 TIE RIE TE RE MPIE TEIE CKE1 CKE0
TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0
SSR TDRE RDRF OER FER PER TEND MPBR MPBT
RDR RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0
ADDRA AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D converter
AD1 AD0 — — — — — —
ADDRB AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
AD1 AD0 — — — — — —
ADDRC AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
AD1 AD0 — — — — — —
ADDRD AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
AD1 AD0 — — — — — —
ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0
ADCR TRGE — — — — — — —
TCSRWD B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST WDT*1
TCWD TCWD7 TCWD6 TCWD5 TCWD4 TCWD3 TCWD2 TCWD1 TCWD0
TMWD — — — — CKS3 CKS2 CKS1 CKS0
ICCR ICE IEIC MST TRS ACKE BBSY IRIC SCP IIC
ICSR ESTP STOP IRTR AASX AL AAS ADZ ACKB
ICDR ICDR7 ICDR6 ICDR5 ICDR4 ICDR3 ICDR2 ICDR1 ICDR0
SARX SVAX6 SVAX5 SVAX4 SVAX3 SVAX2 SVAX1 SVAX0 FSX
ICMR MLS WAIT CKS2 CKS1 CKS0 BC2 BC1 BC0
SAR SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 FS
ABRKCR RTINTE CSEL1 CSEL0 ACMP2 ACMP1 ACMP0 DCMP1 DCMP0 Address break
ABRKSR ABIF ABIE — — — — — —
BARH BARH7 BARH6 BARH5 BARH4 BARH3 BARH2 BARH1 BARH0
BARL BARL7 BARL6 BARL5 BARL4 BARL3 BARL2 BARL1 BARL0
BDRH BDRH7 BDRH6 BDRH5 BDRH4 BDRH3 BDRH2 BDRH1 BDRH0
BDRL BDRL7 BDRL6 BDRL5 BDRL4 BDRL3 BDRL2 BDRL1 BDRL0
PUCR1 PUCR17 PUCR16 PUCR15 PUCR14 — PUCR12 PUCR11 PUCR10 I/O port
PUCR5 — — PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
PDR1 P17 P16 P15 P14 — P12 P11 P10
PDR2 — — — — — P22 P21 P20
PDR5 P57*2 P56*2 P55 P54 P53 P52 P51 P50
Section 19 List of Registers
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Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Module
Name
PDR7 — P76 P75 P74 — — — — I/O port
PDR8 P87 P86 P85 P84 P83 P82 P81 P80
PDRB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
PMR1 IRQ3 IRQ2 IRQ1 IRQ0 — — TXD TMOW
PMR5 — — WKP5 WKP4 WKP3 WKP2 WKP1 WKP0
PCR1 PCR17 PCR16 PCR15 PCR14 — PCR12 PCR11 PCR10
PCR2 — — — — — PCR22 PCR21 PCR20
PCR5 PCR57*2PCR56*2 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50
PCR7 — PCR76 PCR75 PCR74 — — — —
PCR8 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80
SYSCR1 SSBY STS2 STS1 STS0 NESEL — — — Power-down
SYSCR2 SMSEL LSON DTON MA2 MA1 MA0 SA1 SA0
IEGR1 NMIEG — — — IEG3 IEG2 IEG1 IEG0 Interrupts
IEGR2 — — WPEG5 WPEG4 WPEG3 WPEG2 WPEG1 WPEG0
IENR1 IENDT IENTA IENWP — IEN3 IEN2 IEN1 IEN0
IRR1 IRRDT IRRTA — — IRRI3 IRRI2 IRRI1 IRRI0
IWPR — — IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0
MSTCR1 — MSTIIC MSTS3 MSTAD MSTWD MSTTW MSTTV MSTTA Power-down
TSCR — — — — — — IICRST IICX IIC
Notes: 1. WDT: Watchdog timer
2. This bit is not included in H8/3664N.
• EEPROM
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 Module
Name
EKR EKR7 EKR6 EKR5 EKR4 EKR3 EKR2 EKR1 EKR0 EEPROM
Section 19 List of Registers
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19.3 Register States in Each Operating Mode
Register
Name
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
TMRW Initialized — — — — — Timer W
TCRW Initialized — — — — —
TIERW Initialized — — — — —
TSRW Initialized — — — — —
TIOR0 Initialized — — — — —
TIOR1 Initialized — — — — —
TCNT Initialized — — — — —
GRA Initialized — — — — —
GRB Initialized — — — — —
GRC Initialized — — — — —
GRD Initialized — — — — —
FLMCR1 Initialized — — Initialized Initialized Initialized ROM
FLMCR2 Initialized — — — — —
FLPWCR Initialized — — — — —
EBR1 Initialized — — Initialized Initialized Initialized
FENR Initialized — — — — —
TCRV0 Initialized — — Initialized Initialized Initialized Timer V
TCSRV Initialized — — Initialized Initialized Initialized
TCORA Initialized — — Initialized Initialized Initialized
TCORB Initialized — — Initialized Initialized Initialized
TCNTV Initialized — — Initialized Initialized Initialized
TCRV1 Initialized — — Initialized Initialized Initialized
TMA Initialized — — — — — Timer A
TCA Initialized — — — — —
SMR Initialized — — Initialized Initialized Initialized SCI3
BRR Initialized — — Initialized Initialized Initialized
SCR3 Initialized — — Initialized Initialized Initialized
TDR Initialized — — Initialized Initialized Initialized
SSR Initialized — — Initialized Initialized Initialized
RDR Initialized — — Initialized Initialized Initialized
Section 19 List of Registers
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Register
Name
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
ADDRA Initialized — — Initialized Initialized Initialized A/D converter
ADDRB Initialized — — Initialized Initialized Initialized
ADDRC Initialized — — Initialized Initialized Initialized
ADDRD Initialized — — Initialized Initialized Initialized
ADCSR Initialized — — Initialized Initialized Initialized
ADCR Initialized — — Initialized Initialized Initialized
TCSRWD Initialized — — — — — WDT*
TCWD Initialized — — — — —
TMWD Initialized — — — — —
ICCR Initialized — — — — — IIC
ICSR Initialized — — — — —
ICDR Initialized — — — — —
SARX Initialized — — — — —
ICMR Initialized — — — — —
SAR Initialized — — — — —
ABRKCR Initialized — — — — — Address Break
ABRKSR Initialized — — — — —
BARH Initialized — — — — —
BARL Initialized — — — — —
BDRH Initialized — — — — —
BDRL Initialized — — — — —
PUCR1 Initialized — — — — — I/O port
PUCR5 Initialized — — — — —
PDR1 Initialized — — — — —
PDR2 Initialized — — — — —
PDR5 Initialized — — — — —
PDR7 Initialized — — — — —
PDR8 Initialized — — — — —
PDRB Initialized — — — — —
PMR1 Initialized — — — — —
PMR5 Initialized — — — — —
Section 19 List of Registers
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Register
Name
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
PCR1 Initialized
— — — — — I/O port
PCR2 Initialized — — — — —
PCR5 Initialized — — — — —
PCR7 Initialized — — — — —
PCR8 Initialized — — — — —
SYSCR1 Initialized — — — — — Power-down
SYSCR2 Initialized — — — — — Power-down
IEGR1 Initialized — — — — — Interrupts
IEGR2 Initialized — — — — — Interrupts
IENR1 Initialized — — — — — Interrupts
IRR1 Initialized — — — — — Interrupts
IWPR Initialized — — — — — Interrupts
MSTCR1 Initialized — — — — Power-down
TSCR Initialized — — — IIC
Note : is not initialized
* WDT: Watchdog timer
• EEPROM
Register
Name
Reset
Active
Sleep
Subactive
Subsleep
Standby
Module
EKR Initialized
— — — — — EEPROM
Section 20 Electrical Characteristics
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Section 20 Electrical Characteristics
20.1 Absolute Maximum Ratings
Table 20.1 Absolute Maximum Ratings
Item Symbol Value Unit Note
Power supply voltage VCC –0.3 to +7.0 V *
Analog power supply voltage AVCC –0.3 to +7.0 V
Input voltage Ports other than Port B and
X1
VIN –0.3 to VCC +0.3 V
Port B –0.3 to AVCC +0.3 V
X1 –0.3 to 4.3 V
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +125 °C
Note: * Permanent damage may result if maximum ratings are exceeded. Normal operation
should be under the conditions specified in Electrical Characteristics. Exceeding these
values can result in incorrect operation and reduced reliability.
20.2 Electrical Characteristics (F-ZTAT™ Version, F-ZTAT™ Version
with EEPROM)
20.2.1 Power Supply Voltage and Operating Ranges
Power Supply Voltage and Oscillation Frequency Range
10.0
2.0
16.0
3.0 4.0 5.5 V
CC
(V)
φ
OSC
(MHz)
32.768
3.0 4.0 5.5 V
CC
(V)
φ
W
(kHz)
• AV
CC
= 3.3 V to 5.5 V
• Active mode
• Sleep mode
• AV
CC
= 3.3 V to 5.5 V
• All operating modes
Section 20 Electrical Characteristics
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Power Supply Voltage and Operating Frequency Range
10.0
1.0
16.0
3.0 4.0 5.5 VCC (V)
φ (MHz)
16.384
3.0 4.0 5.5 VCC (V)
φ SUB (kHz)
8.192
4.096
1250
78.125
2000
3.0 4.0 5.5 VCC (V)
φ (kHz)
• AVCC = 3.3 V to 5.5 V
• Active mode
• Sleep mode
(When MA2 = 0 in SYSCR2)
• AVCC = 3.3 V to 5.5 V
• Subactive mode
• Subsleep mode
• AVCC = 3.3 V to 5.5 V
• Active mode
• Sleep mode
(When MA2 = 1 in SYSCR2)
Section 20 Electrical Characteristics
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Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range
10.0
2.0
16.0
3.3 4.0 5.5 AVCC (V)
φ (MHz)
• VCC = 3.0 V to 5.5 V
• Active mode
• Sleep mode
Section 20 Electrical Characteristics
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20.2.2 DC Characteristics
Table 20.2 DC Characteristics (1)
VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C unless otherwise indicated.
Values
Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes
Input high
voltage
VIH RES, NMI,
WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG, TMRIV,
VCC = 4.0 V to 5.5 V VCC × 0.8 — VCC + 0.3 V
TMCIV, FTCI,
FTIOA to FTIOD,
SCK3, TRGV
V
CC × 0.9 — VCC + 0.3
RXD, SCL, SDA,
P10 to P12,
P14 to P17,
P20 to P22,
VCC = 4.0 V to 5.5 V VCC × 0.7 — VCC + 0.3 V
P50 to P57*,
P74 to P76,
P80 to P87
V
CC × 0.8 — VCC + 0.3
PB0 to PB7 VCC = 4.0 V to 5.5 V VCC × 0.7 — AVCC + 0.3 V
V
CC × 0.8 — AVCC + 0.3
OSC1 VCC = 4.0 V to 5.5 V VCC – 0.5 — VCC + 0.3 V
V
CC – 0.3 — VCC + 0.3
Input low
voltage
VIL RES, NMI,
WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG, TMRIV,
VCC = 4.0 V to 5.5 V –0.3 — VCC × 0.2 V
TMCIV, FTCI,
FTIOA to FTIOD,
SCK3, TRGV
–0.3 — VCC × 0.1
RXD, SCL, SDA,
P10 to P12,
P14 to P17,
P20 to P22,
VCC = 4.0 V to 5.5 V –0.3 — VCC × 0.3 V
P50 to P57*,
P74 to P76,
P80 to P87,
PB0 to PB7
–0.3 — VCC × 0.2
OSC1 VCC = 4.0 V to 5.5 V –0.3 — 0.5 V
–0.3 — 0.3
Note: * P50 to P55 for H8/3664N
Section 20 Electrical Characteristics
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Values
Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes
Output
high
voltage
VOH V
CC = 4.0 V to 5.5 V
–IOH = 1.5 mA
VCC – 1.0 — — V
P10 to P12,
P14 to P17,
P20 to P22,
P50 to P55,
P74 to P76,
P80 to P87,
–IOH = 0.1 mA VCC – 0.5 — —
P56, P57* V
CC = 4.0 V to 5.5 V
–IOH = 0.1 mA
VCC – 2.5 — — V
V
CC = 3.0 V to 4.0 V
–IOH = 0.1 mA
VCC – 2.0 — —
Output
low
voltage
VOL V
CC = 4.0 V to 5.5 V
IOL = 1.6 mA
— — 0.6 V
P10 to P12,
P14 to P17,
P20 to P22,
P50 to P57*,
P74 to P76,
IOL = 0.4 mA — — 0.4
P80 to P87 VCC = 4.0 V to 5.5 V
IOL = 20.0 mA
— — 1.5 V
V
CC = 4.0 V to 5.5 V
IOL = 10.0 mA
— — 1.0
V
CC = 4.0 V to 5.5 V
IOL = 1.6 mA
— — 0.4
I
OL = 0.4 mA — — 0.4
SCL, SDA VCC = 4.0 V to 5.5 V
IOL = 6.0 mA
— — 0.6 V
I
OL = 3.0 mA — — 0.4
Note: * P50 to P55 for H8/3664N
Section 20 Electrical Characteristics
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Values
Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes
Input/
output
leakage
current
| IIL | OSC1, RES, NMI,
WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG, TRGV,
TMRIV, TMCIV,
FTCI, FTIOA to
FTIOD, RXD,
SCK3, SCL, SDA
VIN = 0.5 V to
(VCC – 0.5 V)
— — 1.0 µA
P10 to P12,
P14 to P17,
P20 to P22,
P50 to P57*1,
P74 to P76,
P80 to P87,
VIN = 0.5 V to
(VCC – 0.5 V)
— — 1.0 µA
PB0 to PB7 VIN = 0.5 V to
(AVCC – 0.5 V)
— — 1.0 µA
–Ip V
CC = 5.0 V,
VIN = 0.0 V
50.0 — 300.0 µA
Pull-up
MOS
current
P10 to P12,
P14 to P17,
P50 to P55 VCC = 3.0 V,
VIN = 0.0 V
— 60.0 — Reference
value
Input
capaci-
tance
Cin All input pins
except power
supply pins
f = 1 MHz,
VIN = 0.0 V,
Ta = 25°C
— — 15.0 pF H8/3664N
SCL, SDA — — 25.0
IOPE1 V
CC Active mode 1
VCC = 5.0 V,
fOSC = 16 MHz
— 15.0 22.5 mA *2 Active
mode
supply
current Active mode 1
VCC = 3.0 V,
fOSC = 10 MHz
— 8.0 — *2
Reference
value
I
OPE2 V
CC Active mode 2
VCC = 5.0 V,
fOSC = 16 MHz
— 1.8 2.7 mA *2
Active mode 2
VCC = 3.0 V,
fOSC = 10 MHz
— 1.2 — *2
Reference
value
Notes: 1. P50 to P55 for H8/3664N
2. Pin states during supply current measurement are given below (excluding current in the
pull-up MOS transistors and output buffers).
Section 20 Electrical Characteristics
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Values
Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes
ISLEEP1 V
CC Sleep mode 1
VCC = 5.0 V,
fOSC = 16 MHz
— 11.5 17.0 mA *
Sleep
mode
supply
current Sleep mode 1
VCC = 3.0 V,
fOSC = 10 MHz
— 6.5 — *
Reference
value
I
SLEEP2 V
CC Sleep mode 2
VCC = 5.0 V,
fOSC = 16 MHz
— 1.7 2.5 mA *
Sleep mode 2
VCC = 3.0 V,
fOSC = 10 MHz
— 1.1 — *
Reference
value
ISUB V
CC V
CC = 3.0 V
32-kHz crystal
resonator
(φSUB = φW/2)
— 35.0 70.0 µA *
Subactive
mode
supply
current
V
CC = 3.0 V
32-kHz crystal
resonator
(φSUB = φW/8)
— 25.0 — *
Reference
value
Subsleep
mode
supply
current
ISUBSP V
CC V
CC = 3.0 V
32-kHz crystal
resonator
(φSUB = φW/2)
— 25.0 50.0 µA *
Standby
mode
supply
current
ISTBY V
CC 32-kHz crystal
resonator not
used
— — 5.0 µA *
RAM data
retaining
voltage
VRAM V
CC 2.0 — — V
Note: * Pin states during supply current measurement are given below (excluding current in the
pull-up MOS transistors and output buffers).
Section 20 Electrical Characteristics
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Mode RES Pin Internal State Other Pins Oscillator Pins
Active mode 1 VCC Operates VCC
Active mode 2 Operates
(φosc/64)
Sleep mode 1 VCC Only timers operate VCC
Sleep mode 2 Only timers operate
(φosc/64)
Main clock:
ceramic or crystal
resonator
Subclock:
Pin X1 = VSS
Subactive mode VCC Operates VCC
Subsleep mode VCC Only timers operate VCC
Main clock:
ceramic or crystal
resonator
Subclock:
crystal resonator
Standby mode VCC CPU and timers
both stop
VCC Main clock:
ceramic or crystal
resonator
Subclock:
Pin X1 = VSS
Table 20.2 DC Characteristics (2)
VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise indicated.
Values
Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes
IEEW V
CC V
CC = 5.0 V, tSCL = 2.5
µs (when writing)
— — 2.0 mA *
IEER V
CC V
CC = 5.0 V, tSCL = 2.5
µs (when reading)
— — 0.3 mA
EEPROM
supply
current
IEESTBY V
CC V
CC = 5.0 V, tSCL = 2.5
µs (at standby)
— — 3.0 µA
Note: * The supply current of the EEPROM chip is shown.
For the supply current of H8/3664N, add the above current values to the supply current
of H8/3664F.
Section 20 Electrical Characteristics
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Table 20.2 DC Characteristics (3)
VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise indicated.
Applicable
Values
Item Symbol Pins
Test Condition Min Typ Max Unit
Allowable output low
current (per pin)
IOL Output pins except
port 8, SCL, and
SDA
VCC = 4.0 V to
5.5 V
— — 2.0 mA
Port 8 — — 20.0 mA
Port 8 — — 10.0 mA
SCL and SDA — — 6.0 mA
Output pins except
port 8, SCL, and
SDA
— — 0.5 mA
Allowable output low
current (total)
∑IOL Output pins except
port 8, SCL, and
SDA
VCC = 4.0 V to
5.5 V
— — 40.0 mA
Port 8,
SCL, and SDA
— — 80.0 mA
Output pins except
port 8, SCL, and
SDA
— — 20.0 mA
Port 8,
SCL, and SDA
— — 40.0 mA
I –IOH I All output pins VCC = 4.0 V to
5.5 V
— — 2.0 mA Allowable output high
current (per pin)
— — 0.2 mA
I –∑IOH I All output pins VCC = 4.0 V to
5.5 V
— — 30.0 mA Allowable output high
current (total)
— — 8.0 mA
Section 20 Electrical Characteristics
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20.2.3 AC Characteristics
Table 20.3 AC Characteri sti cs
VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
Values
Item Symbol
Applicable
Pins Test Condition Min Typ Max Unit Reference
Figure
fOSC OSC1,
OSC2
VCC = 4.0 V to 5.5 V 2.0 — 16.0 MHz *1 System clock
oscillation
frequency 2.0 — 10.0 MHz
tcyc 1 — 64 tOSC *2 System clock (φ)
cycle time — — 12.8 µs
Subclock oscillation
frequency
fW X1, X2 — 32.768 — kHz
Watch clock (φW)
cycle time
tW X1, X2 — 30.5 — µs
Subclock (φSUB)
cycle time
tsubcyc 2 — 8 tW *2
Instruction cycle
time
2 — — tcyc
tsubcyc
Oscillation
stabilization time
(crystal resonator)
trc OSC1,
OSC2
— — 10.0 ms
Oscillation
stabilization time
(ceramic resonator)
trc OSC1,
OSC2
— — 5.0 ms
Oscillation
stabilization time
trcx X1, X2 — — 2.0 s
tCPH OSC1 VCC = 4.0 V to 5.5 V 25.0 — — ns Figure 20.1 External clock
high width 40.0 — —
tCPL OSC1 VCC = 4.0 V to 5.5 V 25.0 — — ns External clock
low width 40.0 — —
External clock tCPr OSC1 VCC = 4.0 V to 5.5 V — — 10.0 ns
rise time — — 15.0
tCPf OSC1 VCC = 4.0 V to 5.5 V — — 10.0 ns External clock
fall time — — 15.0
Section 20 Electrical Characteristics
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Applicable Values Reference
Item Symbol Pins Test Condition Min Typ Max Unit Figure
RES pin low
width
tREL RES At power-on and in
modes other than
those below
trc — — ms Figure 20.2
In active mode and
sleep mode
operation
10 — — tcyc
Input pin high
width
tIH NMI,
IRQ0 to
IRQ3,
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTCI,
FTIOA to
FTIOD
2 — — tcyc
tsubcyc
Figure 20.3
Input pin low
width
tIL NMI,
IRQ0 to
IRQ3,
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTCI,
FTIOA to
FTIOD
2 — — tcyc
tsubcyc
Notes: 1. When an external clock is input, the minimum system clock oscillator frequency is
1.0 MHz.
2. Determined by MA2, MA1, MA0, SA1, and SA0 of system control register 2 (SYSCR2).
Section 20 Electrical Characteristics
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Table 20.4 I2C Bus Interface Timing
VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise specified .
Test Values Reference
Item Symbol Condition Min Typ Max Unit Figure
SCL input cycle time tSCL 12tcyc + 600 — — ns Figure 20.4
SCL input high width tSCLH 3tcyc + 300 — — ns
SCL input low width tSCLL 5tcyc + 300 — — ns
Input fall time of
SCL and SDA
tSf — — 300 ns
SCL and SDA input
spike pulse removal
time
tSP — — 1tcyc ns
SDA input bus-free
time
tBUF 5tcyc — — ns
Start condition input
hold time
tSTAH 3tcyc — — ns
Retransmission start
condition input setup
time
tSTAS 3tcyc — — ns
Setup time for stop
condition input
tSTOS 3tcyc — — ns
Data-input setup time tSDAS 1tcyc+20 — — ns
Data-input hold time tSDAH 0 — — ns
Capacitive load of
SCL and SDA
cb 0 — 400 pF
SCL and SDA output
fall time
tSf V
CC = 4.0 V
to 5.5 V
— — 250 ns
— — 300
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Table 20.5 Serial Interface (SCI3) Timing
VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
Applicable Values Reference
Item Symbol Pins Test Condition Min Typ Max Unit Figure
Asynchro-
nous
tScyc SCK3 4 — — tcyc Figure 20.5 Input
clock
cycle Clocked
synchro-
nous
6 — — tcyc
Input clock pulse
width
tSCKW SCK3 0.4 — 0.6 tScyc
tTXD TXD VCC = 4.0 V to 5.5 V — — 1 tcyc Figure 20.6 Transmit data delay
time (clocked
synchronous) — — 1 tcyc
tRXS RXD VCC = 4.0 V to 5.5 V 62.5 — — ns Receive data setup
time (clocked
synchronous) 100.0 — — ns
tRXH RXD VCC = 4.0 V to 5.5 V 62.5 — — ns Receive data hold time
(clocked synchronous) 100.0 — — ns
Section 20 Electrical Characteristics
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20.2.4 A/D Converter Characteristics
Table 20.6 A/D Converter Characteristics
VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
Applicable Test Values Reference
Item Symbol Pins Condition Min Typ Max Unit Figure
Analog power supply
voltage
AVCC AVCC 3.3 VCC 5.5 V *1
Analog input voltage AVIN AN0 to
AN7
V
SS – 0.3 — AVCC + 0.3 V
Analog power supply
current
AIOPE AVCC AVCC = 5.0 V
fOSC =
16 MHz
— — 2.0 mA
AISTOP1 AVCC — 50 — µA *2
Reference
value
AISTOP2 AVCC — — 5.0 µA *3
Analog input
capacitance
CAIN AN0 to
AN7
— — 30.0 pF
Allowable signal
source impedance
RAIN AN0 to
AN7
— — 5.0 kΩ
Resolution (data
length)
10 10 10 bit
Conversion time
(single mode)
AVCC = 3.3 V
to 5.5 V
134 — — tcyc
Nonlinearity error — — ±7.5 LSB
Offset error — — ±7.5 LSB
Full-scale error — — ±7.5 LSB
Quantization error — — ±0.5 LSB
Absolute accuracy — — ±8.0 LSB
Conversion time
(single mode)
AVCC = 4.0 V
to 5.5 V
70 — — tcyc
Nonlinearity error — — ±7.5 LSB
Offset error — — ±7.5 LSB
Full-scale error — — ±7.5 LSB
Quantization error — — ±0.5 LSB
Absolute accuracy — — ±8.0 LSB
Section 20 Electrical Characteristics
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Applicable Test Values Reference
Item Symbol Pins Condition Min Typ Max Unit Figure
Conversion time
(single mode) AVCC = 4.0 V
to 5.5 V 134 — — tcyc
Nonlinearity error — — ±3.5 LSB
Offset error — — ±3.5 LSB
Full-scale error — — ±3.5 LSB
Quantization error — — ±0.5 LSB
Absolute accuracy — — ±4.0 LSB
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, subactive, and subsleep modes while the
A/D converter is idle.
20.2.5 Watchdog Timer Characteristics
Table 20.7 Watchdog Timer Characteristics
VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
Applicable Values Reference
Item Symbol Pins Test
Condition Min Typ Max Unit Figure
On-chip
oscillator
overflow
time
tOVF 0.2 0.4 — s *
Note: * Shows the time to count from 0 to 255, at which point an internal reset is generated,
when the internal oscillator is selected.
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20.2.6 Memory Characteristics
Table 20.8 Flash Memory Characterist i cs
VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
Test Values
Item Symbol Condition Min Typ Max Unit
Programming time (per 128 bytes)*1*2*4 t
P — 7 200 ms
Erase time (per block) *1*3*6 t
E — 100 1200 ms
Reprogramming count NWEC 1000 10000 — Times
Programming Wait time after SWE
bit setting*1
x 1 — — µs
Wait time after PSU
bit setting*1
y 50 — — µs
Wait time after P bit setting*1*4z1 1 ≤ n ≤ 6 28 30 32 µs
z2 7 ≤ n ≤ 1000 198 200 202 µs
z3 Additional-
programming
8 10 12 µs
Wait time after P bit clear*1 α 5 — — µs
Wait time after PSU bit clear*1 β 5 — — µs
Wait time after PV bit setting*1 γ 4 — — µs
Wait time after dummy write*1 ε 2 — — µs
Wait time after PV bit clear*1 η 2 — — µs
Wait time after SWE bit clear*1θ 100 — — µs
Maximum
programming count*1*4*5
N — — 1000 Times
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Test Values
Item Symbol Condition Min Typ Max Unit
Erase Wait time after SWE
bit setting*1
x 1 — — µs
Wait time after ESU
bit setting*1
y 100 — — µs
Wait time after E bit setting*1*6z 10 — 100 ms
Wait time after E bit clear*1 α 10 — — µs
Wait time after ESU bit clear*1 β 10 — — µs
Wait time after EV bit setting*1 γ 20 — — µs
Wait time after dummy write*1 ε 2 — — µs
Wait time after EV bit clear*1 η 4 — — µs
Wait time after SWE bit clear*1θ 100 — — µs
Maximum erase count*1*6*7 N — — 120 Times
Notes: 1. Make the time settings in accordance with the program/erase algorithms.
2. The programming time for 128 bytes. (Indicates the total time for which the P bit in flash
memory control register 1 (FLMCR1) is set. The program-verify time is not included.)
3. The time required to erase one block. (Indicates the time for which the E bit in flash
memory control register 1 (FLMCR1) is set. The erase-verify time is not included.)
4. Programming time maximum value (tP(MAX)) = wait time after P bit setting (z) ×
maximum programming count (N)
5. Set the maximum programming count (N) according to the actual set values of z1, z2,
and z3, so that it does not exceed the programming time maximum value (tP(MAX)).
The wait time after P bit setting (z1, z2) should be changed as follows according to the
value of the programming count (n).
Programming count (n)
1 ≤ n ≤ 6 z1 = 30 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Erase time maximum value (tE(max)) = wait time after E bit setting (z) × maximum erase
count (N)
7. Set the maximum maximum erase count (N) according to the actual set value of (z), so
that it does not exceed the erase time maximum value (tE(max)).
Section 20 Electrical Characteristics
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20.2.7 EEPROM Characteristics
Table 20.9 EEPROM Characteristi c s
VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
Test Values Reference
Item Symbol Condition Min Typ Max Unit Figure
SCL input cycle time tSCL 2500 ns Figure 20.7
SCL input high pulse width tSCLH 600 µs
SCL input low pulse width tSCLL 1200 ns
SCL, SDA input spike pulse
removal time
tSP 50 ns
SDA input bus-free time tBUF 1200 ns
Start condition input hold time tSTAH 600 ns
Retransmit start condition input
setup time
tSTAS 600 ns
Stop condition input setup time tSTOS 600 ns
Data input setup time tSDAS 160 ns
Data input hold time tSDAH 0 ns
SCL, SDA input fall time tSf 300 ns
SDA input rise time tSr 300 ns
Data output hold time tDH 50 ns
SCL, SDA capacitive load Cb 0 400 pF
Access time tAA 100 900 ns
Cycle time at writing* t
WC 10 ms
Reset release time tRES 13 ms
Note: * Cycle time at writing is a time from the stop condition to write completion (internal
control).
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20.3 Electrical Characteristics (Mask ROM Version)
20.3.1 Power Supply Voltage and Operating Ranges
Power Supply Voltage and Oscillation Frequency Range
10.0
2.0
16.0
2.7 4.0 5.5 V
CC
(V)
φ
OSC
(MHz)
32.768
2.7 4.0 5.5 V
CC
(V)
φ
W
(kHz)
• AV
CC
= 3.0 V to 5.5 V
• Active mode
• Sleep mode
• AV
CC
= 3.0 V to 5.5 V
• All operating modes
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Power Supply Voltage and Operating Frequency Range
10.0
1.0
16.0
2.7 4.0 5.5 V
CC
(V)
φ (MHz)
16.384
2.7 4.0 5.5 V
CC
(V)
φ
SUB
(kHz)
8.192
4.096
1250
78.125
2000
2.7 4.0 5.5 V
CC
(V)
φ (kHz)
• AV
CC
= 3.0 V to 5.5 V
• Active mode
• Sleep mode
(When MA2 = 0 in SYSCR2)
• AV
CC
= 3.0 V to 5.5 V
• Subactive mode
• Subsleep mode
• AV
CC
= 3.0 V to 5.5 V
• Active mode
• Sleep mode
(When MA2 = 1 in SYSCR2)
Section 20 Electrical Characteristics
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Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range:
10.0
2.0
16.0
3.0 4.0 5.5 AVCC (V)
φ (MHz)
• VCC = 2.7 V to 5.5 V
• Active mode
• Sleep mode
20.3.2 DC Characteristics
Table 20.10 DC Characteristics (1)
VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C unless otherwise indicated.
Values
Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes
Input high
voltage
VIH RES, NMI,
WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG, TMRIV,
VCC = 4.0 V to 5.5 V VCC × 0.8 — VCC + 0.3 V
TMCIV, FTCI,
FTIOA to FTIOD,
SCK3, TRGV
V
CC × 0.9 — VCC + 0.3 V
RXD, SCL, SDA,
P10 to P12,
P14 to P17,
P20 to P22,
VCC = 4.0 V to 5.5 V VCC × 0.7 — VCC + 0.3 V
P50 to P57,
P74 to P76,
P80 to P87
V
CC × 0.8 — VCC + 0.3 V
PB0 to PB7 VCC = 4.0 V to 5.5 V VCC × 0.7 — AVCC + 0.3 V
V
CC × 0.8 — AVCC + 0.3 V
OSC1 VCC = 4.0 V to 5.5 V VCC – 0.5 — VCC + 0.3 V
V
CC – 0.3 — VCC + 0.3 V
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Values
Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes
Input low
voltage
VIL RES, NMI,
WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG, TMRIV,
VCC = 4.0 V to 5.5 V –0.3 — VCC × 0.2 V
TMCIV, FTCI,
FTIOA to FTIOD,
SCK3, TRGV
–0.3 — VCC × 0.1 V
RXD, SCL, SDA,
P10 to P12,
P14 to P17,
P20 to P22,
VCC = 4.0 V to 5.5 V –0.3 — VCC × 0.3 V
P50 to P57,
P74 to P76,
P80 to P87,
PB0 to PB7
–0.3 — VCC × 0.2 V
OSC1 VCC = 4.0 V to 5.5 V –0.3 — 0.5 V
–0.3 — 0.3 V
Output
high
voltage
VOH V
CC = 4.0 V to 5.5 V
–IOH = 1.5 mA
VCC –
1.0
— — V
P10 to P12,
P14 to P17,
P20 to P22,
P50 to P55,
P74 to P76,
P80 to P87
–IOH = 0.1 mA VCC –
0.5
— — V
P56, P57 VCC = 4.0 V to 5.5 V
–IOH = 0.1 mA
VCC –
2.5
— — V
V
CC =2.7 V to 4.0 V
–IOH = 0.1 mA
VCC –
2.0
— — V
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Values
Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes
Output
low
voltage
VOL V
CC = 4.0 V to 5.5 V
IOL = 1.6 mA
— — 0.6 V
P10 to P12,
P14 to P17,
P20 to P22,
P50 to P57,
P74 to P76
IOL = 0.4 mA — — 0.4 V
P80 to P87 VCC = 4.0 V to 5.5 V
IOL = 20.0 mA
— — 1.5 V
V
CC = 4.0 V to 5.5 V
IOL = 10.0 mA
— — 1.0 V
V
CC = 4.0 V to 5.5 V
IOL = 1.6 mA
— — 0.4 V
I
OL = 0.4 mA — — 0.4 V
SCL, SDA VCC = 4.0 to
IOL = 6.0 mA
— — 0.6 V
I
OL = 3.0 mA — — 0.4 V
Input/
output
leakage
current
| IIL | OSC1, RES, NMI,
WKP0 to WKP5,
IRQ0 to IRQ3,
ADTRG, TRGV,
TMRIV, TMCIV,
FTCI, FTIOA to
FTIOD, RXD,
SCK3, SCL, SDA
VIN = 0.5 V to
(VCC – 0.5 V)
— — 1.0 µA
P10 to P12,
P14 to P17,
P20 to P22,
P50 to P57,
P74 to P76,
P80 to P87
VIN = 0.5 V to
(VCC – 0.5 V)
— — 1.0 µA
PB0 to PB7 VIN = 0.5 V to
(AVCC – 0.5 V)
— — 1.0 µA
–Ip P10 to P12,
P14 to P17,
VCC = 5.0 V,
VIN = 0.0 V
50.0 — 300.0 µA
Pull-up
MOS
current P50 to P55 VCC = 3.0 V,
VIN = 0.0 V
— 60.0 — µA Reference
value
Section 20 Electrical Characteristics
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Values
Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes
Input
capaci-
tance
Cin All input pins
except power
supply pins
f = 1 MHz,
VIN = 0.0 V,
Ta = 25°C
— — 15.0 pF
IOPE1 V
CC Active mode 1
VCC = 5.0 V,
fOSC = 16 MHz
— 15.0 22.5 mA *
Active
mode
supply
current Active mode 1
VCC = 3.0 V,
fOSC = 10 MHz
— 8.0 — mA *
Reference
value
I
OPE2 V
CC Active mode 2
VCC = 5.0 V,
fOSC = 16 MHz
— 1.8 2.7 mA *
Active mode 2
VCC = 3.0 V,
fOSC = 10 MHz
— 1.2 — mA *
Reference
value
ISLEEP1 V
CC Sleep mode 1
VCC = 5.0 V,
fOSC = 16 MHz
— 7.1 13.0 mA *
Sleep
mode
supply
current Sleep mode 1
VCC = 3.0 V,
fOSC = 10 MHz
— 4.0 — mA *
Reference
value
I
SLEEP2 V
CC Sleep mode 2
VCC = 5.0 V,
fOSC = 16 MHz
— 1.1 2.0 mA *
Sleep mode 2
VCC = 3.0 V,
fOSC = 10 MHz
— 0.5 — mA *
Reference
value
ISUB V
CC V
CC = 3.0 V
32-kHz crystal
resonator
(φSUB = φW/2)
— 35.0 70.0 µA *
Subactive
mode
supply
current
V
CC = 3.0 V
32-kHz crystal
resonator
(φSUB = φW/8)
— 25.0 — µA *
Reference
value
Subsleep
mode
supply
current
ISUBSP V
CC V
CC = 3.0 V
32-kHz crystal
resonator
(φSUB = φW/2)
— 25.0 50.0 µA *
Standby
mode
supply
current
ISTBY V
CC 32-kHz crystal
resonator not used
— — 5.0 µA *
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Values
Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes
RAM data
retaining
voltage
VRAM V
CC 2.0 — — V
Note: * Pin states during supply current measurement are given below (excluding current in the
pull-up MOS transistors and output buffers).
Mode RES Pin Internal State Other Pins Oscillator Pins
Active mode 1 VCC Operates VCC
Active mode 2 Operates
(φosc/64)
Sleep mode 1 VCC Only timers operate VCC
Sleep mode 2 Only timers operate
(φosc/64)
Main clock:
ceramic or crystal
resonator
Subclock:
Pin X1 = VSS
Subactive mode VCC Operates VCC Main clock:
ceramic or crystal
resonator
Subsleep mode VCC Only timers operate VCC Subclock:
crystal resonator
Standby mode VCC CPU and timers
both stop
VCC Main clock:
ceramic or crystal
resonator
Subclock:
Pin X1 = VSS
Section 20 Electrical Characteristics
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Table 20.10 DC Characteristics (2)
VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise indicated.
Applicable
Values
Item Symbol Pins
Test Condition Min Typ Max Unit
Allowable output low
current (per pin)
IOL Output pins
except port 8,
SCL, and SDA
VCC = 4.0 V to 5.5 V — — 2.0 mA
Port 8 — — 20.0 mA
Port 8 — — 10.0 mA
SCL and SDA — — 6.0 mA
Output pins
except port 8,
SCL,, and SDA
— — 0.5 mA
Allowable output low
current (total)
∑IOL Output pins
except port 8,
SCL and SDA
VCC = 4.0 V to 5.5 V — — 40.0 mA
Port 8,
SCL, and SDA
— — 80.0 mA
Output pins
except port 8,
SCL, and SDA
— — 20.0 mA
Port 8,
SCL, and SDA
— — 40.0 mA
I –IOH I All output pins VCC = 4.0 V to 5.5 V — — 2.0 mA Allowable output high
current (per pin) — — 0.2 mA
I –∑IOH I All output pins VCC = 4.0 V to 5.5 V — — 30.0 mA Allowable output high
current (total) — — 8.0 mA
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20.3.3 AC Characteristics
Table 20.11 AC Characteristi c s
VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
Applicable Values Reference
Item Symbol Pins Test Condition Min Typ Max Unit Figure
fOSC OSC1,
OSC2
VCC = 4.0 V to 5.5 V 2.0 — 16.0 MHz *1 System clock
oscillation
frequency 2.0 10.0
tcyc 1 — 64 tOSC *2 System clock (φ)
cycle time — — 12.8 µs
Subclock oscillation
frequency
fW X1, X2 — 32.768 — kHz
Watch clock (φW)
cycle time
tW X1, X2 — 30.5 — µs
Subclock (φSUB)
cycle time
tsubcyc 2 — 8 tW *2
Instruction cycle
time
2 — — tcyc
tsubcyc
Oscillation
stabilization time
(crystal resonator)
trc OSC1,
OSC2
— — 10.0 ms
Oscillation
stabilization time
(ceramic resonator)
trc OSC1,
OSC2
— — 5.0 ms
Oscillation
stabilization time
trcx X1, X2 — — 2.0 s
tCPH OSC1 VCC = 4.0 V to 5.5 V 25.0 — — ns Figure 20.1External clock
high width 40.0 — — ns
tCPL OSC1 VCC = 4.0 V to 5.5 V 25.0 — — ns External clock
low width 40.0 — — ns
tCPr OSC1 VCC = 4.0 V to 5.5 V — — 10.0 ns External clock
rise time — — 15.0 ns
tCPf OSC1 VCC = 4.0 V to 5.5 V — — 10.0 ns External clock
fall time — — 15.0 ns
Section 20 Electrical Characteristics
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Applicable Values Reference
Item Symbol Pins Test Condition Min Typ Max Unit Figure
RES pin low
width
tREL RES At power-on and
in modes other
than those below
trc — — ms Figure 20.2
In active mode
and sleep mode
operation
10 — — tcyc
Input pin high
width
tIH NMI,
IRQ0 to
IRQ3,
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTCI,
FTIOA to
FTIOD
2 — — tcyc
tsubcyc
Figure 20.3
Input pin low
width
tIL NMI,
IRQ0 to
IRQ3,
WKP0 to
WKP5,
TMCIV,
TMRIV,
TRGV,
ADTRG,
FTCI,
FTIOA to
FTIOD
2 — — tcyc
tsubcyc
Notes: 1. When an external clock is input, the minimum system clock oscillator frequency is
1.0 MHz.
2. Determined by MA2, MA1, MA0, SA1, and SA0 of system control register 2 (SYSCR2).
Section 20 Electrical Characteristics
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Table 20.12 I2C Bus Interface Timing
Values Test Reference
Item Symbol Min Typ Max Unit Condition Figure
SCL input cycle time tSCL 12tcyc + 600 — — ns Figure 20.4
SCL input high width tSCLH 3tcyc + 300 — — ns
SCL input low width tSCLL 5tcyc + 300 — — ns
Input fall time of
SCL and SDA
tSf — — 300 ns
SCL and SDA input
spike pulse removal
time
tSP — — 1tcyc ns
SDA input bus-free
time
tBUF 5tcyc — — ns
Start condition input
hold time
tSTAH 3tcyc — — ns
Retransmission start
condition input setup
time
tSTAS 3tcyc — — ns
Setup time for stop
condition input
tSTOS 3tcyc — — ns
Data-input setup time tSDAS 1tcyc+20 — — ns
Data-input hold time tSDAH 0 — — ns
Capacitive load of
SCL and SDA
cb 0 — 400 pF
SCL and SDA output
fall time
tSf — — 250 ns VCC = 4.0 V
to 5.5 V
— — 300 ns
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Table 20.13 Serial Interface (SCI3) Timing
VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
Applicable Values Reference
Item Symbol Pins Test Condition Min Typ Max Unit Figure
Input
clock
Asynchro-
nous
tScyc SCK3 4 — — tcyc Figure 20.5
cycle Clocked
synchronous
6 — — tcyc
Input clock pulse
width
tSCKW SCK3 0.4 — 0.6 tScyc
tTXD TXD VCC = 4.0 V to 5.5 V — — 1 tcyc Figure 20.6 Transmit data delay
time (clocked
synchronous) — — 1 tcyc
tRXS RXD VCC = 4.0 V to 5.5 V 62.5 — — ns Receive data setup
time (clocked
synchronous) 100.0 — — ns
tRXH RXD VCC = 4.0 V to 5.5 V 62.5 — — ns Receive data hold
time (clocked
synchronous) 100.0 — — ns
Section 20 Electrical Characteristics
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20.3.4 A/D Converter Characteristics
Table 20.14 A/D Converter Characteristics
VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
Applicable Test Values Reference
Item Symbol Pins Condition Min Typ Max Unit Figure
Analog power supply
voltage
AVCC AVCC 3.0 VCC 5.5 V *1
Analog input voltage AVIN AN0 to
AN7
V
SS – 0.3 — AVCC + 0.3 V
Analog power supply
current
AIOPE AVCC AVCC = 5.0 V
fOSC =
16 MHz
— — 2.0 mA
AISTOP1 AVCC — 50 — µA *2
Reference
value
AISTOP2 AVCC — — 5.0 µA *3
Analog input
capacitance
CAIN AN0 to
AN7
— — 30.0 pF
Allowable signal
source impedance
RAIN AN0 to
AN7
— — 5.0 kΩ
Resolution (data
length)
10 10 10 bit
Conversion time
(single mode)
AVCC = 3.0 V
to 5.5 V
134 — — tcyc
Nonlinearity error — — ±7.5 LSB
Offset error — — ±7.5 LSB
Full-scale error — — ±7.5 LSB
Quantization error — — ±0.5 LSB
Absolute accuracy — — ±8.0 LSB
Conversion time
(single mode)
AVCC = 4.0 V
to 5.5 V
70 — — tcyc
Nonlinearity error — — ±7.5 LSB
Offset error — — ±7.5 LSB
Full-scale error — — ±7.5 LSB
Quantization error — — ±0.5 LSB
Absolute accuracy — — ±8.0 LSB
Section 20 Electrical Characteristics
Rev. 6.00 Mar. 24, 2006 Page 342 of 412
REJ09B0142-0600
Applicable Test Values Reference
Item Symbol Pins Condition Min Typ Max Unit Figure
Conversion time
(single mode)
AVCC = 4.0 V to
5.5 V 134 — — tcyc
Nonlinearity error — — ±3.5 LSB
Offset error — — ±3.5 LSB
Full-scale error — — ±3.5 LSB
Quantization error — — ±0.5 LSB
Absolute accuracy — — ±4.0 LSB
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, subactive, and subsleep modes while the
A/D converter is idle.
20.3.5 Watchdog Timer Characteristics
Table 20.15 Watchdog Timer Characteristics
VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
Applicable Test Values Reference
Item Symbol Pins Condition Min Typ Max Unit Figure
On-chip
oscillator
overflow
time
tOVF 0.2 0.4 — s *
Note: * Shows the time to count from 0 to 255, at which point an internal reset is generated,
when the internal oscillator is selected.
Section 20 Electrical Characteristics
Rev. 6.00 Mar. 24, 2006 Page 343 of 412
REJ09B0142-0600
20.4 Operation Timing
tOSC
VIH
VIL
tCPH tCPL
tCPr
OSC1
tCPf
Figure 20.1 System Clock Input Timing
tREL
VIL
RES
tREL
VIL
VCC × 0.7
VCC
OSC1
Figure 20.2 RES Low Width Timing
V
IH
V
IL
t
IL
NMI
IRQ0 to IRQ3
WKP0 to WKP5
ADTRG
TMCI
FTIOA to FTIOD
TMCIV, TMRIV
TRGV
t
IH
Figure 20.3 Input Timing
Section 20 Electrical Characteristics
Rev. 6.00 Mar. 24, 2006 Page 344 of 412
REJ09B0142-0600
SCL
VIH
VIL
tSTAH
tBUF
P*S*
tSf
tSCL tSDAH
tSCLH
tSCLL
SDA
Sr*
tSTAS
tSP tSTOS
tSDAS
P*
Note: * S, P, and Sr represent the following:
S: Start condition
P: Stop condition
Sr: Retransmission start condition
Figure 20.4 I2C Bus Interface Input/Output Timing
t
Scyc
t
SCKW
SCK3
Figure 20.5 SCK3 Input Clock Timing
Section 20 Electrical Characteristics
Rev. 6.00 Mar. 24, 2006 Page 345 of 412
REJ09B0142-0600
t
Scyc
t
TXD
t
RXS
t
RXH
V
OH
V or V
IH OH
V or V
IL OL
*
*
*
V
OL*
SCK3
TXD
(transmit data)
RXD
(receive data)
Note: *Output timing reference levels
Output high: V
OH
= 2.0 V
Output low: V
OL
= 0.8 V
Load conditions are shown in figure 20.8.
Figure 20.6 SCI3 Input/Output Timing in Clocked Synchronous Mode
SCL
SDA
(in)
SDA
(out)
tsf tsp
tsr
t
STAS
t
SDAH
t
STOS
t
SCLH
t
SCLL
1/f
SCL
t
BUF
t
SDAS
t
STAH
t
AA
t
DH
Figure 20.7 EEPROM Bus Timing
Section 20 Electrical Characteristics
Rev. 6.00 Mar. 24, 2006 Page 346 of 412
REJ09B0142-0600
20.5 Output Load Condition
V
CC
2.4 kΩ
12 kΩ30 pF
LSI output pin
Figure 20.8 Output Load Circuit
Appendix
Rev. 6.00 Mar. 24, 2006 Page 347 of 412
REJ09B0142-0600
Appendix A Instruction Set
A.1 Instruction List
Operand Notation
Symbol Description
Rd General (destination*) register
Rs General (source*) register
Rn General register*
ERd General destination register (address register or 32-bit register)
ERs General source register (address register or 32-bit register)
ERn General register (32-bit register)
(EAd) Destination operand
(EAs) Source operand
PC Program counter
SP Stack pointer
CCR Condition-code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
disp Displacement
→ Transfer from the operand on the left to the operand on the right, or transition from
the state on the left to the state on the right
+ Addition of the operands on both sides
– Subtraction of the operand on the right from the operand on the left
× Multiplication of the operands on both sides
÷ Division of the operand on the left by the operand on the right
∧ Logical AND of the operands on both sides
∨ Logical OR of the operands on both sides
Appendix
Rev. 6.00 Mar. 24, 2006 Page 348 of 412
REJ09B0142-0600
Symbol Description
⊕ Logical exclusive OR of the operands on both sides
¬ NOT (logical complement)
( ), < > Contents of operand
Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers
(R0 to R7 and E0 to E7).
Condition Code No ta tion
Symbol Description
↔
Changed according to execution result
* Undetermined (no guaranteed value)
0 Cleared to 0
1 Set to 1
— Not affected by execution of the instruction
∆ Varies depending on conditions, described in notes
Appendix
Rev. 6.00 Mar. 24, 2006 Page 349 of 412
REJ09B0142-0600
Table A.1 Instruction Set
1. Data transfer instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @ERs, Rd
MOV.B @(d:16, ERs), Rd
MOV.B @(d:24, ERs), Rd
MOV.B @ERs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B @aa:24, Rd
MOV.B Rs, @ERd
MOV.B Rs, @(d:16, ERd)
MOV.B Rs, @(d:24, ERd)
MOV.B Rs, @–ERd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.B Rs, @aa:24
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @ERs, Rd
MOV.W @(d:16, ERs), Rd
MOV.W @(d:24, ERs), Rd
MOV.W @ERs+, Rd
MOV.W @aa:16, Rd
MOV.W @aa:24, Rd
MOV.W Rs, @ERd
MOV.W Rs, @(d:16, ERd)
MOV.W Rs, @(d:24, ERd)
Operation
#xx:8 → Rd8
Rs8 → Rd8
@ERs → Rd8
@(d:16, ERs) → Rd8
@(d:24, ERs) → Rd8
@ERs → Rd8
ERs32+1 → ERs32
@aa:8 → Rd8
@aa:16 → Rd8
@aa:24 → Rd8
Rs8 → @ERd
Rs8 → @(d:16, ERd)
Rs8 → @(d:24, ERd)
ERd32–1 → ERd32
Rs8 → @ERd
Rs8 → @aa:8
Rs8 → @aa:16
Rs8 → @aa:24
#xx:16 → Rd16
Rs16 → Rd16
@ERs → Rd16
@(d:16, ERs) → Rd16
@(d:24, ERs) → Rd16
@ERs → Rd16
ERs32+2 → @ERd32
@aa:16 → Rd16
@aa:24 → Rd16
Rs16 → @ERd
Rs16 → @(d:16, ERd)
Rs16 → @(d:24, ERd)
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
W
W
W
W
W
W
W
W
W
W
W
2
4
2
2
2
2
2
2
4
8
4
8
4
8
4
8
2
2
2
2
4
6
2
4
6
4
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
4
6
10
6
4
6
8
4
6
10
6
4
6
8
4
2
4
6
10
6
6
8
4
6
10
Normal
Advanced
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MOV
Appendix
Rev. 6.00 Mar. 24, 2006 Page 350 of 412
REJ09B0142-0600
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
MOV.W Rs, @–ERd
MOV.W Rs, @aa:16
MOV.W Rs, @aa:24
MOV.L #xx:32, Rd
MOV.L ERs, ERd
MOV.L @ERs, ERd
MOV.L @(d:16, ERs), ERd
MOV.L @(d:24, ERs), ERd
MOV.L @ERs+, ERd
MOV.L @aa:16, ERd
MOV.L @aa:24, ERd
MOV.L ERs, @ERd
MOV.L ERs, @(d:16, ERd)
MOV.L ERs, @(d:24, ERd)
MOV.L ERs, @–ERd
MOV.L ERs, @aa:16
MOV.L ERs, @aa:24
POP.W Rn
POP.L ERn
PUSH.W Rn
PUSH.L ERn
MOVFPE @aa:16, Rd
MOVTPE Rs, @aa:16
Operation
ERd32–2 → ERd32
Rs16 → @ERd
Rs16 → @aa:16
Rs16 → @aa:24
#xx:32 → Rd32
ERs32 → ERd32
@ERs → ERd32
@(d:16, ERs) → ERd32
@(d:24, ERs) → ERd32
@ERs → ERd32
ERs32+4 → ERs32
@aa:16 → ERd32
@aa:24 → ERd32
ERs32 → @ERd
ERs32 → @(d:16, ERd)
ERs32 → @(d:24, ERd)
ERd32–4 → ERd32
ERs32 → @ERd
ERs32 → @aa:16
ERs32 → @aa:24
@SP → Rn16
SP+2 → SP
@SP → ERn32
SP+4 → SP
SP–2 → SP
Rn16 → @SP
SP–4 → SP
ERn32 → @SP
Cannot be used in
this LSI
Cannot be used in
this LSI
W
W
W
L
L
L
L
L
L
L
L
L
L
L
L
L
L
W
L
W
L
B
B
6
2
4
4
6
10
6
10
2
4
4
4
6
6
8
6
8
4
4
2
4
2
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
6
8
6
2
8
10
14
10
10
12
8
10
14
10
10
12
6
10
6
10
Normal
Advanced
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cannot be used in
this LSI
Cannot be used in
this LSI
MOV
POP
PUSH
MOVFPE
MOVTPE
Appendix
Rev. 6.00 Mar. 24, 2006 Page 351 of 412
REJ09B0142-0600
2. Arithmetic instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W #xx:16, Rd
ADD.W Rs, Rd
ADD.L #xx:32, ERd
ADD.L ERs, ERd
ADDX.B #xx:8, Rd
ADDX.B Rs, Rd
ADDS.L #1, ERd
ADDS.L #2, ERd
ADDS.L #4, ERd
INC.B Rd
INC.W #1, Rd
INC.W #2, Rd
INC.L #1, ERd
INC.L #2, ERd
DAA Rd
SUB.B Rs, Rd
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
SUBX.B #xx:8, Rd
SUBX.B Rs, Rd
SUBS.L #1, ERd
SUBS.L #2, ERd
SUBS.L #4, ERd
DEC.B Rd
DEC.W #1, Rd
DEC.W #2, Rd
Operation
Rd8+#xx:8 → Rd8
Rd8+Rs8 → Rd8
Rd16+#xx:16 → Rd16
Rd16+Rs16 → Rd16
ERd32+#xx:32 →
ERd32
ERd32+ERs32 →
ERd32
Rd8+#xx:8 +C → Rd8
Rd8+Rs8 +C → Rd8
ERd32+1 → ERd32
ERd32+2 → ERd32
ERd32+4 → ERd32
Rd8+1 → Rd8
Rd16+1 → Rd16
Rd16+2 → Rd16
ERd32+1 → ERd32
ERd32+2 → ERd32
Rd8 decimal adjust
→ Rd8
Rd8–Rs8 → Rd8
Rd16–#xx:16 → Rd16
Rd16–Rs16 → Rd16
ERd32–#xx:32 → ERd32
ERd32–ERs32 → ERd32
Rd8–#xx:8–C → Rd8
Rd8–Rs8–C → Rd8
ERd32–1 → ERd32
ERd32–2 → ERd32
ERd32–4 → ERd32
Rd8–1 → Rd8
Rd16–1 → Rd16
Rd16–2 → Rd16
B
B
W
W
L
L
B
B
L
L
L
B
W
W
L
L
B
B
W
W
L
L
B
B
L
L
L
B
W
W
2
4
6
2
4
6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
(1)
(2)
(2)
—
—
—
—
—
—
—
—
*
(1)
(1)
(2)
(2)
—
—
—
—
—
—
2
2
4
2
6
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
6
2
2
2
2
2
2
2
2
2
Normal
Advanced
↔
↔
↔
↔↔↔↔↔↔
↔↔↔↔↔↔↔
—
—
—
—
—
—
↔↔↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔
(3)
(3)
—
—
—
(3)
(3)
—
—
—
↔↔↔
↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔
—
—
—
*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔↔↔↔↔
↔
↔
↔
↔
↔↔↔
↔↔↔
↔↔↔
ADD
ADDX
ADDS
INC
DAA
SUB
SUBX
SUBS
DEC
Appendix
Rev. 6.00 Mar. 24, 2006 Page 352 of 412
REJ09B0142-0600
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
DEC.L #1, ERd
DEC.L #2, ERd
DAS.Rd
MULXU. B Rs, Rd
MULXU. W Rs, ERd
MULXS. B Rs, Rd
MULXS. W Rs, ERd
DIVXU. B Rs, Rd
DIVXU. W Rs, ERd
DIVXS. B Rs, Rd
DIVXS. W Rs, ERd
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
Operation
ERd32–1 → ERd32
ERd32–2 → ERd32
Rd8 decimal adjust
→ Rd8
Rd8 × Rs8 → Rd16
(unsigned multiplication)
Rd16 × Rs16 → ERd32
(unsigned multiplication)
Rd8 × Rs8 → Rd16
(signed multiplication)
Rd16 × Rs16 → ERd32
(signed multiplication)
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(unsigned division)
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(unsigned division)
Rd16 ÷ Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
(signed division)
ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(signed division)
Rd8–#xx:8
Rd8–Rs8
Rd16–#xx:16
Rd16–Rs16
ERd32–#xx:32
ERd32–ERs32
L
L
B
B
W
B
W
B
W
B
W
B
B
W
W
L
L
2
4
6
2
2
2
2
2
4
4
2
2
4
4
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
2
2
14
22
16
24
14
22
16
24
2
2
4
2
4
2
Normal
Advanced
↔
↔
↔
—
—
*
—
—
—
—
—
—
—
—
(1)
(1)
(2)
(2)
↔
↔
↔
↔
↔
*
—
—
—
—
—
—
—
—
—
—
(7)
(7)
(7)
(7)
—
—
(6)
(6)
(8)
(8)
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
DEC
DAS
MULXU
MULXS
DIVXU
DIVXS
CMP
Appendix
Rev. 6.00 Mar. 24, 2006 Page 353 of 412
REJ09B0142-0600
Mnemonic Operation
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
NEG.B Rd
NEG.W Rd
NEG.L ERd
EXTU.W Rd
EXTU.L ERd
EXTS.W Rd
EXTS.L ERd
0–Rd8 → Rd8
0–Rd16 → Rd16
0–ERd32 → ERd32
0 → (<bits 15 to 8>
of Rd16)
0 → (<bits 31 to 16>
of ERd32)
(<bit 7> of Rd16) →
(<bits 15 to 8> of Rd16)
(<bit 15> of ERd32) →
(<bits 31 to 16> of
ERd32)
B
W
L
W
L
W
L
2
2
2
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
2
2
2
2
2
2
2
Normal
Advanced
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
0
0
0
0
0
0
—
—
—
—
↔↔↔↔
↔↔
NEG
EXTU
EXTS
Appendix
Rev. 6.00 Mar. 24, 2006 Page 354 of 412
REJ09B0142-0600
3. Logic instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
AND.B #xx:8, Rd
AND.B Rs, Rd
AND.W #xx:16, Rd
AND.W Rs, Rd
AND.L #xx:32, ERd
AND.L ERs, ERd
OR.B #xx:8, Rd
OR.B Rs, Rd
OR.W #xx:16, Rd
OR.W Rs, Rd
OR.L #xx:32, ERd
OR.L ERs, ERd
XOR.B #xx:8, Rd
XOR.B Rs, Rd
XOR.W #xx:16, Rd
XOR.W Rs, Rd
XOR.L #xx:32, ERd
XOR.L ERs, ERd
NOT.B Rd
NOT.W Rd
NOT.L ERd
Operation
Rd8∧#xx:8 → Rd8
Rd8∧Rs8 → Rd8
Rd16∧#xx:16 → Rd16
Rd16∧Rs16 → Rd16
ERd32∧#xx:32 → ERd32
ERd32∧ERs32 → ERd32
Rd8⁄#xx:8 → Rd8
Rd8⁄Rs8 → Rd8
Rd16⁄#xx:16 → Rd16
Rd16⁄Rs16 → Rd16
ERd32⁄#xx:32 → ERd32
ERd32⁄ERs32 → ERd32
Rd8⊕#xx:8 → Rd8
Rd8⊕Rs8 → Rd8
Rd16⊕#xx:16 → Rd16
Rd16⊕Rs16 → Rd16
ERd32⊕#xx:32 → ERd32
ERd32⊕ERs32 → ERd32
¬ Rd8 → Rd8
¬ Rd16 → Rd16
¬ Rd32 → Rd32
B
B
W
W
L
L
B
B
W
W
L
L
B
B
W
W
L
L
B
W
L
2
4
6
2
4
6
2
4
6
2
2
4
2
2
4
2
2
4
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
4
2
6
4
2
2
4
2
6
4
2
2
4
2
6
4
2
2
2
Normal
Advanced
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AND
OR
XOR
NOT
Appendix
Rev. 6.00 Mar. 24, 2006 Page 355 of 412
REJ09B0142-0600
4. Shift instructions
Mnemonic
Operand Size
No. of
States
*1
Condition Code
IHNZVC
SHAL.B Rd
SHAL.W Rd
SHAL.L ERd
SHAR.B Rd
SHAR.W Rd
SHAR.L ERd
SHLL.B Rd
SHLL.W Rd
SHLL.L ERd
SHLR.B Rd
SHLR.W Rd
SHLR.L ERd
ROTXL.B Rd
ROTXL.W Rd
ROTXL.L ERd
ROTXR.B Rd
ROTXR.W Rd
ROTXR.L ERd
ROTL.B Rd
ROTL.W Rd
ROTL.L ERd
ROTR.B Rd
ROTR.W Rd
ROTR.L ERd
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
B
W
L
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Normal
Advanced
↔
↔
↔
↔
Addressing Mode and
Instruction Length (bytes)
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Operation
MSB LSB
0
C
MSB LSB
0
C
C
MSB LSB
0C
MSB LSB
C
MSB LSB
C
MSB LSB
C
MSB LSB
C
MSB LSB
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SHAL
SHAR
SHLL
SHLR
ROTXL
ROTXR
ROTL
ROTR
Appendix
Rev. 6.00 Mar. 24, 2006 Page 356 of 412
REJ09B0142-0600
5. Bit manipulation instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
BSET #xx:3, Rd
BSET #xx:3, @ERd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @ERd
BSET Rn, @aa:8
BCLR #xx:3, Rd
BCLR #xx:3, @ERd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @ERd
BCLR Rn, @aa:8
BNOT #xx:3, Rd
BNOT #xx:3, @ERd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @ERd
BNOT Rn, @aa:8
BTST #xx:3, Rd
BTST #xx:3, @ERd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @ERd
BTST Rn, @aa:8
BLD #xx:3, Rd
Operation
(#xx:3 of Rd8) ← 1
(#xx:3 of @ERd) ← 1
(#xx:3 of @aa:8) ← 1
(Rn8 of Rd8) ← 1
(Rn8 of @ERd) ← 1
(Rn8 of @aa:8) ← 1
(#xx:3 of Rd8) ← 0
(#xx:3 of @ERd) ← 0
(#xx:3 of @aa:8) ← 0
(Rn8 of Rd8) ← 0
(Rn8 of @ERd) ← 0
(Rn8 of @aa:8) ← 0
(#xx:3 of Rd8) ←
¬ (#xx:3 of Rd8)
(#xx:3 of @ERd) ←
¬ (#xx:3 of @ERd)
(#xx:3 of @aa:8) ←
¬ (#xx:3 of @aa:8)
(Rn8 of Rd8) ←
¬ (Rn8 of Rd8)
(Rn8 of @ERd) ←
¬ (Rn8 of @ERd)
(Rn8 of @aa:8) ←
¬ (Rn8 of @aa:8)
¬ (#xx:3 of Rd8) → Z
¬ (#xx:3 of @ERd) → Z
¬ (#xx:3 of @aa:8) → Z
¬ (Rn8 of @Rd8) → Z
¬ (Rn8 of @ERd) → Z
¬ (Rn8 of @aa:8) → Z
(#xx:3 of Rd8) → C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
8
8
2
8
8
2
8
8
2
8
8
2
8
8
2
8
8
2
6
6
2
6
6
2
Normal
Advanced
↔↔↔↔↔↔
↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BSET
BCLR
BNOT
BTST
BLD
Appendix
Rev. 6.00 Mar. 24, 2006 Page 357 of 412
REJ09B0142-0600
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
BLD #xx:3, @ERd
BLD #xx:3, @aa:8
BILD #xx:3, Rd
BILD #xx:3, @ERd
BILD #xx:3, @aa:8
BST #xx:3, Rd
BST #xx:3, @ERd
BST #xx:3, @aa:8
BIST #xx:3, Rd
BIST #xx:3, @ERd
BIST #xx:3, @aa:8
BAND #xx:3, Rd
BAND #xx:3, @ERd
BAND #xx:3, @aa:8
BIAND #xx:3, Rd
BIAND #xx:3, @ERd
BIAND #xx:3, @aa:8
BOR #xx:3, Rd
BOR #xx:3, @ERd
BOR #xx:3, @aa:8
BIOR #xx:3, Rd
BIOR #xx:3, @ERd
BIOR #xx:3, @aa:8
BXOR #xx:3, Rd
BXOR #xx:3, @ERd
BXOR #xx:3, @aa:8
BIXOR #xx:3, Rd
BIXOR #xx:3, @ERd
BIXOR #xx:3, @aa:8
Operation
(#xx:3 of @ERd) → C
(#xx:3 of @aa:8) → C
¬ (#xx:3 of Rd8) → C
¬ (#xx:3 of @ERd) → C
¬ (#xx:3 of @aa:8) → C
C → (#xx:3 of Rd8)
C → (#xx:3 of @ERd24)
C → (#xx:3 of @aa:8)
¬ C → (#xx:3 of Rd8)
¬ C → (#xx:3 of @ERd24)
¬ C → (#xx:3 of @aa:8)
C∧(#xx:3 of Rd8) → C
C∧(#xx:3 of @ERd24) → C
C∧(#xx:3 of @aa:8) → C
C∧ ¬ (#xx:3 of Rd8) → C
C∧ ¬ (#xx:3 of @ERd24) → C
C∧ ¬ (#xx:3 of @aa:8) → C
C∨(#xx:3 of Rd8) → C
C∨(#xx:3 of @ERd24) → C
C∨(#xx:3 of @aa:8) → C
C∨ ¬ (#xx:3 of Rd8) → C
C∨ ¬ (#xx:3 of @ERd24) → C
C∨ ¬ (#xx:3 of @aa:8) → C
C⊕(#xx:3 of Rd8) → C
C⊕(#xx:3 of @ERd24) → C
C⊕(#xx:3 of @aa:8) → C
C⊕ ¬ (#xx:3 of Rd8) → C
C⊕ ¬ (#xx:3 of @ERd24) → C
C⊕ ¬ (#xx:3 of @aa:8) → C
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
6
6
2
6
6
2
8
8
2
8
8
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
Normal
Advanced
↔↔↔↔↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔↔
BLD
BILD
BIST
BST
BAND
BIAND
BOR
BIOR
BXOR
BIXOR
Appendix
Rev. 6.00 Mar. 24, 2006 Page 358 of 412
REJ09B0142-0600
6. Branching instructions
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Mnemonic
Operand Size
No. of
States
*1
Condition Code
IHNZVC
BRA d:8 (BT d:8)
BRA d:16 (BT d:16)
BRN d:8 (BF d:8)
BRN d:16 (BF d:16)
BHI d:8
BHI d:16
BLS d:8
BLS d:16
BCC d:8 (BHS d:8)
BCC d:16 (BHS d:16)
BCS d:8 (BLO d:8)
BCS d:16 (BLO d:16)
BNE d:8
BNE d:16
BEQ d:8
BEQ d:16
BVC d:8
BVC d:16
BVS d:8
BVS d:16
BPL d:8
BPL d:16
BMI d:8
BMI d:16
BGE d:8
BGE d:16
BLT d:8
BLT d:16
BGT d:8
BGT d:16
BLE d:8
BLE d:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
4
6
Normal
Advanced
Addressing Mode and
Instruction Length (bytes)
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
Operation
Always
Never
C∨ Z = 0
C∨ Z = 1
C = 0
C = 1
Z = 0
Z = 1
V = 0
V = 1
N = 0
N = 1
N⊕V = 0
N⊕V = 1
Z∨ (N⊕V) = 0
Z∨ (N⊕V) = 1
If condition
is true then
PC ← PC+d
else next;
Branch
Condition
Bcc
Appendix
Rev. 6.00 Mar. 24, 2006 Page 359 of 412
REJ09B0142-0600
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
JMP @ERn
JMP @aa:24
JMP @@aa:8
BSR d:8
BSR d:16
JSR @ERn
JSR @aa:24
JSR @@aa:8
RTS
Operation
PC ← ERn
PC ← aa:24
PC ← @aa:8
PC → @–SP
PC ← PC+d:8
PC → @–SP
PC ← PC+d:16
PC → @–SP
PC ← ERn
PC → @–SP
PC ← aa:24
PC → @–SP
PC ← @aa:8
PC ← @SP+
—
—
—
—
—
—
—
—
—
2
2
4
4
2
4
2
2
2
—
—
—
—
—
—
—
—
—
4
6
Normal
Advanced
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8
6
8
6
8
8
8
10
8
10
8
10
12
10
JMP
BSR
JSR
RTS
Appendix
Rev. 6.00 Mar. 24, 2006 Page 360 of 412
REJ09B0142-0600
7. Syst em contro l instruc tions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
TRAPA #x:2
RTE
SLEEP
LDC #xx:8, CCR
LDC Rs, CCR
LDC @ERs, CCR
LDC @(d:16, ERs), CCR
LDC @(d:24, ERs), CCR
LDC @ERs+, CCR
LDC @aa:16, CCR
LDC @aa:24, CCR
STC CCR, Rd
STC CCR, @ERd
STC CCR, @(d:16, ERd)
STC CCR, @(d:24, ERd)
STC CCR, @–ERd
STC CCR, @aa:16
STC CCR, @aa:24
ANDC #xx:8, CCR
ORC #xx:8, CCR
XORC #xx:8, CCR
NOP
Operation
PC → @–SP
CCR → @–SP
<vector> → PC
CCR ← @SP+
PC ← @SP+
Transition to power-
down state
#xx:8 → CCR
Rs8 → CCR
@ERs → CCR
@(d:16, ERs) → CCR
@(d:24, ERs) → CCR
@ERs → CCR
ERs32+2 → ERs32
@aa:16 → CCR
@aa:24 → CCR
CCR → Rd8
CCR → @ERd
CCR → @(d:16, ERd)
CCR → @(d:24, ERd)
ERd32–2 → ERd32
CCR → @ERd
CCR → @aa:16
CCR → @aa:24
CCR∧#xx:8 → CCR
CCR∨#xx:8 → CCR
CCR⊕#xx:8 → CCR
PC ← PC+2
—
—
—
B
B
W
W
W
W
W
W
B
W
W
W
W
W
W
B
B
B
—
2
2
2
2
2
2
4
4
6
10
6
10
4
4
6
8
6
8
2
2
1
—
—
—
—
—
—
—
—
—
10
2
2
2
6
8
12
8
8
10
2
6
8
12
8
8
10
2
2
2
2
Normal
Advanced
↔
↔
↔
↔
↔
↔
↔↔↔↔↔↔↔↔↔↔↔
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔
↔↔↔↔↔↔↔↔↔↔↔
14 16
TRAPA
RTE
SLEEP
LDC
STC
ANDC
ORC
XORC
NOP
Appendix
Rev. 6.00 Mar. 24, 2006 Page 361 of 412
REJ09B0142-0600
8. Block transfer instructions
Mnemonic
Operand Size
Addressing Mode and
Instruction Length (bytes) No. of
States
*1
Condition Code
IHNZVC
#xx
Rn
@ERn
@(d, ERn)
@–ERn/@ERn+
@aa
@(d, PC)
@@aa
—
EEPMOV. B
EEPMOV. W
Operation
if R4L ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
until R4L=0
else next
if R4 ≠ 0 then
repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4–1 → R4
until R4=0
else next
—
—
4
4
—
—
8+
4n
*2
Normal
Advanced
—
—
—
—
—
—
—
—
—
—8+
4n
*2
EEPMOV
Notes: 1. The number of states in cases where the instruction code and its operands are located
in on-chip memory is shown here. For other cases see appendix A.3, Number of
Execution States.
2. n is the value set in register R4L or R4.
(1) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0.
(2) Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0.
(3) Retains its previous value when the result is zero; otherwise cleared to 0.
(4) Set to 1 when the adjustment produces a carry; otherwise retains its previous value.
(5) The number of states required for execution of an instruction that transfers data in
synchronization with the E clock is variable.
(6) Set to 1 when the divisor is negative; otherwise cleared to 0.
(7) Set to 1 when the divisor is zero; otherwise cleared to 0.
(8) Set to 1 when the quotient is negative; otherwise cleared to 0.
Appendix
Rev. 6.00 Mar. 24, 2006 Page 362 of 412
REJ09B0142-0600
A.2 Operation Code Map
Table A.2 Operation Code Map (1)
AH
AL 0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
NOP
BRA
MULXU
BSET
BRN
DIVXU
BNOT
STC
BHI
MULXU
BCLR
LDC
BLS
DIVXU
BTST
ORC
OR.B
BCC
RTS
OR
XORC
XOR.B
BCS
BSR
XOR
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
ANDC
AND.B
BNE
RTE
AND
LDC
BEQ
TRAPA
BLD
BILD
BST
BIST
BVC
MOV
BPL
JMP
BMI
EEPMOV
ADDX
SUBX
BGT
JSR
BLE
MOV
ADD
ADDX
CMP
SUBX
OR
XOR
AND
MOV
Instruction when most significant bit of BH is 0.
Instruction when most significant bit of BH is 1.
Instruction code:
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
BVS BLTBGE
BSR
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(2)
Table A-2
(3)
1st byte 2nd byte
AH BHAL BL
ADD
SUB
MOV
CMP
MOV.B
Appendix
Rev. 6.00 Mar. 24, 2006 Page 363 of 412
REJ09B0142-0600
Table A.2 Operation Code Map (2)
AH AL
BH 0123456789ABCDEF
01
0A
0B
0F
10
11
12
13
17
1A
1B
1F
58
79
7A
MOV
INC
ADDS
DAA
DEC
SUBS
DAS
BRA
MOV
MOV
BHI
CMP
CMP
LDC/STC
BCC
OR
OR
BPL BGT
Instruction code:
BVS
SLEEP
BVC BGE
Table A-2
(3)
Table A-2
(3)
Table A-2
(3)
ADD
MOV
SUB
CMP
BNE
AND
AND
INC
EXTU
DEC
BEQ
INC
EXTU
DEC
BCS
XOR
XOR
SHLL
SHLR
ROTXL
ROTXR
NOT
BLS
SUB
SUB
BRN
ADD
ADD
INC
EXTS
DEC
BLT
INC
EXTS
DEC
BLE
SHAL
SHAR
ROTL
ROTR
NEG
BMI
1st byte 2nd byte
AH BHAL BL
SUB
ADDS
SHLL
SHLR
ROTXL
ROTXR
NOT
SHAL
SHAR
ROTL
ROTR
NEG
Appendix
Rev. 6.00 Mar. 24, 2006 Page 364 of 412
REJ09B0142-0600
Table A.2 Operation Code Map (3)
AH
ALBH
BLCH
CL
0123456789ABCDEF
01406
01C05
01D05
01F06
7Cr06
7Cr07
7Dr06
7Dr07
7Eaa6
7Eaa7
7Faa6
7Faa7
MULXS
BSET
BSET
BSET
BSET
DIVXS
BNOT
BNOT
BNOT
BNOT
MULXS
BCLR
BCLR
BCLR
BCLR
DIVXS
BTST
BTST
BTST
BTST
OR XOR
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
AND
BLD
BILD
BST
BIST
Instruction when most significant bit of DH is 0.
Instruction when most significant bit of DH is 1.
Instruction code:
*
*
*
*
*
*
*
*
1
1
1
1
2
2
2
2
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
BLD
BILD
BST
BIST
Notes: 1.
2.
r is the register designation field.
aa is the absolute address field.
1st byte 2nd byte
AH BHAL BL 3rd byte
CH DHCL DL
4th byte
LDC
STC
LDC LDC LDC
STC STC STC
Appendix
Rev. 6.00 Mar. 24, 2006 Page 365 of 412
REJ09B0142-0600
A.3 Number of Execution States
The status of execution for each instruction of the H8/300H CPU and the method of calculating
the number of states required for instruction execution are shown below. Table A.4 shows the
number of cycles of each type occurring in each instruction, such as instruction fetch and data
read/write. Table A.3 shows the number of states required for each cycle. The total number of
states required for execution of an instruction can be calculated by the following expression:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
SI = 2, SL = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on- chip ROM, branch add ress is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1, L = M = N = 0
From table A.3:
SI = SJ = SK = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Appendix
Rev. 6.00 Mar. 24, 2006 Page 366 of 412
REJ09B0142-0600
Table A.3 Number of Cycles in Each Instruction
Execution Status Access Location
(Instruction Cycle) On-Chip Memory On-Chip Peripheral Module
Instruction fetch SI 2 —
Branch address read SJ
Stack operation SK
Byte data access SL 2 or 3*
Word data access SM —
Internal operation SN 1
Note: * Depends on which on-chip peripheral module is accessed. See section 19.1, Register
Addresses (Address Order).
Appendix
Rev. 6.00 Mar. 24, 2006 Page 367 of 412
REJ09B0142-0600
Table A.4 Number of Cycles in Each Instruction
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
ADD ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W #xx:16, Rd
ADD.W Rs, Rd
ADD.L #xx:32, ERd
ADD.L ERs, ERd
1
1
2
1
3
1
ADDS ADDS #1/2/4, ERd 1
ADDX ADDX #xx:8, Rd
ADDX Rs, Rd
1
1
AND AND.B #xx:8, Rd
AND.B Rs, Rd
AND.W #xx:16, Rd
AND.W Rs, Rd
AND.L #xx:32, ERd
AND.L ERs, ERd
1
1
2
1
3
2
ANDC ANDC #xx:8, CCR 1
BAND BAND #xx:3, Rd
BAND #xx:3, @ERd
BAND #xx:3, @aa:8
1
2
2
1
1
Bcc BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
2
2
2
2
2
2
2
2
2
2
2
2
2
Appendix
Rev. 6.00 Mar. 24, 2006 Page 368 of 412
REJ09B0142-0600
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
Bcc
BLT d:8
BGT d:8
BLE d:8
BRA d:16(BT d:16)
BRN d:16(BF d:16)
BHI d:16
BLS d:16
BCC d:16(BHS d:16)
BCS d:16(BLO d:16)
BNE d:16
BEQ d:16
BVC d:16
BVS d:16
BPL d:16
BMI d:16
BGE d:16
BLT d:16
BGT d:16
BLE d:16
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BCLR BCLR #xx:3, Rd
BCLR #xx:3, @ERd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @ERd
BCLR Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BIAND BIAND #xx:3, Rd
BIAND #xx:3, @ERd
BIAND #xx:3, @aa:8
1
2
2
1
1
BILD BILD #xx:3, Rd
BILD #xx:3, @ERd
BILD #xx:3, @aa:8
1
2
2
1
1
Appendix
Rev. 6.00 Mar. 24, 2006 Page 369 of 412
REJ09B0142-0600
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BIOR BIOR #xx:8, Rd
BIOR #xx:8, @ERd
BIOR #xx:8, @aa:8
1
2
2
1
1
BIST BIST #xx:3, Rd
BIST #xx:3, @ERd
BIST #xx:3, @aa:8
1
2
2
2
2
BIXOR BIXOR #xx:3, Rd
BIXOR #xx:3, @ERd
BIXOR #xx:3, @aa:8
1
2
2
1
1
BLD BLD #xx:3, Rd
BLD #xx:3, @ERd
BLD #xx:3, @aa:8
1
2
2
1
1
BNOT BNOT #xx:3, Rd
BNOT #xx:3, @ERd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @ERd
BNOT Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BOR BOR #xx:3, Rd
BOR #xx:3, @ERd
BOR #xx:3, @aa:8
1
2
2
1
1
BSET BSET #xx:3, Rd
BSET #xx:3, @ERd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @ERd
BSET Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BSR BSR d:8
BSR d:16
2
2
1
1
2
BST BST #xx:3, Rd
BST #xx:3, @ERd
BST #xx:3, @aa:8
1
2
2
2
2
Appendix
Rev. 6.00 Mar. 24, 2006 Page 370 of 412
REJ09B0142-0600
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BTST BTST #xx:3, Rd
BTST #xx:3, @ERd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @ERd
BTST Rn, @aa:8
1
2
2
1
2
2
1
1
1
1
BXOR BXOR #xx:3, Rd
BXOR #xx:3, @ERd
BXOR #xx:3, @aa:8
1
2
2
1
1
CMP CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
1
1
2
1
3
1
DAA DAA Rd 1
DAS DAS Rd 1
DEC DEC.B Rd
DEC.W #1/2, Rd
DEC.L #1/2, ERd
1
1
1
DUVXS DIVXS.B Rs, Rd
DIVXS.W Rs, ERd
2
2
12
20
DIVXU DIVXU.B Rs, Rd
DIVXU.W Rs, ERd
1
1
12
20
EEPMOV EEPMOV.B
EEPMOV.W
2
2
2n+2*1
2n+2*1
EXTS EXTS.W Rd
EXTS.L ERd
1
1
EXTU EXTU.W Rd
EXTU.L ERd
1
1
Appendix
Rev. 6.00 Mar. 24, 2006 Page 371 of 412
REJ09B0142-0600
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
INC INC.B Rd
INC.W #1/2, Rd
INC.L #1/2, ERd
1
1
1
JMP JMP @ERn
JMP @aa:24
JMP @@aa:8
2
2
2
1
2
2
JSR JSR @ERn
JSR @aa:24
JSR @@aa:8
2
2
2
1
1
1
1
2
LDC LDC #xx:8, CCR
LDC Rs, CCR
LDC@ERs, CCR
LDC@(d:16, ERs), CCR
LDC@(d:24,ERs), CCR
LDC@ERs+, CCR
LDC@aa:16, CCR
LDC@aa:24, CCR
1
1
2
3
5
2
3
4
1
1
1
1
1
1
2
MOV MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @ERs, Rd
MOV.B @(d:16, ERs), Rd
MOV.B @(d:24, ERs), Rd
MOV.B @ERs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B @aa:24, Rd
MOV.B Rs, @Erd
MOV.B Rs, @(d:16, ERd)
MOV.B Rs, @(d:24, ERd)
MOV.B Rs, @-ERd
MOV.B Rs, @aa:8
1
1
1
2
4
1
1
2
3
1
2
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
Appendix
Rev. 6.00 Mar. 24, 2006 Page 372 of 412
REJ09B0142-0600
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
MOV MOV.B Rs, @aa:16
MOV.B Rs, @aa:24
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @ERs, Rd
MOV.W @(d:16,ERs), Rd
MOV.W @(d:24,ERs), Rd
MOV.W @ERs+, Rd
MOV.W @aa:16, Rd
MOV.W @aa:24, Rd
MOV.W Rs, @ERd
MOV.W Rs, @(d:16,ERd)
MOV.W Rs, @(d:24,ERd)
2
3
2
1
1
2
4
1
2
3
1
2
4
1
1
1
1
1
1
1
1
1
1
1
2
MOV
MOV.W Rs, @-ERd
MOV.W Rs, @aa:16
MOV.W Rs, @aa:24
MOV.L #xx:32, ERd
MOV.L ERs, ERd
MOV.L @ERs, ERd
MOV.L @(d:16,ERs), ERd
MOV.L @(d:24,ERs), ERd
MOV.L @ERs+, ERd
MOV.L @aa:16, ERd
MOV.L @aa:24, ERd
MOV.L ERs,@ERd
MOV.L ERs, @(d:16,ERd)
MOV.L ERs, @(d:24,ERd)
MOV.L ERs, @-ERd
MOV.L ERs, @aa:16
MOV.L ERs, @aa:24
1
2
3
3
1
2
3
5
2
3
4
2
3
5
2
3
4
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
MOVFPE MOVFPE @aa:16, Rd*2 2 1
MOVTPE MOVTPE Rs,@aa:16*2 2 1
Appendix
Rev. 6.00 Mar. 24, 2006 Page 373 of 412
REJ09B0142-0600
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
MULXS MULXS.B Rs, Rd
MULXS.W Rs, ERd
2
2
12
20
MULXU MULXU.B Rs, Rd
MULXU.W Rs, ERd
1
1
12
20
NEG NEG.B Rd
NEG.W Rd
NEG.L ERd
1
1
1
NOP NOP 1
NOT NOT.B Rd
NOT.W Rd
NOT.L ERd
1
1
1
OR OR.B #xx:8, Rd
OR.B Rs, Rd
OR.W #xx:16, Rd
OR.W Rs, Rd
OR.L #xx:32, ERd
OR.L ERs, ERd
1
1
2
1
3
2
ORC ORC #xx:8, CCR 1
POP POP.W Rn
POP.L ERn
1
2
1
2
2
2
PUSH PUSH.W Rn
PUSH.L ERn
1
2
1
2
2
2
ROTL ROTL.B Rd
ROTL.W Rd
ROTL.L ERd
1
1
1
ROTR ROTR.B Rd
ROTR.W Rd
ROTR.L ERd
1
1
1
ROTXL ROTXL.B Rd
ROTXL.W Rd
ROTXL.L ERd
1
1
1
Appendix
Rev. 6.00 Mar. 24, 2006 Page 374 of 412
REJ09B0142-0600
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
ROTXR ROTXR.B Rd
ROTXR.W Rd
ROTXR.L ERd
1
1
1
RTE RTE 2 2 2
RTS RTS 2 1 2
SHAL SHAL.B Rd
SHAL.W Rd
SHAL.L ERd
1
1
1
SHAR SHAR.B Rd
SHAR.W Rd
SHAR.L ERd
1
1
1
SHLL SHLL.B Rd
SHLL.W Rd
SHLL.L ERd
1
1
1
SHLR SHLR.B Rd
SHLR.W Rd
SHLR.L ERd
1
1
1
SLEEP SLEEP 1
STC STC CCR, Rd
STC CCR, @ERd
STC CCR, @(d:16,ERd)
STC CCR, @(d:24,ERd)
STC CCR,@-ERd
STC CCR, @aa:16
STC CCR, @aa:24
1
2
3
5
2
3
4
1
1
1
1
1
1
2
SUB SUB.B Rs, Rd
SUB.W #xx:16, Rd
SUB.W Rs, Rd
SUB.L #xx:32, ERd
SUB.L ERs, ERd
1
2
1
3
1
SUBS SUBS #1/2/4, ERd 1
Appendix
Rev. 6.00 Mar. 24, 2006 Page 375 of 412
REJ09B0142-0600
Instruction
Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
SUBX SUBX #xx:8, Rd
SUBX. Rs, Rd
1
1
TRAPA TRAPA #xx:2 2 1 2 4
XOR XOR.B #xx:8, Rd
XOR.B Rs, Rd
XOR.W #xx:16, Rd
XOR.W Rs, Rd
XOR.L #xx:32, ERd
XOR.L ERs, ERd
1
1
2
1
3
2
XORC XORC #xx:8, CCR 1
Notes: 1. n:specified value in R4L and R4. The source and destination operands are accessed
n+1 times respectively.
2. Cannot be used in this LSI.
Appendix
Rev. 6.00 Mar. 24, 2006 Page 376 of 412
REJ09B0142-0600
A.4 Combinations of Instructions and Addressing Modes
Table A.5 Combinations of Instructions and Addressing Modes
Addressing Mode
MOV
POP, PUSH
MOVFPE,
MOVTPE
ADD, CMP
SUB
ADDX, SUBX
ADDS, SUBS
INC, DEC
DAA, DAS
MULXU,
MULXS,
DIVXU,
DIVXS
NEG
EXTU, EXTS
AND, OR, XOR
NOT
BCC, BSR
JMP, JSR
RTS
TRAPA
RTE
SLEEP
LDC
STC
ANDC, ORC,
XORC
NOP
Data
transfer
instructions
Arithmetic
operations
Logical
operations
Shift operations
Bit manipulations
Branching
instructions
System
control
instructions
Block data transfer instructions
BWL
—
—
BWL
WL
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
B
—
—
#xx
Rn
@ERn
@(d:16.ERn)
@(d:24.ERn)
@ERn+/@ERn
@aa:8
@aa:16
@aa:24
@(d:8.PC)
@(d:16.PC)
@@aa:8
—
BWL
—
—
BWL
BWL
B
L
BWL
B
BW
BWL
WL
BWL
BWL
BWL
B
—
—
—
—
—
—
B
B
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
W
W
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
B
—
—
—
—
—
—
—
—
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
BWL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BW
Functions Instructions
Appendix
Rev. 6.00 Mar. 24, 2006 Page 377 of 412
REJ09B0142-0600
Appendix B I/O Port Block Diagrams
B.1 I/O Port Block
RES goes low in a reset, and SBY goes low in a reset and in standby mode.
[Legend]
PDR
PUCR
PMR
PCR
SBYRES
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
IRQ
TRGV
Internal data bus
Pull-up MOS
Figure B.1 Port 1 Block Diagram (P17)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 378 of 412
REJ09B0142-0600
[Legend]
PDR
PUCR
PMR
PCR
SBYRES
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
IRQ
Internal data bus
Pull-up MOS
Figure B.2 Port 1 Block Diagram (P16 to P14)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 379 of 412
REJ09B0142-0600
PDR
PUCR
PCR
SBYRES
PUCR: Port pull-up control register
PDR: Port data register
PCR: Port control register
Internal data bus
Pull-up MOS
[Legend]
Figure B.3 Port 1 Block Diagram (P12, P11)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 380 of 412
REJ09B0142-0600
[Legend]
PDR
PUCR
PMR
PCR
SBYRES
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
Internal data bus
TMOW
Timer A
Pull-up MOS
Figure B.4 Port 1 Block Diagram (P10)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 381 of 412
REJ09B0142-0600
PDR
PMR
PCR
SBY
PMR: Port mode register
PDR: Port data register
PCR: Port control register
Internal data bus
TxD
SCI3
[Legend]
Figure B.5 Port 2 Block Diagram (P22)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 382 of 412
REJ09B0142-0600
[Legend]
PDR
PCR
SBY
PDR: Port data register
PCR: Port control register
RE
Internal data bus
RxD
SCI3
Figure B.6 Port 2 Block Diagram (P21)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 383 of 412
REJ09B0142-0600
PDR
PCR
SBY
PDR: Port data register
PCR: Port control register
SCKIE
Internal data bus
SCKI
SCI3
SCKOE
SCKO
[Legend]
Figure B.7 Port 2 Block Diagram (P20)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 384 of 412
REJ09B0142-0600
[Legend]
PDR
PCR
SBY
ICE
SDAO/SCLO
SDAI/SCLI
IIC
PDR: Port data register
PCR: Port control register
Internal data bus
Figure B.8 Port 5 Block Diagram (P57, P56)*
Note: * Not included in H8/3664N.
Appendix
Rev. 6.00 Mar. 24, 2006 Page 385 of 412
REJ09B0142-0600
[Legend]
PDR
PUCR
PMR
PCR
SBYRES
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
WKP
Internal data bus
ADTRG
Pull-up MOS
Figure B.9 Port 5 Block Diagram (P55)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 386 of 412
REJ09B0142-0600
[Legend]
PDR
PUCR
PMR
PCR
SBYRES
PUCR: Port pull-up control register
PMR: Port mode register
PDR: Port data register
PCR: Port control register
WKP
Internal data bus
Pull-up MOS
Figure B.10 Port 5 Block Diagram (P54 to P5 0)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 387 of 412
REJ09B0142-0600
PDR
PCR
SBY
OS3
OS2
OS1
OS0
TMOV
[Legend]
PDR: Port data register
PCR: Port control register
Internal data bus
Timer V
Figure B.11 Port 7 Block Diagram (P76)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 388 of 412
REJ09B0142-0600
PDR
PCR
SBY
TMCIV
PDR: Port data register
PCR: Port control register
Internal data bus
Timer V
[Legend]
Figure B.12 Port 7 Block Diagram (P75)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 389 of 412
REJ09B0142-0600
PDR
PCR
SBY
TMRIV
[Legend]
PDR: Port data register
PCR: Port control register
Internal data bus
Timer V
Figure B.13 Port 7 Block Diagram (P74)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 390 of 412
REJ09B0142-0600
PDR
PCR
SBY
PDR: Port data register
PCR: Port control register
Internal data bus
[Legend]
Figure B.14 Port 8 Block Diagram (P87 to P8 5)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 391 of 412
REJ09B0142-0600
PDR
PCR
SBY
PDR: Port data register
PCR: Port control register
Internal data bus
FTIOA
FTIOB
FTIOC
FTIOD
Timer W
Output
control
signals
A to D
[Legend]
Figure B.15 Port 8 Block Diagram (P84 to P8 1)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 392 of 412
REJ09B0142-0600
PDR
PCR
SBY
FTCI
PDR: Port data register
PCR: Port control register
Internal data bus
Timer W
[Legend]
Figure B.16 Port 8 Block Diagram (P80)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 393 of 412
REJ09B0142-0600
DEC
V
IN
CH3 to CH0
A/D converter
Internal data bus
Figure B.17 Port B Block Diagram (PB7 to PB0)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 394 of 412
REJ09B0142-0600
B.2 Port States in Each Operating State
Port Reset Sleep Subsleep Standby Subactive Active
P17 to P14,
P12 to P10
High
impedance
Retained Retained High
impedance*
Functioning Functioning
P22 to P20 High
impedance
Retained Retained High
impedance*
Functioning Functioning
P57 to P50
(P55 to P50
for
H8/3664N)
High
impedance
Retained Retained High
impedance
Functioning Functioning
P76 to P74 High
impedance
Retained Retained High
impedance
Functioning Functioning
P87 to P80 High
impedance
Retained Retained High
impedance
Functioning Functioning
PB7 to PB0 High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
High
impedance
Note: * High level output when the pull-up MOS is in on state.
Appendix
Rev. 6.00 Mar. 24, 2006 Page 395 of 412
REJ09B0142-0600
Appendix C Product Code Lineup
Product Type Product Code Model Marking Package Code
H8/3664 Flash memory
version with
EEPROM
Standard
product
HD64N3664FP HD64N3664FP LQFP-64 (FP-64E)
Flash memory
version
Standard
product
HD64F3664FP
HD64F3664H
HD64F3664FX
HD64F3664FY
HD64F3664BP
HD64F3664FP
HD64F3664H
HD64F3664FX
HD64F3664FY
HD64F3664BP
LQFP-64 (FP-64E)
QFP-64 (FP-64A)
LQFP-48 (FP-48F)
LQFP-48 (FP-48B)
SDIP-42 (DP-42S)
Mask ROM
version
Standard
product
HD6433664FP
HD6433664H
HD6433664FX
HD6433664FY
HD6433664BP
HD6433664 (***) FP
HD6433664 (***) H
HD6433664 (***) FX
HD6433664 (***) FY
HD6433664 (***) BP
LQFP-64 (FP-64E)
QFP-64 (FP-64A)
LQFP-48 (FP-48F)
LQFP-48 (FP-48B)
SDIP-42 (DP-42S)
H8/3663 Mask ROM
version
Standard
product
HD6433663FP
HD6433663H
HD6433663FX
HD6433663FY
HD6433663BP
HD6433663 (***) FP
HD6433663 (***) H
HD6433663 (***) FX
HD6433663 (***) FY
HD6433663 (***) BP
LQFP-64 (FP-64E)
QFP-64 (FP-64A)
LQFP-48 (FP-48F)
LQFP-48 (FP-48B)
SDIP-42 (DP-42S)
H8/3662 Mask ROM
version
Standard
product
HD6433662FP
HD6433662H
HD6433662FX
HD6433662FY
HD6433662BP
HD6433662 (***) FP
HD6433662 (***) H
HD6433662 (***) FX
HD6433662 (***) FY
HD6433662 (***) BP
LQFP-64 (FP-64E)
QFP-64 (FP-64A)
LQFP-48 (FP-48F)
LQFP-48 (FP-48B)
SDIP-42 (DP-42S)
H8/3661 Mask ROM
version
Standard
product
HD6433661FP
HD6433661H
HD6433661FX
HD6433661FY
HD6433661BP
HD6433661 (***) FP
HD6433661 (***) H
HD6433661 (***) FX
HD6433661 (***) FY
HD6433661 (***) BP
LQFP-64 (FP-64E)
QFP-64 (FP-64A)
LQFP-48 (FP-48F)
LQFP-48 (FP-48B)
SDIP-42 (DP-42S)
Appendix
Rev. 6.00 Mar. 24, 2006 Page 396 of 412
REJ09B0142-0600
Product Type Product Code Model Marking Package Code
H8/3660 Mask ROM
version
Standard
product
HD6433660FP
HD6433660H
HD6433660FX
HD6433660FY
HD6433660BP
HD6433660 (***) FP
HD6433660 (***) H
HD6433660 (***) FX
HD6433660 (***) FY
HD6433660 (***) BP
LQFP-64 (FP-64E)
QFP-64 (FP-64A)
LQFP-48 (FP-48F)
LQFP-48 (FP-48B)
SDIP-42 (DP-42S)
[Legend]
(***): ROM code
Appendix
Rev. 6.00 Mar. 24, 2006 Page 397 of 412
REJ09B0142-0600
Appendix D Package Dimensions
The package dimensions that are shows in the Renesas Semiconductor Packages Data Book have
priority.
Package Code
JEDEC
EIAJ
Mass
(reference value)
FP-64E
−
Conforms
0.4 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
M
12.0 ± 0.2
10
48 33
116
17
32
64
49
*0.22 ± 0.05 0.08
0.5
12.0 ± 0.2
0.10
1.70 Max
*0.17 ± 0.05
0.5 ± 0.2
0° − 8°
1.0
1.45
0.10 ± 0.10
1.25
0.20 ± 0.04
0.15 ± 0.04
Figure D.1 FP-64E Package Dimensions
Appendix
Rev. 6.00 Mar. 24, 2006 Page 398 of 412
REJ09B0142-0600
Package Code
JEDEC
EIAJ
Mass (reference value)
FP-64A
−
Conforms
1.2 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.10
0.15 M
17.2 ± 0.3
48 33
49
64
116
32
17
17.2 ± 0.3
0.35 ± 0.06
0.8
3.05 Max
14
2.70
0° − 8°
1.6
0.8 ± 0.3
*0.17 ± 0.05
0.10+0.15
- 0.10
1.0
*0.37 ± 0.08
0.15 ± 0.04
Figure D.2 FP-64A Package Dimensions
Appendix
Rev. 6.00 Mar. 24, 2006 Page 399 of 412
REJ09B0142-0600
Package Code
JEDEC
EIAJ
Mass
(reference value)
FP-48F
—
—
0.4 g
*Dimension including the plating thickness
Base material dimension
0.10
0 – 8
0.50 ± 0.1
*0.17 ± 0.05
0.1 ± 0.05
1.65 Max
1.0
12.0 ± 0.2
10
*0.32 ± 0.05 0.13
36 25
112
37
48
24
13
0.65
12.0 ± 0.2
M
0.30 ± 0.04
1.425
1.45
0.15 ± 0.04
Unit: mm
°°
Figure D.3 FP-48F Package Dimensions
Appendix
Rev. 6.00 Mar. 24, 2006 Page 400 of 412
REJ09B0142-0600
Package Code
JEDEC
JEITA
Mass
(reference value)
FP-48B
—
—
0.2 g
*Dimension including the plating thickness
Base material dimension
9.0 ± 0.2
7
*0.22 ± 0.05 0.08
36 25
112
37
48
24
13
0.5
9.0 ± 0.2
0.08
1.0
0˚ – 8˚
0.5 ± 0.1
*0.17 ± 0.05
1.70 Max
M
0.75
0.20 ± 0.04
1.40
0.15 ± 0.04
0.10 ± 0.07
Unit: mm
Figure D.4 FP-48B Package Dimensions
Package Code
JEDEC
EIAJ
Mass
(reference value)
DP-42S
−
Conforms
4.8 g
Unit: mm
0.25 + 0.10
- 0.05
0° − 15°
15.24
37.3
38.6 Max
1.0
14.0
14.6 Max
0.51 Min
5.10 Max
2.54 Min
0.48 ± 0.10
1.78 ± 0.25
42 22
121
1.38 Max
Figure D.5 DP-42S Pack age Dimensions
Appendix
Rev. 6.00 Mar. 24, 2006 Page 401 of 412
REJ09B0142-0600
Appendix E EEPROM Stacked-Structure Cross-Sectional
View
Figure E.1 EEPROM Stacked-Structure Cross-Sectional View
Appendix
Rev. 6.00 Mar. 24, 2006 Page 402 of 412
REJ09B0142-0600
Rev. 6.00 Mar. 24, 2006 Page 403 of 412
REJ09B0142-0600
Main Revisions and Additions in this Edition
Item Page Revision (See Manual for Details)
Preface
Notes
vi, vii Amended
When using the on-chip emulator (E7, E8) for H8/3664
program development and debugging, the following
restrictions must be noted (the on-chip debugging
emulator (E7) can also be used).
1. The NMI pin is reserved for the E7 or E8, and
cannot be used.
2. Pins P85, P86, and P87 cannot be used. In order to
use these pins, additional hardware must be
provided on the user board.
3. Area H'7000 to H'7FFF is used by the E7 or E8, and
is not available to the user.
4. Area H'F780 to H'FB7F must on no account be
accessed.
5. When the E7 or E8 is used, address breaks can be
set as either available to the user or for use by the
E7 or E8. If address breaks are set as being used
by the E7 or E8, the address break control registers
must not be accessed.
6. When the E7 or E8 is used, NMI is an input/output
pin (open-drain in output mode), P85 and P87 are
input pins, and P86 is an output pin.
Figure 5.3 Typical Connection to
Crystal Resonator
Figure 5.5 Typical Connection to
Ceramic Resonator
Figure 5.8 Typical Connection to
32.768-kHz Crystal Resonator
78 to
80
Added
Note: Capacitances are reference values.
Rev. 6.00 Mar. 24, 2006 Page 404 of 412
REJ09B0142-0600
Item Page Revision (See Manual for Details)
6.1.1 System Control Register 1
(SYSCR1)
85 Amended
Bit Bit Name Description
3 NESEL Noise Elimination Sampling Frequency Select
The subclock pulse generator generates the watch
clock signal (φW) and the system clock pulse
generator generates the oscillator clock (φOSC). This
bit selects the sampling frequency of the oscillator
clock when the watch clock signal (φW) is sampled.
When φOSC = 4 to 16 MHz, clear NESEL to 0.
0: Sampling rate is φOSC/16
1: Sampling rate is φOSC/4
Table 7.2 Boot Mode Operation 102 Amended
Communication Contents
Processing Contents
Host Operation LSI Operation
Processing Contents
Continuously transmits data H'00
at specified bit rate.
H'00, H'00 . . . H'00
H'00
H'55 H'55 reception.
Transmits data H'55 when data H'00
is received error-free.
Item
• Measures low-level period of receive data
H'00.
• Calculates bit rate and sets BRR in SCI3.
• Transmits data H'00 to host as adjustment
end indication.
Bit rate adjustment
9.5.3 Pin Functions
• P84/FTIOD Pin
136 Amended
Register TMRW TIOR1 PCR8
Bit Name PWMD IOD2 IOD1 IOD0 PCR84 Pin Function
0 0 0 0 0 P84 input/FTIOD input pin
1 P84 output/FTIOD input pin
0 0 1 X FTIOD output pin
0 1 X X FTIOD output pin
1 X X 0 P84 input/FTIOD input pin
1 P84 output/FTIOD input pin
Setting Value
1 X X X X PWM output pin
Rev. 6.00 Mar. 24, 2006 Page 405 of 412
REJ09B0142-0600
Item Page Revision (See Manual for Details)
9.5.3 Pin Functions
• P83/FTIOC Pin
136 Amended
Register TMRW TIOR1 PCR8
Bit Name PWMC IOC2 IOC1 IOC0 PCR83 Pin Function
0 0 0 0 0 P83 input/FTIOC input pin
1 P83 output/FTIOC input pin
0 0 1 X FTIOC output pin
0 1 X X FTIOC output pin
1 X X 0 P83 input/FTIOC input pin
1 P83 output/FTIOC input pin
Setting Value
1 X X X X PWM output pin
9.5.3 Pin Functions
• P82/FTIOB Pin
137 Amended
Register TMRW TIOR0 PCR8
Bit Name PWMB IOB2 IOB1 IOB0 PCR82 Pin Function
0 0 0 0 0 P82 input/FTIOB input pin
1 P82 output/FTIOB input pin
0 0 1 X FTIOB output pin
0 1 X X FTIOB output pin
1 X X 0 P82 input/FTIOB input pin
1 P82 output/FTIOB input pin
Setting Value
1 X X X X PWM output pin
11.3.4 Timer Control/Status
Register V (TCSRV)
150,
151
Amended
Bit Bit Name Description
3
2
OS3
OS2
Output Select 3 and 2
These bits select an output method for the
TMOV pin by the compare match of TCORB and
TCNTV.
00: No change
01: 0 output1
:
1
0
OS1
OS0
Output Select 1 and 0
These bits select an output method for the
TMOV pin by the compare match of TCORA and
TCNTV.
:
13.2.1 Timer Control/Status
Register WD (TCSRWD)
192 Amended
Bit Bit Name Description
4 TCSRWE Timer Control/Status Register WD Write Enable
:
Rev. 6.00 Mar. 24, 2006 Page 406 of 412
REJ09B0142-0600
Item Page Revision (See Manual for Details)
15.5 Usage Notes
• Notes on WAIT Function
• Notes on TRS Bit Setting and
ICDR Register Access
271 to
274
Added.
16.3.1 A/D Data Registers A to D
(ADDRA to ADDRD)
278 Amended
… Therefore, byte access to ADDR should be done by
reading the upper byte first then the lower one. Word
access is also possible. ADDR is initialized to H'0000.
Table 20.2 DC Characteristics (1) 314 Amended
Values
Item Applicable Pins Test Condition Min
Input high
voltage
PB0 to PB7 VCC = 4.0 V to 5.5 V VCC × 0.7
AVCC = 3.3 V to 5.5 V VCC × 0.8
Input low
voltage
P50 to P57*,
P74 to P76,
P80 to P87,
PB0 to PB7
–0.3
Pb0 to PB7 AVCC = 4.0 V to 5.5 V –0.3
AVCC = 3.3 V to 5.5 V –0.3
Table 20.2 DC Characteristics (1)
Table 20.10 DC Characteristics
(1)
318,
335
Amended
Note: * Pin states during supply current
measurement are given below (excluding
current in the pull-up MOS transistors and
output buffers).
Mode RES Pin Internal State
Active mode 1 VCC Operates
Active mode 2 Operates
(φosc/64)
Sleep mode 1 VCC Only timers operate
Sleep mode 2 Only timers operate
(φosc/64)
Rev. 6.00 Mar. 24, 2006 Page 407 of 412
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Item Page Revision (See Manual for Details)
Table 20.10 DC Characteristics
(1)
331,
332
Amended
Values
Item Applicable Pins Test Condition Mi n
Input high
voltage
PB0 to PB7 VCC = 4.0 V to 5.5 V VCC × 0.7
AVCC = 3.3 V to 5.5 V VCC × 0.8
Input low
voltage
P50 to P57*,
P74 to P76,
P80 to P87,
PB0 to PB7
–0.3
Pb0 to PB7 AVCC = 4.0 V to 5.5 V –0.3
AVCC = 3.3 V to 5.5 V –0.3
Table A.1 Instruction Set
2. Arithmetic instructions
351 Amended
Mnemonic
Operand Size
No. of
States
*1
Condition Code
IHNZVC
DAA Rd B *2
Normal
Advanced
↔
*
↔
DAA
↔
Rev. 6.00 Mar. 24, 2006 Page 408 of 412
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Rev. 6.00 Mar. 24, 2006 Page 409 of 412
REJ09B0142-0600
Index
A
A/D converter ......................................... 275
Sample-and-hold circuit...................... 282
Scan mode........................................... 281
Single mode ........................................ 281
Absolute maximum ratings..................... 311
Address break ........................................... 67
Addressing modes..................................... 35
Absolute address................................... 37
Immediate ............................................. 37
Memory indirect ................................... 38
Program-counter relative ...................... 37
Register direct....................................... 36
Register indirect.................................... 36
Register indirect with displacement...... 36
Register indirect with post-increment... 36
Register indirect with pre-decrement.... 36
C
Clock
Clock pulse generators.......................... 77
Subclock generator ............................... 80
System clock generator......................... 78
Condition-code register (CCR)................. 19
CPU .......................................................... 13
E
EEPROM................................................ 287
acknowledge ....................................... 291
Acknowledge polling.......................... 294
Byte write ........................................... 293
Corresponding slave address reference
address (ESAR) .................................. 292
Current address read ........................... 295
EEPROM interface ............................. 290
EEPROM key register (EKR) ............. 289
Page write ...........................................293
Random address read ..........................296
Sequential read.................................... 296
Slave addressing..................................292
Start condition..................................... 291
Stop condition ..................................... 291
Effective address.......................................39
Electrical characteristics
(F-ZTAT™ version, F-ZTAT™ version
with EEPROM)
AC characteristics ............................... 320
Electrical characteristics
(F-ZTAT™ version, F-ZTAT™ version
with EEPROM).......................................311
DC characteristics ............................... 314
Electrical characteristics
(Mask ROM version) ..............................329
AC characteristics ............................... 337
DC characteristics ............................... 331
Exception handling ................................... 51
Reset exception handling ......................59
Trap instruction..................................... 51
F
Flash memory
On-board programming modes ........... 100
Flash memory ........................................... 95
Boot mode........................................... 101
Boot program ......................................100
Erase/erase-verify ............................... 107
Error protection................................... 109
Hardware protection............................ 109
Power-down state................................ 110
Program/program-verify ..................... 104
Programmer mode............................... 110
Rev. 6.00 Mar. 24, 2006 Page 410 of 412
REJ09B0142-0600
Software protection............................. 109
G
General registers....................................... 18
I
I/O ports.................................................. 115
I/O port block diagrams...................... 377
I2C bus interface (IIC) ............................ 233
Acknowledge...................................... 250
Clock synchronous serial format ........ 259
General call address............................ 247
I2C bus data formats ........................... 250
I2C transfer rate................................... 241
Slave address ...................................... 250
Start condition .................................... 250
Stop condition..................................... 250
Instruction set ........................................... 24
Interrupt
Internal interrupts ................................. 61
Interrupt response time ......................... 62
IRQ3 to IRQ0 interrupts....................... 59
NMI interrupt........................................ 59
WKP5 to WKP0 interrupts ................... 60
Interrupt mask bit (I)................................. 19
L
Laminated-structure cross section of
H8/3664N ............................................... 401
Large current ports...................................... 1
M
Memory map ............................................ 14
P
Package....................................................... 2
Package dimensions................................ 397
Pin arrangement .......................................... 5
Power supply circuit
Internal power supply step-down circuit
............................................................ 299
Power supply circuit ............................... 299
Power-down modes................................... 83
Module standby function ...................... 94
Sleep mode............................................ 91
Standby mode ....................................... 91
Subactive mode..................................... 92
Subsleep mode ...................................... 92
Prescaler S ................................................ 81
Prescaler W............................................... 81
Product code lineup ................................ 395
Program counter (PC) ............................... 19
R
Registers
ABRKCR...................... 68, 303, 306, 309
ABRKSR ...................... 70, 303, 306, 309
ADCR ......................... 280, 303, 306, 309
ADCSR....................... 279, 303, 306, 309
ADDRA ...................... 278, 303, 306, 309
ADDRB ...................... 278, 303, 306, 309
ADDRC ...................... 278, 303, 306, 309
ADDRD ...................... 278, 303, 306, 309
BARH ........................... 70, 303, 306, 309
BARL............................ 70, 303, 306, 309
BDRH ........................... 70, 303, 306, 309
BDRL............................ 70, 303, 306, 309
BRR ............................ 205, 302, 306, 308
EBR1............................. 99, 302, 305, 308
EKR ............................ 289, 304, 307, 310
FENR .......................... 100, 302, 305, 308
FLMCR1....................... 97, 302, 305, 308
FLMCR2....................... 98, 302, 305, 308
FLPWCR ...................... 99, 302, 305, 308
GRA............................ 171, 302, 305, 308
Rev. 6.00 Mar. 24, 2006 Page 411 of 412
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GRB............................ 171, 302, 305, 308
GRC............................ 171, 302, 305, 308
GRD............................ 171, 302, 305, 308
ICCR........................... 242, 303, 306, 309
ICDR........................... 236, 303, 306, 309
ICMR.......................... 239, 303, 306, 309
ICSR ........................... 245, 303, 306, 309
IEGR1........................... 53, 304, 307, 310
IEGR2........................... 54, 304, 307, 310
IENR1........................... 55, 304, 307, 310
IRR1 ............................. 56, 304, 307, 310
IWPR ............................ 57, 304, 307, 310
MSTCR1....................... 87, 304, 307, 310
PCR1........................... 117, 304, 307, 310
PCR2........................... 121, 304, 307, 310
PCR5........................... 126, 304, 307, 310
PCR7........................... 131, 304, 307, 310
PCR8........................... 134, 304, 307, 310
PDR1 .......................... 118, 303, 306, 309
PDR2 .......................... 122, 303, 306, 309
PDR5 .......................... 127, 303, 306, 309
PDR7 .......................... 131, 303, 307, 309
PDR8 .......................... 134, 303, 307, 309
PDRB.......................... 138, 304, 307, 309
PMR1.......................... 116, 304, 307, 309
PMR5.......................... 125, 304, 307, 309
PUCR1........................ 118, 303, 306, 309
PUCR5........................ 127, 303, 306, 309
RDR............................ 199, 303, 306, 308
RSR..................................................... 199
SAR ............................ 238, 303, 306, 309
SARX ......................... 238, 303, 306, 309
SCR3........................... 201, 302, 306, 308
SMR............................ 200, 302, 306, 308
SSR............................. 203, 303, 306, 308
SYSCR1 ....................... 84, 304, 307, 310
SYSCR2 ....................... 86, 304, 307, 310
TCA ............................ 142, 302, 305, 308
TCNT.......................... 170, 302, 305, 308
TCNTV....................... 147, 302, 305, 308
TCORA....................... 148, 302, 305, 308
TCORB ....................... 148, 302, 305, 308
TCRV0........................ 148, 302, 305, 308
TCRV1........................ 151, 302, 305, 308
TCRW......................... 164, 302, 305, 308
TCSRV........................ 150, 302, 305, 308
TCSRWD.................... 192, 303, 306, 309
TCWD......................... 193, 303, 306, 309
TDR ............................ 200, 303, 306, 308
TIERW........................ 165, 302, 305, 308
TIOR0 ......................... 167, 302, 305, 308
TIOR1 ......................... 169, 302, 305, 308
TMA............................ 141, 302, 305, 308
TMRW........................ 163, 302, 305, 308
TMWD........................ 194, 303, 306, 309
TSCR .......................... 248, 304, 307, 310
TSR ..................................................... 199
TSRW ......................... 166, 302, 305, 308
S
Serial communication interface 3 (SCI3) 197
Asynchronous mode............................ 210
Bit rate................................................. 205
Break detection ................................... 230
Clocked synchronous mode ................ 218
Framing error ......................................214
Mark state ...........................................231
Multiprocessor communication
function ...............................................224
Overrun error ...................................... 214
Parity error ..........................................214
Stack pointer (SP) .....................................19
T
Timer A................................................... 139
Timer V................................................... 145
Timer W.................................................. 159
PWM operation................................... 176
Rev. 6.00 Mar. 24, 2006 Page 412 of 412
REJ09B0142-0600
V
Vector address .......................................... 52
W
Watchdog timer....................................... 191
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8/3664 Group
Publication Date: 1st Edition, Mar, 2000
Rev.6.00, Mar. 24, 2006
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by: Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
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Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
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H8/3664 Group
REJ09B0142-0600
Hardware Manual
