1
TM HIP0050
0.3A/50V Octal Low Side Power Driver with
Serial Bus C ontrol and Over-C urrent Fau lt Flag
Description
The HIP0050 is a logic controlled, eight channel Octal Low Side
Power Driver. As shown in the block diagram, the outputs are con-
trolled via the serial data interface which allows the data to be
shifted out, allowing control of other cascaded serial devices. If an
Ove r-Current (OC) short ci rcui t exist s in one out put, it may be inde -
pendently shutdown while the other outputs remain in operation.
When a shorted output is latched off, it may be turned back on
when the next serial input data is latched. A fault flag (FLT) is set
to a low status to indicate current-limited shutdown. The outputs
are independently latched off when an OC fault is detected. The
fault latch is cleared on the next data strobe. Over-Temperature
(OT) shutdown is provided with hysteresis to force global shut-
down of all output dri vers. Shu tdown is m aintained until the on-chip
temperature falls below the minimum hys ter esis threshold point.
The HIP0050 is fabricated in a Power BiMOS IC process, and is
intended for use in automotive and other applications having a
wide range of temperature and electrical stress conditions. It is
particularly suited for driving lamps, displays, relays, and solenoids in
applications where low operating power, high breakdown voltage,
and high output current at high temperature is required. Higher
current needs can be met by paralleli ng adjacent output drivers.
Ordering Information
PART
NUMBER TEMP.
RANGE (oC) PACKAGE PKG. NO.
HIP050IP -40 to 85 20 Ld PDIP E20.3
HIP0050IB -40 to 85 24 Ld SOI C M24. 3
Features
• Octal NDMOS Output Drivers in a High Voltage
Power BiMOS Process
- Each Capable of Sinking 300mA
- Low Idle and Standby Current
• Over-Stress Prot ection - Each Output:
- Over -Current Latch Off . . . . . . . . . 300mA Min
- Over-Voltage Clamp . . . . . . . . . . . . . . . 50V Typ
• Thermal Shutdown with Hysteresis
• Serial Data Input, Parallel Output Power Drive
• Short Circuit Latch Off for Each Output
• Common Enable for Output Drivers and
Data Stor age Register
• Ambient Operating
T emperature Range. . . . . . . . . . . . .-40oC to 85oC
- Optional 125oC Maximum Ambient Operating
Tem perature Range (Dissi patio n Limit ed)
Applications
• Automotive and Industrial Systems
• Solenoids, Relays and Lamp Drivers
• Logic and µP Control led Drivers
• Robotic Cont rol s
December 1996
FN4034.1
Pinouts HIP0050
(PDIP)
T OP VIEW
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
DR2
DR3
FLT
EN
GND
GND
SCK
STR
DR4
DR5
DR1
SI
VCC
GND
DR0
GND
LGND
SO
DR7
DR6
HIP0050
(SOIC)
TOP VIEW
DR2
DR3
FLT
EN
GND
GND
GND
GND
STR
SCK
DR4
DR5
DR1
SI
VCC
GND
GND
GND
SO
DR7
DR6
DR0
GND
LGND
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
CAUTION: These devices are sensitive to electrosta tic dis charge; follow proper I C Handling Proc edures.
1- 888-INTE R SIL or 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
2
HIP0050
Block Diagram
Output Control Logic Table
STROBE 8-BIT S ERIAL DATA (LATCHED) OUTPUT
D1 D2 D3 D4 D5 D6 D7 D8 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DR8
0 0 0 0 0 0 0 0 OFF OFF OFF OFF OFF OFF OFF OFF
1 0 0 0 0 0 0 0 ON OFF OFF OFF OFF OFF OFF OFF
1 1 0 0 0 0 0 0 ON ON OFF OFF OFF OFF OFF OFF
1 1 1 0 0 0 0 0 ON ON ON OFF OFF OFF OFF OFF
1 1 1 1 0 0 0 0 ON ON ON ON OFF OFF OFF OFF
0 0 0 0 1 1 1 1 OFF OFF OFF OFF ON ON ON ON
1 1 1 1 1 1 1 1 ON ON ON ON ON ON ON ON
SCK
OUTPUT
OC
SHUT-
OVER-TEMPERATURE
SHUTDOWN W/HYS
OUTPUT DRIVER
(CHANNEL 1 OF 8)
DR#0
LATCH
POR
EN
FAULT
LATCH
FLT
(STROBE)
SI
SO
DOWN
SERIAL
(SPI)
PARALLEL
(DATA IS
REGISTER
INPUT
STR
(ENABLE)
Q1
Q2
Q3
Q4
Q5
Q6
Q7
STROBED)
WHEN
LATCHED
OUTPUT
S
R
Q0
3
HIP0050
Absolute Maximum Ratings Thermal Information
Output Voltage, VOUT (Note 1) . . . . . . . . . . . . . . . . . . . -0.3V to VOC
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC +0.3V
Logic S up pl y Voltag e, VCC . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Max O utput Load Current, ILOAD (Per Output, Note 2). . . . . . . . . ICL
Max. Output Load Curre nt, ILOAD (All Outputs ON, Note 2) . . . . . 2A
Operating Ambient Temperature Range, TA. . . . . . . . -40oC to 85oC
Operating Junction Temperature Range. . . . . . . . . . -40oC to 150oC
Storage Temperature Range, TSTG . . . . . . . . . . . . . -55oC to 150oC
Maximum Lead Temperature (Soldering 10s Max). . . . . . . . . 300oC
(L ea d Tips Onl y )
CAUTIO N: Stresses abov e those listed i n “Abso lute Ma ximum Rati ngs” ma y cause pe rmanent dam age to the dev ice. T his is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Ope rat i ng Condi t io ns
Ty pi c al Lo gic S up pl y Volt ag e, VCC . . . . . . . . . . . . . . . . . . . . . +5V
ICC Supply Current, with 200mA each Output . . . . . . . . . . . . 2mA
ICC Supply Current, with No Load . . . . . . . . . . . . . . . . . . . . . 2mA
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0V
Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5V
Power Output Driver Voltage Range. . . . . . . . . . . . . . . . . 0 to VOC
Power Output Driver Current Load, IDR . . . . . . . . . . . . . . . 0 to ICL
Ty p ical O utp ut rDSON Channel Resistance . . . . . . . . . . . . . . . . 2Ω
Typical Output Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4µs
Typical Output Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µs
Electrical Specifications VCC = 4 .5V to 5.5V, VBATT = 8V to 16V, TA = -40oC to 85oC; Unless Otherwise Specified
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OUTPUTS DRIVERS (DR0 TO DR7)
Ou t p ut C hannel Re si stance rDSON Output Current = 20 0mA, TA=85
oC- 24.0Ω
Outp ut Over-Current Shutdown
Threshold ICL 300 - 500 mA
Output Clamping Voltage VOC Outputs OFF 425058 V
Output Clamping Energy EOC 1ms Single Pulse Width, TA = 25 oC,
(Refer to Figure 2 for SOA). -25-mJ
Ou tput O F F Le ak ag e C urr e nt IOFF Output Voltage = 40V, TA=85
oC--10µA
Output Ris e Time tRISE Load = 75Ω, 0.01µF (Parallel) 0.5 4 30 µs
Ou tp ut Fa ll Tim e tFALL Load = 75Ω, 0.01µF (Parallel) 0.5 10 30 µs
Output Delay from Strobe, High
to Low Output Transition tDHL 1410µs
Output Delay from Strobe, Low to
High Output Transition tDLH 0.2 2.6 10 µs
LOGIC SUPPLY
Logic Supply Current, Loaded ICC All Out puts ON, 0.2A Load Per Output - 2 4 mA
Logic Supply Cur rent, No Loa d ICC A ll Output s OFF - 2 4 mA
Logic Supply Under-Voltage
Reset Threshold All Output s OFF 3.5 - 4 V
LOGIC INPUTS (EN, SI, SCK, STR)
Threshold Volt age at Falling
Edge VT-V
CC = 5V ±10% 0.2VCC 0.3VCC -V
Threshold Volt age at Rising
Edge VT+V
CC = 5V ±10% - 0.6VCC 0.7VCC V
Hysteresis Voltage VHVT+ - VT- 0.85 1.4 2.25 V
Leakage Current ILIN -10 - 10 µA
SERIAL DATA CLOCK (SCK) (Refer to Figure 1 for W aveform Detail)
Frequency fSCK --1.6MHz
Pulse Width High tW(SCKH) - 27 175 ns
P
ackage
θJC (
o
C/W)
†
θJA (
o
C/W)
††
02
PDIP . . . . . . . . . . . . . 10 50 35
SOIC . . . . . . . . . . . . . 10 60 40
†
Versus Additional Square Inches 1oz. copper on PCB.
†
†Standard Test Board, 0.002 diameter T/C located at lea
d
shoulder, middle lead.
4
HIP0050
FIGURE 1. LOGIC TIMING CONTROL WAVEFORMS
Pulse Width Low tW(SCKL) - 27 175 ns
SERIAL DATA IN (SI) (Refer to Figure 1 for Waveform Detail)
In p ut Setup Time tSUI -1.175ns
In p ut Hold Time THI -1.575ns
STR OBE (STR)
Strobe Pulse Width tW(S) - 12 150 ns
Clock to Strobe Delay tD(CS) -575ns
SERIAL DATA OUT (SO) (Refer to Figure 1 for Waveform Detail)
Low Level Output Voltage VOL Sink Curr ent = 1.6mA - 0.2 0.4 V
High Level Output Voltage VOH Source Current = -1.6mA 3.7 4.4 - V
Propagation Delay tP(CD) 75 260 500 ns
PROTECTION PARAMETERS
Fault Output (FLT) Low VOL Sink Current = 1.6mA - - 0.4 V
Over -Temp. (OT) Shutdown TSD 145 155 165 oC
OT Shutdown Hysteresis TH51020
oC
NOTES:
1. The MOSFET Outp ut Drain is internally cl amped w ith a Drain -to-G ate Ze ner Diode that turns on the MOSFET; holding the d rain at the
out p ut clam p vo ltage V OC.
2. The HIP0050 Output Drive is protected by an internal current shutdown. The ICL over- curre nt shut down th reshol d par amete r spe cifica tio n
defines the maximum current. The minimum limit for this threshold is 300mA. The maximum curre nt with all outputs ON may be further
limited by dissipation.
3. Pack age dissipation is based o n thermal resistance capability in a n ormal operating envir onment. The junction to ambient therma l resi s-
tance value s are d efined he re as a PC Board mounted de vice w ith minimal copper. Due to t he heat conducting capabi lity of the DIP a n d
SOIC pac k age lead fram es, 35oC /W thermal resistan ce can be achieved with ap proxi m ately 2 square inches of 1 oz. copper PC Board
area. The junction to lead thermal resistance values are based on measurements from the chip to the ground leads of the package.
Electrical Specifications VCC = 4 .5V to 5.5V, VBATT = 8V to 16V, TA = -40oC to 85oC; Unless Otherwise Specified (Continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCK (CLOCK)
SI (SERIAL DATA IN)
STR (STROBE)
DRx (POWER OUTPUT DRIVER)
SO (SERIAL DATA OUT)
tW(SCK) tW(SCK)
tSUI tHI
tD(CS) tW(S)
tD(LH)
tD(HL)
tP(CD) tFALL, tRISE
10%
90%
5
HIP0050
Pin D escr ipt ion s
VCC Power Pin
The VCC pin is the positive 5V logic voltage supply input f or
the IC. The normal operating voltage range is 4.5V to 5.5V.
When switched on, the POR forces all outputs off.
SCK Serial Clock Pi n
SCK is the clock input for the SPI Interf ace. Output ON/OFF
control data is clocked into an eight stage shift register on
the rising edge of an external clock. This input has a Schm itt
trigger.
SI Serial Data In Pin
SI i s the Ser ial Data I nput Pin for the SPI Interface. The eight
power outputs are contro ll ed by the ser ial data via th e outp ut
data buffer. This input has a Schmitt Trigger.
STR S tr obe Pin fo r the SPI Interface
When t he STR Pin is high, data from the 8-bit shi ft regist er i s
passed into the output data buff ers where it controls the ON-
OFF state of each output driver. The data is latched in the
output data buffers when STR goes low. This input has a
Schm it t t ri gger.
SO Serial Data Out Pin
The serial data out allows other I Cs to be serially cascaded.
For example, a 10-bit LED driver may be located behind the
HIP0050. A controlling microprocessor may then clock out
18-bits of information and simultaneously strobe both parts.
The cascaded ICs may be the same or different from the
HIP0050.
DR0 - DR7 Output s 0 Thru 7
The drain output pi ns of the DMOS Power Drivers are capa-
ble of sinking 300mA. Each output has short cir cuit protection to
independently shutdown the outpu t under excessive high load
current conditions.
FLT Fault Flag
The fault flag pin indicates an over-current in any one of the
output driver s. (It i s not an i ndicator for the therm al shutdown
mode.) The FLT output is active low and can sink 1.6mA
when acti vated. When latched low, it will remain latched until
the next data strobe.
EN Enable Pin
The enable pin is an active low enable function for all eight
output drivers. When EN is high, drive from the output data
buffer is held low and all output drivers are disabled. When
EN is lo w, the output drivers are en abled and data in t he 8- bit
shi ft re gi s ter is t ran sparent to the output data buff er. This input
has a Schmitt t rigger.
LGND and GND Pins
The LGND Pin is the 5V Logic Supply Ground for the I C and
GND is a common ground for the power output d ri vers.
FIGURE 2. MAXIMUM SINGLE PULSE ENERGY SAFE OPERATING AREA FOR EACH CLAMPED OUTPUT DRIVER, T A = 25oC
0.1 1 10 100
1
10
100
TIME (ms)
ENERGY (mJ)
SAFE OPERATING AREA
BELOW LINE
1000
6
HIP0050
E20.3 (J EDEC MS-00 1-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.55 1.77 8
C 0.008 0.014 0.204 0.355 -
D 0.980 1.060 24.89 26.9 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N20 209
Re v. 0 1 2 /93
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Me tric di mensions, t he inch dimensions control.
2. Dim ensioning and tol erancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dim ens ions A , A1 a nd L a re me as ur ed wit h th e p ac kag e s ea ted
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mo ld flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and are measured with the leads constrained to be per-
pendic ular to da tum .
7. eB and eC are measured at the lea d tips with the leads uncon-
strained. eC must be ze r o or gr e ate r .
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 in ch (0.25mm).
9. N is the maximum number of terminal positio ns.
10. Corner l eads (1, N, N/2 and N/2 + 1) for E 8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
C
L
E
eA
C
eB
eC
-B-
E1
I
NDEX 12 3 N/2
N
AREA
S
EATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
eA-C
-
Du al-In-L ine Pla stic Pac kag es (PDIP)
7
HIP0050
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N24 247
α0o8o0o8o-
Re v. 0 1 2 /93
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dim ensioning and tol erancing per ANSI Y14.5M-1982.
3. Dimen si on “ D” does no t inc lu de mol d f la sh , pro tru si ons or ga te
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for r efer ence only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETE R. Converted inch di men-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C A
MBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45 o
C
H
µ
0.25(0.010) B
MM
α
Small Outline Plastic Packages (S OIC)
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersi l prod ucts are sold by descripti on only. Intersil Corporati on res erves the rig ht to make changes in circuit desi gn and/ or specificat ions at any time w ithout noti ce.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is bel ieved to be accurate and reli-
able. However, no responsibility is assumed by Intersil or i ts subsidiaries for its use; nor for any infringements of patents o r other rights of third parties which may
result from its use. No license is gra n ted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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