!
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DLow Supply Voltage . . . 1.8 V to 3.6 V
DVery Low Supply Current ...20 µA (per
channel)
DUltralow Power Shut-Down Mode
− IDD(SHDN) = 10 nA/Channel
DCMOS Rail-to-Rail Input/Output
DInput Common-Mode Voltage
Range . . . −0.2 V to VDD + 0.2 V
DInput Offset Voltage . . . 550 µV
DWide Bandwidth . . . 500 kHz
DSlew Rate . . . 0.20 V/µs
DSpecified Temperature Range:
0°C to 70°C . . . Commercial Grade
−40°C to 85°C . . . Industrial Grade
DUltrasmall Packaging
5 or 6 Pin SOT-23 (TLV2760/1)
8 or 10 Pin MSOP (TLV2762/3)
DUniversal Op-Amp EVM
description
The TLV276x single supply operational amplifiers provide 500 kHz bandwidth from only 20 µA while operating
down to 1.8 V over the industrial temperature range. The maximum recommended supply voltage is 3.6 V, which
allows the devices to be operated from ("1.8 V supplies down to "0.9 V) two AA or AAA cells. The devices
have been characterized at 1.8 V (end of life of 2 AA(A) cells) and at 2.4 V (nominal voltage of 2 NiCd/NiMH
cells). The TLV276x have rail-to-rail input and output capability which is a necessity at 1.8 V.
The low supply current is coupled with extremely low input bias currents enabling them to be used with
mega-ohm resistors. Low shutdown current of only 10 nA make these devices ideal for low frequency
measurement applications desiring long active battery life.
All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP,
and quads in the TSSOP package.
SELECTION OF SINGLE SUPPLY AMPLIFIER PRODUCTS
DEVICE VDD
(V) VIO
(µV) IDD/Ch
(µA) IIB
(pA)GBW
(MHz) SR
(V/µs) Vn,1kHz
(nV/√Hz)IO
(mA) SHUT-
DOWN RAIL-TO-
RAIL
TLV224x 2.5 − 12 600 1 100 0.0055 0.002 NA 0.2 — I/O
TLV2211 2.7 − 10 450 13 1 0.065 0.025 21 0.4 — O
TLV276x 1.8 − 3.6 550 20 3 0.5 0.23 95 5 Y I/O
TLV245x(A) 2.7 − 6 20 23 500 0.22 0.11 49 2.5 Y I/O
TLV246x(A) 2.7 − 6 150 550 1300 6.4 1.6 11 25 Y I/O
TLV278x(A) 1.8 − 3.6 250 650 2.5 8 5 18 10 Y I/O
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
! ! "#$%&'()"%# "* +,&&-#) (* %$ .,/0"+()"%# 1()-
&%1,+)* +%#$%&' )% *.-+"$"+()"%#* .-& )2- )-&'* %$ -3(* #*)&,'-#)*
*)(#1(&1 4(&&(#)5 &%1,+)"%# .&%+-**"#6 1%-* #%) #-+-**(&"05 "#+0,1-
)-*)"#6 %$ (00 .(&('-)-&*
Copyright 2000−2005, Texas Instruments Incorporated
Operational Amplifier
−
+
0
2
4
6
8
10
12
14
0 0.6 1.2 1.8 2.4 3 3.6
VDD − Supply Voltage − V
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
DD
I Supply Current − −Aµ
20
18
16
AV= 1
VIC = VDD/2
TA = 25° C
!
SLOS326E − JUNE 2000 − REVISED JANUAR Y 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2760 and TLV2761 AVAILABLE OPTIONS(1)
V max
PACKAGED DEVICES
T
A
VIOmax
AT 25
°
C
SMALL OUTLINE
†
SOT-23
PLASTIC DIP
TA
IO
AT 25
°
C
SMALL OUTLINE
(D)†(DBV)‡SYMBOL
PLASTIC DIP
(P)
0°C to 70°C3500 µVTLV2760CD
TLV2761CD —
——
——
—
−40°C to 85°C3500 µVTLV2760ID
TLV2761ID TLV2760IDBV
TLV2761IDBV VANI
VAXI TLV2760IP
TLV2761IP
†This package is available taped and reeled. To order this packaging option, add an R suf fix to the part number (e.g., TLV2760CDR).
‡This package is only available taped and reeled. For standard quantities (3,000 pieces per reel), add an R suffix (i.e., TLV2760CDBVR). For
smaller quantities (250 pieces per mini-reel), add a T suf fix to the part number (e.g. TLV2760CDBVT).
TLV2762 and TLV2763 AVAILABLE OPTIONS(1)
PACKAGED DEVICES
T
A
VIOmax
AT 25
°
C
SMALL
OUTLINE
MSOP PLASTIC
DIP
PLASTIC
DIP
TA
IO
AT 25
°
C
OUTLINE
(D)†DGK†SYMBOL DGS†SYMBOL
DIP
(N)
DIP
(P)
0°C to 70°C3500 µVTLV2762CD
TLV2763CD —
——
——
——
——
——
—
−40°C to 85°C3500 µVTLV2762ID
TLV2763ID TLV2762IDGK
—xxTIAJP
——
TLV2763IDGS —
xxTIAJR —
TLV2763IN TLV2762IP
—
†This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2762CDR).
TLV2764 and TLV2765 AVAILABLE OPTIONS(1)
VIOmax
PACKAGED DEVICES
TAVIOmax
AT 25°CSMALL OUTLINE
(D)†PLASTIC DIP
(N) TSSOP
(PW)†
0°C to 70°C3500 µVTLV2764CD
TLV2765CD —
——
—
−40°C to 85°C3500 µVTLV2764ID
TLV2765ID TLV2764IN
TLV2765IN TLV2764IPW
TLV2765IPW
†This package is available taped and reeled. To order this packaging option, add an R suffix to the part
number (e.g., TLV2764CDR).
1. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV276x PACKAGE PINOUTS
3
2
4
5
(TOP VIEW)
1
OUT
GND
IN+
VDD
IN−
TLV2761
DBV PACKAGE
3
2
4
6
(TOP VIEW)
1
OUT
GND
IN+
VDD
IN−
TLV2760
DBV PACKAGE
5SHDN
NC − No internal connection
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
VDD
2OUT
2IN−
2IN+
TLV2762
D, DGK, OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
SHDN
VDD
OUT
NC
TLV2760
D OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
NC
VDD
OUT
NC
TLV2761
D OR P PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
GND
NC
1SHDN
NC
VDD
2OUT
2IN−
2IN+
NC
2SHDN
NC
(TOP VIEW)
TLV2763
D OR N PACKAGE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
(TOP VIEW)
TLV2764
D, N, OR PW PACKAGE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
1/2SHDN
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
3/4SHDN
(TOP VIEW)
TLV2765
D, N, OR PW PACKAGE
1
2
3
4
5
10
9
8
7
6
1OUT
1IN−
1IN+
GND
1SHDN
VDD
2OUT
2IN−
2IN+
2SHDN
TLV2763
DGS PACKAGE
(TOP VIEW)
!
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage range, VID ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range, II ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current range, IO ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: C-suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I-suffix −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND
DISSIPATION RATING TABLE
PACKAGE
Θ
JC
Θ
JA
TA
≤
25
°
C
TA = 85
°
C
PACKAGE
ΘJC
(°C/W)
ΘJA
(°C/W)
TA ≤ 25 C
POWER RATING
TA = 85 C
POWER RATING
D (8) 38.3 176 710 mW 369 mW
D (14) 26.9 122 1022 mW 531 mW
D (16) 25.7 114 1090 mW 567 mW
DBV (5) 55 324 385 mW 201 mW
DBV (6) 55 294 425 mW 221 mW
DGK(8) 54.2 260 481 mW 250 mW
DGS(10) 54.1 258 485 mW 252 mW
N (14,16) 32 78 1600 mW 833 mW
P 41 104 1200 mW 625 mW
PW (14) 29.3 174 720 mW 374 mW
PW (16) 28.7 161 774 mW 403 mW
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD
Single supply 1.8 3.6
V
Supply voltage, VDD Split supply ±0.8 ±1.8 V
Common-mode input voltage range, VICR −0.2 VDD+0.2 V
Operating free-air temperature, TA
C-suffix 0 70
°C
Operating free-air temperature, T
AI-suffix −40 85 °
C
VIH
VDD < 2.7 V 0.75 VDD
Shutdown on/off voltage level (see Note 2)
V
IH VDD = 2.7 to 3.6 V 2V
Shutdown on/off voltage level (see Note 2)
VIL 0.6
V
NOTE 2: Relative to GND
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electrical characteristics at recommended operating conditions, VDD = 1.8 V, 2.4 V (unless
otherwise noted)
dc performance
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VIO
Input offset voltage
VIC = VDD/2,
V = V /2,
TLV276x
25°C 550 3500
V
VIO Input offset voltage
IC DD
VO = VDD/2,
RL = 300 kΩ
TLV276x Full range 6800 µV
αVIO Offset voltage drift
RL = 300 kΩ
,
R
S
= 50 Ω9µV/°C
VDD = 1.8 V
25°C 50 70
dB
V
DD
= 1.8 V
Full range 48
dB
VICR = 0 V to VDD,
VDD = 2.4 V
25°C 53 72 dB
CMRR
Common-mode rejection ratio
VICR = 0 V to VDD,
RS = 50 Ω
V
DD
= 2.4 V
Full range 50 dB
CMRR
Common-mode rejection ratio
S
VDD = 3.6 V
25°C 55 76
dB
V
DD
= 3.6 V
Full range 55
dB
VICR = 1.2 V to VDD,
VDD = 2.4 V, 3.6 V
25°C 63 82
dB
VICR = 1.2 V to VDD,
RS = 50 Ω
V
DD
= 2.4 V, 3.6 V
Full range 60
dB
VDD = 1.8 V
25°C 20 60
VDD = 1.8 V Full range 18
V/mV
AVD
Large-signal differential voltage
RL = 10 k
Ω
,
VDD = 2.4 V
25°C 28 78 V/mV
AVD
Large-signal differential voltage
amplification
RL = 10 kΩ,
VO(PP) = VDD/2 VDD = 2.4 V Full range 23
amplification
VO(PP) = VDD/2
VDD = 3.6 V
25°C 45 120
V/mV
VDD = 3.6 V Full range 37 V/mV
†Full range is 0°C to 70°C for the C-suffix and −40°C to 85°C for the I-suffix. If not specified, full range is −40°C to 85°C.
input characteristics
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
25°C 3 15
I
IO
Input offset current
VIC = VDD/2,
TLV276xC Full range 100 pA
IIO
Input offset current
VIC = VDD/2,
V
O
= V
DD
/2, TLV276xI Full range 200
pA
VO = VDD/2,
RL = 300 kΩ,
R = 50
25°C 3 15
I
IB
Input bias current
RL = 300 k
RS = 50 ΩTLV276xC Full range 100 pA
IIB
Input bias current
TLV276xI Full range 200
pA
ri(d) Differential input resistance 25°C 1000 GΩ
ci(c) Common-mode input capacitance f = 16 kHz 25°C 10 pF
†Full range is 0°C to 70°C for the C-suffix and −40°C to 85°C for the I-suffix. If not specified, full range is −40°C to 85°C.
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electrical characteristics at recommended operating conditions, VDD = 1.8 V, 2.4 V (unless
otherwise noted) (continued)
output characteristics
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VDD = 1.8V
25°C 1.77 1.79
VDD = 1.8V Full range 1.76
VIC = VDD/2,
VDD = 2.4V
25°C 2.38 2.39
VIC = VDD/2,
IOH = −100 µAVDD = 2.4V Full range 2.37
IOH = −100 µA
VDD = 3.6V
25°C 3.58 3.59
VOH
High-level output voltage
VDD = 3.6V Full range 3.57
V
VOH High-level output voltage
VDD = 1.8V
25°C 1.725 1.75 V
VDD = 1.8V Full range 1.7
VIC = VDD/2,
VDD = 2.4V
25°C 2.325 2.35
VIC = VDD/2,
IOH = −500 µAVDD = 2.4V Full range 2.3
IOH = −500 µA
VDD = 3.6V
25°C 3.525 3.55
VDD = 3.6V Full range 3.5
VIC = VDD/2,
IOL = 100 A
25°C 10 20
VOL
Low-level output voltage
VIC = VDD/2, IOL = 100 µAFull range 30
mV
VOL Low-level output voltage
VIC = VDD/2,
IOL = 500 A
25°C 50 75 mV
VIC = VDD/2, IOL = 500 µAFull range 100
VDD = 1.8 V,
Positive rail
25°C
4.8
IO
Output current
VDD = 1.8 V,
VO = 0.5 V from Negative rail 25°C7.2
mA
IOOutput current
VDD = 2.4 V,
Positive rail
25°C
7.3 mA
VDD = 2.4 V,
VO = 0.5 V from Negative rail 25°C10.2
VDD = 1.8 V
Sourcing
25°C
7
IOS
Short-circuit output current
VDD = 1.8 V Sinking 25°C10
mA
IOS Short-circuit output current
VDD = 2.4 V
Sourcing
25°C
15 mA
VDD = 2.4 V Sinking 25°C19
†Full range is 0°C to 70°C for the C-suffix and −40°C to 85°C for the I-suffix. If not specified, full range is −40°C to 85°C.
power supply, VDD = 1.8 V, 2.4 V, 3.6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
IDD
Supply current (per channel)
VO = VDD/2,
SHDN = V
25°C 20 28
A
IDD Supply current (per channel) VO = VDD/2, SHDN = VDD Full range 30 µA
VDD = 1.8 V to 2.4 V,
25°C 65 85
VDD = 1.8 V to 2.4 V,
VIC = VDD/2 Full range 63
kSVR
Supply voltage rejection ratio
VDD = 2.4 V to 3.6 V,
No load
25°C 65 85
dB
kSVR
Supply voltage rejection ratio
(∆VDD /∆VIO)
VDD = 2.4 V to 3.6 V,
VIC = VDD/2 No load Full range 63 dB
( VDD / VIO)
VDD = 1.8 V to 3.6 V,
25°C 65 85
VDD = 1.8 V to 3.6 V,
VIC = VDD/2 Full range 63
†Full range is 0°C to 70°C for the C-suffix and −40°C to 85°C for the I-suffix. If not specified, full range is −40°C to 85°C.
!
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at recommended operating conditions, VDD = 1.8 V, 2.4 V (unless
otherwise noted) (continued)
dynamic performance
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
UGBW Unity gain bandwidth RL = 300 kΩ, CL = 10 pF 25°C 500 kHz
VDD = 1.8 V
25°C0.11 0.20
VDD = 1.8 V Full range 0.09
V/ s
SR+
Positive slew rate at
VO(PP) = 1 V, RL = 300 k
Ω,
VDD = 2.4 V
25°C0.11 0.22 V/µs
SR+
Positive slew rate at
unity gain
VO(PP) = 1 V, RL = 300 kΩ
,
CL = 50 pF, VDD = 2.4 V Full range 0.09
unity gain
CL = 50 pF,
VDD = 3.6 V
25°C0.11 0.23
V/ s
VDD = 3.6 V Full range 0.09 V/µs
VDD = 1.8 V
25°C0.08 0.15
VDD = 1.8 V Full range 0.07
V/ s
SR−
Negative slew rate at
VO(PP) = 1 V, RL = 300 k
Ω,
VDD = 2.4 V
25°C0.10 0.18 V/µs
SR−
Negative slew rate at
unity gain
VO(PP) = 1 V, RL = 300 kΩ
,
CL = 50 pF, VDD = 2.4 V Full range 0.09
unity gain
CL = 50 pF,
VDD = 3.6 V
25°C0.10 0.22
V/ s
VDD = 3.6 V Full range 0.09 V/µs
φmPhase margin
RL = 300 kΩ,
CL = 100 pF
25°C 63 °
Gain margin
R
L
= 300 k
Ω
,
C
L
= 100 pF
25°C 20 dB
VDD = 1.8 V, V(STEP)PP = 1 V,
0.1% 6.4
ts
Settling time
VDD = 1.8 V, V(STEP)PP = 1 V,
AV = −1, CL = 10 pF, RL = 300 kΩ0.01%
25°C
13.7
s
tsSettling time
VDD = 2.4 V, V(STEP)PP = 1 V,
0.1% 25°C6µs
VDD = 2.4 V, V(STEP)PP = 1 V,
AV = −1, CL = 10 pF, RL = 300 kΩ0.01% 13.9
†Full range is 0°C to 70°C for the C-suffix and −40°C to 85°C for the I-suffix. If not specified, full range is −40°C to 85°C.
noise/distortion
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
V
DD
= 1.8 V,
V = V /2 V,
AV = 1 0.08%
VDD = 1.8 V,
VO(PP) = VDD/2 V,
RL = 300 kΩ,
AV = 10 25°C0.10%
THD + N
Total harmonic distortion plus noise
RL = 300 kΩ,
f = 1 kHz AV = 100
25 C
0.27%
THD + N Total harmonic distortion plus noise V
DD
= 2.4 V,
V = V /2 V,
AV = 1 0.06%
VDD = 2.4 V,
VO(PP) = VDD/2 V,
RL = 300 kΩ,
AV = 10 25°C0.08%
RL = 300 kΩ,
f = 1 kHz AV = 100
25 C
0.24%
Vn
Equivalent input noise voltage
f = 1 kHz 25°C 95
nV/√Hz
VnEquivalent input noise voltage f = 10 kHz 25°C 75
nV/√Hz
InEquivalent input noise current f = 1 kHz 25°C 0.8 fA/√Hz
shutdown characteristics
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
IDD(SHDN)
Supply current, all channels in shutdown mode
SHDN = 0 V
25°C 10 50
nA
IDD(SHDN
)
Supply current, all channels in shutdown mode
(TLV2760, TLV2763, TLV2765) (per channel)
SHDN = 0 V
Full range 400 nA
t(on) Amplifier turnon time (see Note 3) RL = 300 kΩ25°C 5 µs
t(off) Amplifier turnoff time (see Note 3) RL = 300 kΩ25°C 0.8 µs
†Full range is 0°C to 70°C for the C-suffix and −40°C to 85°C for the I-suffix. If not specified, full range is −40°C to 85°C.
NOTE 3: Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply
current has reached half its final value.
!
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8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage vs Common-mode input voltage 1, 2
CMRR Common-mode rejection ratio vs Frequency 3
VOH High-level output voltage vs High-level output current 4, 6
VOL Low-level output voltage vs Low-level output current 5, 7
VO(PP) Maximum peak-to-peak output voltage vs Frequency 8
IDD Supply current vs Supply voltage 9
IDD Supply current vs Free-air temperature 10
PSRR Power supply rejection ratio vs Frequency 11
AVD Differential voltage amplification & phase vs Frequency 12
Gain-bandwidth product
vs Temperature 13
Gain-bandwidth product vs Supply voltage 14
SR
Slew rate
vs Supply voltage 15
SR Slew rate vs Free-air temperature 16, 17
φmPhase margin vs Load capacitance 18
VnEquivalent input noise voltage vs Frequency 19
Supply current and output voltage vs Time 20
Voltage-follower large-signal pulse response vs Time 21
Voltage-follower small-signal pulse response vs Time 22
Inverting large-signal response vs Time 23
Inverting small-signal response vs Time 24
Crosstalk vs Frequency 25
Shutdown forward & reverse isolation vs Frequency 26
IDD(SHDN) Shutdown supply current vs Supply voltage 27
IDD(SHDN) Shutdown supply current vs Free-air temperature 28
IDD(SHDN) Shutdown pin leakage current vs Shutdown pin voltage 29
IDD(SHDN) Shutdown supply current/output voltage vs Time 30
!
SLOS326E − JUNE 2000 − REVISED JANUAR Y 2005
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 1
−50
0
50
100
150
200
250
300
−0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
IO
VInput Offset Voltage −−Vµ
VICR − Common-Mode Input Voltage − V
VDD=1.8 V
TA=25° C
−100
Figure 2
−50
0
50
100
150
200
250
300
350
1.4 1.8 2.2 2.6
IO
VInput Offset Voltage −−Vµ
VDD=2.4 V
TA=25 °C
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VICR − Common-Mode Input Voltage − V
10.60.2−0.2 0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
Figure 3
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
1 10 100 10k 1M
CMRR − Common-Mode Rejection Ratio − dB
VDD = 1.8 V
VDD = 2.4 V
1k 100k
Figure 4
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
012345678
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH − High-Level Output Current − mA
VDD=1.8 V
VOH − High-Level Output Voltage − V
TA=85°C
TA=70°C
TA=25°C
TA=0°C
TA=−40°C
Figure 5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0 1 2 3 4 5 6 7 8 9 10 11 12
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL − Low-Level Output Current − mA
VDD=1.8 V
OL
V − Low-Level Output Voltage − V
TA=85°C
TA=70°C
TA=25°C
TA=0°C
TA=−40°C
Figure 6
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
0246810121416
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH − High-Level Output Current − mA
VDD = 2.4 V
VOH − High-Level Output Voltage − V
TA=85°C
TA=70°C
TA=25°C
TA=0°C
TA=−40°C
18 20
Figure 7
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL − Low-Level Output Current − mA
VDD= 2.4 V
OL
V − Low-Level Output Voltage − V
TA=85°C
TA= 70°C
TA=25°C
TA=0°C
TA=−40°C
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
10 100 1k 10k 100k 1M
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
FREQUENCY
f − Frequency − Hz
VO(PP) − Maximum Peak-To-Peak Output Voltage − V
0.2
AV = −10
RL=300 kΩ
CL = 10 pF
TA = 25° C
VO(PP)= 2.4 V
VO(PP)= 1.8 V
Figure 8
!
SLOS326E − JUNE 2000 − REVISED JANUAR Y 2005
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
0
2
4
6
8
10
12
14
0 0.6 1.2 1.8 2.4 3 3.6
VDD − Supply Voltage − V
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
DD
I Supply Current − −Aµ
20
18
16
AV= 1
VIC = VDD/2
TA = −40°C
TA = 25°C
TA = 85°C
TA = 0°C
TA = 70°C
Figure 10
10
12
14
16
18
20
22
24
−40 −15 10 35 60 85
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
IDD − Supply Current − mA
VDD = 3.6 V
VDD = 2.4 V
VDD = 1.8 V
Figure 11
−20
0
20
40
60
80
100
10 100 1k 10k 100k 1M
VDD=2.4 V
TA=25°C
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
− Power Supply Rejection Ratio − dBPSRR
Figure 12
180
150
120
90
60
30
0
−30
−60
−90
−120
−150
−180
Phase Margin − °
0
20
40
80
1k 10k 100k
DIFFERENTIAL VOLTAGE GAIN AND PHASE
vs
FREQUENCY
f − Frequency − Hz
− Differential Voltage Gain − dBAVD
60
−20
−40 1M
VDD = 1.8 V & 2.4 V
RL= 300 kΩ
CL = 10 pF
TA = 25° C
Gain
Phase
10 100
100
−40 −25 −10 5 20 35 50 65 80 85
Figure 13
0
100
200
300
400
500
600
700 RL = 300 kΩ
CL = 10 pF
f = 10 kHz
VDD = 2.4 V
VDD = 1.8 V
TA − Temperature − °C
GAIN BANDWIDTH PRODUCT
vs
TEMPERATURE
GBWP − Gain Bandwidth Product − kHz
Figure 14
400
420
440
460
480
500
520
540
560
1 1.2 1.4 1.61.8 2 2.2 2.42.62.8 3 3.2
VDD − Supply Voltage − V
GAIN-BANDWIDTH PRODUCT
vs
SUPPLY VOLTAGE
GBWP − Gain Bandwidth Product − kHz
3.63.4
RL = 300 kΩ
CL = 10 pF
f = 10 kHz
Ta = 25°C
Figure 15
0.00
0.04
0.08
0.12
0.16
0.20
0.24
0.28
0.32
1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6
SR−
SR+
SLEW RATE
vs
SUPPLY VOLTAGE
VDD − Supply Voltage − V
SR − Slew Rate − V/µs
AV = 1
RL = 300 kΩ
CL =50 pF
TA = 25° C
0.36
!
SLOS326E − JUNE 2000 − REVISED JANUAR Y 2005
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 16
0.04
0.08
0.12
0.16
0.20
0.28
0.32
VDD = 1.8 V
AV = 1
RL=300 kΩ
CL=50 pF
VIC = VDD/2
SR−
SLEW RATE
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
SR − Slew Rate − V/µs
0.00
SR+
0.24
−40 −25 −10 5 20 35 50 65 8085
Figure 17
0.08
0.12
0.16
0.20
0.24
0.28
0.32
−40 −15 10 35 60 85
SLEW RATE
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
SR − Slew Rate − V/µs
SR−
0.00
0.04
SR+
VDD = 2.4 V
AV = 1
RL= 300 kΩ
CL = 50 pF
VIC = VDD/2
Figure 18
0
10
20
30
40
50
60
70
80
90
10 100 1k
PHASE MARGIN
vs
LOAD CAPACITANCE
CL − Load Capacitance − pF
φm− Phase Margin − °
Rnull=100 Ω
Rnull=0 Ω
VDD = 2.4 V
RL = 300 kΩ
AV = Open Loop
TA = 25°C
Figure 19
150
200
250
300
350
400
450
500
10 100 1k 10k 100k
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
f − Frequency − Hz
nV/ Hz− Equivalent Input Noise Voltage −Vn
0
50
100 VDD = 1.8 V
VDD = 2.4 V
TA = 25°C
Figure 20
012345
t − Time − µs
SUPPLY CURRENT AND OUTPUT VOLTAGE
vs
TIME
VDD = 3.6 V
AV = 1
VIN = VDD/2
RL = 300 kΩ
CL = 10 pF
TA = 25°C
IDD
VO
− Output Voltage − VVO
− Supply Current −IDD
0
0.5
1
1.5
2
−0.5
0
5
10
15
20
µA
Figure 21
1
1.5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
0.5
1
1.5
2
2.5
t − Time − µs
VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE
vs
TIME
VDD = 2.4 V
AV =1
RL = 300 kΩ
CL = 10 pF
TA = 25°C
VO
− Output Voltage − VVO
0
0.5
2
2.5
0
VI
− Input Voltage − VVI
Figure 22
t − Time − µs
VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE
vs
TIME
− Output Voltage − VVO
1.14
1.16
1.18
1.20
01234567
1.18
1.20
1.22
1.24
1.26
VO
1.22
1.24
1.26
1.14
1.16
8
VDD = 2.4 V
AV = 1
RL = 300 kΩ
CL = 10 pF
TA = 25°C
VI
− Input Voltage − VVI
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SLOS326E − JUNE 2000 − REVISED JANUAR Y 2005
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 23
0
0.5
1
1.5
2
2.5
010 2030 40506070 8090
0.5
1
1.5
2
2.5
t − Time − µs
INVERTING LARGE-SIGNAL RESPONSE
vs
TIME
VDD = 2.4 V
AV = 1
RL = 300 kΩ
CL = 10 pF
TA = 25°CVO
− Output Voltage − VVO
0
VI
− Input Voltage − VVI
Figure 24
t − Time − µs
INVERTING SMALL-SIGNAL PULSE RESPONSE
vs
TIME
VDD = 2.4 V
RL = 300 kΩ
CL = 10 pF
AV = 1
TA = 25°C
− Output Voltage − VVO
1.12
1.16
1.20
1.24
0 5 10 15 20 30 1.12
1.16
1.20
1.24
1.28
1.28
35 40 4525
VO
VI
− Input Voltage − VVI
Figure 25
−140
−120
−100
−80
−60
−40
−20
0
10 100 1k 10k 100k
Crosstalk in Shutdown
VDD = 1.8 V & 2.4 V
VI = VDD/2
AV = 1
RL= 300 kΩ
TA = 25°C
All Channels
CROSSTALK
vs
FREQUENCY
f − Frequency − Hz
Crosstalk − dB
Crosstalk/No Shutdown
Figure 26
0
10
20
30
40
50
60
70
10 100 1k 10k 100k 1M
Forward and Reverse Isolation
SHUTDOWN FORWARD AND
REVERSE ISOLATION
vs
FREQUENCY
f − Frequency − Hz
Shutdown Forward and Reverse Isolation − dB
80
90
100
VDD = 1.8 & 2.4 V
VI = VDD /2
RL = 300 kΩ
CL= 10 pF
AV = +1
TA = 25°C
0
.002
.004
.006
.008
.010
.012
.014
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
− Shutdown Supply Current −
SHUTDOWN SUPPLY CURRENT
vs
SUPPLY VOLTAGE
IDD Aµ
SHDN = 0 V
VIN = VDD/2
AV = 1
VDD − Supply Voltage − V
TA = 0°C
TA = 25°C
TA = −40°C
Figure 27 Figure 28
0
.02
.04
.06
.08
.10
.12
−40 −25 −10 5 20 35 50 65 80 85
SHUTDOWN SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
VDD = 1.8, 2.4, 3.6 V
SHDN = 0V
VIN = VDD/2
AV = 1
DD
I Shutdown Supply Current −−Aµ
Figure 29
−15
−10
−5
0
5
10
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6
SHUTDOWN PIN LEAKAGE CURRENT
vs
SHUTDOWN PIN VOLTAGE
Shutdown Pin Voltage − V
DD
I Shutdown Pin Leakage Current −−pA
15
20 VDD = 3.6 V
TA = 85°C
!
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
20 40 60 80 100 120 140
SHUTDOWN SUPPLY CURRENT / OUTPUT VOLTAGE
vs
TIME
160
− Supply Current − A
IDD SHDN − Shutdown Pulse − V
t − Time − µs
SHDN
VDD = 2.4 V
AV = 1
RL = 300 kΩ
CL = 10 pF
VIC = VDD/2
TA = 25°C
IDD(SHDN = 0)
VO
1.5
0.0
0.3
0.5
0.8
1.0
1.3
−0.3
16
0
4
6
8
10
12
14
2
18
Figure 30
3.0
0.0
0.5
1.0
1.5
2.0
2.5
−0.5
− Output Voltage − VVO
−2
µ
!
SLOS326E − JUNE 2000 − REVISED JANUAR Y 2005
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as
shown in Figure 31. A minimum value of 20 Ω should work well for most applications.
CLOAD
RF
Input Output
RGRNULL
+
−
VDD/2
Figure 31. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
VOO +VIOǒ1)ǒRF
RGǓǓ"IIB)RSǒ1)ǒRF
RGǓǓ"IIB– RF
+
−
VI+
RG
RS
RF
IIB−
VO
IIB+
Figure 32. Output Offset Voltage Model
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 33).
!
SLOS326E − JUNE 2000 − REVISED JANUAR Y 2005
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general configurations (continued)
VIVO
C1
+
−
RGRF
R1
f–3dB +1
2pR1C1
VO
VI+ǒ1)RF
RGǓǒ1
1)2pfR1C1Ǔ
VDD/2
Figure 33. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
VI
C2
R2R1
C1
RF
RG
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
(
=1
Q
2 − )
RGRF
_
+f–3dB +1
2pRC
VDD/2
Figure 34. 2-Pole Low-Pass Sallen-Key Filter
circuit layout considerations
To achieve the levels of high performance o f the TLV276x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
DGround planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
DProper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
!
SLOS326E − JUNE 2000 − REVISED JANUAR Y 2005
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
circuit layout considerations (continued)
DSockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
DShort trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at
the input of the amplifier.
DSurface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
shutdown function
Three members of the TLV276x family (TLV2760/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is pulled low, the supply current is reduced to 10 nA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal must be pulled high. The shutdown terminal should never be left floating. If the shutdown
feature is not desired, directly tie the shutdown terminal to the positive rail. The shutdown terminal threshold
is always referenced to the GND terminal of the device. Therefore, when operating the device with split supply
voltages (e.g. ±1.8 V), the shutdown terminal needs to be pulled to the negative rail, not the system ground,
to disable the operational amplifier.
The amplifier is powered with a single 2.4-V supply and configured as a noninverting configuration with a unity
gain. Turnon and turnoff times are defined as the interval between application of the logic signal to the shutdown
pin and the point at which the supply current has reached half its final value. The times for the single, dual, and
quad are listed in the data tables.
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 35 and is calculated by the following formula:
PD+ǒTMAX *TA
qJA Ǔ
Where: PD= Maximum power dissipation of TLV276x IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
!
SLOS326E − JUNE 2000 − REVISED JANUAR Y 2005
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general power dissipation considerations (continued)
1
0.75
0.5
0
−55−40 −25 −10 5
Maximum Power Dissipation − W
1.25
1.5
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
1.75
20 35 50
0.25
TA − Free-Air Temperature − °C
2
65 80 95 110 125
MSOP Package
Low-K Test PCB
θJA = 260°C/W
TJ = 150°C
PDIP Package
Low-K Test PCB
θJA = 104°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 35. Maximum Power Dissipation vs Free-Air Temperature
!
SLOS326E − JUNE 2000 − REVISED JANUAR Y 2005
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim PartsRelease 9.1, the model generation
software used with Microsim PSpice. The Boyle macromodel (see Note 4) and subcircuit in Figure 36 are
generated using TLV276x typical electrical and operating characteristics at TA = 25°C. Using this information,
output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
DMaximum positive output voltage swing
DMaximum negative output voltage swing
DSlew rate
DQuiescent power dissipation
DInput bias current
DOpen-loop voltage amplification
DUnity-gain frequency
DCommon-mode rejection ratio
DPhase margin
DDC output resistance
DAC output resistance
DShort-circuit output current limit
NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
*DEVICE=amp_tlv276x_highVdd,OPAMP,NJF,INT
* amp_tlv_276x_highVdd operational amplifier ”macromodel”
* subcircuit updated using Model Editor release 9.1 on 05/15/00
* at 14:40 Model Editor is an OrCAD product.
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
.subckt amp_tlv276x_highVdd 1 2 3 4 5
*c1 11 12 457.48E−15
c2 6 7 5.0000E−12
css 10 99 1.1431E−12
dc 5 53 dy
de 54 5 dy
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0
176.02E6 −1E3 1E3 180E6
−180E6
ga 6 0 11 12 16.272E−6
gcm 0 6 10 99 6.8698E−9
iss 10 4 dc 1.3371E−6
hlim 90 0 vlim 1K
j1 11 2 10 jx1
J2 12 1 10 jx2
r2 6 9 100.00E3
rd1 3 11 61.456E3
rd2 3 12 61.456E3
ro1 8 5 10
ro2 7 99 10
rp 3 4 150.51E3
rss 10 99 149.58E6
vb 9 0 dc 0
vc 3 53 dc .78905
ve 54 4 dc .78905
vlim 7 8 dc 0
vlp 91 0 dc 14.200
vln 0 92 dc 14.200
.model dx D(Is=800.00E−18)
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 NJF(Is=500.00E−15 Beta=198.03E−6 Vto=−1)
.model jx2 NJF(Is=500.00E−15 Beta=198.03E−6 Vto=−1)
.ends
IN− G
D
S
D
S
G
rp
IN+
rd1 rd2 rss egnd fb ro2
ro1
vlim
OUT
ga
ioffgcm
vb
c1
dc
iss
dp
GND
VDD
css
c2
ve de
dlp dln
vlnhlimvlp
10
4
1
11 12
3
53
54
96
8
5
7
91 90 92
vc
99
+
+
+
+
+
+
+
−
−
−
−
−−
−
−+
r2
2
Figure 36. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2760ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2760IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2760IDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2760IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2760IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2760IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2760IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2760IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2761CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2761CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2761ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2761IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2761IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2761IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2761IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2761IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2761IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2761IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2762CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2762CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2762CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2762CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2762ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2762IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2762IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2762IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2762IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2762IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2762IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2762IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2763CDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2763CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2763IDGS ACTIVE MSOP DGS 10 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2763IDGSG4 ACTIVE MSOP DGS 10 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2763IDGSR ACTIVE MSOP DGS 10 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2763IDGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2763IDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2763IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2764CD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2764CDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2764CDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2764CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2764ID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2764IDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2764IDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2764IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2764IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2764INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2764IPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2764IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2764IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2764IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2765CD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2765CDG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2765CDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2765CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2765ID ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2765IDG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2765IDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2765IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2765IPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2765IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2765IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2765IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 5
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2760IDBVR SOT-23 DBV 6 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2760IDBVT SOT-23 DBV 6 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2761IDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2761IDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2762CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2762IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2762IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2762IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2763CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV2763IDGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2763IDGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2763IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV2764CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV2764IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV2764IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLV2765CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TLV2765IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TLV2765IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2760IDBVR SOT-23 DBV 6 3000 182.0 182.0 20.0
TLV2760IDBVT SOT-23 DBV 6 250 182.0 182.0 20.0
TLV2761IDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0
TLV2761IDBVT SOT-23 DBV 5 250 182.0 182.0 20.0
TLV2762CDR SOIC D 8 2500 340.5 338.1 20.6
TLV2762IDGKR VSSOP DGK 8 2500 364.0 364.0 27.0
TLV2762IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0
TLV2762IDR SOIC D 8 2500 340.5 338.1 20.6
TLV2763CDR SOIC D 14 2500 367.0 367.0 38.0
TLV2763IDGSR MSOP DGS 10 2500 366.0 364.0 50.0
TLV2763IDGSR MSOP DGS 10 2500 358.0 335.0 35.0
TLV2763IDR SOIC D 14 2500 367.0 367.0 38.0
TLV2764CDR SOIC D 14 2500 333.2 345.9 28.6
TLV2764IDR SOIC D 14 2500 333.2 345.9 28.6
TLV2764IPWR TSSOP PW 14 2000 367.0 367.0 35.0
TLV2765CDR SOIC D 16 2500 333.2 345.9 28.6
TLV2765IDR SOIC D 16 2500 333.2 345.9 28.6
TLV2765IPWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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