! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 D Low Supply Voltage . . . 1.8 V to 3.6 V D Very Low Supply Current . . . 20 A (per D D D D D D D D - channel) Ultralow Power Shut-Down Mode - IDD(SHDN) = 10 nA/Channel CMOS Rail-to-Rail Input/Output Input Common-Mode Voltage Range . . . -0.2 V to VDD + 0.2 V Input Offset Voltage . . . 550 V Wide Bandwidth . . . 500 kHz Slew Rate . . . 0.20 V/s Specified Temperature Range: 0C to 70C . . . Commercial Grade -40C to 85C . . . Industrial Grade Ultrasmall Packaging 5 or 6 Pin SOT-23 (TLV2760/1) 8 or 10 Pin MSOP (TLV2762/3) Universal Op-Amp EVM + SUPPLY CURRENT vs SUPPLY VOLTAGE 20 AV= 1 VIC = VDD/2 TA = 25 C 18 I DD - Supply Current - A D Operational Amplifier 16 14 12 10 8 6 4 2 0 0 0.6 1.2 1.8 2.4 3 3.6 VDD - Supply Voltage - V description The TLV276x single supply operational amplifiers provide 500 kHz bandwidth from only 20 A while operating down to 1.8 V over the industrial temperature range. The maximum recommended supply voltage is 3.6 V, which allows the devices to be operated from ("1.8 V supplies down to "0.9 V) two AA or AAA cells. The devices have been characterized at 1.8 V (end of life of 2 AA(A) cells) and at 2.4 V (nominal voltage of 2 NiCd/NiMH cells). The TLV276x have rail-to-rail input and output capability which is a necessity at 1.8 V. The low supply current is coupled with extremely low input bias currents enabling them to be used with mega-ohm resistors. Low shutdown current of only 10 nA make these devices ideal for low frequency measurement applications desiring long active battery life. All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP, and quads in the TSSOP package. SELECTION OF SINGLE SUPPLY AMPLIFIER PRODUCTS DEVICE VDD (V) VIO (V) IDD/Ch (A) IIB (pA) GBW (MHz) SR (V/s) Vn,1kHz (nV/Hz) IO (mA) SHUTDOWN RAIL-TORAIL TLV224x 2.5 - 12 TLV2211 2.7 - 10 600 1 100 0.0055 0.002 NA 0.2 -- I/O 450 13 1 0.065 0.025 21 0.4 -- TLV276x 1.8 - 3.6 O 550 20 3 0.5 0.23 95 5 Y I/O TLV245x(A) 2.7 - 6 20 TLV246x(A) 2.7 - 6 150 23 500 0.22 0.11 49 2.5 Y I/O 550 1300 6.4 1.6 11 25 Y I/O TLV278x(A) 1.8 - 3.6 250 650 2.5 8 5 18 10 Y I/O Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000-2005, Texas Instruments Incorporated ! ! "#$%&'()"%# "* +,&&-#) (* %$ .,/0"+()"%# 1()- &%1,+)* +%#$%&' )% *.-+"$"+()"%#* .-& )2- )-&'* %$ -3(* #*)&,'-#)* *)(#1(&1 4(&&(#)5 &%1,+)"%# .&%+-**"#6 1%-* #%) #-+-**(&"05 "#+0,1)-*)"#6 %$ (00 .(&('-)-&* POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 TLV2760 and TLV2761 AVAILABLE OPTIONS(1) PACKAGED DEVICES VIOmax AT 25C TA SOT-23 SMALL OUTLINE (D) (DBV) SYMBOL PLASTIC DIP (P) -- -- -- -- -- -- 0C to 70C 3500 V TLV2760CD TLV2761CD -40C to 85C 3500 V TLV2760ID TLV2761ID TLV2760IDBV TLV2761IDBV VANI VAXI TLV2760IP TLV2761IP This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2760CDR). This package is only available taped and reeled. For standard quantities (3,000 pieces per reel), add an R suffix (i.e., TLV2760CDBVR). For smaller quantities (250 pieces per mini-reel), add a T suffix to the part number (e.g. TLV2760CDBVT). TLV2762 and TLV2763 AVAILABLE OPTIONS(1) PACKAGED DEVICES TA VIOmax AT 25C SMALL OUTLINE (D) DGK SYMBOL DGS SYMBOL PLASTIC DIP (N) MSOP PLASTIC DIP (P) 0C to 70C 3500 V TLV2762CD TLV2763CD -- -- -- -- -- -- -- -- -- -- -- -- -40C to 85C 3500 V TLV2762ID TLV2763ID TLV2762IDGK -- xxTIAJP -- -- TLV2763IDGS -- xxTIAJR -- TLV2763IN TLV2762IP -- This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2762CDR). TLV2764 and TLV2765 AVAILABLE OPTIONS(1) PACKAGED DEVICES TA VIOmax AT 25C 0C to 70C -40C to 85C SMALL OUTLINE (D) PLASTIC DIP (N) 3500 V TLV2764CD TLV2765CD -- -- 3500 V TLV2764ID TLV2765ID TLV2764IN TLV2765IN TSSOP (PW) -- -- TLV2764IPW TLV2765IPW This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLV2764CDR). 1. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 TLV276x PACKAGE PINOUTS TLV2760 D OR P PACKAGE (TOP VIEW) TLV2760 DBV PACKAGE (TOP VIEW) OUT 1 6 VDD GND 2 5 SHDN IN+ 3 4 IN - TLV2761 D OR P PACKAGE (TOP VIEW) NC IN - IN + GND 1OUT 1IN - 1IN+ GND NC 1SHDN NC 1 8 2 7 3 6 4 5 NC IN - IN + GND 1 8 2 7 3 6 4 5 TLV2761 DBV PACKAGE (TOP VIEW) SHDN VDD OUT NC OUT 1 GND 2 IN+ 3 1OUT 1IN - 1IN + GND 1 8 2 7 3 6 4 5 VDD 2OUT 2IN - 2IN+ VDD 4 IN - TLV2763 DGS PACKAGE (TOP VIEW) TLV2762 D, DGK, OR P PACKAGE (TOP VIEW) NC VDD OUT NC 5 1OUT 1IN - 1IN+ GND 1SHDN 1 2 3 4 5 10 9 8 7 6 VDD 2OUT 2IN - 2IN+ 2SHDN TLV2763 D OR N PACKAGE TLV2764 D, N, OR PW PACKAGE TLV2765 D, N, OR PW PACKAGE (TOP VIEW) (TOP VIEW) (TOP VIEW) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VDD 2OUT 2IN - 2IN+ NC 2SHDN NC 1OUT 1IN - 1IN+ VDD 2IN+ 2IN - 2OUT 1 14 2 13 3 12 4 11 5 10 6 9 7 8 4OUT 4IN - 4IN+ GND 3IN+ 3IN - 3OUT 1OUT 1IN - 1IN+ VDD 2IN+ 2IN - 2OUT 1/2SHDN 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 4OUT 4IN - 4IN+ GND 3IN + 3IN- 3OUT 3/4SHDN NC - No internal connection POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Differential input voltage range, VID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Input current range, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Output current range, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential voltages, are with respect to GND DISSIPATION RATING TABLE PACKAGE JC (C/W) JA (C/W) TA 25C 25 C POWER RATING TA = 85 85C C POWER RATING D (8) 38.3 176 710 mW 369 mW D (14) 26.9 122 1022 mW 531 mW D (16) 25.7 114 1090 mW 567 mW DBV (5) 55 324 385 mW 201 mW DBV (6) 55 294 425 mW 221 mW DGK(8) 54.2 260 481 mW 250 mW DGS(10) 54.1 258 485 mW 252 mW N (14,16) 32 78 1600 mW 833 mW P 41 104 1200 mW 625 mW PW (14) 29.3 174 720 mW 374 mW PW (16) 28.7 161 774 mW 403 mW recommended operating conditions Single supply Supply voltage, VDD Split supply Common-mode input voltage range, VICR Operating free-air temperature, TA Shutdown on/off voltage level (see Note 2) C-suffix I-suffix VIH VDD < 2.7 V VDD = 2.7 to 3.6 V VIL POST OFFICE BOX 655303 MAX 1.8 3.6 0.8 1.8 V -0.2 V 0 VDD+0.2 70 -40 85 * DALLAS, TEXAS 75265 UNIT C 0.75 VDD 2 V 0.6 NOTE 2: Relative to GND 4 MIN ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 electrical characteristics at recommended operating conditions, VDD = 1.8 V, 2.4 V (unless otherwise noted) dc performance PARAMETER VIO Input offset voltage VIO Offset voltage drift TEST CONDITIONS VIC = VDD/2, VO = VDD/2, RL = 300 k, k RS = 50 TLV276x VICR = 0 V to VDD, RS = 50 VICR = 1.2 V to VDD, RS = 50 VDD = 2.4 V VDD = 2.4 V, 3.6 V VDD = 1.8 V Large-signal differential voltage amplification TYP MAX 550 3500 Full range 6800 RL = 10 k, VO(PP) = VDD/2 VDD = 2.4 V VDD = 3.6 V 25C 50 Full range 48 25C 53 Full range 50 25C 55 Full range 55 25C 63 Full range 60 25C 20 Full range 18 25C 28 Full range 23 25C 45 Full range 37 UNIT V V V/C 9 VDD = 3.6 V AVD MIN 25C VDD = 1.8 V CMRR Common-mode rejection ratio TA 70 dB 72 dB dB 76 dB 82 dB 60 V/mV 78 120 V/mV Full range is 0C to 70C for the C-suffix and -40C to 85C for the I-suffix. If not specified, full range is - 40C to 85C. input characteristics PARAMETER IIO IIB ri(d) Input offset current Input bias current TEST CONDITIONS VIC = VDD/2, VO = VDD/2, RL = 300 kk, RS = 50 TA 25C MIN TYP 3 MAX 15 TLV276xC Full range 100 TLV276xI Full range 200 TLV276xC Full range 100 TLV276xI Full range 200 25C Differential input resistance 25C 3 UNIT pA 15 pA 1000 G ci(c) Common-mode input capacitance f = 16 kHz 25C 10 Full range is 0C to 70C for the C-suffix and -40C to 85C for the I-suffix. If not specified, full range is - 40C to 85C. pF POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 electrical characteristics at recommended operating conditions, VDD = 1.8 V, 2.4 V (unless otherwise noted) (continued) output characteristics PARAMETER TA MIN TYP 25C 1.77 1.79 VDD = 1.8V Full range 1.76 25C 2.38 VDD = 2.4V Full range 2.37 25C 3.58 TEST CONDITIONS VIC = VDD/2, IOH = - 100 A VDD = 3.6V VOH High-level output voltage VDD = 1.8V Full range 3.57 25C 1.725 Full range 25C VIC = VDD/2, IOH = - 500 A VDD = 2.4V Full range VDD = 3.6V Full range 25C IOL = 100 A A VIC = VDD/2, VOL IO Low-level output voltage Output current VIC = VDD/2, A IOL = 500 A VDD = 1.8 V, VO = 0.5 V from Positive rail VDD = 2.4 V, VO = 0.5 V from Positive rail Negative rail Negative rail IOS Sinking Short-circuit output current 3.59 V 1.75 1.7 2.325 2.35 2.3 3.525 3.55 3.5 25C 10 Full range 20 30 25C 50 Full range 75 mV 100 4.8 25C 7.2 mA 7.3 25C 10.2 7 25C 10 Sourcing VDD = 2.4 V UNIT 2.39 Sourcing VDD = 1.8 V MAX mA 15 25C Sinking 19 Full range is 0C to 70C for the C-suffix and -40C to 85C for the I-suffix. If not specified, full range is - 40C to 85C. power supply, VDD = 1.8 V, 2.4 V, 3.6 V (unless otherwise noted) PARAMETER IDD Supply current (per channel) TEST CONDITIONS VO = VDD/2, SHDN = VDD VDD = 1.8 V to 2.4 V, VIC = VDD /2 kSVR Supply voltage rejection ratio ((V VDD //V VIO) VDD = 2.4 V to 3.6 V, VIC = VDD /2 No load VDD = 1.8 V to 3.6 V, VIC = VDD /2 TA 25C MIN TYP MAX 20 28 Full range 30 25C 65 Full range 63 25C 65 Full range 63 25C 65 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 A A 85 85 dB 85 Full range 63 Full range is 0C to 70C for the C-suffix and -40C to 85C for the I-suffix. If not specified, full range is - 40C to 85C. 6 UNIT ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 electrical characteristics at recommended operating conditions, VDD = 1.8 V, 2.4 V (unless otherwise noted) (continued) dynamic performance PARAMETER UGBW TA TEST CONDITIONS Unity gain bandwidth RL = 300 k , CL = 10 pF VDD = 1.8 V SR+ SR- Positive slew rate at unity gain Negative slew rate at unity gain VO(PP) = 1 V, RL = 300 k, CL = 50 pF, VDD = 2.4 V VO(PP) = 1 V, RL = 300 k, CL = 50 pF, ts Settling time 25C 0.11 Full range 0.09 25C 0.11 Full range 0.09 0.11 Full range 0.09 25C 0.08 VDD = 1.8 V Full range 0.07 25C 0.10 Full range 0.09 25C 0.10 Full range 0.09 VDD = 2.4 V TYP MAX 500 VDD = 3.6 V Phase margin Gain margin 25C 25C VDD = 3.6 V m MIN UNIT kHz 0.20 V/ s V/s 0.22 0.23 V/ s V/s 0.15 V/ s V/s 0.18 0.22 V/ s V/s 25C 63 25C 20 dB RL = 300 k, CL = 100 pF VDD = 1.8 V, V(STEP)PP = 1 V, AV = -1, CL = 10 pF, RL = 300 k 0.1% 6.4 0.01% 13.7 VDD = 2.4 V, V(STEP)PP = 1 V, AV = -1, CL = 10 pF, RL = 300 k 0.1% 25C ss 6 0.01% 13.9 Full range is 0C to 70C for the C-suffix and -40C to 85C for the I-suffix. If not specified, full range is - 40C to 85C. noise/distortion PARAMETER THD + N Total harmonic distortion plus noise Vn Equivalent input noise voltage In Equivalent input noise current TEST CONDITIONS VDD = 1.8 V, VO(PP) = VDD/2 V, RL = 300 k, f = 1 kHz AV = 1 VDD = 2.4 V, VO(PP) = VDD/2 V, RL = 300 k, f = 1 kHz AV = 1 AV = 10 TA MIN MAX UNIT 0.08% 0.10% 25C 25 C AV = 100 AV = 10 TYP 0.27% 0.06% 0.08% 25C 25 C AV = 100 0.24% f = 1 kHz 25C 95 f = 10 kHz 25C 75 f = 1 kHz 25C 0.8 nV/Hz fA /Hz shutdown characteristics PARAMETER IDD(SHDN) TEST CONDITIONS Supply current, all channels in shutdown mode (TLV2760, TLV2763, TLV2765) (per channel) SHDN = 0 V TA 25C Full range MIN TYP 10 MAX UNIT 50 400 nA t(on) Amplifier turnon time (see Note 3) RL = 300 k 25C 5 s t(off) Amplifier turnoff time (see Note 3) RL = 300 k 25C 0.8 s Full range is 0C to 70C for the C-suffix and -40C to 85C for the I-suffix. If not specified, full range is - 40C to 85C. NOTE 3: Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the supply current has reached half its final value. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO CMRR Input offset voltage vs Common-mode input voltage Common-mode rejection ratio vs Frequency VOH VOL High-level output voltage vs High-level output current 4, 6 Low-level output voltage vs Low-level output current 5, 7 VO(PP) IDD Maximum peak-to-peak output voltage vs Frequency Supply current vs Supply voltage 9 IDD PSRR Supply current vs Free-air temperature 10 Power supply rejection ratio vs Frequency 11 AVD Differential voltage amplification & phase vs Frequency 12 vs Temperature 13 vs Supply voltage 14 Gain-bandwidth product vs Supply voltage 1, 2 3 8 15 SR Slew rate m Vn Phase margin vs Load capacitance 18 Equivalent input noise voltage vs Frequency 19 Supply current and output voltage vs Time 20 Voltage-follower large-signal pulse response vs Time 21 Voltage-follower small-signal pulse response vs Time 22 Inverting large-signal response vs Time 23 Inverting small-signal response vs Time 24 Crosstalk vs Frequency 25 vs Free-air temperature 16, 17 Shutdown forward & reverse isolation vs Frequency 26 IDD(SHDN) IDD(SHDN) Shutdown supply current vs Supply voltage 27 Shutdown supply current vs Free-air temperature 28 IDD(SHDN) IDD(SHDN) Shutdown pin leakage current vs Shutdown pin voltage 29 Shutdown supply current/output voltage vs Time 30 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 TYPICAL CHARACTERISTICS INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE 300 350 VDD=1.8 V VDD=2.4 V TA=25 C VIO - Input Offset Voltage - V 200 150 100 50 0 -50 -100 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VICR - Common-Mode Input Voltage - V 300 TA=25 C 250 200 150 100 50 0 -50 -0.2 0.2 0.6 1 1.4 1.8 2.2 2.6 VICR - Common-Mode Input Voltage - V HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 0.8 TA=25C TA=0C TA=-40C 0.6 0.4 0.2 1 2 3 4 5 6 7 8 IOH - High-Level Output Current - mA 1.6 1.4 TA=85C 1.2 TA=70C 1.0 TA=25C TA=0C TA=-40C 0.8 0.6 0.4 0.2 0 1 2 3 4 5 LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT VOL - Low-Level Output Voltage - V 2.4 VDD= 2.4 V 2.1 TA=85C TA= 70C TA=25C TA=0C TA=-40C 1.2 0.9 0.6 0.3 0.0 0 6 7 8 VDD = 2.4 V 1.8 1.5 TA=85C 1.2 TA=70C 0.9 TA=25C TA=0C TA=-40C 0.6 0.3 0 0 9 10 11 12 2 4 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 IOL - Low-Level Output Current - mA 6 8 10 12 14 16 18 20 IOH - High-Level Output Current - mA Figure 5 1.5 1M 2.1 IOL - Low-Level Output Current - mA Figure 4 1.8 100k 2.4 0.0 0.0 0 100 10k 1k f - Frequency - Hz HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT V OH - High-Level Output Voltage - V VOL - Low-Level Output Voltage - V 1.4 TA=70C 10 Figure 3 VDD=1.8 V VDD=1.8 V 1.6 1.0 VDD = 1.8 V 1 1.8 TA=85C VDD = 2.4 V LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 1.8 1.2 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 Figure 2 Figure 1 Figure 6 V O(PP) - Maximum Peak-To-Peak Output Voltage - V VIO - Input Offset Voltage - V 250 V OH - High-Level Output Voltage - V COMMON-MODE REJECTION RATIO vs FREQUENCY CMRR - Common-Mode Rejection Ratio - dB INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE vs FREQUENCY 2.8 2.6 2.4 2.2 VO(PP)= 2.4 V 2.0 1.8 1.6 VO(PP)= 1.8 V 1.4 1.2 1.0 0.8 0.6 0.4 AV = -10 RL=300 k CL = 10 pF TA = 25 C 0.2 10 100 1k 10k 100k 1M f - Frequency - Hz Figure 8 Figure 7 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE AV= 1 VIC = VDD/2 16 TA = 85C 14 TA = 25C 12 TA = 0C 10 TA = -40C 8 6 TA = 70C 4 22 I DD - Supply Current - mA 18 PSRR - Power Supply Rejection Ratio - dB 24 20 I DD - Supply Current - A POWER SUPPLY REJECTION RATIO vs FREQUENCY VDD = 3.6 V 20 18 VDD = 2.4 V VDD = 1.8 V 16 14 12 2 0 0 0.6 1.2 1.8 2.4 3 10 -40 3.6 -15 10 35 60 TA - Free-Air Temperature - C VDD - Supply Voltage - V Figure 9 85 90 Phase 60 30 40 0 20 -30 -60 Gain VDD = 1.8 V & 2.4 V RL= 300 k CL = 10 pF TA = 25 C 100 1k 10k -90 -120 -150 RL = 300 k CL = 10 pF f = 10 kHz 200 100 5 20 35 50 65 80 85 TA - Temperature - C Figure 13 GAIN-BANDWIDTH PRODUCT vs SUPPLY VOLTAGE SLEW RATE vs SUPPLY VOLTAGE 0.36 RL = 300 k CL = 10 pF f = 10 kHz Ta = 25C 0.32 SR - Slew Rate - V/s GBWP - Gain Bandwidth Product - kHz 10k VDD = 1.8 V 300 480 460 440 0.28 SR+ 0.24 0.20 SR- 0.16 AV = 1 RL = 300 k CL =50 pF TA = 25 C 0.12 0.08 420 0.04 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 0.00 1.8 VDD - Supply Voltage - V Figure 14 10 1k 400 0 -40 -25 -10 -180 1M 100k 500 400 100 500 Figure 12 520 -20 10 VDD = 2.4 V 600 f - Frequency - Hz 540 0 GAIN BANDWIDTH PRODUCT vs TEMPERATURE GBWP - Gain Bandwidth Product - kHz 120 Phase Margin - A VD - Differential Voltage Gain - dB 80 560 20 700 150 -40 10 40 Figure 11 180 -20 60 Figure 10 100 0 VDD=2.4 V TA=25C 80 f - Frequency - Hz DIFFERENTIAL VOLTAGE GAIN AND PHASE vs FREQUENCY 60 100 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VDD - Supply Voltage - V Figure 15 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 100k 1M ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 TYPICAL CHARACTERISTICS SLEW RATE vs FREE-AIR TEMPERATURE 0.32 0.28 0.28 90 SR - Slew Rate - V/s 0.24 0.20 SR- 0.16 VDD = 1.8 V AV = 1 RL=300 k CL=50 pF VIC = VDD/2 0.08 0.04 0.00 -40 -25 -10 5 20 35 50 65 SR- 0.20 0.16 0.12 VDD = 2.4 V AV = 1 RL= 300 k CL = 50 pF VIC = VDD/2 0.08 0.04 0.00 -40 80 85 TA - Free-Air Temperature - C 10 35 60 40 30 VDD = 2.4 V RL = 300 k AV = Open Loop TA = 25C 20 10 85 10 100 Figure 18 SUPPLY CURRENT AND OUTPUT VOLTAGE vs TIME 20 500 15 TA = 25C 450 VDD = 2.4 V 350 300 250 200 150 10 IDD 5 0 2 0 VO VDD = 1.8 V 10 100 1k 10k 0 100k 1 Figure 19 2 VI 0 2.5 2 VO 1.5 1 0.5 0 0.2 0.4 0.6 0.8 0 1 1.2 1.4 1.6 1.8 V O - Output Voltage - V 1 0 -0.5 4 5 VOLTAGE-FOLLOWER SMALL-SIGNAL PULSE RESPONSE vs TIME V I - Input Voltage - V 2.5 0.5 3 0.5 Figure 20 VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE vs TIME VDD = 2.4 V AV =1 RL = 300 k CL = 10 pF TA = 25C 2 1 t - Time - s f - Frequency - Hz 1.5 1.5 VDD = 3.6 V AV = 1 VIN = VDD/2 RL = 300 k CL = 10 pF TA = 25C 100 50 1k CL - Load Capacitance - pF Figure 17 IDD - Supply Current - A Hz Rnull=100 50 TA - Free-Air Temperature - C EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY V n - Equivalent Input Noise Voltage - nV/ 60 0 -15 Figure 16 400 70 1.26 1.24 1.22 VI 1.20 1.18 1.16 1.14 1.26 1.24 VDD = 2.4 V AV = 1 RL = 300 k CL = 10 pF TA = 25C 0 1 2 3 4 VO 1.22 1.20 1.18 1.16 5 6 7 1.14 8 V O - Output Voltage - V 0.12 Rnull=0 80 SR+ V O - Output Voltage - V SR+ 0.24 PHASE MARGIN vs LOAD CAPACITANCE m - Phase Margin - 0.32 V I - Input Voltage - V SR - Slew Rate - V/s SLEW RATE vs FREE-AIR TEMPERATURE t - Time - s t - Time - s Figure 21 Figure 22 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 TYPICAL CHARACTERISTICS INVERTING SMALL-SIGNAL PULSE RESPONSE vs TIME 2 1.5 VI 1 0.5 0 2.5 VDD = 2.4 V AV = 1 RL = 300 k CL = 10 pF TA = 25C 2 1.5 VO 1 0.5 0 10 20 30 40 50 60 70 80 90 0 1.28 1.24 1.20 VI 1.16 VDD = 2.4 V RL = 300 k CL = 10 pF AV = 1 TA = 25C 1.12 0 5 1.16 Figure 24 Shutdown Forward and Reverse Isolation - dB 0 VDD = 1.8 V & 2.4 V VI = VDD/2 AV = 1 RL= 300 k TA = 25C All Channels Crosstalk - dB -60 Crosstalk in Shutdown -80 -100 -120 Crosstalk/No Shutdown 10 100 1k 10k f - Frequency - Hz 100k SHUTDOWN FORWARD AND REVERSE ISOLATION vs FREQUENCY 100 90 Forward and Reverse Isolation 80 70 60 50 40 VDD = 1.8 & 2.4 V VI = VDD /2 RL = 300 k CL= 10 pF AV = +1 TA = 25C 30 20 10 0 10 100 1k .12 I DD - Shutdown Supply Current - A I DD - Shutdown Supply Current - A TA = 25C .008 .006 TA = 0C .004 TA = -40C .002 0 0 0.4 0.8 1.2 1.6 2 2.4 2.8 VDD - Supply Voltage - V Figure 27 12 3.2 3.6 1M .10 VDD = 1.8, 2.4, 3.6 V SHDN = 0V VIN = VDD/2 AV = 1 .08 .06 .04 .02 0 -40 -25 -10 5 20 35 50 65 80 85 TA - Free-Air Temperature - C Figure 28 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SHUTDOWN PIN LEAKAGE CURRENT vs SHUTDOWN PIN VOLTAGE I DD - Shutdown Pin Leakage Current - pA SHUTDOWN SUPPLY CURRENT vs FREE-AIR TEMPERATURE .014 .010 100k Figure 26 SHUTDOWN SUPPLY CURRENT vs SUPPLY VOLTAGE .012 10k f - Frequency - Hz Figure 25 SHDN = 0 V VIN = VDD/2 AV = 1 1.12 40 45 t - Time - s CROSSTALK vs FREQUENCY -140 1.20 10 15 20 25 30 35 Figure 23 -40 1.24 VO t - Time - s -20 1.28 V O - Output Voltage - V V I - Input Voltage - V 2.5 V O - Output Voltage - V V I - Input Voltage - V INVERTING LARGE-SIGNAL RESPONSE vs TIME 20 VDD = 3.6 V TA = 85C 15 10 5 0 -5 -10 -15 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 Shutdown Pin Voltage - V Figure 29 ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 TYPICAL CHARACTERISTICS V O - Output Voltage - V SHDN - Shutdown Pulse - V SHUTDOWN SUPPLY CURRENT / OUTPUT VOLTAGE vs TIME 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 SHDN 1.5 1.3 1.0 0.8 VO 0.5 0.3 0.0 VDD = 2.4 V AV = 1 RL = 300 k CL = 10 pF VIC = VDD/2 TA = 25 C I DD - Supply Current - A -0.3 18 16 14 12 10 8 6 4 2 0 -2 20 IDD(SHDN = 0) 40 60 80 100 120 140 160 t - Time - s Figure 30 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 APPLICATION INFORMATION driving a capacitive load When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the device's phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown in Figure 31. A minimum value of 20 should work well for most applications. RF RG RNULL - Input Output + CLOAD VDD/2 Figure 31. Driving a Capacitive Load offset voltage The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage: RF IIB- RG + - VI IIB+ V OO +V IO 1) R R F G VO + RS "I IB) R S 1) R R F G "I IB- R F Figure 32. Output Offset Voltage Model general configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure 33). 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 APPLICATION INFORMATION general configurations (continued) RG RF VDD/2 - VO + VI R1 C1 f V O + V I 1) R R F G + -3dB 1 2pR1C1 1 1 ) 2pfR1C1 Figure 33. Single-Pole Low-Pass Filter If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth. Failure to do this can result in phase shift of the amplifier. C1 + _ VI R1 R1 = R2 = R C1 = C2 = C Q = Peaking Factor (Butterworth Q = 0.707) R2 f C2 RF RG -3dB RG = + ( 1 2pRC RF 1 2- Q ) VDD/2 Figure 34. 2-Pole Low-Pass Sallen-Key Filter circuit layout considerations To achieve the levels of high performance of the TLV276x, follow proper printed-circuit board design techniques. A general set of guidelines is given in the following. D Ground planes--It is highly recommended that a ground plane be used on the board to provide all components with a low inductive ground connection. However, in the areas of the amplifier inputs and output, the ground plane can be removed to minimize the stray capacitance. D Proper power supply decoupling--Use a 6.8-F tantalum capacitor in parallel with a 0.1-F ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-F ceramic capacitor should always be used on the supply terminal of every amplifier. In addition, the 0.1-F capacitor should be placed as close as possible to the supply terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 APPLICATION INFORMATION circuit layout considerations (continued) D Sockets--Sockets can be used but are not recommended. The additional lead inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is the best implementation. D Short trace runs/compact part placements--Optimum high performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the input of the amplifier. D Surface-mount passive components--Using surface-mount passive components is recommended for high performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept as short as possible. shutdown function Three members of the TLV276x family (TLV2760/3/5) have a shutdown terminal for conserving battery life in portable applications. When the shutdown terminal is pulled low, the supply current is reduced to 10 nA/channel, the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the shutdown terminal must be pulled high. The shutdown terminal should never be left floating. If the shutdown feature is not desired, directly tie the shutdown terminal to the positive rail. The shutdown terminal threshold is always referenced to the GND terminal of the device. Therefore, when operating the device with split supply voltages (e.g. 1.8 V), the shutdown terminal needs to be pulled to the negative rail, not the system ground, to disable the operational amplifier. The amplifier is powered with a single 2.4-V supply and configured as a noninverting configuration with a unity gain. Turnon and turnoff times are defined as the interval between application of the logic signal to the shutdown pin and the point at which the supply current has reached half its final value. The times for the single, dual, and quad are listed in the data tables. general power dissipation considerations For a given JA, the maximum power dissipation is shown in Figure 35 and is calculated by the following formula: P Where: D + T *T MAX A q JA PD = Maximum power dissipation of TLV276x IC (watts) TMAX = Absolute maximum junction temperature (150C) TA = Free-ambient air temperature (C) JA = JC + CA JC = Thermal coefficient from junction to case CA = Thermal coefficient from case to ambient air (C/W) 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 APPLICATION INFORMATION general power dissipation considerations (continued) MAXIMUM POWER DISSIPATION vs FREE-AIR TEMPERATURE 2 Maximum Power Dissipation - W 1.75 PDIP Package Low-K Test PCB JA = 104C/W 1.5 1.25 TJ = 150C MSOP Package Low-K Test PCB JA = 260C/W SOIC Package Low-K Test PCB JA = 176C/W 1 0.75 0.5 0.25 SOT-23 Package Low-K Test PCB JA = 324C/W 0 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 TA - Free-Air Temperature - C NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB. Figure 35. Maximum Power Dissipation vs Free-Air Temperature POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 ! SLOS326E - JUNE 2000 - REVISED JANUARY 2005 APPLICATION INFORMATION macromodel information Macromodel information provided was derived using Microsim Parts Release 9.1, the model generation software used with Microsim PSpice . The Boyle macromodel (see Note 4) and subcircuit in Figure 36 are generated using TLV276x typical electrical and operating characteristics at TA = 25C. Using this information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases): D Maximum positive output voltage swing D Unity-gain frequency D Maximum negative output voltage swing D Common-mode rejection ratio D Slew rate D Phase margin D Quiescent power dissipation D DC output resistance D Input bias current D AC output resistance D Open-loop voltage amplification D Short-circuit output current limit NOTE 4: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, "Macromodeling of Integrated Circuit Operational Amplifiers," IEEE Journal of Solid-State Circuits, SC-9, 353 (1974). 3 99 VDD + egnd rd1 rd2 rss ro2 css fb rp - c1 7 11 12 + c2 vlim 1 r2 + 9 6 IN+ - vc D D 8 + - vb ga 2 G G - IN- ro1 gcm ioff 53 S S OUT dp 91 10 iss GND 4 dlp + dc - ve + 54 vlp - + hlim - 5 92 - vln + de *DEVICE=amp_tlv276x_highVdd,OPAMP,NJF,INT * amp_tlv_276x_highVdd operational amplifier "macromodel" * subcircuit updated using Model Editor release 9.1 on 05/15/00 * at 14:40 Model Editor is an OrCAD product. * * connections: non-inverting input * | inverting input * | | positive power supply * | | | negative power supply * | | | | output * | | | | | .subckt amp_tlv276x_highVdd 1 2 3 4 5 * c1 11 12 457.48E-15 c2 6 7 5.0000E-12 css 10 99 1.1431E-12 dc 5 53 dy de 54 5 dy dlp 90 91 dx dln 92 90 dx dp 4 3 dx egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5 fb 7 99 poly(5) vb vc ve vlp vln 0 176.02E6 -1E3 1E3 180E6 -180E6 ga gcm iss hlim j1 J2 r2 rd1 rd2 ro1 ro2 rp rss vb vc ve vlim vlp vln .model .model .model .model .ends 6 0 10 90 11 12 6 3 3 8 7 3 10 9 3 54 7 91 0 dx dy jx1 jx2 0 11 12 16.272E-6 6 10 99 6.8698E-9 4 dc 1.3371E-6 0 vlim 1K 2 10 jx1 1 10 jx2 9 100.00E3 11 61.456E3 12 61.456E3 5 10 99 10 4 150.51E3 99 149.58E6 0 dc 0 53 dc .78905 4 dc .78905 8 dc 0 0 dc 14.200 92 dc 14.200 D(Is=800.00E-18) D(Is=800.00E-18 Rs=1m Cjo=10p) NJF(Is=500.00E-15 Beta=198.03E-6 Vto=-1) NJF(Is=500.00E-15 Beta=198.03E-6 Vto=-1) Figure 36. Boyle Macromodel and Subcircuit PSpice and Parts are trademarks of MicroSim Corporation. 18 90 dln POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV2760ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2760IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2760IDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2760IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2760IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2760IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2760IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV2760IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV2761CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2761CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2761ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2761IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2761IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2761IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2761IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2761IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2761IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV2761IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV2762CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2762CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2762CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2762CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2762ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2762IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2762IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2762IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2762IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2762IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2762IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2762IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2763CDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2763CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2763IDGS ACTIVE MSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2763IDGSG4 ACTIVE MSOP DGS 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2763IDGSR ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2763IDGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 2 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV2763IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2763IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2764CD ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2764CDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2764CDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2764CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2764ID ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2764IDG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2764IDR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2764IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2764IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV2764INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type TLV2764IPW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2764IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2764IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2764IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2765CD ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2765CDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2765CDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 3 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TLV2765CDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2765ID ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2765IDG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2765IDR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2765IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2765IPW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2765IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2765IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TLV2765IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 4 PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 5 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TLV2760IDBVR SOT-23 DBV 6 3000 180.0 9.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.15 3.2 1.4 4.0 8.0 Q3 TLV2760IDBVT SOT-23 DBV 6 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2761IDBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2761IDBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 TLV2762CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2762IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2762IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2762IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLV2763CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2763IDGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2763IDGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TLV2763IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2764CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2764IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TLV2764IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV2765CDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TLV2765IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 TLV2765IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV2760IDBVR SOT-23 DBV 6 3000 182.0 182.0 20.0 TLV2760IDBVT SOT-23 DBV 6 250 182.0 182.0 20.0 TLV2761IDBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 TLV2761IDBVT SOT-23 DBV 5 250 182.0 182.0 20.0 TLV2762CDR SOIC D 8 2500 340.5 338.1 20.6 TLV2762IDGKR VSSOP DGK 8 2500 364.0 364.0 27.0 TLV2762IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 TLV2762IDR SOIC D 8 2500 340.5 338.1 20.6 TLV2763CDR SOIC D 14 2500 367.0 367.0 38.0 TLV2763IDGSR MSOP DGS 10 2500 366.0 364.0 50.0 TLV2763IDGSR MSOP DGS 10 2500 358.0 335.0 35.0 TLV2763IDR SOIC D 14 2500 367.0 367.0 38.0 TLV2764CDR SOIC D 14 2500 333.2 345.9 28.6 TLV2764IDR SOIC D 14 2500 333.2 345.9 28.6 TLV2764IPWR TSSOP PW 14 2000 367.0 367.0 35.0 TLV2765CDR SOIC D 16 2500 333.2 345.9 28.6 TLV2765IDR SOIC D 16 2500 333.2 345.9 28.6 TLV2765IPWR TSSOP PW 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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