IRL3705NSPbF
IRL3705NLPbF
HEXFET® Power MOSFET
PD - 95381
lAdvanced Process Technology
lSurface Mount (IRL3705NS)
lLow-profile through-hole (IRL3705NL)
l175°C Operating Temperature
lFast Switching
lFully Avalanche Rated
lLead-Free
Absolute Maximum Ratings
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRL3705NL) is available for low-
profile applications.
Description
VDSS = 55V
RDS(on) = 0.01Ω
ID = 89A
2
D Pak
TO-262
S
D
G
06/08/04
lLogic-Level Gate Drive
Parameter Typ. Max. Units
RθJC Junction-to-Case 0.90
RθJA Junction-to-Ambient ( PCB Mounted,steady-state)** 40
Thermal Resistance
°C/W
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 89
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V63 A
IDM Pulsed Drain Current 310
PD @TA = 25°C Power Dissipation 3.8 W
PD @TC = 25°C Power Dissipation 170 W
Linear Derating Factor 1.1 W/°C
VGS Gate-to-Source Voltage ± 16 V
EAS Single Pulse Avalanche Energy 340 mJ
IAR Avalanche Current46 A
EAR Repetitive Avalanche Energy1.7 mJ
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
°C
IRL3705NS/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
I
SContinuous Source Current MOSFET symbol
(Body Diode) showing the
ISM Pulsed Source Current integral reverse
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage 1.3 V TJ = 25°C, IS = 46A, VGS = 0V
trr Reverse Recovery Time 94 140 ns TJ = 25°C, IF = 46A
Qrr Reverse Recovery Charge 290 440 nC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Source-Drain Ratings and Characteristics
S
D
G
A
89
310
Pulse width ≤ 300µs; duty cycle ≤ 2%.
Notes:
Uses IRL3705N data and test conditions
** When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
ISD ≤ 46A, di/dt ≤ 250A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
VDD = 25V, starting TJ = 25°C, L = 320µH
RG = 25Ω, IAS = 46A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 55 V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient 0.056 V/°C Reference to 25°C, ID = 1mA
0.010 VGS = 10V, ID = 46A
0.012 ΩVGS = 5.0V, ID = 46A
0.018 VGS = 4.0V, ID = 39A
VGS(th) Gate Threshold Voltage 1.0 2.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 50 S VDS = 25V, ID = 46A
25 VDS = 55V, VGS = 0V
250 VDS = 44V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage 100 nA VGS = 16V
Gate-to-Source Reverse Leakage -100 VGS = -16V
QgTotal Gate Charge 98 ID = 46A
Qgs Gate-to-Source Charge 19 nC VDS = 44V
Qgd Gate-to-Drain ("Miller") Charge 49 VGS = 5.0V, See Fig. 6 and 13
td(on) Turn-On Delay Time 12 VDD = 28V
trRise Time 140 ID = 46A
td(off) Turn-Off Delay Time 37 RG = 1.8Ω, VGS = 5.0V
tfFall Time 78 RD = 0.59Ω, See Fig. 10
Between lead,
and center of die contact
Ciss Input Capacitance 3600 VGS = 0V
Coss Output Capacitance 870 pF VDS = 25V
Crss Reverse Transfer Capacitance 320 = 1.0MHz, See Fig. 5
nH
IGSS
RDS(on) Static Drain-to-Source On-Resistance
LSInternal Source Inductance 7.5
ns
IDSS Drain-to-Source Leakage Current µA
Calculated continuous current based on maximum allowable
junction temperature; for recommended current-handling of the
package refer to Design Tip # 93-4
IRL3705NS/LPbF
Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 3. Typical Transfer Characteristics
1
10
100
1000
0.1 1 10 10
0
I , Drain-to-S ource Current (A)
D
V , Drain-to -Source Voltage (V)
DS
A
20µs PULS E WIDT H
T = 25°C
J
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
2.5V
1
10
100
1000
0.1 1 10 10
0
I , Drain-to-Source Current (A)
D
V , Drain-to -Source Voltage (V)
DS
A
20µs PULS E WIDT H
T = 175°C
VGS
TOP 15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
2.5V
J
1
10
100
1000
2.0 3.0 4.0 5.0 6.0 7.0 8.0
T = 25°C
J
GS
V , Gate-to-Sour ce Volta ge (V)
D
I , Drain-to-Source Current (A)
T = 175°C
J
A
V = 25V
20µs PUL SE WIDTH
DS
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
J
T , Junction Temp erature (°C)
R , Drain-to-Source On Resis tance
DS(on)
(Normalized)
V = 10V
GS
A
I = 77A
D
IRL3705NS/LPbF
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0
1000
2000
3000
4000
5000
6000
1 10 100
C, Capacitance (pF)
DS
V , Drain-to-Source Voltage (V)
A
V = 0V, f = 1MHz
C = C + C , C SHORTED
C = C
C = C + C
GS
iss gs gd ds
rss gd
os s ds gd
C
iss
C
oss
C
rss
0
3
6
9
12
15
0 20 40 60 80 100 120 140
Q , Total Gate Charge (nC)
G
V , Gate -to-Source Voltage (V)
GS
A
FOR TEST CIRCUIT
SEE FIGURE 13
I = 46A V = 44V
V = 28V
D
DS
DS
10
100
1000
0.4 0.8 1.2 1.6 2.0 2.4 2.
8
T = 25°C
J
V = 0V
GS
V , Source-to-Drain Voltage (V)
I , Revers e Drain Current (A)
SD
SD
A
T = 175° C
J
1
10
100
1000
1 10 100
V , Drain-to-Source Voltage (V)
DS
I , Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY R
D
DS(on)
10µs
100µs
1ms
10ms
A
T = 25°C
T = 175° C
Singl e Pul s e
C
J
IRL3705NS/LPbF
Fig 10a. Switching Time Test Circuit
V
DS
9
0%
1
0%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
5.0V
+
-
VDD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
25 50 75 100 125 150 175
0
20
40
60
80
100
T , C a se Temperature ( C)
I , Drain Current (A)
°
C
D
LIMITED BY PACKAGE
0.01
0.1
1
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Du ty facto r D = t / t
2. Peak T =P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Durat ion (sec)
Therm al R esponse (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
IRL3705NS/LPbF
QG
QGS QGD
V
G
Charge
D.U.T. V
D
S
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
5.0 V
Fig 13b. Gate Charge Test CircuitFig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
0
200
400
600
800
25 50 75 100 125 150 17
5
J
E , Single Pulse Avalanche Energy (mJ)
AS
A
Starting T , Junction Temperatu re (°C)
V = 25V
I
TOP 19A
3 3A
BOTTOM 46A
DD
D
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
10V
IRL3705NS/LPbF
Peak Diode Recovery dv/dt Test Circuit
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFETS
* V
GS = 5V for Logic Level Devices
RG
VDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
IRL3705NS/LPbF
D2Pak Part Marking Information
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
Note: "P" in assembly line
po s it ion indicat es "L ead-F ree"
F530S
THIS I S AN IRF530S WITH
LOT CODE 8024
ASSEMBLED O N WW 02, 2000
IN TH E ASSEMB LY LINE "L "
ASSEMBLY
LOT CODE
INTERNATIONAL
RECTIFIER
LOGO
PART N UMBE
R
DATE CODE
YEAR 0 = 2000
WEEK 02
LINE L
OR
F530S
A = ASSEMBLY SITE CODE
WEEK 02
P = DESIGNATES LEAD-FREE
PROD UCT (OPTIONAL)
RECTIFIER
INTERNATIONAL
LOGO
LOT CODE
ASSEMBLY YEA R 0 = 2000
DATE CODE
PART NUMB ER
IRL3705NS/LPbF
TO-262 Part Marking Information
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
ASSEMBLY
LOT CODE
RECTIFIER
INTERNATIONAL
ASSEMBLED ON WW 19 , 19 97
Note: "P" in assembly line
pos ition indicates "Lead-F ree"
IN THE ASSEMBLY L I N E "C" LOGO
THIS IS AN IRL3103L
LO T CODE 1789
EXAMPLE:
LINE C
DATE CO DE
WEEK 19
YEAR 7 = 1997
PART NUMBER
PAR T NUMBER
LOGO
LOT CODE
AS S EMB LY
INTERNATIONAL
RECTIFIER
PRODUCT (OPTIONAL)
P = DES IGNAT ES LEAD-FREE
A = AS S E MB LY S IT E CODE
WEEK 19
YEAR 7 = 1997
DATE CODE
OR
IRL3705NS/LPbF
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 06/04
D2Pak Tape & Reel Information
Dimensions are shown in millimeters (inches)
3
4
4
TRR
F
EED DIRECTION
1.85 (. 073)
1.65 (. 065)
1.60 (. 063)
1.50 (. 059)
4.10 (.161)
3.90 (.153)
TRL
F
EED DIRECTION
10.90 (.42 9)
10.70 (.42 1) 16. 10 ( .634 )
15. 90 ( .626 )
1.75 (.069)
1.25 (.049)
11.60 (.457 )
11.40 (.449 ) 15 .42 (.609)
15.22 (.601)
4.72 (. 136)
4.52 (. 178)
24. 30 ( .957
)
23. 90 ( .941
)
0.368 (. 0145)
0.342 (. 0135)
1.60 (. 063)
1.50 (. 059)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362
)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCL UD ES FLANGE DISTORTION @ OUTER EDGE.
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
