REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD8017
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Dual High Output Current,
High Speed Amplifier
PIN CONFIGURATION
8-Lead Thermal Coastline SOIC (SO-8)
8
7
6
5
1
2
3
4
OUT1
–IN1
+IN1
–VS
+VS
OUT2
–IN2
+IN2
AD8017
–
+
–
+
FEATURES
High Output Drive Capability
20 V p-p Differential Output Voltage, RL = 50 ⍀
10 V p-p Single-Ended Output Voltage While
Delivering 200 mA to a 25 ⍀ Load
Low Power Operation
5 V to 12 V Voltage Supply @ 7 mA/Amplifier
Low Distortion
–78 dBc @ 500 kHz SFDR, RL = 100 ⍀, VO = 2 V p-p
–58 dBc Highest Harmonic @ 1 MHz, IO = 270 mA
(RL = 10 ⍀)
High Speed
160 MHz, –3 dB Bandwidth (G = +2)
1600 V/␮s Slew Rate
APPLICATIONS
xDSL PCI Cards
Consumer DSL Modems
Line Driver
Video Distribution
PRODUCT DESCRIPTION
The AD8017 is a low cost, dual high speed amplifier capable of
driving low distortion signals to within 1.0 V of the supply rail.
It is intended for use in single supply xDSL systems where low
distortion and low cost are essential. The amplifiers will be able
to drive a minimum of 200 mA of output current per amplifier.
The AD8017 will deliver –78 dBc of SFDR at 500 kHz, required
for many xDSL applications.
Fabricated in ADI’s high speed XFCB process, the high bandwidth
and fast slew rate of the AD8017 keep distortion to a minimum, while
dissipating a minimum amount of power. The quiescent current of
the AD8017 is 7 mA/amplifier.
Low distortion, high output voltage drive, and high output current
drive make the AD8017 ideal for use in low cost Customer Premise
End (CPE) equipment for ADSL, SDSL, VDSL and proprietary
xDSL systems.
The AD8017 drive capability comes in a very compact form.
Utilizing ADI’s proprietary Thermal Coastline SOIC package,
the AD8017’s total (static and dynamic) power on 12 V supplies
is easily dissipated without external heat sink, other than to place
the AD8017 on a 4-layer PCB.
The AD8017 will operate over the commercial temperature
range –40°C to +85°C.
LOAD RESISTANCE – ⍀
0
11000
OUTPUT VOLTAGE SWING – V p-p
6
10010
2
4
8
10
12
VS = ⴞ2.5V
VS = ⴞ6V
Figure 1. Output Swing vs. Load Resistance
+VS
R1
+
–
–VS
R2
NP:NS
TRANSFORMER
VIN VREF VOUT
LINE
POWER
IN dB
+
–
RL = 100⍀
OR
135⍀
Figure 2. Differential Drive Circuit for xDSL Applications
–2– REV. C
AD8017–SPECIFICATIONS
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth G = +2, V
OUT
< 0.4 V p-p 100 160 MHz
0.1 dB Bandwidth V
OUT
< 0.4 V p-p 70 MHz
Large Signal Bandwidth V
OUT
= 4 V p-p 105 MHz
Slew Rate Noninverting, V
OUT
= 4 V p-p, G = +2 1600 V/µs
Rise and Fall Time Noninverting, V
OUT
= 2 V p-p 2.0 ns
Settling Time 0.1%, V
OUT
= 4 V Step 35 ns
Overload Recovery V
IN
= 5 V p-p 74 ns
NOISE/HARMONIC PERFORMANCE
Distortion V
OUT
= 2 V p-p
Second Harmonic 500 kHz, R
L
= 100 Ω/25 Ω–78/–71 dBc
1 MHz, R
L
= 100 Ω/25 Ω–76/–69 dBc
Third Harmonic 500 kHz, R
L
= 100 Ω/25 Ω–105/–91 dBc
1 MHz, R
L
= 100 Ω/25 Ω–81/–72 dBc
IP3 500 kHz, R
L
= 100 Ω/25 Ω40/35 dBm
IMD 500 kHz, R
L
= 100 Ω/25 Ω–76/–66 dBc
MTPR 26 kHz to 1.1 MHz –66 dBc
Input Noise Voltage f = 10 kHz 1.9 nV/√Hz
Input Noise Current f = 10 kHz (+ Inputs) 23 pA/√Hz
f = 10 kHz (– Inputs) 21 pA/√Hz
Crosstalk f = 5 MHz, G = +2 –66 dB
DC PERFORMANCE
Input Offset Voltage 1.8 3.0 mV
T
MIN
to T
MAX
4.0 mV
Open Loop Transimpedance V
OUT
= 2 V p-p 185 700 kΩ
T
MIN
to T
MAX
143 kΩ
INPUT CHARACTERISTICS
Input Resistance +Input 50 kΩ
Input Capacitance +Input 2.4 pF
Input Bias Current (+) 16 ±45 µA
T
MIN
to T
MAX
±67 µA
Input Bias Current (–) 1.0 ±25 µA
T
MIN
to T
MAX
±32 µA
CMRR V
CM
= ±2.5 V 59 63 dB
Input CM Voltage Range ±5.1 V
OUTPUT CHARACTERISTICS
Output Resistance 0.2 Ω
Output Voltage Swing R
L
= 25 Ω±4.6 ±5.0 V
Output Current
1
Highest Harmonic < –58 dBc, 200 270 mA
f = 1 MHz, R
L
= 10 Ω
T
MIN
to T
MAX
, Highest Harmonic < –52 dBc 100 mA
Short-Circuit Current 1500 mA
POWER SUPPLY
Supply Current/Amp 7.0 7.7 mA
T
MIN
to T
MAX
7.8 mA
Operating Range Dual Supply ±2.2 ±6.0 V
Power Supply Rejection Ratio 58 61 dB
Operating Temperature Range –40 +85 °C
NOTE
1
Output current is defined here as the highest current load delivered by the output of each amplifier into a specified resistive load ( R
L
= 10 Ω), while maintaining an
acceptable distortion level (i.e., less than –60 dBc highest harmonic) at a given frequency (f = 1 MHz).
Specifications subject to change without notice.
(@ 25ⴗC, VS = ⴞ6 V, RL = 100 ⍀, RF = RG = 619 ⍀, unless otherwise noted.)
–3–REV. C
AD8017
SPECIFICATIONS
(@ 25ⴗC, VS = ⴞ2.5 V, RL = 100 ⍀, RF = RG = 619 ⍀, unless otherwise noted.)
Parameter Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
–3 dB Bandwidth G = +2, V
OUT
< 0.4 V p-p 75 120 MHz
0.1 dB Bandwidth V
OUT
< 0.4 V p-p 40 MHz
Large Signal Bandwidth V
OUT
= 4 V p-p 100 MHz
Slew Rate Noninverting, V
OUT
= 2 V p-p, G = +2 800 V/µs
Rise and Fall Time Noninverting, V
OUT
= 2 V p-p 2.2 ns
Settling Time 0.1%, V
OUT
= 2 V Step 35 ns
Overload Recovery V
IN
= 2.5 V p-p 74 ns
NOISE/HARMONIC PERFORMANCE
Distortion V
OUT
= 2 V p-p
Second Harmonic 500 kHz, R
L
= 100 Ω/25 Ω–75/–68 dBc
1 MHz, R
L
= 100 Ω/25 Ω–73/–66 dBc
Third Harmonic 500 kHz, R
L
= 100 Ω/25 Ω–91/–88 dBc
1 MHz, R
L
= 100 Ω/25 Ω–79/–74 dBc
IP3 500 kHz, R
L
= 100 Ω/25 Ω40/36 dBm
IMD 500 kHz, R
L
= 100 Ω/25 Ω–78/–64 dBc
MTPR 26 kHz to 1.1 MHz –66 dBc
Input Noise Voltage f = 10 kHz 1.8 nV/√Hz
Input Noise Current f = 10 kHz (+ Inputs) 23 pA/√Hz
f = 10 kHz (– Inputs) 21 pA/√Hz
Crosstalk f = 5 MHz, G = +2 –66 dB
DC PERFORMANCE
Input Offset Voltage 0.8 2.0 mV
T
MIN
to T
MAX
2.6 mV
Open Loop Transimpedance V
OUT
= 2 V p-p 40 166 kΩ
T
MIN
to T
MAX
45 kΩ
INPUT CHARACTERISTICS
Input Resistance +Input 50 kΩ
Input Capacitance +Input 2.4 pF
Input Bias Current (+) 16 ±40 µA
T
MIN
to T
MAX
±62 µA
Input Bias Current (–) 2±25 µA
T
MIN
to T
MAX
±32 µA
CMRR V
CM
= ±1.0 (±1.0) 57 60 dB
Input CM Voltage Range ±1.6 V
OUTPUT CHARACTERISTICS
Output Resistance 0.2 Ω
Output Voltage Swing R
L
= 25 Ω±1.55 ±1.65 V
Output Current
1
Highest Harmonic < –55 dBc, 100 120 mA
f = 1 MHz, R
L
= 10 Ω
T
MIN
to T
MAX
Highest Harmonic
< 50 dBc 60 mA
Short-Circuit Current 1300 mA
POWER SUPPLY
Supply Current/Amp 6.2 7 mA
T
MIN
to T
MAX
7.3 mA
Operating Range Dual Supply ±2.2 ±6.0 V
Power Supply Rejection Ratio 59 62 dB
Operating Temperature Range –40 +85 °C
NOTE
1
Output current is defined here as the highest current load delivered by the output of each amplifier into a specified resistive load ( R
L
= 10 Ω), while maintaining an
acceptable distortion level (i.e., less than –60 dBc highest harmonic) at a given frequency (f = 1 MHz).
Specifications subject to change without notice.
AD8017
–4– REV. C
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 V
Internal Power Dissipation
2
Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . ±V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . ±2.5 V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range . . . . . . . . . . . . –65°C to +125°C
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device on a two-layer board with 2500 mm
2
of 2 oz. copper at
+25°C 8-lead SOIC package: θ
JA
= 95.0°C/W.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8017
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
device is determined by the glass transition temperature of the
plastic, approximately 150°C. Temporarily exceeding this limit
may cause a shift in parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a junc-
tion temperature of 175°C for an extended period can result in
device failure.
The output stage of the AD8017 is designed for maximum load
current capability. As a result, shorting the output to common
can cause the AD8017 to source or sink 500 mA. To ensure
proper operation, it is necessary to observe the maximum power
derating curves. Direct connection of the output to either power
supply rail can destroy the device.
AMBIENT TEMPERATURE – ⴗC
2.0
1.5
0090
10
MAXIMUM POWER DISSIPATION – Watts
20 30 40 50 60 70 80
1.0
0.5
T
J
= 150ⴗC
T
J
= 125ⴗC
Figure 3. Plot of Maximum Power Dissipation vs.
Temperature for AD8017
619⍀619⍀
RL
VOUT
+VS
–VS
10␮F
10␮F
+
+
0.1␮F
0.1␮F
49.9⍀
VIN
Figure 4. Test Circuit: Gain = +2
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD8017AR –40°C to +85°C 8-Lead SOIC SO-8
AD8017AR-REEL –40°C to +85°C Tape and Reel 13" SO-8
AD8017AR-REEL7 –40°C to +85°C Tape and Reel 7" SO-8
AD8017AR-EVAL Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8017 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
619⍀619⍀
R
L
V
OUT
+V
S
–V
S
10␮F
10␮F
+
+
0.1␮F
0.1␮F
54.4⍀
V
IN
Figure 5. Test Circuit: Gain = –1
AD8017
–5–REV. C
Typical Performance Characteristics–
OUTPUT = 100mV
INPUT = 50mV
200ns/DIV
25mV/DIV
TPC 1. 100 mV Step Response; G = +2, V
S
=
±
2.5 V
or
±
6 V, R
L
= 100
Ω
OUTPUT = 4V
INPUT = 2V
200ns/DIV
1V/DIV
TPC 2. 4 V Step Response; G = +2, V
S
=
±
6 V,
R
L
= 100
Ω
OUTPUT = 100mV
INPUT = 100mV
200ns/DIV
50mV/DIV 25 mV/DIV
TPC 3. 100 mV Step Response; G = –1, V
S
=
±
2.5 V
or
±
6 V, R
L
= 100
Ω
OUTPUT = 4V
INPUT = 4V
200ns/DIV
2V/DIV 1V/DIV
TPC 4. 4 V Step Response; G = –1, V
S
=
±
6 V,
R
L
= 100
Ω
AD8017
–6– REV. C
VOUT = 2V p-p
G = +2
FREQUENCY – MHz
0
–120
0.1 100
DISTORTION – dBc
–60
101
–20
–40
–80
–100
2ND
3RD
TPC 5. Distortion vs. Frequency; V
S
=
±
6 V, R
L
= 100
Ω
FREQUENCY – MHz
0
0.1 100
DISTORTION – dBc
–60
101
–20
–40
–80
–100
2ND
3RD
V
OUT
= 2V p-p
G = +2
TPC 6. Distortion vs. Frequency; V
S
=
±
6 V, R
L
= 25
Ω
OUTPUT CURRENT – mA
HIGHEST HARMONIC DISTORTION – dBc
–70
0 500
–30
100 200 300 400
–60
–50
–40
V
S
= ⴞ6V
R
L
= 25⍀
–20
600
V
S
= ⴞ6V
R
L
= 10⍀
V
S
= ⴞ6V
R
L
= 5⍀
TPC 7. Distortion vs. Output Current; V
S
=
±
6 V,
f = 1 MHz, G = +2
FREQUENCY – MHz
0
–120
0.1 100
DISTORTION – dBc
–60
101
–20
–40
–80
–100
2ND
3RD
VOUT = 2V p-p
G = +2
TPC 8. Distortion vs. Frequency; V
S
=
±
2.5 V, R
L
= 100
Ω
FREQUENCY – MHz
0
–90
0.1 100
DISTORTION – dBc
–60
101
–40
–50
–70
–80
2ND
3RD
–30
–20
–10 VOUT = 2V p-p
G = +2
TPC 9. Distortion vs. Frequency; V
S
=
±
2.5 V, R
L
= 25
Ω
OUTPUT CURRENT – mA
–20
HIGHEST HARMONIC DISTORTION – dBc
–60
–70
–50
400100 200
V
S
= ⴞ2.5V
R
L
= 25⍀
0 300
–40
–30
V
S
= ⴞ2.5V
R
L
= 10⍀
V
S
= ⴞ2.5V
R
L
= 5⍀
TPC 10. Distortion vs. Output Current; V
S
=
±
2.5 V,
f = 1 MHz, G = +2
AD8017
–7–REV. C
LOAD RESISTANCE – ⍀
0 1000
DISTORTION – dBc
10010
–40
–20
–60
–80
–100
–140
–120
3RD
2ND
TPC 11. Distortion vs. R
L
, V
S
=
±
6 V, G = +2,
V
OUT
= 2 V p-p, f = 1 MHz
RL = 100⍀
OUTPUT VOLTAGE – Volts
HIGHEST HARMONIC DISTORTION – dBc
–80
06
0
RL = 25⍀
VS = ⴞ6V
f = 1MHz
G = +2
–20
–40
–60
54321
–10
–30
–50
–70
TPC 12. Distortion vs. Output Voltage, V
S
=
±
6 V,
G = +2, f = 1 MHz
OUTPUT VOLTAGE – Volts
–70 6
HIGHEST HARMONIC DISTORTION – dBc
0
R
L
= 25⍀
V
S
= ⴞ6V
f
= 10MHz
G = +2
–40
–50
–60
54321
R
L
= 100⍀
–30
–20
–10
0
TPC 13. Distortion vs. Output Voltage, V
S
=
±
6 V,
G = +2, f = 10 MHz
LOAD RESISTANCE – ⍀
0
–140
0 1000
DISTORTION – dBc
–60
10010
–20
–40
–80
–100
2ND
3RD
–120
TPC 14. Distortion vs. R
L
, V
S
=
±
2.5 V, G = +2,
V
OUT
= 2 V p-p, f = 1 MHz
0 0.5
OUTPUT VOLTAGE – Volts
–80
HIGHEST HARMONIC DISTORTION – dBc
R
L
= 25⍀
V
S
= ⴞ2.5V
f
= 1MHz
G = +2
–40
–50
–60
R
L
= 100⍀
–30
–10
0
–20
1.0 1.5 2.0 2.5
–70
TPC 15. Distortion vs. Output Voltage, V
S
=
±
2.5 V,
G = +2, f = 1 MHz
OUTPUT VOLTAGE – Volts
0
–60
0 2.50.5
HIGHEST HARMONIC DISTORTION – dBc
1 1.5
–10
–20
–30
–40
–50
R
L
= 25⍀
R
L
= 100⍀
V
S
= ⴞ2.5V
f
= 10MHz
G = +2
–70
–80
2
TPC 16. Distortion vs. Output Voltage, V
S
=
±
2.5 V,
G = +2, f = 10 MHz
AD8017
–8– REV. C
FREQUENCY – MHz
0
100
NORMALIZED GAIN – dB
101
3
1000
–3
–6
GAIN = +5
GAIN = +2
GAIN = +10
RL = 100⍀
TPC 17. Frequency Response; V
S
=
±
6 V
FREQUENCY – MHz
0.1 10001
0.1dB FLATNESS – dB
10 100
0.3
0.2
–0.3
0.1
0.0
–0.1
–0.2
G = +2
RL = 100⍀
TPC 18. Gain Flatness; V
S
=
±
6 V
FREQUENCY – MHz
0.1 10001
OUTPUT VOLTAGE – dBV
10 100
0
–15
–3
–6
–9
–12
–18
–21
–24
–27
–30
V
OUT
= 2V p-p
G = +2
R
L
= 100⍀
–33
TPC 19. Output Voltage vs. Frequency; V
S
=
±
6 V
FREQUENCY – MHz
2
1
0.1 10001
NORMALIZED GAIN – dB
10 100
0
–1
–6
–2
–3
–4
–5
GAIN = +2
GAIN = +10
GAIN = +5
R
L
= 100⍀
TPC 20. Frequency Response; V
S
=
±
2.5 V
FREQUENCY – MHz
0.1 10001
0.1dB FLATNESS – dB
10 100
0.3
0.2
–0.3
0.1
0.0
–0.1
–0.2
G = +2
RL = 100⍀
TPC 21. Gain Flatness; V
S
=
±
2.5 V
FREQUENCY – MHz
0.1 10001
OUTPUT VOLTAGE – dBV
10 100
3
0
–15
–3
–6
–9
–12
–18
–21
–24
–27
–30
V
OUT
= 1V
RMS
G = +2
R
L
= 100⍀
TPC 22. Output Voltage vs. Frequency; V
S
=
±
2.5 V
AD8017
–9–REV. C
FREQUENCY – kHz
+20
–80
POWER – dBm
–20
–40
–60
0
050 100 150
TPC 23. Multitone Power Ratio: V
S
=
±
6 V, 13 dBm
Output Power into 25
Ω
FREQUENCY – MHz
0.1 10001
CMRR – dB
10 100
0
–50
–10
–20
–30
–40
–60
–70
–80
–90
–100
TPC 24. CMRR vs. Frequency; V
S
=
±
6 V or V
S
=
±
2.5 V
FREQUENCY – kHz
0.01 1000.1
INPUT CURRENT NOISE – nA/ Hz
110
0.4
0.3
0.1
0
0.2
12
10
6
0
8
4
2
INPUT VOLTAGE NOISE – nA/ Hz
iNeN
TPC 25. Noise vs. Frequency
SERIES RESISTANCE – ⍀
120
20
CAP LOAD – pF
80
60
40
100
024 8
0
6
TPC 26. R
S
and C
L
vs. 30% Overshoot
FREQUENCY – MHz
0.1 10001
PSRR – dB
10 100
0
–50
–10
–20
–30
–40
–60
–70
–80
–PSRR
+PSRR
TPC 27. PSRR vs. Frequency; V
S
=
±
6 V or V
S
=
±
2.5 V
FREQUENCY – MHz
0.001 10
TRANSIMPEDANCE – k⍀
0.1 1
1
180
0
120
60
PHASE – Degrees
1000100
100
TRANSIMPEDANCE
PHASE
10
1000
0.01
TPC 28. Open-Loop Transimpedance and Phase vs.
Frequency
AD8017
–10– REV. C
TIME – ns
OUTPUT VOLTAGE ERROR – mV/DIV (% /DIV)
G = +2
V
OUT
= 2V
STEP
R
L
- 100⍀
V
S
= ⴞ6V
+2mV
(+0.1%)
–2mV
(+0.1%)
0 102030405060708090
0
TPC 29. Settling Time; V
S
=
±
6.0 V
FREQUENCY – MHz
0.1 10001
CROSSTALK – dB
10 100
–50
–20
–30
–40
–60
–70
–80
V
OUT
= 2V p-p
G = +2
R
L
= 100⍀
–90
–100
TPC 30. Output Crosstalk vs. Frequency
FREQUENCY – MHz
0.1 100
INPUT IMPEDANCE – ⍀
110
100
0.1
10
1
OUTPUT IMPEDANCE – ⍀
1000
1000
10000
100000
Z
IN
Z
OUT
1000000
TPC 31. Input and Output Impedance vs. Frequency
VOLTS
–2
–1
0
1
2
3
4
5
6
–10 10 30 50 70 90 110 130 150
VOLTS
–6
–5
–4
–3
2
–10 10 30 50 70 90 110 130 150
–3
–3
0
1
V
OUT
V
IN
V
OUT
V
IN
TIME – ns
TPC 32. Overload Recovery; V
S
=
±
6 V, G = +2,
R
L
= 100
Ω
, V
IN
= 5 V p-p, T = 1
µ
s
AD8017
–11–REV. C
THEORY OF OPERATION
The AD8017 is a dual high speed CF amplifier that attains new
levels of bandwidth (BW), power, distortion and signal swing,
under heavy current loads. Its wide dynamic performance
(including noise) is the result of both a new complementary
high speed bipolar process and a new and unique architectural
design. The AD8017 basically uses a two gain stage comple-
mentary design approach versus the traditional “single stage”
complementary mirror structure sometimes referred to as the
Nelson amplifier. Though twin stages have been tried before,
they typically consumed high power since they were of a folded
cascode design much like the AD9617.
This design allows for the standing or quiescent current to add
to the high signal or slew current-induced stages. In the time
domain, the large signal output rise/fall time and slew rate is
typically controlled by the small signal BW of the amplifier and
the input signal step amplitude respectively, not the dc quies-
cent current of the gain stages (with the exception of input level
shift diodes Q1/Q2). Using two stages as opposed to one, also
allows for a higher overall gain bandwidth product (GBWP) for
the same power, thus providing lower signal distortion and the
ability to drive heavier external loads. In addition, the second
gain stage also isolates (divides down) A3’s input reflected load
drive and the nonlinearities created resulting in relatively lower
distortion and higher open-loop gain. See Figure 6.
Overall, when “high” external load drive and low ac distortion is
a requirement, a twin gain stage integrating amplifier like the
AD8017 will provide excellent results for low power over the
traditional single stage complementary devices. In addition,
being a CF amplifier, closed-loop BW variations versus external
gain variations (varying R
G
) will be much lower compared to a
VF op amp, where the BW varies inversely with gain. Another
key attribute of this amplifier is its ability to run on a single 5 V
supply due in part to its wide common-mode input and output
voltage range capability. For 5 V supply operation, the device
obviously consumes less than half the quiescent power (versus
12 V supply) with little degradation in its ac and dc performance
characteristics. See specification pages for comparisons.
DC GAIN CHARACTER
Gain stages A1/A1 and A2/A2 combined provide negative feed-
forward transresistance gain. See Figure 6. Stage A3 is a unity
gain buffer which provides external load isolation to A2. Each
stage uses a symmetrical complementary design. (A3 is also
complementary, though not explicitly shown). This is done to
reduce both second order signal distortion and overall quiescent
power as discussed above. In the quasi dc-to-low frequency
region, the closed loop gain relationship can be approximated as:
G = 1+R
F
/R
G
for Noninverting Operation
G = –R
F
/R
G
for Inverting Operation
These basic relationships above are common to all traditional
operational amplifiers.
A1
IPN
IQ1
Q3
IPP
V
P
+
Q1
Q2
Z1
Q4
–
INP IPN
A1
V
N
IR + IFC
IR – IFC
IQ1
IE
AD8017
–V
I
C
P
1
–V
I
C
P
1
–A2
C
P
2ICQ + IO
V
O
9
–A3
–A2
C
D
Z1 ICQ – IO
R
N
R
F
Z2 R
L
C
L
V
O
Z1 = R1 || C1
Z1
C
D
Figure 6. Simplified Block Diagram
AD8017
–12– REV. C
APPLICATIONS
Output Power Characteristics as Applied to ADSL Signals
The AD8017 was designed to provide both relatively high cur-
rent and voltage output capability. TPCs 12 and 15 quantify the
ac load current versus distortion of the device at loads of 100 Ω
and 25 Ω at 1 MHz. Using approximately –50 dBc as the worst
case distortion limit, the AD8017 exhibits acceptable linearity
to within approximately 1.4 V of either supply rail (12 V or ±6 V)
while simultaneously providing 200 mA of load current.
These levels are achieved at only 7 mA of quiescent current for
each amplifier.
ADSL applications require signal line powers of 13 dBm that
can randomly peak to an instantaneous power (or V × I product)
of 28.5 dBm. This equates to peak-to-rms voltage ratio of 5.3-
to-1. Using a 1:2 transformer in the ADSL circuit illustrated
below and 100 Ω as the line resistance, a peak voltage of 4.2 V
at a peak current of 168 mA will be required from the line driver
output (see Table I). See detailed application below. A higher
turns ratio transformer can be used to reduce the primary out-
put voltage swing of the amplifier (for devices that do not have
the voltage swing, but do have the current drive capability).
However, this requires more than an equivalent increase in
current due to the added I × R losses from the transformer for
the same receiver power. Generally this will result in added
distortion. Table I below shows the ADSL ac current and volt-
ages required for both a 1:1 and 1:2 transformer turns ratio.
VIN
1k⍀
1k⍀0.1␮F
0.1␮F
8
2
3
1
7
5
6
4.7V
4.7V
VOUT
1:2
12V
1k⍀
0.1␮F
169⍀
169⍀
4
1k⍀
1␮F
1␮F
0.1␮F10␮F
12.5⍀
12.5⍀
100⍀
AD8017
50⍀
EFFECTIVE
LOAD
Figure 7. Single 12 V Supply ADSL Remote Terminal
Transmitter
Table I. DSL Drive Amplifier Requirements for Various Combinations of Line Power, Line Impedance, and Turn Ratios
Line Insertion Line Turns Crest Reflected Per Amp Peak Per Amplifier Peak Current
Power Loss Load Ratio Factor Impedance R1 = R2 Voltage Voltage Output Output
13 dBm 1 dB 100 Ω1:1 5.3 100 Ω50 Ω1.585 V rms 8.4 V peak 84 mA
13 dBm 1 dB 100 Ω1:2 5.3 25 Ω12.5 Ω0.792 V rms 4.2 V peak 168 mA
Single 12 V Supply ADSL Remote Terminal (RT) Transmitter
For consumer use, it is desirable to create an ADSL modem
that can be a plug-in accessory for a PC. In such an application,
the circuit should dissipate a minimum of power, yet still meet
the ADSL specification.
The circuit in Figure 7 shows a single 12 V supply circuit that
uses the AD8017 as a remote terminal transmitter. This supply
voltage is readily available on the PCI connector of PCs. The
circuit configures each half of the AD8017 as an inverter with a
gain of about six. Both of the amplifier circuits are ac coupled at
both the inputs and the outputs. This makes the dc levels of the
circuit independent of the other dc levels of the signal chain.
The inputs will generally be driven by the output of an active
filter, which has a low output impedance. Thus there will be a
minimum of loading of the source caused by the 169 Ω input
impedance in the pass band. The output will require a 1:2 step-
up transformer to drive a 100 Ω line. The reflected impedance
back to the primary will be 25 Ω. With 25 Ω of series termina-
tion added (12.5 Ω in each output), the effective load that the
differential amplifier outputs will drive is 50 Ω.
The input and output ac coupling provides two high pass cir-
cuits. The inputs are formed by the 0.1 µF capacitor and the
169 Ω resistor, which provides a break frequency of about
9.4 kHz. The two 1 µF capacitors in the output along with the
50 Ω effective load provides a 6.4 kHz break frequency in the
output side. Both of these circuits want to reject the Plain Old
Telephone System (POTS) band (dc to 4 kHz) while passing
the ADSL upstream band, which starts at about 20 kHz.
The positive inputs must be biased at midsupply, which is nomi-
nally 6 V. This will maintain the maximum dynamic range of
the output in each direction, regardless of the tolerance of the
supply. The inverting configuration was chosen as this requires
a steady dc current from this supply, as opposed to the signal-
dependent current that would be required in a noninverting
configuration. Several options were studied for creating this supply.
A voltage regulator could be used, but there are several disad-
vantages. The first is that this will not track the middle of the
supplies as it will always have an output that is a fixed voltage
from ground. This also requires an additional active component
that will impact the cost of the total solution.
A two-resistor divider could also be used. There is a tradeoff
required here in the selection of the value of the resistors. As the
resistors become smaller, the amount of power that they will
dissipate will increase. For two 1 kΩ resistors, the power dissi-
pation in this circuit would be 72 mW. Thus, in order to keep
this power to a minimum, it is desirable to make the resistors as
large as possible.
AD8017
–13–REV. C
The practical maximum value that these resistors can have is
determined by the offset voltage that is created by the input bias
current that flows through them. The maximum input bias
current into the + inputs is 45 µA. This will create an offset
voltage of 45 mV per 1 kΩ of bias resistor. Fortunately, the ac
coupling of the stages provides only unity gain for this dc offset
voltage, which is another advantage of this configuration. Any
dc offset in the output will limit the amount of dynamic signal
swing that will be available between the rails.
The circuit shown uses two 4.7 V Zener diodes that provide a
voltage drop which serves to limit the power dissipation in the
bias circuit. This allows the use of smaller value resistors in the
bias circuit. Thus, for this circuit the current will be (12 V –
(2 × 4.7 V))/2 kΩ = 1.3 mA. Thus, this circuit will dissipate
only 15.6 mW, yet only induce a maximum of 40 mV of offset
at the output. This circuit will also track the midpoint of the
supplies over their specified tolerance range.
The distortion of the circuit was measured with a 50 Ω load.
The frequency used was 500 kHz, which is beyond the maxi-
mum required for the upstream signal. For ADSL over POTS,
a maximum frequency of 135 kHz is required. For ADSL over
ISDN, the maximum frequency is 276 kHz. The amplitude was
20 V p-p (10 V p-p for each amplifier), which is the maximum
crest signal that will be required. The second harmonic was better
than –80 dBc, while the third harmonic was –64 dBc. This
represents a worst case of the absolute maximum signal that will
be required for only a very small statistical basis and at a fre-
quency that is higher than the maximum required. For a statisti-
cal majority of the time, the signal will be at a lower amplitude
and frequency, where the distortion performance will be better.
When the circuit was run while providing the upstream drive signal
in an ADSL system, the supply current to the part was mea-
sured at 25 mA. Thus, the total power to the drive circuit was
300 mW. This power winds up in three places: the drive ampli-
fier, down the line and in the termination and interface circuitry.
The ADSL specification calls for 13 dBm or 20 mW into the line.
The line termination will consume an equal amount of power, as
it is the same resistance value. About a 1 dB loss can be expected
in the losses in the interface circuitry, which translates into about
10 mW of power. Thus, the total power dissipated in the AD8017
when used as a driver in this application is about 250 mW.
A1
A1
R
L
V
O1
V
O2
VCC
VEE
Figure 8. Differential Driver Simplified Circuit Schematic
It is important to consider the total power dissipation of the
AD8017 in order to properly size the heat sinking area for your
application. The dc power dissipation for V
IN
= 0 is simply,
I
Q
. (V
CC
+ V
EE
), or 2 × I
Q
× V
S
. For the AD8017, this number is
0.17 W. In this purely differential circuit we can use symmetry
to simplify the computation for a dc input signal,
PIVVV
V
R
DQS SO
O
L
=× × +×
()
×24–
This formula is slightly pessimistic due to the fact that some of
the quiescent supply current commutates during sourcing or
sinking current into the load. For a sine wave source, integration
over a half cycle yields:
PIV VV
R
V
R
DQS
OS
L
O
L
=× × +× −
22
42
π
(Refer to Figure 41)
The situation is more complicated with a complex modulated
signal. In the case of a DMT signal, taking the equivalent sine wave
power overestimates the power dissipation by > 15%. For example:
P
OUT
= 16 dBm = 40 mW
V
OUT
@ 50 Ω = 1.41 V rms or V
O
= 1.0 V
at each amplifier output, which yields a P
D
of 0.436 W. By
actual measurement, P
D
for a DMT signal of 16 dBm requires
0.38 W of power to be dissipated by the AD8017.
OUTPUT VOLTAGE (VO) – VPK
POWER DISSIPATION (PD) – W
0.8
0
0.2
41203
0.3
0.4
0.5
0.6
0.7
0.1
56
Figure 9. Power Dissipation (P
D
) vs. Output Voltage (V
O
),
R
L
= 50
Ω
Thermal Considerations
The AD8017 in a “Thermal Coastline” SO-8 package relies on
the device pins to assist in removing heat from the die at a faster
rate than that of conventional packages. The effect is to provide
a lower θ
JC
for the device. To make the most effective use of
this, special details should be worked into the copper traces of
the printed circuit board.
There will be a tradeoff, however, between designing a board
that will maximally remove heat, and one that will provide the
desired ac performance. This is the result of the additional para-
sitic capacitance on some of the pins that would be caused by
the addition of extra heat sinking copper traces.
AD8017
–14– REV. C
The first technique for maximum heat sinking is to use a heavy
layer of copper. 2 oz. copper will provide better heat sinking
than 1 oz. copper. Additional internal circuit layers can also be
used to more effectively remove heat, and to provide better
power and ground distribution.
There are no “ground” pins per se on the AD8017 (when run
on a dual supply), but the power supplies (Pins 4 and 8) are at
ac ground. Thus, these pins can be safely tied to a maximum
area of copper foil without affecting the ac performance of the
part. On the surface side of the board, the copper area that
connects to Pins 4 and 8 should be enlarged and spread out to
the maximum extent possible. As a practical matter, there will
be diminishing returns from adding copper more than a few
centimeters from the pins.
When the power supplies are run on the board on internal
power planes, then these should also be made as large as practi-
cal, and multiple vias (~0.012 in. or 0.3 mm) should be provided
from the component layer near the power supply pins of the
AD8017 to the inner layers. These vias should not have any of
the traditional “thermal relief” spokes to the planes, because the
function of these is to impede heat flow for ease of soldering.
This is counter to the effect desired for heat sinking.
On the side of the board opposite the component, additional
heat sinking can be provided by adding copper area near the vias
to further lower the thermal resistance. Additional vias can be
provided throughout to better conduct heat from the inner layers
to the outer layers.
The remainder of the device pins are active signal pins and must
be treated a bit more carefully. Pins 2 and 6 are the summing
junctions of the op amps and will be the most adversely affected by
stray capacitance. For this reason, the copper area of these pins
should be minimized. In addition, the copper nearby on the
component layer should be kept more than 3 mm–5 mm away
from these pins, where possible. The inner and opposite side
circuit layers directly below the summing junctions should also
be void of copper.
The positive inputs and outputs can withstand somewhat more
capacitance than the summing junctions without adversely
affecting ac performance. However, these pins should be treated
carefully, and the amount of heat sinking and excess capacitance
should be analyzed and adjusted depending on the application.
If maximum ac performance is desired and the power dissipa-
tion is not extreme, then the copper area connected to these pins
should be minimized. If the ac performance is not very critical
and maximum power must be dissipated, then the copper area
connected to these pins can be increased. As in many other
areas of analog design, the designer must use some judgment
based on the consideration of the above, in order to produce a
satisfactory design.
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8017 requires
careful attention to board layout and component selection.
Table II shows recommended component values for the AD8017
and Figures 10–12 show recommended layouts for the 8-lead
SOIC package for a positive gain. Proper RF design techniques
and low parasitic component selections are mandatory.
Table II. Typical Bandwidth vs. Gain Setting Resistors
(V
S
= 6 V, R
L
= 100 ⍀)
Small Signal
Gain R
F
(⍀)R
G
(⍀)R
T
(⍀) –3 dB BW (MHz)
–1 619 619 54.5 110
+1 619 49.9 320
+2 619 619 49.9 160
+10 619 68.8 49.9 40
R
T
chosen for 50 Ω characteristic input impedance.
The PCB should have a ground plane covering all unused
portions of the component side of the board to provide a low
impedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see Fig-
ures 4 and 5). One end should be connected to the ground
plane and the other within 1/8 in. of each power pin. An addi-
tional (4.7 µF–10 µF) tantalum electrolytic capacitor should be
connected in parallel.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to
a minimum. Capacitance greater than 1.5 pF at the inverting
input will significantly affect high speed performance when
operating at low noninverting gain.
Figure 10. Universal SOIC Noninverter Top Silkscreen
AD8017
–15–REV. C
Figure 11. Universal SOIC Noninverter Top Figure 12. Universal SOIC Noninverter Bottom
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC
(R-8)
0.1968 (5.00)
0.1890 (4.80)
85
41
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)x 45
–16–
C01042–0–2/02(C)
PRINTED IN U.S.A.
AD8017
REV. C
Revision History
Location Page
Data Sheet changed from REV. B to REV. C.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3