Philips ComponentsSignetics Document No. | 353-1496 74AC/ACT1 1 286 | ore 9-bit odd/even parity generator/ checker with bus drive I/O port Date of Issue | October 17, 1990 Status Product Specification ACL Products FEATURES QUICK REFERENCE DATA * Generates either odd or even parity CONDITIONS TYPICAL for nine data lines SYMBOL PARAMETER Tamb = 25C; GND = OV; UNIT * Word length easily expanded by cas- Voo = .0V AC | ACT cading cue Seen ee oR C, = 50pF 59 | 7.3 ns * Direct bus connection for parity gen- n eration or for checking by using the f = 1MHz; Enabled 53 56 i Power dissipation parity I/O port Cpp capacitanes' pF * Glitch-free bus during power up/down C, = 50pF Disabled 46 50 * Output capability: t24mA Cw Input capacitance V,= OV or Veg 35 | 35 pF . CMOS (AC) and TTL (ACT) voltage Cyva VO capacitance Vyo = OV or Veg: Disabled 8.5 8.5 pF level inputs Per Jad wo st e JG40.2 * 50Q incident wave switching lLatcH ; Latch-up current Standard 17 500 | 500 } mA * Center-pin Veg and ground configu- Note: ration to minimize high-speed switch- 1. Cop is used to determine the dynamic power dissipation (P,, in pW): ing noise 2 2 Poe Cop x Voc xf + {C, x Voc xf) where: * Icc category: MSI f, = input frequency in MHz, C, = output load capacitance in pF, f, = output frequency in MHz, V.... = supply voltage in V, DESCRIPTION F(C nt 2 "t } yum of out sits The 74AC/ACT1 1286 high-performance L* "ce lol = CMOS devices combine very high ORDERING INFORMATION speed and high output drive compa- PACKAGES TEMPERATURE RANGE ORDER CODE rable to the most advanced TTL fami- d4pin clastic DIP F4AC1 1286N ; -pin plastic 5 lies. (300mil-wide) 40C to +85C 74ACT11286N The T4AC/IACTI 1286 39-bit parity gen- 14-pin plastic so -40C to +85C 74AC 1 1286D erator or checker is commonly used to (150mil-wide) 74ACT11286D detect errors in high-speed data trans- mission or data retrieval systems. It fea- (continued) PIN CONFIGURATION LOGIC SYMBOL LOGIC SYMBOL (IEEE/IEC) N and D Packages 2 4 141312 109 9 7 2 aK Li Ett ; 'y hy Ip '5 "4 Js 1g y '5 14 ~ wo = rx} | 1 3 nL al PARITY PARITY = = r=) vO __ ERROR + | : 3 5 6 4 ot EN1 185Philips ComponentsSignetics ACL Products Product Specification 9-bit odd/even parity generator/checker with bus drive I/O port 74AC/ACT11286 tures a local output for parity checking and a bus-driving parity /O port for par- ity generation/checking. The XMIT control input is implemented specifically for cascading for expanding word length. When XMIT is held Low the parity tree is disabled and the Parity Error output remains at a High logic level regardless of the other inputs (Ig - lg). When XMIT is High the parity tree is enabled. Parity Error indicates a par- ity error when either an even number of inputs are High and Parity l/O is forced to Low, or when an odd number of in- puts are High and Parity I/O is forced High. The VO control circuitry is designed so that the I/O port will remain in the high- impedance state during power-up or power-down to prevent bus glitches. LOGIC DIAGRAM 1, 2 \, 14 1 32 \, 12 } i, 2 4 5. PARITY 1 8 ERROR i _) parity _3 | ao oN MM. - xmir 6 Pe. L-~ PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION 2,1, 14, 13, : 12, 10,9,8.7 to- te Data inputs 3 PARITY I/O Parity VO 6 XMIT Transmit input (active Low) PARITY . 5 ERROR Parity error output 4 GND Ground (OV) 11 Voc Positive supply voltage FUNCTION TABLE Number of High Data xMiT PARITY PARITY Inputs (Ig - 1) vo ERROR 0,2,4,6,8 | H H 1,3,5,7,9 I L H h h H 0, 2,4,6,8 h I L h h L 1,3,5,7,9 h I H | = Low voltage level input h = High voltage level input H = High voltage level output L = Low voltage level output October 17, 1990 186Philips ComponentsSignetics ACL Products Product Specification 9-bit odd/even parity generator/checker with bus drive I/O port 7AACIACT11286 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER 74AC11286 74ACT11286 UNIT Min Nom Max Min Nom Max Vec DC supply voltage 3.0! 5.0 5.5 45 5.0 5.5 vy Input voltage 0 Voce 0 Veco Vo Output voltage 0 Veo 0 Veco Vv AvAv Input transition rise or fall rate 0 10 0 10 ns/V Tame Operating free-air temperature range -40 +85 -40 +85 C NOTE: 1. No electrical or switching characteristics are specified at V Output will maintain a previously established logic state. ABSOLUTE MAXIMUM RATINGS! cc < 3V. Operation between 2V and 3V is not recommended, but within that range, a device SYMBOL PARAMETER TEST CONDITIONS RATING UNIT Veo DC supply voltage -0.5 TO +7.0 V | 2 Vv, <0 -20 i DC input dicde current mA or Vi> Voc 20 Vv DC input voltage ~0.5 to Veg 40.5 Vv i 2 Vo <0 -50 OK DC output diode current mA or Vo> Voc 50 Vv DCoutput voltage -0.5 to Ver +0.5 V DC output source or | Vg = 9 sink current per output pin 0 = O10 Voc +50 mA lee DC Veg current +100 or mA l eno DC ground current +100 Tstq Storage temperature -65 to 150 C Power dissipation per package Above 70C; derate linearly by 8mW/K 500 mw Prot Power dissipation per package ; Plastic surface mount (SO) Above 70C; derate linearly by 8mW/K 400 mw NOTES; 1, Stresses beyond those listed may cause permanent damage to the device. These are stre any other conditions beyond those indicated under recommended operating conditions is extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed, October 17, 1990 187 S$ ratings only and functional operation of the device at these or not implied. Exposure to absolute-maximum-rated conditions forPhilips ComponentsSignetics ACL Products Product Specification 9-bit odd/even parity generator/checker . . 74AC/ACT11286 with bus drive I/O port DC ELECTRICAL CHARACTERISTICS 74AC11286 74ACT11286 _ ono: | Tam = 40C = 425C | Tamb = 40C SYMBOL PARAMETER TEST CONDITIONS Veo | Tamb = +25C to 485C Tamb = + to 485C UNIT v Min | Max | Min | Max | Min | Max | Min | Max 3.0 | 2.10 2.10 High-level Vin input voltage 45 | 3.15 3.15 2.0 2.0 Vv 5.5 | 3.85 3.85 2.0 2.0 3.0 0.90 0.90 Low-level Vv IL input valtage 45 1.35 1.35 08 0.8 Vv 5.5 1.65 1.65 0.8 0.8 3.0 29 29 lon = -50pA 1 45 | 44 4.4 44 44 5.5 5.4 5.4 5.4 5.4 High-level Vi= Vi Tigy=-4mA | 3.0 | 2.58 2.48 Vou output voltage orV, {SR . : V . . 3.8 3.94 3.8 low = -24mA 45 | 3.94 5.5 | 4.94 4.8 4,94 48 loy=-75mMA' | 5.5 3.85 3.85 3.0 0.1 0.1 lo, = SOWA 45 0.1 0.1 0.1 0.1 5.5 0.1 0.1 0.1 0.1 Low-level M=aVMi lo toma = . 36 4 Vou output voltage or Vin OL 3.0 0.3 0.44 Vv lo, = 24mA 45 0.36 0.44 0.36 0.44 65 0.36 0.44 0.36 0.44 lo = 75mAl | 5.5 1.65 1.65 L Input leakage current | V|= Voc or GND 55 +0.1 +1.0 +01 41.0] pA 3-State output V, = Vicor Vin, I oz off-state current Vo= Vecor GND 55 40.5 5.0 40. 5.0 Quiescent supply Vi = Veco or GND, | cc current lo =<OmA 5.5 8.0 80 8.0 80 Supply current, One input at 3.4V, other Alec TTL inputs High? inputs at Veg or GND 5.5 0.9 1.0 7 mA NOTES: 1, Notmore than one output should be tested at a time, and the duration of the test should not exceed 10ms. 2. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than OV or V.. October 17, 1990 188Philips Components--Signetics ACL Products Product Specification 9-bit odd/even parity generator/checker with bus drive I/O port 7AACIACT11286 AC ELECTRICAL CHARACTERISTICS AT 3.3V +0.3V 74AC11286 Tamb = -40C to SYMBOL PARAMETER WAVEFORM Tamb = +25C +85C UNIT Min Typ Max Min Max tpLH Propagation delay { 2.6 10.0 11.7 2.6 13.1 ns teu I, to PARITY I/O 3.8 11.6 14.5 3.8 16.4 tet Propagation delay 1 3.0 8.5 13.1 3.0 14.7 ns teu 1, to PARITY ERROR 4.0 10.9 16.0 40 17.8 teLH Propagation delay 1 2.2 5.9 7.6 2.2 8.4 tut PARITY /O to PARITY ERROR 3.4 7.9 10.2 3.4 114 ns tezy Propagation delay 2 1.8 4.9 6.4 1.8 7.0 ns touz XMIT to PARITY VO 3.2 5.4 6.6 3.2 7.0 tea Propagation delay 2 3.5 9.7 12.8 3.5 13.6 ns lez XMIT to PARITY VO 3.2 6.4 6.7 3.2 7.2 AC ELECTRICAL CHARACTERISTICS AT 5.0V +0.5V 74AC11286 SYMBOL PARAMETER WAVEFORM Tamb = +25C Tan 5 re to UNIT Min Typ Max Min Max teLy Propagation delay 1 2.0 5.5 8.0 2.0 9.0 ns teHL In to PARITY VO 3.1 6.9 9.1 3.1 10.7 tery Propagation delay 1 2.5 5.2 8.9 2.5 10.0 ns teHL |, to PARITY ERROR 3.3 6.5 10.7 3.3 12.0 teLH Propagation delay { 1.9 3.9 5.6 1.9 6.2 ns teHt PARITY I/O to PARITY ERROR 2.9 5.0 7.2 2.9 7.9 tpzy Propagation delay 2 1.4 3.3 4.9 1.4 5.3 ns tpuz XMIT to PARITY lO 3.1 48 6.1 3.1 6.5 tez, Propagation delay 2 3.0 5.4 8.3 3.0 8.9 ns tpiz XMIT to PARITY VO 3.0 4.6 6.0 3.0 6.3 AC ELECTRICAL CHARACTERISTICS AT 5.0V +0.5V 74ACT11286 SYMBOL PARAMETER WAVEFORM Toma = #25C Fane 5 ee to UNIT Min Typ Max Min Max tecH Propagation delay 1 2.7 6.1 8.0 2.7 10.4 ns teu |, to PARITY VO 3.6 7.3 10.8 3.6 12.0 tet Propagation delay 1 3.0 6.9 9.7 3.0 11.3 ns te. 1, to PARITY ERROR 3.9 7.7 11.4 3.9 12.9 teLH Propagation delay 1 2.2 4.6 6.8 2.2 7.7 ns teu PARITY (/O to PARITY ERROR 3.1 5.6 8.3 3.4 9.4 tpzy Propagation delay 2 1.8 4.2 6.3 1.8 7.3 ns teuz XMIT to PARITY VO 4.7 6.5 7.9 4.7 8.5 tpz, Propagation delay 2 3.0 6.3 9.4 3.0 11.4 ns teiz XMIT to PARITY VO 41 6.0 7.3 43 7.8 October 17, 1990 189Philips ComponentsSignetics ACL Products Product Specification 9-bit odd/even parity generator/checker with bus drive I/O port TAACIACTI1286 AC WAVEFORMS PARITY I/O, |, INPUTS PARITY I/O, PARITY ERROR OUTPUTS Waveform 1. Waveforms Showing the Inputs (ly PARITY I/O) to Outputs (PARITY ERROR, PARITY I/O) Propagation Delays XMIT INPUT Vee PARITY VO OUTPUT PARITY VC OUTPUT ov Waveform 2, Waveforms Showing the 3-State Output Enable and Disable Times WAVEFORM CONDITIONS INPUTS OUTPUTS Vin = GND to Vee, Ac Vout = Vo, to Vou Vy = 50% Voc Vin = GND to 3.0V, ACT Vu = 50% Voc Vy = 1.5V October 17, 1990 190Philips GomponentsSignetics ACL Products Product Specification 9-bit odd/even parity generator/checker ; 74AC/ACT11286 with bus drive I/O port TEST CIRCUIT 2 Voc GENERATOR Open | GND Test Circuit TEST S1 DEFINITIONS includ C.= Load capacitance, 50pF; includes jig beunt put Open and probe capacitance tpyz't pz 2"Voc RL= Load resistor, 5002 t puz/t pz GND Ry= Termination resistance should be equal to Zoyy of pulse generators SWITCH POSITION Input pulses: PRR < 10MHz thp=t=3ns October 17, 1990 191