MC74HC73A Dual J-K Flip-Flop with Reset High-Performance Silicon-Gate CMOS The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip-flop is negative-edge clocked and has an active-low asynchronous reset. The MC74HC73A is identical in function to the HC107, but has a different pinout. MARKING DIAGRAMS 14 PDIP-14 N SUFFIX CASE 646 14 Features * * * * * * * * http://onsemi.com Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the JEDEC Standard No. 7.0 A Requirements Chip Complexity: 92 FETs or 23 Equivalent Gates These are Pb-Free Devices LOGIC DIAGRAM 14 J1 PIN ASSIGNMENT 12 Q1 1 CLOCK 1 13 3 K1 Q1 2 RESET 1 7 J2 9 Q2 5 CLOCK 2 8 10 K2 CLOCK 1 1 14 J1 RESET 1 2 13 Q1 K1 3 12 Q1 VCC 4 11 GND CLOCK 2 5 10 K2 RESET 2 6 9 Q2 J2 7 8 Q2 1 MC74HC73AN AWLYYWWG 1 14 SOIC-14 D SUFFIX CASE 751A 14 1 HC73AG AWLYWW 1 14 14 1 TSSOP-14 DT SUFFIX CASE 948G 1 HC 73A ALYWG G A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION Q2 See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. 6 RESET 2 PIN 4 = VCC PIN 11 = GND FUNCTION TABLE Inputs Outputs Reset Clock J K L H H H H H H H X X L L H H X X X X L H L H X X X L H Q Q L H No Change L H H L Toggle No Change No Change No Change (c) Semiconductor Components Industries, LLC, 2009 December, 2009 - Rev. 7 1 Publication Order Number: MC74HC73/D MC74HC73A MAXIMUM RATINGS* Symbol Parameter Value Unit - 0.5 to + 7.0 V VCC DC Supply Voltage (Referenced to GND) Vin DC Input Voltage (Referenced to GND) - 1.5 to VCC + 1.5 V Vout DC Output Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V Iin DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air 750 500 mW Tstg Storage Temperature - 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Plastic DIP SOIC Package This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. _C 260 *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Min Max Unit 2.0 6.0 V 0 VCC V - 55 + 125 _C 0 0 0 1000 500 400 ns DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC V - 55 to 25_C v 85_C v 125_C Unit VIH Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 A 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 A 2.0 4.5 6.0 0.3 0.9 1.2 0.3 0.9 1.2 0.3 0.9 1.2 V VOH Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| v 20 A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.70 5.20 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4.5 6.0 0.26 0.26 0.33 0.33 0.40 0.40 Symbol Parameter Test Conditions Vin = VIH or VIL VOL Maximum Low-Level Output Voltage |Iout| v 4.0 mA |Iout| v 5.2 mA Vin = VIH or VIL |Iout| v 20 A Vin = VIH or VIL |Iout| v 4.0 mA |Iout| v 5.2 mA V Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 0.1 1.0 1.0 A ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 A 6.0 4 40 80 A http://onsemi.com 2 MC74HC73A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V - 55 to 25_C v 85_C v 125_C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 4.5 6.0 6.0 30 35 4.8 24 28 4.0 20 24 MHz tPLH, tPHL Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4) 2.0 4.5 6.0 125 25 21 155 31 26 190 38 32 ns tPLH, tPHL Maximum Propagation Delay, Reset to Q or Q (Figures 2 and 4) 2.0 4.5 6.0 155 31 26 195 39 33 235 47 40 ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns Maximum Input Capacitance -- 10 10 10 pF Cin Typical @ 25C, VCC = 5.0 V CPD 35 Power Dissipation Capacitance (Per Flip-Flop)* pF * Used to determine the no-load dynamic power consumption: P D = CPD VCC 2 f + ICC VCC . TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V - 55 to 25_C v 85_C v 125_C Unit tsu Minimum Setup Time, J or K to Clock (Figure 3) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns th Minimum Hold Time, Clock to J or K (Figure 3) 2.0 4.5 6.0 3 3 3 3 3 3 3 3 3 ns trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 4.5 6.0 100 20 17 125 25 21 150 30 26 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 4.5 6.0 80 16 14 100 20 17 120 24 20 ns Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns tr, tf http://onsemi.com 3 MC74HC73A SWITCHING WAVEFORMS CLOCK tf 90% 50% 10% tr tw VCC VCC 50% RESET GND GND tPHL tw 1/fmax tPLH tPHL Q or Q 50% Q 90% 50% 10% tPLH 50% Q trec tTHL tTLH VCC Figure 1. 50% CLOCK GND Figure 2. VALID VCC TEST POINT J or K GND tsu OUTPUT th DEVICE UNDER TEST VCC CLOCK 50% GND CL* Figure 3. *Includes all probe and jig capacitance Figure 4. EXPANDED LOGIC DIAGRAM RESET 2, 6 12, 9 CL J K 14, 7 3, 10 CL CLOCK Q CL CL CL CL CL CL CL CL CL 1, 5 CL CL CL http://onsemi.com 4 13, 8 Q MC74HC73A ORDERING INFORMATION Package Shipping MC74HC73ANG PDIP-14 (Pb-Free) 25 Units / Rail MC74HC73ADG SOIC-14 (Pb-Free) 55 Units / Rail MC74HC73ADR2G SOIC-14 (Pb-Free) Device MC74HC73ADTR2G 2500 / Tape & Reel TSSOP-14* For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 5 MC74HC73A PACKAGE DIMENSIONS PDIP-14 CASE 646-06 ISSUE P 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F L N C -T- SEATING PLANE H G D 14 PL J K 0.13 (0.005) M M http://onsemi.com 6 DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01 MC74HC73A PACKAGE DIMENSIONS SOIC-14 CASE 751A-03 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 8 -B- P 7 PL 0.25 (0.010) M 7 1 G -T- 0.25 (0.010) M T B S A DIM A B C D F G J K M P R J M K D 14 PL F R X 45 _ C SEATING PLANE B M S SOLDERING FOOTPRINT* 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 MC74HC73A PACKAGE DIMENSIONS TSSOP-14 CASE 948G-01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 M B -U- L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U 0.25 (0.010) 8 S DETAIL E K A -V- EEE CCC CCC EEE K1 J J1 SECTION N-N C 0.10 (0.004) -T- SEATING PLANE D H G DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 -W- K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 8 MC74HC73A ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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