© Semiconductor Components Industries, LLC, 2009
December, 2009 − Rev. 7
1Publication Order Number:
MC74HC73/D
MC74HC73A
Dual J-K Flip-Flop with
Reset
High−Performance Silicon−Gate CMOS
The MC74HC73A is identical in pinout to the LS73. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Each flip−flop is negative−edge clocked and has an active−low
asynchronous reset.
The MC74HC73A is identical in function to the HC107, but has a
different pinout.
Features
•Output Drive Capability: 10 LSTTL Loads
•Outputs Directly Interface to CMOS, NMOS, and TTL
•Operating Voltage Range: 2.0 to 6.0 V
•Low Input Current: 1.0 mA
•High Noise Immunity Characteristic of CMOS Devices
•In Compliance with the JEDEC Standard No. 7.0 A Requirements
•Chip Complexity: 92 FETs or 23 Equivalent Gates
•These are Pb−Free Devices
PIN ASSIGNMENT
FUNCTION TABLE
LOGIC DIAGRAM
PIN 4 = VCC
PIN 11 = GND
RESET 2
K2
CLOCK 2
J2
RESET 1
K1
CLOCK 1
J1
Q2
Q2
Q1
Q1
14
1
3
2
7
5
10
6
12
13
9
8
11
12
13
14
8
9
105
4
3
2
1
7
6
K2
GND
Q1
Q1
J1
Q2
Q2
VCC
K1
RESET 1
CLOCK 1
J2
RESET 2
CLOCK 2
Inputs Outputs
Reset Clock J K Q Q
L XXXLH
H L L No Change
HLHLH
HHLHL
H H H Toggle
H L X X No Change
H H X X No Change
H X X No Change
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MARKING
DIAGRAMS
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G= Pb−Free Package
TSSOP−14
DT SUFFIX
CASE 948G
14
1
SOIC−14
D SUFFIX
CASE 751A
14
1
HC73AG
AWLYWW
1
14
HC
73A
ALYWG
G
1
14
1
4
1
PDIP−14
N SUFFIX
CASE 646
MC74HC73AN
AWLYYWWG
1
14
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
MC74HC73A
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2
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 V
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
Iin DC Input Current, per Pin ±20 mA
Iout DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PDPower Dissipation in Still Air Plastic DIP†
SOIC Package†
750
500
mW
Tstg Storage Temperature – 65 to + 150 _C
TLLead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260
_C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TAOperating Temperature, All Package Types – 55 + 125 _C
tr, tfInput Rise and Fall Time VCC = 2.0 V
(Figure 1) VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol Parameter Test Conditions
VCC
V
Guaranteed Limit
Unit
– 55 to
25_Cv 85_Cv 125_C
VIH Minimum High−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 μA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL Maximum Low−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 μA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH Minimum High−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 20 μA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout| v 4.0 mA
|Iout| v 5.2 mA
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
VOL Maximum Low−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 20 μA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout| v 4.0 mA
|Iout| v 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 μA
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 μA
6.0 4 40 80 μA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC73A
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3
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to
25_Cv 85_Cv 125_C
fmax Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tPLH,
tPHL
Maximum Propagation Delay, Reset to Q or Q
(Figures 2 and 4)
2.0
4.5
6.0
155
31
26
195
39
33
235
47
40
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin Maximum Input Capacitance — 10 10 10 pF
CPD Power Dissipation Capacitance (Per Flip−Flop)*
Typical @ 25°C, VCC = 5.0 V
pF
35
* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to
25_Cv 85_Cv 125_C
tsu Minimum Setup Time, J or K to Clock
(Figure 3)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
thMinimum Hold Time, Clock to J or K
(Figure 3)
2.0
4.5
6.0
3
3
3
3
3
3
3
3
3
ns
trec Minimum Recovery Time, Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
twMinimum Pulse Width, Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
twMinimum Pulse Width, Reset
(Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
ns
tr, tfMaximum Input Rise and Fall Times
(Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
MC74HC73A
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4
SWITCHING WAVEFORMS
tsu
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CLOCK
Q or Q
90%90%
50%
10%
tftrVCC
GND
tw
1/fmax
tPLH tPHL
90%
50%
10%
tTLH tTHL
Figure 1.
Figure 2.
Figure 3.
Figure 4.
50%
50%
50%
50%
VCC
VCC
GND
GND
RESET
Q
Q
CLOCK
tPLH
tPHL
trec
tw
VALID
50%
J or K
CLOCK
VCC
VCC
GND
GND
th
EXPANDED LOGIC DIAGRAM
RESET
K
CLOCK
2, 6
14, 7
3, 10
1, 5
CL CL
CL
CL
CL CL
CL
CL CL
CL
CL
Q
Q
12, 9
13, 8
CL
CL
CL
J
MC74HC73A
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5
ORDERING INFORMATION
Device Package Shipping†
MC74HC73ANG PDIP−14
(Pb−Free) 25 Units / Rail
MC74HC73ADG SOIC−14
(Pb−Free) 55 Units / Rail
MC74HC73ADR2G SOIC−14
(Pb−Free) 2500 / Tape & Reel
MC74HC73ADTR2G TSSOP−14*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
MC74HC73A
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6
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
17
14 8
B
ADIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.715 0.770 18.16 19.56
B0.240 0.260 6.10 6.60
C0.145 0.185 3.69 4.69
D0.015 0.021 0.38 0.53
F0.040 0.070 1.02 1.78
G0.100 BSC 2.54 BSC
H0.052 0.095 1.32 2.41
J0.008 0.015 0.20 0.38
K0.115 0.135 2.92 3.43
L
M−−− 10 −−− 10
N0.015 0.039 0.38 1.01
__
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
F
HG D
K
C
SEATING
PLANE
N
−T−
14 PL
M
0.13 (0.005)
L
M
J0.290 0.310 7.37 7.87
MC74HC73A
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7
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
−B−
G
P7 PL
14 8
7
1
M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
−T−
F
RX 45
SEATING
PLANE D14 PL K
C
J
M
_DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
__ __
7.04
14X
0.58
14X
1.52
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
7X
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74HC73A
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8
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.50 0.60 0.020 0.024
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
____
S
U0.15 (0.006) T
2X L/2
S
U
M
0.10 (0.004) V S
T
L−U−
SEATING
PLANE
0.10 (0.004)
−T−
ÇÇÇ
ÇÇÇ
SECTION N−N
DETAIL E
JJ1
K
K1
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
−W−
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U0.15 (0.006) T
−V−
14X REFK
N
N
7.06
14X
0.36 14X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74HC73A
http://onsemi.com
9
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 81−3−5773−3850
MC74HC73/D
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