RX630 Group
Renesas MCUs
DATASHEET
R01DS0060EJ0100 Rev.1.00 Page 1 of 168
Sep 13, 2011
Features
32-bit RX CPU core
Max. operating frequency: 100 MHz
Capable of 165 DMIPS in operation at 100 MHz
Single precision 32-bit IEEE-754 floating poin t
Two types of multiply-and-accumulation unit (between memories
and between registers)
32-bit multiplier (fastest instruction execution takes one CPU
clock cycle)
Divider (fastest instruction execution takes two CPU clock cycles)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions: Ultra-compact code
Supports the memory protection unit (MPU)
JTAG and FINE (two-line) debugging interfaces
Low-power design and architecture
Operation from a single 2.7- to 3.6-V supply
Low power consumption: A product that supports all peripheral
functions draws only 500 μA/MHz.
RTC is capable of operation from a dedicated power supply (min.
operating voltage: 2.3 V).
Four low-power modes
On-chip main flash memory, no wait states
100-MHz operation, 10-ns read cycle (no wait states)
384-Kbyte to 2-Mbyte capacities
User code programmable via the USB, SCI, or JTAG
On-chip data flash memory
Max. 32 Kbytes, reprogrammable up to 100,000 times
Programming/erasing as background operations (BGOs)
On-chip SRAM, no wait states
32- to 128-Kbyte capacities
For instructions and operands
Can provide backup on deep software standby
DMA
DMAC: Incorporates four channels
DTC
Reset and supply management
Power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
External crystal oscillator or internal PLL for operation at 4 to 16
MHz
Internal 125-kHz LOCO and 50-MHz HOCO
Dedicated 125-kHz LOCO for the IWDT
Frequency of the oscillator for sub-clock generation: 32 kHz
Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Time capture function
(for capturing times in response to event-signal input on external
pins)
Independent watchdog timer
125-kHz LOCO clock operation
Useful functions for IEC60730 compliance
Oscillation-stop detection, frequency measurement, CRC, IWDT,
self-diagnostic function for the A/D converter, etc.
Up to 22 communications interfaces
USB 2.0 full-speed function interface (1 channel)
CAN (compliant with ISO11898-1), incorporating 32 mailboxes
(up to 3 channels)
SCI with multiple functionalities (up to 13 channels)
Choose from amon g asynchronous mode, clock-synchrono us
mode, smart-card interface mode, simple SPI, simple I2C, and
extended serial mode.
I2C bus interface for transfer at up to 1 Mbps (up to 4 channels)
RSPI for high-speed transfer (up to 3 channels)
External address space
8 CS areas (8 × 16 Mbytes)
Multiplexed address data or separate address lines are selectable
per area.
8-, 16-, or 32-bit bus space is selectable per area
Up to 20 extended-function timers
16-bit MTU2: input capture, output capture, complementary PWM
output, phase-counting mode (6 channels)
16-bit TPU: input capture, output capture, phase-counting mode
(12 channels)
8-bit TMR (4 channels)
16-bit compare-match timers (4 channels)
A/D converter for 1-MHz Operation
Up to 21 12-bit channels, and incorporating 1 sample-and-hold
circuit
Up to 8 10-bit channels, and incorp or atin g 1 sample-and-h o l d
circuit
Addition of results of A/D conversion (in the 12-bit A/D converter)
Self diagnosis (for the 10-bit A/D converter)
10-bit D/A converter: 2 channels
Temperatur e sensor for measuring temperature
within the chip
Register write protec tion function can protect
values in important registers against overwriting.
Up to 148 pins for GPIO
5-V tolerance, open drain, input pull-up, switchable driving ability
Operating temp. range
–40 C to +85C
PLQP0176KB-A 24 × 24 m m, 0.5-mm pitch
PLQP0144KA-A 20 × 20 m m, 0.5-mm pitch
PLQP0100KB-A 14 × 14 m m, 0.5-mm pitch
PLQP0080KB-A 12 × 12 m m, 0.5-mm pitch
PTLG0177JB-A 8 × 8 mm, 0.5-mm pitch
PTLG0145KA-A 7 × 7 mm, 0.5-mm pitch
PTLG0100KA-A 5 .5 × 5.5 m m , 0.5-mm pitch
PLBG0176GA-A 13 × 13 mm, 0.8-mm pitch
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS,
up to 2-MB flash memory, USB 2.0 full-speed function interface,
CAN, 10- & 12-bit A/D converter, RTC, up to 22 comms interfaces
R01DS0060EJ0100
Rev.1.00
Sep 13, 2011
Features
R01DS0060EJ0100 Rev.1.00 Page 2 of 168
Sep 13, 2011
RX630 Group 1. Overview
1. Overview
1.1 Outline of Specifications
Table 1.1 lists the specifications in outline, and Table 1.2 lists the functions of products.
Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs
depending on the pin number on the pack age and the on-chip ROM capacity. For details, see Table 1.2, Fu nc tion s of
RX630 Group Products.
Table 1.1 Outline of Specifications (1/5)
Classification Module/Function Description
CPU CPU Maximum operating frequency: 100 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system
clock)
Address space: 4-Gbyte linear
Register set of the CPU
General purpose: Sixteen 32-bit registers
Control: Nine 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
Floating-point operation instructions: 8
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 × 32 64 bits
On-chip divider: 32 / 32 32 bits
Barrel shifter: 32 bits
FPU Single precision floating point (32 bits)
Data types and floating-point exceptions in conformance with the IEEE754 standard
Memory ROM ROM capacity: 2 Mbytes max.
Two on-board programming modes
Boot mode (The user area is programmable via the SCI and USB.)
User program mode
Parallel programmer mode (for off-board programming)
RAM RAM capacity: 128 Kbytes
E2 data flash Data ROM capacity: 32 Kbytes
MCU operating modes Single-chip mode, on-chip ROM enabled expansion mode, and on-chip ROM disabled
expansion mode (software switching)
Clock Clock generation circuit Main clock oscillator, sub-clock oscillator, low-speed/high-speed on-chip oscillator, PLL
frequency synthesizer, and dedicated on-chip oscillator for the IWDT
Main-clock oscillation stop detection
Separate frequency-division and multiplication settings for the system clock (ICLK),
peripheral module clock (PCLK), and external bus clock (BCLK)
The CPU and other bus masters run in synchronization with the system clock (ICLK):
Up to 100 MHz
Peripheral modules run in synchronization with the peripher al module clock (PCLK):
Up to 50 MHz
Devices connected to the external bus run in synchronization with the external bus
clock (BCLK): Up to 50 MHz
Reset Pin reset, power-on reset, voltage-monitoring reset, independent watchdog timer reset,
watchdog timer reset, deep software standby reset, and software reset
Voltage detection circuit When the voltage on VCC passes the voltage detection level (Vdet), an internal reset or
internal interrupt is generated.
Low power
consumption Low power
consumption facilities Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software
standby mode
Battery backup function
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Sep 13, 2011
RX630 Group 1. Overview
Interrupt Interrupt control unit
(ICUb) Peripheral function interrupts: 180 sources
External interrupts: 16 (pins IRQ0 to IRQ15)
Software interrupts: One source
Non-maskable interrupts: 6 sources
Sixteen levels specifiable for the order of priority
External bus extension The external address space can be divided into eight areas (CS0 to CS7), each with
independent control of access settings.
Capacity of each area: 16 Mbytes (CS0 to CS7)
A chip-select signal (CS0# to CS7#) can be output for each area.
Each area is specifiable as an 8-, 16- or 32-bit bus space
The data arrangement in each area is selectable as little or big endian (only for data).
Bus format: Separate bus, multiplex bus
Wait control
Write buffer facility
DMA DMA controller
(DMACA) 4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
Data transfer controller
(DTCa) Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: External interrupts and interrupt requests from peripheral functions
I/O ports Programmable I/O ports 177-pin TFLGA (in planning), 176-pin LFBGA (in planning), 176-pin LQFP
I/O pins: 148
Input pin: 1
Pull-up resistors: 148
Open-drain outputs: 148
5-V tolerance: 54
145-pin TFLGA (in planning), 144-pin LQFP
I/O pins: 117
Input pin: 1
Pull-up resistors: 117
Open-drain outputs: 117
5-V tolerance: 53
100-pin TFLGA (in planning), 100-pin LQFP
I/O pins: 78
Input pin: 1
Pull-up resistors: 78
Open-drain outputs: 78
5-V tolerance: 44
80-pin LQFP
I/O pins: 58
Input pin: 1
Pull-up resistors: 58
Open-drain outputs: 58
5-V tolerance: 34
Table 1.1 Outline of Specifications (2/5)
Classification Module/Function Description
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RX630 Group 1. Overview
Timers 16-bit timer pulse unit
(TPUa) (16 bits × 6 channels) × 2 units
Maximum of 16 pulse-input/output possible
Select from among seven or eight counter-input clock signals for each channel
Supports the input capture/output compare function
Output of PWM waveforms in up to 15 phases in PWM mode
Support for buffered operation, phase-counting mode (two phase encoder input) and
cascade-connected operation (32 bits × 2 channels) depending on the channel.
PPG output trigger can be generated
Capable of generating conversion start triggers for the A/D converters
Signals from the input capture pins are input via a digital filter
Clock frequency measuring method
Multi-function timer
pulse unit 2 (MTU2a) (16 bits × 6 channels) × 1 unit
Time bases for the 6 16-bit timer channels can be provided via up to 16 pulse-input/
output lines and three pulse-input lines
Select from among eight counter-input clock signals for each channel (PCLK/1, PCLK/
4, PCLK/16, PCLK/64, TCLKA, TCLKB, TCLKC, TCLKD) other than channel 5, for
which only four signals are available.
Input capture function
21 output compare/input capture registers
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Digital filter
Signals from the input capture pins are input via a digital filter
PPG output trigger can be generated
Clock frequency measuring function
Frequency
measurement function
(MCK)
The MTU or unit 0 TPU module can be used to monitor the main clock, sub-clock, HOCO
clock, LOCO clock, and PLL clock for abnormal fr equencies.
Port output enable 2
(POE2a) Controls the high-impedance state of the MTU’s waveform output pins
Programmable pulse
generator (PPG) (4 bits × 4 groups) × 2 units
Pulse output with the MTU or TPU output as a trigger
Maximum of 32 pulse-output possible
8-bit timers (TMR) (8 bits × 2 channels) × 2 units
Select from among seven internal clock signals (PCLK, PCLK/2, PCLK/8, PCLK/32,
PCLK/64, PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Generation of triggers for A/D converter conversion
Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12
Compare match timer
(CMT) (16 bits × 2 channels) × 2 units
Select from among four internal clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/
512)
Realtime clock (RTCa) Clock sources: Main clock, sub-clock
Clock and calendar functions
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Battery backup operation
Time-capture facility for three values
Watchdog timer
(WDTA) 14 bits × 1 channel
Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/
512, PCLK/2048, PCLK/8192)
Independent watchdog
timer (IWDTA) 14 bits × 1 channel
Counter-input clock: Dedicated on-chip oscillator for IWDT
Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,
dedicated clock/128, dedicated clock/256
Table 1.1 Outline of Specifications (3/5)
Classification Module/Function Description
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Sep 13, 2011
RX630 Group 1. Overview
Communication
function USB 2.0 function
module (USBa) Includes a UDC (USB Device Controller) and transceiver for USB 2.0
Single port
Compliance with the USB 2.0 specification
Transfer rate: Full speed (12 Mbps)
Self-power mode and bus power are selectable
Incorporates 2 Kbytes of RAM as a transfer buffer
Serial communications
interfaces (SCIc, SCId) 13 channels (SCIc: 12 channels + SCId: 1 channel)
SCIc
Serial communications modes: Asynchronous, clock synchronous, and smart-card
interface
Multi-processor function
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12
Simple I2C
Simple SPI
SCId (The following functions are added to SCIc)
Supports the serial communications protocol, which contains the start frame and
information frame
Supports the LIN format
I2C bus interfaces
(RIIC) 4 channels (one of them is FM+)
Communication formats
I2C bus format/SMBus format
Supports the multi-master
Max. transfer rate: 1 Mbps (channel 0)
IEBus (IEB) 1 channel
Supports protocol control for the IEBus
Half-duplex asynchronous transfer
Multi-master operation
Broadcast communications function
Two selectable modes, differentiated by transfer rate
CAN module (CAN) 3 channels
Compliance with the ISO11898-1 specification (standard frame and extended frame)
32 mailboxes each
Serial peripheral
interfaces (RSPI) 3 channels
RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16,
or to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with
each frame having up to 32 bits)
Buffered structure
Double buffers for both transmission and reception
12-bit A/D converter (S12ADa) 1 unit (1 unit × 21 channels)
12-bit resolution
Conversion time: 1.0 s per channel (in operation with PCLK at 50 MHz)
Operating mode
Scan mode (single scan mode or continuous scan mode)
Sample-and-hold function
Reference voltage generation
Three ways to start A/D conversion
Conversion can be started by software, a conversion start trigger from a timer (MTU,
TPU, or TMR), or an external trigger signal.
A/D conversion of the temperature sensor output
Table 1.1 Outline of Specifications (4/5)
Classification Module/Function Description
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RX630 Group 1. Overview
10-bit A/D converter (ADb) 1 unit (1 unit × 8 channels)
10-bit resolution
Conversion time: 1.0 µs per channel (in operation with PCLK at 50 MHz)
Operating mode
Scan mode (single scan mode or continuous scan mode)
External amplifier connection mode
Sample-and-hold function
Three ways to start A/D conversion
Conversion can be started by software, a conversion start trigger from a timer (MTU,
TPU, or TMR), or an external trigger signal.
D/A converter (DAa) 2 channels
10-bit resolution
Output voltage: 0 V to VREFH
Temper ature sensor 1 channel
Precision: TBD
Absolute accuracy: TBD
The voltage of the temperature is converted into a digital value by the 12-bit A/D
converter.
CRC calculator (CRC) CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1.
Generation of CRC codes for use with LSB-first or MSB-first communications is
selectable
Operating frequency Up to 100 MHz
Power supply voltage VCC = AVCC0 = VREFH = 2.7 to 3.6 V, VREFH0 = 2.7 V to AVCC0, Vbatt = 2.0 to 3.6 V
Supply current TBD mA
Operating temperature 40 to +85C (products with wide-temperature-range spec.)
Package 177-pin TFLGA (PTLG0177KA-A) (in planning)
176-pin LFBGA (PLBG0176GA-A) (in planning)
176-pin LQFP (PLQP0176KB-A)
145-pin TFLGA (PTLG0145KA-A) (in planning)
144-pin LQFP (PLQP0144KA-A)
100-pin TFLGA (PTLG0100KA-A) (in planning)
100-pin LQFP (PLQP0100KB-A)
80-pin LQFP (PLQP0080KB-A)
On-chip debugging system E1 emulator (JTAG and FINE interfaces)
E20 emulator (JTAG interface)
Table 1.1 Outline of Specifications (5/5)
Classification Module/Function Description
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Sep 13, 2011
RX630 Group 1. Overview
Table 1.2 Functions of RX630 Group Produc ts
Functions RX630 Group
Package 177 Pins,
176 Pins 145 Pins,
144 Pins 100 Pins 80 Pins
External bus External bus width 32 bits 16 bits Not supported
DMA DMA controller Ch. 0 to 3
Data transfer controller Supported
Timers 16-bit timer pulse unit Ch. 0 to 11 Ch. 0 to 5
Multi-function timer pulse unit 2 Ch. 0 to 5
Port output enable 2 Supported
Programmable pulse generator Ch. 0 and 1
8-bit timers Ch. 0 to 3
Compare match timer Ch. 0 to 3
Realtime clock Supported
Watchdog timer Supported
Independent watchdog timer Supported
Communication
function USB 2.0 function module Ch. 0
Serial communications interfaces (SClc) Ch. 0 to 11 Ch. 0 to 3, 5, 6,
8, 9 Ch. 1, 5, 6, 8, 9
Serial communications interfaces (SCld) Ch. 12
I2C bus interfaces Ch. 0 to 3 Ch. 0, 2
IEBus Supported
Serial peripheral interfaces Ch. 0 to 2 Ch. 0, 1
CAN module For 1 M or less: Ch. 0, 1
For 1.5 M or more: Ch. 0 to 2 For 512 K or
less: Ch. 1
For 768 K or
more: Ch. 0, 1
Ch. 1
12-bit A/D converter AN000 to 020 AN000 to 013 AN000 to 010
10-bit A/D converter AN0 to 7 AN0 to 3
D/A converter Ch. 0, 1 Ch. 1
Temper ature sensor Supported
CRC calculator Supported
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Sep 13, 2011
RX630 Group 1. Overview
1.2 List of Products
Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part num ber.
Table 1.3 List of Products (1/2)
Group Part No. Package ROM Capacity RAM Capacity E2 Data Flash
Operating
Frequency
(Max.)
RX630 R5F56307CDFN PLQP0080KB-A 384 Kbytes 64 Kbyte s 32 Kbytes 100 MHz
R5F56307DDFN PLQP0080KB-A 384 Kbytes 64 Kbytes 32 Kbytes 100 MHz
R5F56307CDFP PLQP0100KB-A 384 Kbytes 64 Kbytes 32 Kbytes 100 MHz
R5F56307DDFP PLQP0100KB-A 384 Kbytes 64 Kbytes 32 Kbytes 100 MHz
R5F56307CDLA PTLG0100KA-A*1384 Kbytes 64 Kbytes 32 Kbytes 100 MHz
R5F56307DDLA PTLG0100KA-A*1384 Kbytes 64 Kbytes 32 Kbytes 100 MHz
R5F56308CDFN PLQP0080KB-A 512 Kbytes 64 Kbytes 32 Kbytes 100 MHz
R5F56308DDFN PLQP0080KB-A 512 Kbytes 64 Kbytes 32 Kbytes 100 MHz
R5F56308CDFP PLQP0100KB-A 512 Kbytes 64 Kbytes 32 Kbytes 100 MHz
R5F56308DDFP PLQP0100KB-A 512 Kbytes 64 Kbytes 32 Kbytes 100 MHz
R5F56308CDLA PTLG0100KA-A*1512 Kbytes 64 Kbytes 32 Kbytes 100 MHz
R5F56308DDLA PTLG0100KA-A*1512 Kbytes 64 Kbytes 32 Kbytes 100 MHz
R5F5630ACDFP PLQP0100KB-A 768 Kbytes 96 Kbyte s 32 Kbytes 100 MHz
R5F5630ADDFP PLQP0100KB-A 768 Kbytes 96 Kbyte s 32 Kbytes 100 MHz
R5F5630ACDFB PLQP0144KA-A 768 Kbytes 96 Kbyte s 32 Kbytes 100 MHz
R5F5630ADDFB PLQP0144KA-A 768 Kbytes 96 Kbyte s 32 Kbytes 100 MHz
R5F5630ACDLK PTLG0145KA-A*1768 Kbytes 96 Kbytes 32 Kbytes 100 MHz
R5F5630ADDLK PTLG0145KA-A*1768 Kbytes 96 Kbytes 32 Kbytes 100 MHz
R5F5630ACDFC PLQP0176KB-A 768 Kbytes 96 Kbyte s 32 Kbytes 100 MHz
R5F5630ADDFC PLQP0176KB-A 768 Kbytes 96 Kbyte s 32 Kbytes 100 MHz
R5F5630ACDBG PLBG0176GA-A*1768 Kbytes 96 Kbytes 32 Kbytes 100 MHz
R5F5630ADDBG PLBG0176GA-A*1768 Kbytes 96 Kbytes 32 Kbytes 100 MHz
R5F5630ACDLC PTLG0177KA-A*1768 Kbytes 96 Kbytes 32 Kbytes 100 MHz
R5F5630ADDLC PTLG0177KA-A*1768 Kbytes 96 Kbytes 32 Kbytes 100 MHz
R5F5630BCDFP PLQP0100KB-A 1 Mbyte 96 Kbytes 32 Kbytes 100 MHz
R5F5630BDDFP PLQP0100KB-A 1 Mbyte 96 Kbytes 32 Kbytes 100 MHz
R5F5630BCDFB PLQP0144KA-A 1 Mbyte 96 Kbytes 32 Kbytes 100 MHz
R5F5630BDDFB PLQP0144KA-A 1 Mbyte 96 Kbytes 32 Kbytes 100 MHz
R5F5630BCDLK PTLG0145KA-A*11 Mbyte 96 Kbytes 32 Kbytes 100 MHz
R5F5630BDDLK PTLG0145KA-A*11 Mbyte 96 Kbytes 32 Kbytes 100 MHz
R5F5630BCDFC PLQP0176KB-A 1 Mbyte 96 Kbytes 32 Kbytes 100 MHz
R5F5630BDDFC PLQP0176KB-A 1 Mbyte 96 Kbytes 32 Kbytes 100 MHz
R5F5630BCDBG PLBG0176GA-A*11 Mbyte 96 Kbytes 32 Kbytes 100 MHz
R5F5630BDDBG PLBG0176GA-A*11 Mbyte 96 Kbytes 32 Kbytes 100 MHz
R5F5630BCDLC PTLG0177KA-A*11 Mbyte 96 Kbytes 32 Kbytes 100 MHz
R5F5630BDDLC PTLG0177KA-A*11 Mbyte 96 Kbytes 32 Kbytes 100 MHz
R5F5630DCDFP PLQP0100KB-A 1.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630DDDFP PLQP0100KB-A 1.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630DCDLB PLQP0144KA-A 1.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630DDDFB PLQP0144KA-A 1.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630DCDLK PTLG0145KA-A*11.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz
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RX630 Group 1. Overview
Note 1. In planning
RX630 R5F5630DDDLK PTLG0145KA-A*11.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630DCDFC PLQP0176KB-A 1.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630DDDFC PLQP0176KB-A 1.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630DCDBG PLBG0176GA-A*11.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630DDDBG PLBG0176GA-A*11.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630DCDLC PTLG0177KA-A*11.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630DDDLC PTLG0177KA-A*11.5 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630ECDFP PLQP0100KB-A 2 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630EDDFP PLQP0100KB-A 2 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630ECDFB PLQP0144KA-A 2 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630EDDFB PLQP0144KA-A 2 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630ECDLK PTLG0145KA-A*12 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630EDDLK PTLG0145KA-A*12 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630ECDFC PLQP0176KB-A 2 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630EDDFC PLQP0176KB-A 2 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630ECDBG PLBG0176GA-A*12 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630EDDBG PLBG0176GA-A*12 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630ECDLC PTLG0177KA-A*12 Mbytes 128 Kbytes 32 Kbytes 100 MHz
R5F5630EDDLC PTLG0177KA-A*12 Mbytes 128 Kbytes 32 Kbytes 100 MHz
Table 1.3 List of Products (2/2)
Group Part No. Package ROM Capacity RAM Capacity E2 Data Flash
Operating
Frequency
(Max.)
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RX630 Group 1. Overview
Figure 1.1 How to Read the Product Part Number
Type of memory
F: Flash memory version
Package type, number of pins, and pin pitch
FC: LQFP/176/0.50
BG: LFBGA/176/0.80
LC: TFLGA/177/0.50
FB: LQFP/144/0.50
LK: TFLGA/145/0.50
FP: LQFP/100/0.50
LA: TFLGA/100/0.50
FN: LQFP/80/0.50
ROM, RAM, and E2 data flash capacity
E: 2 Mbytes/128 Kbytes/32 Kbytes
D: 1.5 Mbytes/128 Kbytes/32 Kbytes
B: 1 Mbyte/96 Kbytes/32 Kbytes
A: 768 Kbytes/96 Kbytes/32 Kbytes
8: 512 Kbytes/64 Kbytes/32 Kbytes
7: 384 Kbytes/64 Kbytes/32 Kbytes
Group name
30: RX630 Group
Renesas MCU
Renesas semiconductor product
C: CAN module not included
D: CAN module included
Series name
RX600 Series
R 5 F 5 6 D F NC703
D: Products with wide temperature-range spec. (–40 to +85°C)
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RX630 Group 1. Overview
1.3 Block Diagram
Figure 1.2 shows a block diagram.
Figure 1.2 Block Diagram
ICUb: Interrupt control unit
DTCa: Data transfer controller
DMACA: DMA controller
BSC: Bus controller
WDTA: Watchdog timer
IWDTa: Independent watchd og time r
CRC: CRC (cyclic redundancy check) calculator
SCIc, SCId: Serial communications interface
USBa: USB 2.0 function module
RSPI: Serial peripheral interface
CAN: CAN module
MTU2a: Multi-function timer pulse unit 2
POE2a: Port output enable 2
TPUA: 16-bit timer pulse unit
PPG: Programmable pulse generator
TMR: 8-bit timer
CMT: Compare match timer
RTCa: Realtime clock
RIIC: I2C bus interface
IEB: IEBus controller
External busBSC
Operand bus
Instruction bus
Internal main bus 1
Clock
generation
circuit
RX CPU
RAM
ROM
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port A
Port B
Port C
10-bit ADC × 8 channels
12-bit ADC × 21 channels
MTU2a × 6 channels (unit 0)
10-bit DAC × 2 channels
SCIc × 12 channels
WDTA
RIIC × 4 channels
E2 DataFlash
CRC
IWDTa
USBa (1 port)
CAN × 3 channels
RTCa
POE2a
TPUa × 6 channels (unit 1)
IEB
CMT × 2 channels (unit 1)
CMT × 2 channels (unit 0)
TMR × 2 channels (unit 1)
TMR × 2 channels (unit 0)
PPG (unit 1)
PPG (unit 0)
RSPI (unit 1)
RSPI (unit 0)
Internal peripheral buses 1 to 6
Internal main bus 2
DTCa
DMACA ×
4 channels
ICUb
Temperature sensor
TPUa × 6 channels (unit 0)
RSPI (unit 2)
SCId × 1 channel
Port D
Port E
Port F
Port G
Port H
Port J
Port K
Port L
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Sep 13, 2011
RX630 Group 1. Overview
1.4 Pin Functions
Table 1.4 lists the pin functions.
Table 1.4 Pin Functi ons (1/5)
Classifications Pin Name I/O Description
Power supply VCC Input Power supply pin. Connect it to the system power supply.
VCL Input Connect this pin to VSS via a 0.1-F capacitor. The capacitor
should be placed close to the pin.
VSS Input Ground pin. Connect it to the system power supply (0 V).
VBATT Input Backup power pin
Clock XTAL Output Pins for a crystal resonator. An external clock signal can be input
through the EXTAL pin.
EXTAL Input
BCLK Output Outputs the external bus clock for external devices.
XCOUT Output Input/output pins for the sub-clock oscillator circuit. Connect a
crystal resonator between XCOUT and XCIN.
XCIN Input
Operating mode control MD Input Pins for setting the operating mode. The signal levels on these pins
must not be changed during operation.
System control RES# Input Reset signal input pin. This LSI enters the reset state when this
signal goes low.
EMLE Input Input pin for the on-chip emulator enable signal. When the on-chip
emulator is used, this pin should be driven high. When not used, it
should be driven low.
BSCANP Input Boundary scan enable pin. Boundary scan is enabled when this pin
goes high. When not used, it should be driven low.
On-chip emulator FINEC Input Fine interface clock pin
FINED I/O Fine interface pin
TRST# Input On-chip emulator or boundary scan pins. When the EMLE pin is
driven high, these pins are dedicated for the on-chip emulator.
TMS Input
TDI Input
TCK Input
TDO Output
TRCLK Output This pin outputs the clock for synchronization with the trace data.
TRSYNC# Output This pin indicates that output from the TRDATA0 to TRDATA3 pins
is valid.
TRDATA0 to TRDATA3 Output These pins output the trace information.
Address bus A0 to A23 Output Output pins for the address.
Data bus D0 to D31 I/O Input and output pins for the bidirectional data bus.
Multiplexed bus A0/D0 to A15/D15 I/O Address/data multiplexed bus
Bus control RD# Output Strobe signal which indicates that reading from the external bus
interface space is in progress.
WR# Output Strobe signal which indicates that writing to the external bus
interface space is in progress, in 1-write strobe mode.
WR0# to WR3# Output Strobe signals which indicate that either group of data bus pins (D7
to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in writing to
the external bus interface space, in byte strobe mode.
BC0# to BC3# Output Strobe signals which indicate that either group of data bus pins (D7
to D0, D15 to D8, D23 to D16 and D31 to D24) is valid in access to
the external bus interface space, in 1-write strobe mode.
ALE Output Address latch signal when address/data multiplexed bus is
selected.
WAIT# Input Input pins for wait request signals in access to the external space.
CS0# to CS7# Output Select signals for CS areas.
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Sep 13, 2011
RX630 Group 1. Overview
Interrupt NMI Input Non-maskable interrupt request signal.
IRQ0 to IRQ15 Input Maskable interrupt request signals.
Multi-function timer pulse
unit 2 MTIOC0A, MTIOC0B
MTIOC0C, MTIOC0D I/O The TGRA0 to TGRD0 input capture input/output compare output/
PWM output pins.
MTIOC1A, MTIOC1B I/O The TGRA1 and TGRB1 input capture input/output compare output/
PWM output pins.
MTIOC2A, MTIOC2B I/O The TGRA2 and TGRB2 input capture input/output compare output/
PWM output pins.
MTIOC3A, MTIOC3B
MTIOC3C, MTIOC3D I/O The TGRA3 to TGRD3 input capture input/output compare output/
PWM output pins.
MTIOC4A, MTIOC4B
MTIOC4C, MTIOC4D I/O The TGRA4 to TGRD4 input capture input/output compare output/
PWM output pins.
MTIC5U, MTIC5V
MTIC5W Input The TGRU5, TGRV5, and TGRW5 input capture input/dead time
compensation input pins.
MTCLKA, MTCLKB
MTCLKC, MTCLKD Input Input pins for external clock signals.
Port output enable 2 POE0# to POE3#
POE8# Input Input pins for request signals to place the MTU large-current pins in
the high impedance state.
16-bit timer pulse unit TIOCA0, TIOCB0
TIOCC0, TIOCD0 I/O The TGRA0 to TGRD0 input cap ture input/output compare output/
PWM output pins.
TIOCA1, TIOCB1 I/O The TGRA1 and TGRB1 input capture input/output compare output/
PWM output pins.
TIOCA2, TIOCB2 I/O The TGRA2 and TGRB2 input capture input/output compare output/
PWM output pins.
TIOCA3, TIOCB3
TIOCC3, TIOCD3 I/O The TGRA3 to TGRD3 input cap ture input/output compare output/
PWM output pins.
TIOCA4, TIOCB4 I/O The TGRA4 and TGRB4 input capture input/output compare output/
PWM output pins.
TIOCA5, TIOCB5 I/O The TGRA5 and TGRB5 input capture input/output compare output/
PWM output pins.
TCLKA, TCLKB
TCLKC, TCLKD Input Input pins for external clock signals.
TIOCA6, TIOCB6,
TIOCC6, TIOCD6 I/O The TGRA6 to TGRD6 input cap ture input/output compare output/
PWM output pins.
TIOCA7, TIOCB7 I/O The TGRA7 and TGRB7 input capture input/output compare output/
PWM output pins.
TIOCA8, TIOCB8 I/O The TGRA8 and TGRB8 input capture input/output compare output/
PWM output pins.
TIOCA9, TIOCB9,
TIOCC9, TIOCD9 I/O The TGRA9 to TGRD9 input cap ture input/output compare output/
PWM output pins.
TIOCA10, TIOCB10 I/O The TGRA10 and TGRB10 input capture input/output compare
output/PWM output pins.
TIOCA11, TIOCB11 I/O The TGRA11 and TGRB11 input capture input/output compare
output/PWM output pins.
TCLKE, TCLKF,
TCLKG, TCLKH Input Input pins for external clock signals.
Programmable pulse
generator PO0 to PO31 Output Output pins for the pulse signals.
8-bit timer TMO0 to TMO3 Output Output pins for the compare match signals.
TMCI0 to TMCI3 Input Input pins for the external clock signals that drive for the counters.
TMRI0 to TMRI3 Input Input pins for the counter-reset signals.
Table 1.4 Pin Functi ons (2/5)
Classifications Pin Name I/O Description
R01DS0060EJ0100 Rev.1.00 Page 14 of 168
Sep 13, 2011
RX630 Group 1. Overview
Serial communications
interface (SCIc) Asynchronous mode/clock synchronous mode
SCK0 to SCK11 I/O Input/output pins for clock signals.
RXD0 to RXD11 Input Input pins for data reception.
TXD0 to TXD11 Output Output pins for data transmission.
CTS0# to CTS11# Input Transfer start control input pins
RTS0# to RTS11# Output Transfer start control output pins
Simple I2C mode
SSCL0 to SSCL11 I/O Input/output pins for the I2C clock
SSDA0 to SSDA11 I/O Input/output pins for the I2C data
Simple SPI mode
SCK0 to SCK11 I/O Input/output pins for the clock
SMISO0 to SMISO11 I/O Input/output pins for slave transmit data.
SMOSI0 to SMOSI11 I/O Input/output pins for master transmit data.
SS0# to SS11# Input Input pins for chip select signals
Serial communications
interface (SCId) Asynchronous mode/clock synchronous mode
SCK12 I/O Input/output pin for clock signals.
RXD12 Input Input pin for data reception.
TXD12 Output Output pin for data transmission.
CTS12# Input Transfer start control input pins
RTS12# Output Transfer start control output pins
Simple I2C mode
SSCL12 I/O Input/output pins for the I2C clock
SSDA12 I/O Input/output pins for the I2C data
Simple SPI mode
SCK12 I/O Input/output pins for the clock
SMISO12 I/O Input/output pins for slave transmit data.
SMOSI12 I/O Input/output pins for master transmit data.
SS12# Input Input pins for chip select signals
Extended serial mode
RXDX12 Input Input pin for receive data
TXDX12 Output Output pin for transmit data
SIOX12 I/O Input/output pin for transfer data
I2C bus interface SCL0[FM+],
SCL1 to SCL3 I/O Input/output pin for clocks. Bus can be directly driven by the N-
channel open drain.
SDA0[FM+],
SDA1 to SDA3 I/O Input/output pin for data. Bus can be directly driven by the N-
channel open drain.
USB 2.0 function module VCC_USB Input Power supply pin
VSS_USB Input Ground pin
USB0_DP I/O Inputs or outputs D+ data for the USB bus
USB0_DM I/O Inputs or outputs D- data for the USB bus.
USB0_DPUPE Output Pull-up pin.
USB0_VBUS Input Input pin for detection of connection and disconnection of the USB
cable.
CAN module CRX0 to CRX2 Input Input pin.
CTX0 to CTX2 Output Output pin.
Table 1.4 Pin Functi ons (3/5)
Classifications Pin Name I/O Description
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Sep 13, 2011
RX630 Group 1. Overview
Serial peripheral interface RSPCKA, RSPCKB
RSPCKC I/O Clock input/output pin.
MOSIA, MOSIB, MOSIC I/O Inputs or outputs data output from the master.
MISOA, MISOB, MISOC I/O Inputs or outputs data output from the slave.
SSLA0, SSLB0, SSLC0 I/O Input or output pins for slave selection
SSLA1 to SSLA3
SSLB1 to SSLB3
SSLC1 to SSLC3
Output Output pins for slave selection
IEBus controller IERXD Input Input pin for data reception.
IETXD Output Output pin for data transmission.
Realtime clock RTCOUT Output Output pin for 1-Hz clock.
RTCIC0 to RTCIC2 Input Time capture event input pin
12-bit A/D converter AN000 to AN020 Input Input pins for the analog signals to be processed by the A/D
converter.
ADTRG0# Input Input pins for the external trigger signals that start the A/D
conversion.
10-bit A/D converter AN0 to AN7 Input Input pins for the analog signals to be processed by the A/D
converter.
ANEX0 Output Extended analog output pin
ANEX1 Input Extended analog input pin
ADTRG# Input Input pins for the external trigger signals that start the A/D
conversion.
D/A converter DA0, DA1 Output Output pins for the analog signals to be processed by the D/A
converter.
Analog power supply AVCC0 Input Analog voltage supply pin for the 12-bit A/D converter. Connect this
pin to VCC if the 12-bit A/D converter is not to be used.
AVSS0 Input Analog ground pin for the 12-bit A/D converter. Connect this pin to
VSS if the 12-bit A/D converter is not to be used.
VREFH0 Input Analog reference voltage supply pin for the 12-bit A/D converter.
Connect this pin to VCC if the 12-bit A/D converter is not to be used.
VREFL0 Input Analog reference ground pin for the 12-bit A/D converter. Connect
this pin to VSS if the 12-bit A/D converter is not to be used.
VREFH Input Reference voltage input pin for the 10-bit A/D converter and D/A
converter. This is used as the analog power supply for the
respective modules. Connect this pin to VCC if neither the 10-bit A/
D converter nor the D/A converter is in use.
VREFL Input Reference ground pin for the 10-bit A/D converter and D/A
converter. This is used as the analog ground for the respective
modules. Set this pin to the same potential as the VSS pin.
Table 1.4 Pin Functi ons (4/5)
Classifications Pin Name I/O Description
R01DS0060EJ0100 Rev.1.00 Page 16 of 168
Sep 13, 2011
RX630 Group 1. Overview
I/O ports P00 to P03, P05, P07 I/O 6-bit input/output pins.
P10 to P17 I/O 8-bit input/output pins.
P20 to P27 I/O 8-bit input/output pins.
P30 to P37 I/O 8-bit input/output pins. (P35 input/output pins)
P40 to P47 I/O 8-bit input/output pins.
P50 to P57 I/O 8-bit input/output pins.
P60 to P67 I/O 8-bit input/output pins.
P70 to P77 I/O 8-bit input/output pins.
P80 to P87 I/O 8-bit input/output pins.
P90 to P97 I/O 8-bit input/output pins.
PA0 to PA7 I/O 8-bit input/output pins.
PB0 to PB7 I/O 8-bit input/output pins.
PC0 to PC7 I/O 8-bit input/output pins.
PD0 to PD7 I/O 8-bit input/output pins.
PE0 to PE7 I/O 8-bit input/output pins.
PF0 to PF5 I/O 6-bit input/output pins.
PG0 to PG7 I/O 8-bit input/output pins.
PH4, PH5 I/O 2-bit input/output pins.
PJ3, PJ5 I/O 2-bit input/output pins.
PK0 to PK7 I/O 8-bit input/output pins.
PL0 to PL4 I/O 5-bit input/output pins.
Table 1.4 Pin Functi ons (5/5)
Classifications Pin Name I/O Description
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Sep 13, 2011
RX630 Group 1. Overview
1.5 Pin Assignments
Figure 1.3 to Figure 1.10 show the pin assig nm ents. Table 1.5 to Tab le 1.11 show the lists of pins and pin functions.
Figure 1.3 Pin Assignment (177-Pin TFLGA)
ABCDEFGHJKLMNPR
15 PE2 PE3 P70 P65 P67 VSS VCC PG7 PA6 PB0 P72 PB4 PL0 PL1 PC1 15
14 PE1 PE0 PK4 PE7 PG3 PA0 PA1 PA2 PA7 PK7 PB1 PB5 P73 P75 P74 14
13 P63 P64 PE4 PK5 PG2 PG4 PG6 PA3 PK6 P71 PB3 PB7 PC0 PC2 P76 13
12 P60 PK3 P62 PE5 PE6 P66 PG5 PA4 PA5 PB2 PB6 P77 PC3 PC4 P80 12
11 PD6 PG1 PK2 P61
RX630 Group
PTLG0177KA-A
(177-Pin TFLGA)
(Top View)
P81 P82 PC6 VCC 11
10 P97 PD4 PG0 PD7 PC5 PC7 P83 VSS 10
9PK0 P96 PD3 PD5 P50 P51 P52 P84 9
8P94 PD1 PD2 PK1 P53 PL2 PL3 PL4 8
7VSS P92 PD0 P95 P54 P55 VSS_
USB USB0_
DP 7
6VCC P91 P90 P93 P56 P57 VCC_
USB USB0_
DM 6
5P46 P47 P45 P44 NC P13 P12 P10 P11 5
4P42 P41 P43 P00 VSS BSCANP PF4 P35 PF3 PF1 P25 P86 P15 P14 P85 4
3VREFL0 P40 VREFH0 P03 PF5 PJ3 MD RES# P34 PF2 PF0 P24 P22 P87 P16 3
2AVCC0 P07 VREFH P02 EMLE VCL XCOUT VSS VCC P32 P30 P26 P23 P17 P20 2
1AVSS P05 VREFL P01 PJ5 VBATT XCIN XTAL EXTAL P33 P31 P27 PH5 PH4 P21 1
ABCDEFGHJKLMNPR
R01DS0060EJ0100 Rev.1.00 Page 18 of 168
Sep 13, 2011
RX630 Group 1. Overview
Figure 1.4 Pin Assignment (176-Pin LFBGA)
ABCDEFGHJKLMNPR
15 PE2 PE3 P70 P65 P67 VSS VCC PG7 PA6 PB0 P72 PB4 PL0 PL1 PC1 15
14 PE1 PE0 PK4 PE7 PG3 PA0 PA1 PA2 PA7 PK7 PB1 PB5 P73 P75 P74 14
13 P63 P64 PE4 PK5 PG2 PG4 PG6 PA3 PK6 P71 PB3 PB7 PC0 PC2 P76 13
12 P60 PK3 P62 PE5 PE6 P66 PG5 PA4 PA5 PB2 PB6 P77 PC3 PC4 P80 12
11 PD6 PG1 PK2 P61
RX630 Group
PLBG0176GA-A
(176-Pin LFBGA)
(Top View)
P81 P82 PC6 VCC 11
10 P97 PD4 PG0 PD7 PC5 PC7 P83 VSS 10
9PK0 P96 PD3 PD5 P50 P51 P52 P84 9
8P94 PD1 PD2 PK1 P53 PL2 PL3 PL4 8
7VSS P92 PD0 P95 P54 P55 VSS_
USB USB0_
DP 7
6VCC P91 P90 P93 P56 P57 VCC_
USB USB0_
DM 6
5P46 P47 P45 P44 P13 P12 P10 P11 5
4P42 P41 P43 P00 VSS BSCANP PF4 P35 PF3 PF1 P25 P86 P15 P14 P85 4
3VREFL0 P40 VREFH0 P03 PF5 PJ3 MD RES# P34 PF2 PF0 P24 P22 P87 P16 3
2AVCC0 P07 VREFH P02 EMLE VCL XCOUT VSS VCC P32 P30 P26 P23 P17 P20 2
1AVSS P05 VREFL P01 PJ5 VBATT XCIN XTAL EXTAL P33 P31 P27 PH5 PH4 P21 1
ABCDEFGHJKLMNPR