LTM2892 SPI/Digital or I2C Module Isolator Features Description 6-Channel Logic Isolator: 3500VRMS for 1 Minute nn UL-CSA Recognized File #E151738 nn 3V to 5.5V Supply Operation nn No External Components Required nn SPI/Digital (LTM2892-S) or I2C (LTM2892-I) Options nn High Common Mode Transient Immunity: 50kV/s nn High Speed Operation: nn 10MHz Digital Isolation nn 4MHz/8MHz SPI Isolation nn 400kHz I2C Isolation nn Operation Up to 125C (H-Grade) nn 1.62V to 5.5V Logic Supplies for Flexible Digital Interfacing nn 15kV ESD HBM Across the Isolation Barrier nn Maximum Continuous Working Voltage: 850V PEAK nn Low Current Shutdown Mode (<10A) nn Small (9mm x 6.25mm x 2.91mm) BGA Package The LTM(R)2892 is a complete galvanic digital Module(R) (micromodule) isolator. No external components are required. Individual 3V to 5.5V supplies power each side of the digital isolator. Separate logic supply pins allow easy interfacing with different logic levels from 1.62V to 5.5V, independent of the main supply. nn Module options are available with compatibility to SPI (LTM2892-S) and I2C (LTM2892-I), master mode only, specifications. Coupled inductors provide 3500VRMS of isolation between the input and output logic interface. This device is ideal for systems where the ground loop is broken, allowing uninterrupted communication through large common mode transients faster than 50kV/s. L, LT, LTC, LTM, Linear Technology, the Linear logo and Module are registered trademarks and HotSwap is a trademark of of Linear Technology Corporation. All other trademarks are the property of their respective owners. Applications Isolated SPI or I2C Interfaces nn Industrial Systems nn Test and Measurement Equipment nn Breaking Ground Loops nn Typical Application Isolated 4MHz SPI Interface SCK MOSI SS MISO VCC1 VL1 ON1 EOUTD INA INB INC LTM2892-S OUTD OUTE OUTF GND1 ISOLATION BARRIER 3V TO 5.5V LTM2892 Operating Through 50kV/s CM Transients VCC2 VL2 ON2 EOUTA OUTA OUTB OUTC IND INE INF GND2 3V TO 5.5V INA 5V/DIV 5V/DIV OUTD SCK MOSI SS MISO GND2-GND1 200V/ DIV 20ns/DIV OUTA CONNECTED TO IND 2892 TA01b 2892 TA01a 2892fa For more information www.linear.com/LTM2892 1 LTM2892 Absolute Maximum Ratings (Note 1) VCC1 to GND1................................................ -0.3V to 6V VL1 to GND1.................................................. -0.3V to 6V VCC2 to GND2................................................ -0.3V to 6V VL2 to GND2.................................................. -0.3V to 6V Logic Inputs INA, INB, INC, SCLIN, SDA1, EOUTD, ON1 to GND1............................. -0.3V to (VL1 + 0.3V) INB, INC, IND, INE, INF, SDA2, EOUTA, ON2 to GND2.............................-0.3V to (VL2 + 0.3V) Logic Outputs OUTB, OUTC, OUTD, OUTE, OUTF to GND1.......................... - 0.3V to (VL1 + 0.3V) OUTA, OUTB, OUTC, SCLOUT to GND2...................... - 0.3V to (VL2 + 0.3V) Operating Temperature Range (Note 4) LTM2892C................................................ 0C to 70C LTM2892I.............................................-40C to 85C LTM2892H.......................................... -40C to 125C Maximum Internal Operating Temperature............. 125C Storage Temperature Range................... -55C to 150C Peak Body Reflow Temperature............................. 260C Pin Configuration LTM2892-I LTM2892-S TOP VIEW TOP VIEW 1 2 SCLIN SDA1 3 4 5 6 1 2 3 4 5 6 INA ON1 VL1 VCC1 INA INB INC ON1 VL1 VCC1 A A B C B OUTB SDA1 OUTC GND1 C D D E E F F G OUTF EOUTD GND1 OUTB OUTC EOUTA GND2 G SCLOUT SDA2 OUTA GND2 OUTA H H J J INB SDA2 INC ON2 VL2 VCC2 IND BGA PACKAGE 24-PIN (9mm x 6.25mm x 2.91mm) INE INF ON2 VL2 VCC2 BGA PACKAGE 24-PIN (9mm x 6.25mm x 2.91mm) TJMAX = 125C, JA = 30C/W, JC(bottom) = 15.7C/W, JC(top) = 25C/W, JB = 14.5C/W VALUES DETERMINED PER JESD 51-9, WEIGHT = 0.3g 2 OUTD OUTE TJMAX = 125C, JA = 30C/W, JC(bottom) = 15.7C/W, JC(top) = 25C/W, JB = 14.5C/W VALUES DETERMINED PER JESD 51-9, WEIGHT = 0.3g 2892fa For more information www.linear.com/LTM2892 LTM2892 Order Information http://www.linear.com/product/LTM2892#orderinfo LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTM2892CY-I#PBF LTM2892CY-I#PBF LTM2892Y-I 24-Lead (9mm x 6.25mm x 2.91mm) BGA 0C to 70C LTM2892IY-I#PBF LTM2892IY-I#PBF LTM2892Y-I 24-Lead (9mm x 6.25mm x 2.91mm) BGA -40C to 85C LTM2892HY-I#PBF LTM2892HY-I#PBF LTM2892Y-I 24-Lead (9mm x 6.25mm x 2.91mm) BGA -40C to 125C LTM2892CY-S#PBF LTM2892CY-S#PBF LTM2892Y-S 24-Lead (9mm x 6.25mm x 2.91mm) BGA 0C to 70C LTM2892IY-S#PBF LTM2892IY-S#PBF LTM2892Y-S 24-Lead (9mm x 6.25mm x 2.91mm) BGA -40C to 85C LTM2892HY-S#PBF LTM2892HY-S#PBF LTM2892Y-S 24-Lead (9mm x 6.25mm x 2.91mm) BGA -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ This product is moisture sensitive. For more information go to: http://www.linear.com/packaging/ Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2 unless otherwise noted. Specifications apply to all options unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Power Supplies VCC1, VCC2 Input Supply Range l 3 5.5 V VL1, VL2 Logic Supply Range LTM2892-S LTM2892-I l l 1.62 3 5.5 5.5 V V ICC1, ICC2 Input Supply Current ON1 = ON2 = 0V ON1 = VL1, ON2 = VL2 l l 0 3.2 10 4.5 A mA IL1, IL2 Logic Supply Current ON1 = ON2 = 0V LTM2892-S, ON1 = VL1, ON2 = VL2 IL1, LTM2892-I, ON1 = VL1, ON2 = VL2 IL2, LTM2892-I, ON1 = VL1, ON2 = VL2 l l 0 10 10 150 300 A A A A ON1, INx, EOUTD, 1.62V VL1 < 2.35V ON1, INx, EOUTD, 2.35V VL1 ON2, INx, EOUTA, 1.62V VL2 < 2.35V ON2, INx, EOUTA, 2.35V VL2 l l l l 0.75*VL1 0.67*VL1 0.75*VL2 0.67*VL2 V V V V 1 A Logic/SPI VITH Input Threshold Voltage IINL Input Current VHYS Input Hysteresis (Note 2) VOH Output High Voltage OUTx, ILOAD = -1mA, 1.62V VL1 < 3V OUTx, ILOAD = -4mA, 3V VL1 5.5V OUTB (LTM2892-I), ILOAD = -2mA, 3V VL1 5.5V l VL1 - 0.4 V OUTx, ILOAD = -1mA, 1.62V VL2 < 3V OUTx, ILOAD = -4mA, 3V VL2 5.5V l VL2 - 0.4 V 0.25*VL1 0.33*VL1 0.25*VL2 0.33*VL2 l 150 mV 2892fa For more information www.linear.com/LTM2892 3 LTM2892 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2 unless otherwise noted. Specifications apply to all options unless otherwise noted. SYMBOL PARAMETER CONDITIONS VOL Output Low Voltage OUTx, ILOAD = 1mA, 1.62V VL1 < 3V OUTx, ILOAD = 4mA, 3V VL1 5.5V OUTB (LTM2892-I), ILOAD = 2mA, 3V VL1 5.5V l 0.4 V OUTx, ILOAD = 1mA, 1.62V VL2 < 3V OUTx, ILOAD = 4mA, 3V VL2 5.5V l 0.4 V 0V OUTx VL1 0V OUTB (LTM2892-I) VL1 0V OUTx VL2 l 85 l 85 mA mA mA 0.3*VL1 0.3*VL2 ISC Short-Circuit Current MIN TYP 30 MAX UNITS I 2C VIL Low Level Input Voltage SCLIN, SDA1 SDA2 l l VIH High Level Input Voltage SCLIN, SDA1 SDA2 l l IINL Input Current SCLIN, SDA1 = VL1 or 0V SDA2 = VL2, SDA2 = VL2 = 0V l l VHYS Input Hysteresis SCLIN, SDA1 SDA2 VOH Output High Voltage SCLOUT, ILOAD = -2mA l VOL Output Low Voltage SDA1, ILOAD = 3mA, SCLOUT, ILOAD = 2mA SDA2 = No Load, SDA1 = 0V, 4.5V VL2 < 5.5V SDA2 = No Load, SDA1 = 0V, 3V VL2 < 4.5V l l l 0.7*VL1 0.7*VL2 V V V V 1 1 0.05*VL1 0.05*VL2 A A mV mV VL2 - 0.4 V 0.3 0.4 0.45 0.55 V V V CIN Input Pin Capacitance SCLIN, SDA1, SDA2 (Note 2) l 10 pF CB Bus Capacitive Load SCLOUT, Standard Speed (Note 2) SCLOUT, Fast Speed SDA1, SDA2, SR 1V/s, Standard Speed (Note 2) SDA1, SDA2, SR 1V/s, Fast Speed l l l l 400 200 400 200 pF pF pF pF SDA, SDA2 Slew Rate ISC Short-Circuit Current l SDA2 = 0, SDA1 = VL1 0V SCLOUT VL2 SDA1 = 0, SDA2 = VL2 SDA1 = VL1, SDA2 = 0 1 V/s l 30 6 -1.8 100 mA mA mA mA ESD (HBM) (Note 2) Isolation Boundary 4 GND2 to GND1 (VCC2, VL2, GND2) to (VCC1, VL1, GND1) 15 10 kV kV 2892fa For more information www.linear.com/LTM2892 LTM2892 Switching Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2 unless otherwise noted. Specifications apply to all options unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN Maximum Data Rate INx OUTx, CL = 15pF (Note 3) Bidirectional SPI Communication Unidirectional SPI Communication l l l 10 4 8 tPHL, tPLH Propagation Delay INx OUTx, CL = 15pF (Figure 1) l 35 tR, tF Rise and Fall Time OUTx, CL = 15pF (Figure 1) LTM2892-I, OUTB, CL = 15pF (Figure 1) l l tPWU Output Pulse Width Uncertainty OUTB, OUTC, OUTE, OUTF (Note 2) tPZH, tPZL Output Enable Time EOUTx = to OUTx, RL = 1k, CL = 15pF (Figure 2) tPHZ, tPLZ Output Disable Time EOUTx = to OUTx, RL = 1k, CL = 15pF (Figure 2) tPZH, tPZL ONx Enable Time tPHZ, tPLZ TYP MAX UNITS Logic/SPI MHz MHz MHz 60 100 ns 3 20 12.5 35 ns ns 50 ns l 50 ns l 50 ns ONx = to OUTx, RL = 1k, CL = 15pF (Figure 4) l 60 s ONx Disable Time ONx = to OUTx, RL = 1k, CL = 15pF (Figure 4) l 50 ns Maximum Data Rate (Note 3) l tPHL, tPLH Propagation Delay SCLIN SCLOUT, CL = 15pF (Figure 1) SDA1 SDA2, RL = Open, CL = 15pF (Figure 3) SDA2 SDA1, RL = 1.1k, CL = 15pF (Figure 3) l l l tR Rise Time SDA2, CL = 200pF (Figure 3) SDA2, CL = 200pF (Figure 3) SDA1, RL = 1.1k, CL = 200pF (Figure 3) SCLOUT, CL = 200pF (Figure 3) l l l l -20 I2C tF Fall Time SDA2, CL = 200pF (Figure 3) SDA1, RL = 1.1k, CL = 200pF (Figure 3) SCLOUT, CL = 200pF (Figure 3) tPWU Output Pulse Width Uncertainty SDA1, SDA2 (Note 2) tPZH, tPZL ONx Enable Time tPHZ, tPLZ ONx Disable Time tSP Pulse Width of Spikes Suppressed by Input Filter l l 400 kHz 150 150 300 225 250 500 ns ns ns 40 40 40 300 250 250 250 ns ns ns ns 40 40 250 250 250 ns ns ns -20 50 ns ON1 = to SDA1, RL = 1k, CL = 15pF (Figure 4) ON2 = to (SCLOUT, SDA2), CL = 15pF (Figure 4) l l 60 s ON1 = to SDA1, RL = 1k, CL = 15pF (Figure 4) ON2 = to SCLOUT, RL = 1k, CL = 15pF (Figure 4) ON2 = to SDA2, RL = Open, CL = 15pF (Figure 4) l l l 50 50 225 ns ns ns 50 ns l 0 2892fa For more information www.linear.com/LTM2892 5 LTM2892 Isolation Characteristics TA = 25C SYMBOL PARAMETER CONDITIONS MIN VISO Rated Dielectric Insulation Voltage 1 Minute, Derived from 1 Second Test 1 Second (Notes 5, 6) 3500 4200 VRMS VRMS Common Mode Transient Immunity VCC1 = VL1 = ON1 = 5V, VCC2 = VL2 = ON2 = 5V VCM = 1kV, t = 20ns (Note 2) 50 kV/s VIORM Maximum Continuous Working Voltage (Notes 2, 5) 850 600 VPEAK VRMS Partial Discharge VPD = 1590VPEAK (Note 5) CTI Comparative Tracking Index IEC 60112 (Note 2) Depth of Erosion IEC 60112 (Note 2) Distance Through Insulation (Note 2) DTI Input to Output Resistance MAX 5 600 UNITS pC VRMS 0.1 0.1 1012 (Notes 2, 5) mm mm Input to Output Capacitance (Notes 2, 5) 3 pF Creepage Distance (Note 2) 5 mm Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Guaranteed by design and not subject to production test. Note 3: Maximum data rate is guaranteed by other measured parameters and is not tested directly. 6 TYP Note 4: This Module isolator includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above specified maximum operating junction temperature may result in device degradation or failure. Note 5: Device is considered a 2-terminal device. Pin group A1 through B6 shorted together and pin group H1 through J6 shorted together. Note 6: The rated dielectric insulation voltage should not be interpreted as a continuous voltage rating. 2892fa For more information www.linear.com/LTM2892 LTM2892 Typical Performance Characteristics TA = 25C, VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2, unless otherwise noted. VCCx and VLx Supply Current vs Temperature 3.2 3.0 2.8 VCC1 = VL1 = 3.3V VCC2 = VL2 = 3.3V VCC1 = VL1 = 5V VCC2 = VL2 = 5V 2.6 2.4 -50 3.2 3.0 2.8 VCC1 = 3.3V VCC2 = 3.3V VCC1 = 5V VCC2 = 5V 2.6 0 50 25 75 TEMPERATURE (C) -25 100 2.4 -50 125 0 50 25 75 TEMPERATURE (C) -25 Logic Input Threshold vs VLx Supply Voltage OUTPUT VOLTAGE (V) INPUT FALLING 1 2 3 4 5 VLx SUPPLY VOLTAGE (V) 2 SUPPLY CURRENT (mA) OUTPUT VOLTAGE (V) 0.4 VL2 = 3.3V VL2 = 5V -25 25 75 0 50 TEMPERATURE (C) 100 0.2 0.1 0 1 2 3 4 5 6 7 8 |LOAD CURRENT| (mA) 9 0 -50 10 125 2892 G07 VL1 = 3.3V VL1 = 5V -25 25 75 0 50 TEMPERATURE (C) 125 Supply Current vs INA to OUTA Data Rate 16 LTM2892-S 14 VCC1 = VL1 = 3.3V VCC2 = VL2 = 3.3V ICC1, OUTA = ANY LOAD 12 ICC2 , OUTA = ANY LOAD IL2, OUTA = NO LOAD 10 IL2, OUTA = 100pF LOAD 8 6 4 LTM2892-S 14 VCC1 = VL1 = 3.3V VCC2 = VL2 = 5V ICC1, OUTA = ANY LOAD 12 ICC2 , OUTA = ANY LOAD IL2, OUTA = NO LOAD 10 IL2, OUTA = 100pF LOAD 8 6 4 2 2 0 100 2892 G06 16 LTM2892-I 0 -50 0.3 Supply Current vs INA to OUTA Data Rate 0.1 LTM2892-I SDA1 RPU = 1.1k 2892 G05 SDA2 Low Level Output Voltage vs Temperature 125 100 0.4 3 2892 G04 0.2 25 75 0 50 TEMPERATURE (C) SDA1 Low Level Output Voltage vs Temperature VLx = 5.5V VLx = 3.3V VLx = 1.62V 4 0 6 0.3 -25 2892 G03 1 0.5 0.5 100 -50 125 SUPPLY CURRENT (mA) THRESHOLD VOLTAGE (V) INPUT RISING 1.0 0 100 0.5 5 1.5 150 6 2.0 VL1 = 3.3V VL2 = 3.3V VL1 = 5V VL2 = 5V 200 Logic Output Voltage vs Load Current 3.0 2.5 250 2892 G02 2892 G01 3.5 LTM2892-I NO LOAD, REFRESH DATA ONLY 300 3.4 SUPPLY CURRENT (A) 3.4 350 LTM2892-I NO LOAD, REFRESH DATA ONLY 3.6 SUPPLY CURRENT (mA) 3.6 SUPPLY CURRENT (mA) 3.8 LTM2892-S NO LOAD, REFRESH DATA ONLY VLx Supply Current vs Temperature OUTPUT VOLTAGE (V) 3.8 VCCx Supply Current vs Temperature 1 10 1000 100 FREQUENCY (kHz) 10000 2892 G08 0 1 10 1000 100 FREQUENCY (kHz) 10000 2892 G09 2892fa For more information www.linear.com/LTM2892 7 LTM2892 Typical Performance Characteristics TA = 25C, VCC1 = 5V, VCC2 = 5V, VL1 = 3.3V, VL2 = 3.3V, GND1 = GND2 = 0V, ON1 = VL1, and ON2 = VL2, unless otherwise noted. Supply Current vs INA to OUTA Data Rate Supply Current vs INA to OUTA Data Rate 16 6 4 6 4 2 2 0 0 10 1000 100 FREQUENCY (kHz) 10000 8 6 1 10 1000 100 FREQUENCY (kHz) 0 10000 SUPPLY CURRENT (mA) 6 LTM2892-S 18 VCC1 = VL1 = 5V VCC2 = VL2 = 5V 16 ICC1 OR ICC2, ANY LOAD, 14 ALL CHANNELS IL1 OR IL2 , NO LOAD, 12 EACH CHANNEL IL1 OR IL2 , 100pF LOAD, 10 ALL CHANNELS 8 6 4 4 2 2 2 0 0 10 1000 100 FREQUENCY (kHz) 10000 2892 G13 1 10 1000 100 FREQUENCY (kHz) 10000 20 LTM2892-S 18 VCC1 = VL1 = 5V VCC2 = VL2 = 3.3V 16 ICC1 OR ICC2, ANY LOAD, 14 ALL CHANNELS IL1, NO LOAD, EACH CHANNEL 12 IL2, NO LOAD, EACH CHANNEL IL1, 100pF LOAD, ALL CHANNELS 10 IL2, 100pF LOAD, ALL CHANNELS 8 4 1 1000 100 FREQUENCY (kHz) Supply Current vs Data Rate, All Channels 20 20 6 10 2892 G12 Supply Current vs Data Rate, All Channels LTM2892-S 18 VCC1 = VL1 = 3.3V VCC2 = VL2 = 5V 16 ICC1 OR ICC2, ANY LOAD, 14 ALL CHANNELS IL1, NO LOAD, EACH CHANNEL 12 IL2, NO LOAD, EACH CHANNEL IL1, 100pF LOAD, ALL CHANNELS 10 IL2, 100pF LOAD, ALL CHANNELS 8 1 2892 G11 Supply Current vs Data Rate, All Channels SUPPLY CURRENT (mA) 10 2 2892 G10 8 LTM2892-S 18 VCC1 = VL1 = 3.3V VCC2 = VL2 = 3.3V 16 ICC1 OR ICC2, ANY LOAD ALL CHANNELS 14 IL1 OR IL2 , NO LOAD EACH CHANNEL IL1 OR IL2 , 100pF LOAD ALL CHANNELS 12 4 SUPPLY CURRENT (mA) 1 20 LTM2892-S 14 VCC1 = VL1 = 5V VCC2 = VL2 = 5V ICC1, OUTA = ANY LOAD 12 ICC2 , OUTA = ANY LOAD IL2, OUTA = NO LOAD 10 IL2, OUTA = 100pF LOAD 8 SUPPLY CURRENT (mA) LTM2892-S 14 VCC1 = VL1 = 5V VCC2 = VL2 = 3.3V ICC1, OUTA = ANY LOAD 12 ICC2 , OUTA = ANY LOAD IL2, OUTA = NO LOAD 10 IL2, OUTA = 100pF LOAD 8 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 16 Supply Current vs Data Rate, All Channels 10000 2892 G14 0 1 10 1000 100 FREQUENCY (kHz) 10000 2892 G15 2892fa For more information www.linear.com/LTM2892 LTM2892 Pin Functions (LTM2892-I) Logic Side Isolated Side SCLIN (A1): Serial I2C Clock Input, Referenced to VL1 and GND1. Logic input connected to isolated side SCLOUT pin through the isolation barrier. Clock is unidirectional from logic to isolated side. Pull up to VL1 if not used. SCLOUT (H1): Serial I2C Clock Output, Referenced to VL2 and GND2. Logic output connected to logic side SCLIN pin through the isolation barrier. Clock is unidirectional from logic to isolated side. SCLOUT has a push-pull output stage; do not connect an external pull-up device. Under the condition of an isolation communication failure this output defaults to a high state. SDA1 (A2, B2): Serial I2C Data Pins, Referenced to VL1 and GND1. Bidirectional logic pins connected to isolated side SDA2 pins through the isolation barrier. Under the condition of an isolation communication failure pins are in a high impedance state. Pins connected internally. Pull up to VL1 if not used. INA (A3): Digital Input, Referenced to VL1 and GND1. Logic input connected to OUTA through the isolation barrier. The logic state on INA translates to the same logic state on OUTA. Connect to GND1 or VL1 if not used. ON1 (A4): Enable, Referenced to VL1 and GND1. Enables data communication through the isolation barrier. If ON1 is high the part is enabled and communications are functional to the isolated side. If ON1 is low the logic side is held in reset, all digital outputs are in a high impedance state. Connect to VL1 if not driven. VL1 (A5): Logic Supply. Interface supply voltage for pins SCLIN, INA, OUTB, OUTC, and ON1. Operating voltage is 3V to 5.5V. Internally bypassed with 0.22F. VCC1 (A6): Supply Voltage. Operating voltage is 3V to 5.5V. Internally bypassed with 1.0F. OUTB (B1): Digital Output, Referenced to VL1 and GND1. Logic output connected to INB through the isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. OUTC (B3): Digital Output, Referenced to VL1 and GND1. Logic output connected to INC through the isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. GND1 (B4 to B6): Circuit Ground. SDA2 (H2, J2): Serial I2C Data Pins, Referenced to VL2 and GND2. Bidirectional logic pins connected to logic side SDA1 pins through the isolation barrier. Output is biased high by a 1.8mA current source. Do not connect an external pull-up device to SDA2. Under the condition of an isolation communication failure outputs default to a high state. Pins connected internally. OUTA (H3): Digital Output, Referenced to VL2 and GND2. Logic output connected to INA through the isolation barrier. Under the condition of an isolation communication failure OUTA defaults to a high state. GND2 (H3 to H5): Isolated Ground. INB (J1): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTB through the isolation barrier. The logic state on INB translates to the same logic state on OUTB. Connect to GND2 or VL2 if not used. INC (J3): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTC through the isolation barrier. The logic state on INC translates to the same logic state on OUTC. Connect to GND2 or VL2 if not used. ON2 (J4): Enable, Referenced to VL2 and GND2. Enables data communication through the isolation barrier. If ON2 is high the part is enabled and communications are functional to the logic side. If ON2 is low the isolated side is held in reset, all digital outputs are in a high state. Connect to VL2 if not driven. VL2 (J5): Logic Supply, Referred to GND2. Interface supply voltage for pins SCLOUT, SDA2, INB, INC, OUTA, and ON2. Operating voltage is 3V to 5.5V. Internally bypassed with 0.22F. VCC2 (J6): Supply Voltage, Referred to GND2. Operating voltage is 3V to 5.5V. Internally bypassed with 1.0F. 2892fa For more information www.linear.com/LTM2892 9 LTM2892 Pin Functions (LTM2892-S) Logic Side Isolated Side INA (A1): Digital Input, Referenced to VL1 and GND1. Logic input connected to OUTA through the isolation barrier. The logic state on INA translates to the same logic state on OUTA. Connect to GND1 or VL1 if not used. OUTA (H1): Digital Output, Referenced to VL2 and GND2. Logic output connected to INA through the isolation barrier. Under the condition of an isolation communication failure OUTA defaults to a low state. INB (A2): Digital Input, Referenced to VL1 and GND1. Logic input connected to OUTB through the isolation barrier. The logic state on INB translates to the same logic state on OUTB. Connect to GND1 or VL1 if not used. OUTB (H2): Digital Output, Referenced to VL2 and GND2. Logic output connected to INB through the isolation barrier. Under the condition of an isolation communication failure OUTB defaults to a low state. INC (A3): Digital Input, Referenced to VL1 and GND1. Logic input connected to OUTC through the isolation barrier. The logic state on INC translates to the same logic state on OUTC. Connect to GND1 or VL1 if not used. OUTC (H3): Digital Output, Referenced to VL2 and GND2. Logic output connected to INC through the isolation barrier. Under the condition of an isolation communication failure OUTC defaults to a high state. ON1 (A4): Enable, Referenced to VL1 and GND1. Enables data communication through the isolation barrier. If ON1 is high the part is enabled and communications are functional to the isolated side. If ON1 is low the logic side is held in reset, all digital outputs are in a high impedance state. Connect to VL1 if not driven. EOUTA (H4): Digital Output Enable, Referenced to VL2 and GND2. A logic high on EOUTA places the logic side OUTA pin in a high impedance state, a logic low enables the output. Connect to GND2 or VL2 if not used. VL1 (A5): Logic Supply. Interface supply voltage for pins INA, INB, INC, OUTD, OUTE, OUTF, EOUTD, and ON1. Operating voltage is 1.62V to 5.5V. Internally bypassed with 0.22F. VCC1 (A6): Supply Voltage. Operating voltage is 3V to 5.5V. Internally bypassed with 1.0F. OUTD (B1): Digital Output, Referenced to VL1 and GND1. Logic output connected to IND through the isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. OUTE (B2): Digital Output, Referenced to VL1 and GND1. Logic output connected to INE through the isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. OUTF (B3): Digital Output, Referenced to VL1 and GND1. Logic output connected to INF through the isolation barrier. Under the condition of an isolation communication failure this output is in a high impedance state. EOUTD (B4): Digital Output Enable, Referenced to VL1 and GND1. A logic high on EOUTD places the logic side OUTD pin in a high impedance state, a logic low enables the output. Connect to GND1 or VL1 if not used. GND1 (B5, B6): Circuit Ground. 10 GND2 (H5, H6): Isolated Ground. IND (J1): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTD through the isolation barrier. The logic state on IND translates to the same logic state on OUTD. Connect to GND2 or VL2 if not used. INE (J2): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTE through the isolation barrier. The logic state on INE translates to the same logic state on OUTE. Connect to GND2 or VL2 if not used. INF (J3): Digital Input, Referenced to VL2 and GND2. Logic input connected to OUTF through the isolation barrier. The logic state on INF translates to the same logic state on OUTF. Connect to GND2 or VL2 if not used. ON2 (J4): Enable, Referenced to VL2 and GND2. Enables data communication through the isolation barrier. If ON2 is high the part is enabled and communications are functional to the logic side. If ON2 is low the isolated side is held in reset, OUTA and OUTB are in a low state, and OUTC is in a high state. Connect to VL2 if not driven. VL2 (J5): Logic Supply, Referred to GND2. Interface supply voltage for pins OUTA, OUTB, OUTC, IND, INE, INF, EOUTA, and ON2. Operating voltage is 1.62V to 5.5V. Internally bypassed with 0.22F. VCC2 (J6): Supply Voltage, Referred to GND2. Operating voltage is 3V to 5.5V. Internally bypassed with 1.0F. 2892fa For more information www.linear.com/LTM2892 LTM2892 Block Diagrams LTM2892-I VCC1 VCC2 VL1 1F 1F 0.22F VL2 0.22F GND2 GND1 ON1 ON2 SDA1 SDA2 INA OUTB SDA1 ISOLATED COMMUNICATIONS INTERFACE SCLOUT ISOLATED COMMUNICATIONS INTERFACE SCLIN OUTC OUTA INB SDA2 INC 2892 BD1 LTM2892-I 2892fa For more information www.linear.com/LTM2892 11 LTM2892 Block Diagrams LTM2892-S VCC1 VCC2 VL1 1F 1F 0.22F VL2 0.22F GND2 GND1 ON1 ON2 EOUTA EOUTD INB OUTB INC OUTD OUTE ISOLATED COMMUNICATIONS INTERFACE OUTA ISOLATED COMMUNICATIONS INTERFACE INA OUTF OUTC IND INE INF 2892 BD2 LTM2892-S 12 2892fa For more information www.linear.com/LTM2892 LTM2892 Test Circuits INx 0V OUTPUT CL INx VL1 OUTx CL INx OUTx 90% tPHL 10% 1/2VL2 10% 90% tR tF VL2 0V OUTx tPLH VOH VOL INx 1/2VL1 1/2VL2 tPLH VOH VOL 90% tPHL 10% 1/2VL1 10% 90% tR tF 2892 F01 Figure 1. Logic Timing Measurements VL2 OR 0V VL2 EOUTA RL OUTA INA CL 1/2VL2 0V OUTA EOUTA OUTA tPZH VOH VOH - 0.5V 1/2VL2 0V VL2 tPZL tPLZ 1/2VL2 VOL VL1 OR 0V tPHZ VOL + 0.5V VL1 EOUTD RL 1/2VL1 0V IND OUTD CL OUTD EOUTD OUTD tPZH VOH 0V VL1 VOL tPHZ VOH - 0.5V 1/2VL1 tPZL 1/2VL1 tPLZ VOL + 0.5V 2892 F02 Figure 2. Logic Enable/Disable Time 2892fa For more information www.linear.com/LTM2892 13 LTM2892 Test Circuits VL1 RL SDA1 1/2VL1 0V SDA2 CL SDA1 VL1 SDA2 tPHL VOH VOL 1/2VL2 tPLH 30% 70% 70% 30% tF tR VL1 RL SDA2 VL2 1/2VL2 0V SDA1 CL SDA2 SDA1 tPHL VOH VOL 1/2VL1 tPLH 70% 30% 70% 30% tF tR 2892 F03 Figure 3. I2C Timing Measurements VL2 OR 0V VL2 ON2 RL INx 0V OUTx CL OUTx ON2 OUTx 1/2VL2 tPZH VOH VOH - 0.5V 1/2VL2 0V VL2 tPZL tPLZ 1/2VL2 VOL VL1 OR 0V tPHZ VOL + 0.5V VL1 ON1 RL 1/2VL1 0V INx OUTx CL OUTx ON1 OUTx tPZH VOH 0V VL1 VOL tPHZ VOH - 0.5V 1/2VL1 tPZL 1/2VL1 tPLZ VOL + 0.5V 2892 F04 Figure 4. ONx Enable/Disable Time 14 2892fa For more information www.linear.com/LTM2892 LTM2892 Applications Information Overview Logic Supplies (VL1, VL2) The LTM2892 digital Module isolator provides a galvanically-isolated robust logic interface, complete with decoupling capacitors. The LTM2892 is ideal for use in networks where grounds can take on different voltages. Isolation in the LTM2892 blocks high voltage differences and eliminates ground loops, and is extremely tolerant of common mode transients between ground planes. Errorfree operation is maintained through common mode events as fast as 50kV/s providing excellent noise isolation. Separate logic supply pins, VL1 and VL2, allow the LTM2892 to interface with any logic signal from 1.62V to 5.5V for the SPI version and 3V to 5.5V for the I2C version, as shown in Figure 5. Simply connect the desired logic supplies to VL1 and VL2. There is no interdependency between VCC1, VCC2, VL1, and VL2; they may simultaneously operate at any voltage within their specified operating ranges and sequence in any order. VL1 and VL2 are bypassed internally by 0.22F capacitors. Input Supplies (VCC1, VCC2) Hot Plugging Safely The LTM2892 is powered by 3V to 5.5V supplies on each side of the isolation interface. The input supplies provide power to the internal isolated communications interface and are completely independent of the logic power supplies. VCC1 and VCC2 are each bypassed with 1.0F ceramic capacitors. Caution must be exercised in applications where power is plugged into the LTM2892's power supplies, VCC1, VCC2, VL1, or VL2 due to the integrated ceramic decoupling capacitors. The parasitic cable inductance along with the high Q characteristics of ceramic capacitors can cause substantial ringing which could exceed the maximum voltage ratings and damage the LTM2892. Refer to Application Note 88, entitled "Ceramic Input Capacitors Can Cause Overvoltage Transients" for a detailed discussion and mitigation of this phenomenon. 3V TO 5.5V EXTERNAL DEVICE SCK MOSI SS MISO VCC1 VL1 ON1 EOUTD INA INB INC LTM2892-S OUTD OUTE OUTF GND1 ISOLATION BARRIER 1.62V TO 5.5V 3V TO 5.5V VCC2 VL2 ON2 EOUTA OUTA OUTB OUTC IND INE INF 1.62V TO 5.5V EXTERNAL DEVICE SCK MOSI SS MISO GND2 2892 F05 Figure 5. Supplies Are Independent 2892fa For more information www.linear.com/LTM2892 15 LTM2892 Applications Information Channel Timing Uncertainty Multiple channels are supported across the isolation boundary by encoding and decoding of the inputs and outputs. Up to three signals in each direction are assembled as serial packets and transferred across the isolation barrier. The time required to transfer all three bits is 100ns maximum, and sets the limit for how often a signal can change on the opposite side of the barrier. Encoding and transmission is independent for each data direction. The technique used assigns INA(-S) or SCL(-I) on the logic side, and IND(-S) or INB(-I) on the isolated side, the highest priority such that there is no jitter on the associated output channels, only delay. This preemptive scheme will produce a certain amount of uncertainty on the other isolation channels. The resulting pulse width uncertainty on these low priority channels is typically 6ns, but may vary up to 44ns if the low priority channels are not encoded within the same high priority serial packet. = CS, IND = SDO2, OUTA = SCK2, OUTB = SDI2, OUTC = CS2, and OUTD = SDO. * * The LTM2892-S provides an SPI compatible isolated interface. The maximum data rate is a function of the inherent channel propagation delays, channel to channel pulse width uncertainty, and data direction requirements. Channel timing is detailed in Figures 6 through 9 and Tables 2 and 3. The SPI protocol supports four unique timing configurations defined by the clock polarity (CPOL) and clock phase (CPHA) summarized in Table 1. Table 1. SPI Mode CPOL CPHA DATA TO (CLOCK) RELATIONSHIP 0 0 Sample (Rising) Setup (Falling) 0 1 Setup (Rising) Sample (Falling) 1 0 Sample (Falling) Setup (Rising) 1 1 Setup (Falling) Sample (Rising) The maximum data rate for bidirectional communication is 4MHz, based on a synchronous system, as detailed in the timing waveforms. Slightly higher data rates may be achieved by skewing the clock duty cycle and minimizing the SDO to SCK setup time, however the clock rate is still dominated by the system propagation delays. A discussion of the critical timing paths relative to Figures 6 and 7 follows. For SPI communication INA = SCK, INB = SDI, INC 16 t0 t1 t1 t1+ t1 t3 50ns, CS to CS2 propagation delay Isolated slave device propagation (response time), asserts SDO2 50ns, SDO2 to SDO propagation delay t3 t5 Setup time for master SDO to SCK SDI to SCK (master data write to slave) 50ns, SDI to SDI2 propagation delay t2 t4 t5 t6 t2 t5 t4 t6 * Serial Peripheral Interface (SPI) Bus CS to SCK (master sample SDO, 1st SDO valid) 50ns, SCK to SCK2 propagation delay 50ns, SDI to SCK, separate packet non-zero setup time 50ns, SDI2 to SCK2, separate packet non-zero setup time SDO to SCK (master sample SDO, subsequent SDO valid) Setup data transition SDI and SCK t8 t8 t10 50ns, SDI to SDI2 and SCK to SCK2 propagation delay t10 SDO2 data transition in response to SCK2 t10 t11 50ns, SDO2 to SDO propagation delay t11 t12 Setup time for master SDO to SCK Maximum data rate for single direction communication, master to slave, is 8MHz, limited by the systems encoding/decoding scheme or propagation delay. Timing details for both variations of clock phase are shown in Figures 8 and 9 and Table 3. Additional requirements to insure maximum data rate are: * CS is transmitted prior to (asynchronous) or within the same (synchronous) data packet as SDI * SDI and SCK setup data transition occur within the same data packet. Referencing Figure 6, SDI can precede SCK by up to 13ns (t7 t8) or lag SCK by 3ns (t8 t9) and not violate this requirement. Similarly in Figure 8, SDI can precede SCK by up to 13ns (t4 t5) or lag SCK by 3ns (t5 t6). 2892fa For more information www.linear.com/LTM2892 LTM2892 Applications Information CPHA = 0 CS = EOUTD CS2 SDI SDI2 SCK (CPOL = 0) SCK2 (CPOL = 0) SCK (CPOL = 1) SCK2 (CPOL = 1) SDO INVALID SDO2 t0 t1 t2 t3 t4 t5 t6 t 7 t 8 t9 t10 t11 t12 t13 t14 t15 t17 t18 2892 F06 Figure 6. SPI Timing, Bidirectional, CPHA = 0 CPHA = 1 CS = EOUTD CS2 SDI SDI2 SCK (CPOL = 0) SCK2 (CPOL = 0) SCK (CPOL = 1) SCK2 (CPOL = 1) SDO INVALID SDO2 t0 t1 t2 t3 t4 t5 t6 t 7 t 8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 2892 F07 Figure 7. SPI Timing, Bidirectional, CPHA = 1 2892fa For more information www.linear.com/LTM2892 17 LTM2892 Applications Information Table 2. Bidirectional SPI Timing Event Description TIME CPHA EVENT DESCRIPTION t0 0, 1 Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Logic side slave data output enabled, initial data is not equivalent to slave device data output. t0-t1, t17-t18 0, 1 Propagation delay chip select, logic to isolated side, 50ns typical. t1 0, 1 Slave device chip select output data enable. t2 0 1 Start of data transmission, data setup. Start of transmission, data and clock setup. Data transition must be within -13ns to 3ns of clock edge. t1-t3 0, 1 Propagation delay of slave data, isolated to logic side, 50ns typical. t3 0, 1 Slave data output valid, logic side. t2-t4 0 Propagation delay of data, logic side to isolated side. 1 Propagation delay of data and clock, logic side to isolated side. t5 0, 1 Logic side data sample time, half clock period delay from data setup transition. t5-t6 0, 1 Propagation delay of clock, logic to isolated side. t6 0, 1 Isolated side data sample time. t8 0, 1 Synchronous data and clock transition, logic side. t7-t8 0, 1 Data to clock delay, must be 13ns. t8-t9 0, 1 Clock to data delay, must be 3ns. t8-t10 0, 1 Propagation delay clock and data, logic to isolated side. t10, t14 0, 1 Slave device data transition. t10-t11, t14-t15 0, 1 Propagation delay slave data, isolated to logic side. t11-t12 0, 1 Slave data output to sample clock setup time. t13 t13-t14 t15 t15-t16 0 Last data and clock transition logic side. 1 Last sample clock transition logic side. 0 Propagation delay data and clock, logic to isolated side. 1 Propagation delay clock, logic to isolated side. 0 Last slave data output transition logic side. 1 Last slave data output and data transition, logic side. 1 Propagation delay data, logic to isolated side. t17 0, 1 Asynchronous chip select transition, end of transmission. Disable slave data output logic side. t18 0, 1 Chip select transition isolated side, slave data output disabled. 18 2892fa For more information www.linear.com/LTM2892 LTM2892 Applications Information CPHA = 0 CS = EOUTD CS2 SDI SDI2 SCK (CPOL = 0) SCK2 (CPOL = 0) SCK (CPOL = 1) 2892 F06 SCK2 (CPOL = 1) t0 t1 t 2 t3 t4 t 5 t 6 t7 t8 t9 t11 t12 Figure 8. SPI Timing, Unidirectional, CPHA=0 CPHA = 1 CS = EOUTD CS2 SDI SDI2 SCK (CPOL = 0) SCK2 (CPOL = 0) SCK (CPOL = 1) 2892 F09 SCK2 (CPOL = 1) t0 t1 t2 t3 t4 t 5 t 6 t7 t8 t9 t10 t11 t12 Figure 9. SPI Timing, Unidirectional, CPHA=1 2892fa For more information www.linear.com/LTM2892 19 LTM2892 Applications Information Table 3. Unidirectional SPI Timing Event Description TIME CPHA t0 0, 1 t0-t1 0, 1 t2 t2-t3 EVENT DESCRIPTION Asynchronous chip select, may be synchronous to SDI but may not lag by more than 3ns. Propagation delay chip select, logic to isolated side. 0 Start of data transmission, data setup. 1 Start of transmission, data and clock setup. Data transition must be within -13ns to 3ns of clock edge. 0 Propagation delay of data, logic side to isolated side. 1 Propagation delay of data and clock, logic side to isolated side. t3 0, 1 Logic side data sample time, half clock period delay from data setup transition. t3-t5 0, 1 Clock propagation delay, clock and data transition. t4-t5 0, 1 Data to clock delay, must be 13ns. t5-t6 0, 1 Clock to data delay, must be 3ns. t5-t7 0, 1 Data and clock propagation delay. t8 t8-t9 t9-t10 0 Last clock and data transition. 1 Last clock transition. 0 Clock and data propagation delay. 1 Clock propagation delay. 1 Data propagation delay. t11 0, 1 Asynchronous chip select transition, end of transmission. t12 0, 1 Chip select transition isolated side. 20 2892fa For more information www.linear.com/LTM2892 LTM2892 Applications Information Inter-IC Communication (I2C) Bus The isolated side bidirectional serial data pin, SDA2, simplified schematic is shown in Figure 11. An internal 1.8mA current source provides a pull-up for SDA2. Do not connect any other pull-up device to SDA2. This current source is sufficient to satisfy the system requirements for bus capacitances greater than 200pF in fast mode and greater than 400pF in standard mode. The LTM2892-I provides an isolated I2C compatible interface supporting master mode only, with a unidirectional clock (SCLIN), and bidirectional data (SDA1). The maximum data rate is 400kHz which supports fast-mode I2C. Timing is detailed in Figure 10. The data rate is limited by the slave acknowledge setup time (tSU;ACK), consisting of the I2C standard minimum setup time (tSU;DAT) of 100ns, maximum clock propagation delay of 225ns, glitch filter and isolated data delay of 500ns maximum, and the combined isolated and logic data fall time of 300ns at maximum bus loading. The total setup time reduces the I2C data hold time (tHD;DAT) to a maximum of 175ns, guaranteeing sufficient data setup time (tSU;ACK). Additional proprietary circuitry monitors the slew rate on the SDA1 and SDA2 signals to manage directional control across the isolation barrier. Slew rates on both pins must be greater than 1V/s for proper operation. SDA1 SLAVE ACK SDA2 SCLIN 1 8 9 SCLOUT START tPROP tSU;DAT STOP tSU; ACK tHD;DAT 2892 F10 Figure 10. I2C Timing Diagram GLITCH FILTER 1.8mA TO LOGIC SIDE SDA2 FROM LOGIC SIDE 2892 F11 Figure 11. Isolated SDA2 Pin Schematic 2892fa For more information www.linear.com/LTM2892 21 LTM2892 Applications Information The logic side bidirectional serial data pin, SDA1, requires a pull-up resistor or current source connected to VL1. Follow the requirements in Figures 12 and 13 for the appropriate pull-up resistor on SDA1 that satisfies the desired rise time specifications and VOL maximum limits for fast and standard modes. The resistance curves represent the maximum resistance boundary; any value may be used to the left of the appropriate curve. The isolated side clock pin, SCLOUT, has a weak pushpull output driver; do not connect an external pull-up device. SCLOUT is compatible with I2C devices without clock stretching. On lightly loaded connections, a 100pF 30 Some consideration must be given to signal coupling between SCLOUT and SDA2. Separate these signals on a printed circuit board or route with ground between. If these signals are wired off board, twist SCLOUT with VL2 and/ or GND2 and SDA2 with GND2 and/or VL2; do not twist SCLOUT and SDA2 together. If coupling between SCLOUT and SDA2 is unavoidable, place the aforementioned RC filter at the SCLOUT pin to reduce noise injection onto SDA2. VL1 = 3.0V VL1 = 3.3V VL1 = 3.6V VL1 = 4.5V TO 5.5V 25 RPULL-UP (k) capacitor from SCLOUT to GND2 or RC lowpass filter (R = 500, C = 100pF) can be used to decrease the rise and fall times and minimize noise. 20 15 10 5 0 10 100 CBUS (pF) 1000 2892 F12 Figure 12. Maximum Standard Speed Pull-Up Resistance on SDA1 10 VL1 = 3.0V VL1 = 3.3V VL1 = 3.6V VL1 = 4.5V TO 5.5V 9 8 RPULL-UP (k) 7 6 5 4 3 2 1 0 10 100 CBUS (pF) 1000 2892 F13 Figure 13. Maximum Fast Speed Pull-Up Resistance on SDA1 22 2892fa For more information www.linear.com/LTM2892 LTM2892 Applications Information Common Mode Transient Immunity (CMTI) The minimum specified common mode transient immunity for the LTM2892 is 50kV/s, with typical performance of 70kV/s. This rating applies to the LTM2892 while actively transmitting data across the isolation barrier as shown in Figures 14 through 16. The following oscilloscope screen capture characteristics apply to all figures related to the discussion of CMTI. The topmost trace input signal on INA, the trace immediately below is output signal on OUTD, data is looped on the isolated side (OUTA tied to IND), and the bottom trace is the common mode transient applied from GND2 to GND1. All data was captured using infinite persistence unless otherwise noted. The common mode transient repetition rate is 10Hz. Measurements were done using the LTM2892-S with VCC1 = VL1 = 5V, and VCC2 = VL2 at approximately 4.7V under battery power. Figures 16 and 18 show the actual transient rate of change using data averaging. This exceptional level of transient immunity is a direct result of the differential receiver and center tapped data coils employed in the isolated data communication system. Figure 17 shows the LTM2892 in a static data state in the presence of 200kV/s transients with no state change or system latch-up. The system is known to be in a static state since the data changed approximately 600ns prior to the transient; the internal data refresh which guarantees the correct DC state does not occur until 1.2s after the last transition. Figure 18 shows 200kV/s transients occurring in a data communication interval, just prior to data transmission across the isolation barrier. For transients greater than 70kV/s it is possible to corrupt the dynamic data communication. In this case the output data may be incorrect for up to one data refresh period. This situation is shown in Figure 19. The output state is automatically corrected after approximately 1.2s. The output data states may also be corrupted for transients greater than 70kV/s, if the common mode transient aligns with the refresh data transmission. Figures 20 and 21 show data corruption for one refresh period with common mode transients of 200kV/s. RF, Magnetic Field Immunity The isolator Module technology used within the LTM2892 has been independently evaluated, and successfully passed the RF and magnetic field immunity testing requirements per European Standard EN 55024, in accordance with the following test standards: EN 61000-4-3 Radiated, radio-frequency, electromagnetic field immunity EN 61000-4-8 Power frequency magnetic field immunity EN 61000-4-9 Pulsed magnetic field immunity Tests were performed using an unshielded test card designed per the data sheet PCB layout recommendations. Specific limits per test are detailed in Table 4. Table 4. EMC Immunity Tests TEST FREQUENCY FIELD STRENGTH 80MHz to 1GHz 10V/m 1.4MHz to 2GHz 3V/m 2GHz to 2.7GHz 1V/m 50Hz and 60Hz 30A/m EN 61000-4-8 Level 5 60Hz 100A/m* EN 61000-4-9 Level 5 Pulse 1000A/m EN 61000-4-3 Annex D EN 61000-4-8 Level 4 * Non IEC method. 2892fa For more information www.linear.com/LTM2892 23 LTM2892 Applications Information INA INA 5V/DIV 5V/DIV OUTD 5V/DIV 5V/DIV 200V/ DIV 2892 F14 20ns/DIV INA 5V/DIV 5V/DIV OUTD OUTD 2892 F16 Figure 16. Transient dV/dT, 70kV/s Figure 15. 70kV/s Transient Operation Coincident with Data Transmission/Reception INA dV/dT 2892 F15 20ns/DIV Figure 14. Operation with Repetitive Bursts of Common Mode Transients, 50kV/s 5V/DIV CMT 20kV/ s/DIV 200V/DIV 200V/ DIV 5V/DIV OUTD CMT CMT 20ns/DIV INA 5V/DIV 5V/DIV OUTD INA 5V/DIV CMT OUTD 5V/DIV CMT 50kV/s/ DIV 500V/DIV CMT 500V/ DIV 2892 F17 100ns/DIV Figure 17. Static Operation with 200kV/s Transients 5V/DIV dV/dT Figure 18. 200kV/s Transient Prior to Data Transmission 5V/DIV 5V/DIV 500V/DIV OUTD 5V/DIV CMT 500V/DIV 400ns/DIV 200ns/DIV 2892 F19 Figure 19. Data Refresh Recovery for 200kV/s Transient INA OUTD CMT 2892 F20 Figure 20. Common Mode Transient (200kV/s) Coincident with Data Refresh, Data Low 24 2892 F18 20ns/DIV INA 500V/ DIV 400ns/DIV 2892 F21 Figure 21. Common Mode Transient (200kV/s) Coincident with Data Refresh, Data High 2892fa For more information www.linear.com/LTM2892 LTM2892 Applications Information PCB Layout * For large ground planes a small capacitance ( 330pF) from GND1 to GND2, either discrete or embedded within the substrate, provides a low impedance current return path for the module parasitic capacitance, minimizing any high frequency differential voltages and substantially reducing radiated emissions. Discrete capacitance will not be as effective due to parasitic ESL. In addition, voltage rating, leakage, and clearance must be considered for component selection. Embedding the capacitance within the PCB substrate provides a near ideal capacitor and eliminates component selection issues; however, the PCB must be 4 layers. Care must be exercised in applying either technique to ensure the voltage rating of the barrier is not compromised. * In applications without an embedded PCB substrate capacitance, a slot may be added between the logic side and isolated side device pins. The slot extends the creepage path between terminals on the PCB side, and may reduce leakage caused by PCB contamination. The slot should be placed in the middle of the device and extend beyond the package perimeter. The high integration of the LTM2892 makes PCB layout very simple. However, to optimize its electrical isolation characteristics and EMI performance, some layout considerations are necessary. * Input and output supply decoupling is not required, since these components are integrated within the package. An additional polarized bulk capacitor with a value of 3.3F to 10F is recommended. The high ESR of this capacitor reduces board resonances and minimizes voltage spikes caused by hot plugging of the supply voltage. For EMI sensitive applications, an additional low ESL ceramic capacitor of 1F to 4.7F, placed as close to the power and ground terminals as possible, is recommended. Alternatively, a number of smaller value parallel capacitors may be used to reduce ESL and achieve the same net capacitance. * Do not place copper on the PCB between the inner columns of pads. This area must remain open to withstand the rated isolation voltage. * The use of solid ground planes for GND1 and GND2 is recommended for non-EMI critical applications to optimize signal fidelity, and minimize RF emissions due to uncoupled PCB trace conduction. The drawback of using ground planes, where EMI is of concern, is the creation of a dipole antenna structure which can radiate differential voltages formed between GND1 and GND2. If ground planes are used it is recommended to minimize their area, and use contiguous planes as any openings or splits can exacerbate RF emissions. The PCB layout in Figures 22a and 22b shows the demo boards for the LTM2892. EMI performance is shown in Figure 23, measured using a gigahertz transverse electromagnetic (GTEM) cell and method detailed in IEC 61000-4-20, "Testing and Measurement Techniques - Emission and Immunity Testing in Transverse Electromagnetic Waveguides." 2892fa For more information www.linear.com/LTM2892 25 LTM2892 Applications Information Figure 22a. LTM2892-S Demo Board Layout (DC1957A) 26 2892fa For more information www.linear.com/LTM2892 LTM2892 Applications Information Figure 22b. LTM2892-I Demo Board Layout (DC1986A) 2892fa For more information www.linear.com/LTM2892 27 LTM2892 Applications Information 60 DETECTOR = PEAK HOLD, RBW = 120kHz, VBW = 300kHz 50 SWEEP TIME = 680ms, 10 SWEEPS # OF POINTS = 501 40 CISPR 22 CLASS B LIMIT dVV/m 30 20 10 0 DUT -10 -20 -30 0 100 200 300 400 500 600 700 800 FREQUENCY (MHz) 900 1000 2892 F23 Figure 23. LTM2892 Demo Board Emissions 28 2892fa For more information www.linear.com/LTM2892 LTM2892 Typical Applications C2 C1 C0 D2 D0 D1 V+ AV+ V- AV- VCC2 AVCC2 CS2 SDI2 SCK2 I2 SDO2 I1 GND2 L8 K8 L7 K7 L6 K6 L5 L4 L3 L2 L1 K1 K2 E2 E1 E0 F2 F0 F1 E0 E1 E2 E3 E4 E5 E6 E7 F5 F4 F3 E5 E4 E3 F0 F1 F2 F3 F4 F5 F6 F7 LTM2892-S D7 D6 C7 C6 A6 A5 A4 B3 B2 B1 A3 A2 A1 B4 B5 B6 VCC1 VL1 ON1 OUTF OUTE OUTD INC INB INA EOUTD GND1 GND1 VCC2 VL2 ON2 INF INE IND OUTC OUTB OUTA EOUTA GND2 GND2 J6 J5 J4 J3 J2 J1 H3 H2 H1 H4 H5 H6 DIGITAL OUTPUTS F[0:7] VCC2 VL2 ON2 INF INE IND OUTC OUTB OUTA EOUTA GND2 GND2 C[0:7] D0 D1 D2 D3 D4 D5 D6 D7 VCC VL1 ON1 OUTF OUTE OUTD INC INB INA EOUTD GND1 GND1 J6 J5 J4 J3 J2 J1 H3 H2 H1 H4 H5 H6 E[0:7] D[0:7] C5 C4 C3 A6 A5 A4 B3 B2 B1 A3 A2 A1 B4 B5 B6 ISOLATION BARRIER LTM2892-S D5 D4 D3 DIGITAL OUTPUTS ON SDOE CS SDI SCK DO2 SDO DO1 GND ISOLATION BARRIER DIGITAL INPUTS C0 C1 C2 C3 C4 C5 C6 C7 A7 A6 A5 A4 A3 A2 A1 B1 B2 ISOLATION BARRIER LTM2883-5S B8 VCC A8 VL 5V 1.62V TO 5V DIGITAL INPUTS F7 F6 E7 E6 2892 F16 Figure 24. High Speed Bidirectional 8-Bit Parallel Isolator 2892fa For more information www.linear.com/LTM2892 29 LTM2892 Typical Applications SSA MOSI SCK MISO LTM2883-5S B8 VCC A8 VL A7 A6 A5 A4 A3 A2 A1 B1 B2 ISOLATION BARRIER 5V ON SDOE CS SDI SCK DO2 SDO DO1 GND V+ AV+ V- AV- VCC2 AVCC2 CS2 SDI2 SCK2 I2 SDO2 I1 GND2 L8 K8 L7 K7 L6 K6 L5 L4 L3 L2 L1 K1 K2 4.7k DEVICE A SS MOSI MISO SCK DEVICE B SS MOSI MISO SCK SSD SSC SSB VCC1 VL1 ON1 OUTF INC OUTE INB OUTD INA EOUTD GND1 GND1 ISOLATION BARRIER LTM2892-S A6 A5 A4 B3 A3 B2 A2 B1 A1 B4 B5 B6 VCC2 VL2 ON2 INF OUTC INE OUTB IND OUTA EOUTA GND2 GND2 J6 J5 J4 J3 H3 J2 H2 J1 H1 H4 H5 H6 DEVICE C SS MOSI MISO SCK DEVICE D SS MOSI MISO SCK 2892 F17 Figure 25. Isolated SPI Interface with Multiple Chip Select 30 2892fa For more information www.linear.com/LTM2892 LTM2892 Typical Applications 5V R1 200k C4 10nF R6 10k R7 56.2k C3 1.5nF VIN BIAS SHDN TC RILIM SS VC D1 1N4148W R3 26.1k 13 RFB 14 RREF D2 TR1:A 5V1 * SW * 5V 2 3 1 16 17 8 9 5k 5k SDA SCL A6 A5 A4 B3 A3 B2 A2 B1 A1 B4 B5 B6 VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 VCC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 D6 TR1:F * COM5 SCL5 VCC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 A6 A5 A4 B3 A3 B2 A2 B1 A1 B4 B5 B6 5V 5V A6 A5 A4 B3 A3 B2 A2 B1 A1 B4 B5 B6 VCC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 J6 J5 J4 J3 H3 J2 H2 J1 H1 H4 H5 H6 SDA2 SCL2 C7 10F TR1:D * COM3 LTM2892-I ISOLATION BARRIER SCL4 VCC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 5V3 TR1:E LTM2892-I J6 J5 J4 J3 H3 J2 H2 J1 H1 H4 H5 H6 COM2 D4 * COM4 SDA4 VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 D5 C8 10F C6 10F * VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 A6 A5 A4 B3 A3 B2 A2 B1 A1 B4 B5 B6 5V 5V A6 A5 A4 B3 A3 B2 A2 B1 A1 B4 B5 B6 VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 ISOLATION BARRIER 5V4 SCL1 LTM2892-I ISOLATION BARRIER SDA5 SDA1 5V2 TR1:C LTM2892-I J6 J5 J4 J3 H3 J2 H2 J1 H1 H4 H5 H6 J6 J5 J4 J3 H3 J2 H2 J1 H1 H4 H5 H6 D3 ISOLATION BARRIER C9 10F COM1 LTM2892-I 4 TR1: WURTH ELEKTRONIK 749196111 D2-D6: DIODES, INC. B0520LW 5V5 C5 10F TR1:B R8 6.04k LT3574 TEST GND GND GND GND GND GND R5 26.1k 5 6 C4 2.2nF ISOLATION BARRIER R2 90.9k 7 15 11 10 12 R8 2k C1 10F VCC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 J6 J5 J4 J3 H3 J2 H2 J1 H1 H4 H5 H6 SDA3 SCL3 2892 F18 Figure 26. Parallel Multi-Zone Isolated I2C Interface 2892fa For more information www.linear.com/LTM2892 31 LTM2892 Typical Applications 5V C1 10F R3 20k C5 4.7nF C4 10nF R6 10k 1F R7 50k C3 2.2nF C2 220pF SHDN TC RILIM SS VC 13 RFB 14 RREF D1 R4 6.04k LT3574 SW R3 124k 150H 4 * 2 3 1 16 17 8 9 50V 1M Ox C Ox CS MOSI SCK MISO GND VCC2 VL2 ON2 INF OUTC INE OUTB IND OUTA EOUTA GND2 GND2 ISOLATION BARRIER LTM2892-S J6 J5 J4 J3 H3 J2 H2 J1 H1 H4 H5 H6 50V C6 1F * 5V VCC D2 ES1D T1 1:2 TEST GND GND GND GND GND GND R5 249k 7 15 11 10 12 VIN BIAS 5 6 VCC1 VL1 ON1 OUTF INC OUTE INB OUTD INA EOUTD GND1 GND1 A6 A5 A4 B3 A3 B2 A2 B1 A1 B4 B5 B6 1M 1M 1F 100k 100k 1F 100k 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 LTC6803-2 CS SDO SDI SCK A3 A2 A1 A0 GPIO2 GPIO1 WDT MM TOS VREG VREF VTEMP2 VTEMP1 NC V- S1 C1 S2 V+ C12 S12 C11 S11 C10 S10 C9 S9 C8 S8 C7 S7 C6 S6 C5 S5 C4 S4 C3 S3 C2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 100k T1: BH ELECTRONICS L10-0111 D1: DIODES INC. 1N4148WT-7 2892 F19 Figure 27. Battery Stack Monitor with Isolated SPI Interface 32 2892fa For more information www.linear.com/LTM2892 LTM2892 Typical Applications 1F 5V LTM2892-I 10k VCC OX C GND SDA IX SCL VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 VCC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 ISOLATION BARRIER 10k A6 A5 A4 B3 A3 B2 A2 B1 A1 B4 B5 B6 J6 J5 J4 J3 H3 J2 H2 J1 H1 H4 H5 H6 10k VEE -48V RTN 4x 1k IN SERIES 1/4W EACH 453k 7 8 UVL 9 UVH 16.9k 100nF 1F 11.8k 10 11 19 20 26 1 25 24 220nF 0.1F 47nF 21 VIN INTVCC ADIN2 OV SS TMR EN PGI ADR1 ADR0 FLTIN SCL SDAI SDAO ALERT ON LTC4261CGN PGIO PG ADIN VEE SENSE 13 0.1F 47nF GATE 14 DRAIN RAMP 16 18 15 10 VEE 10k 28 27 23 PWRGD2 PWRGD1 + 1k IRF1310NS 330F 100V VOUT 10nF 100V 0.008 1% -48V INPUT 1M 22 6 5 4 3 2 402k 2892 F20 Figure 28. -48V, 200W Hot SwapTM Controller with Isolated I2C Interface 2892fa For more information www.linear.com/LTM2892 33 LTM2892 Typical Applications 0.01 3V TO 5V 3.3V 2k SDA SCL 2k VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 ISOLATION BARRIER LTM2892-I A6 A5 A4 B3 A3 B2 A2 B1 A1 B4 B5 B6 VCC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 J6 J5 J4 J3 H3 J2 H2 J1 H1 H4 H5 H6 10 9 8 7 6 LTC2990 VCC V1 ADR1 V2 ADR0 V3 SCL V4 SDA GND ILOAD 0A TO 1A 1 2 3 4 5 MMBT3904 470pF 2892 F21 Figure 29. Isolated I2C Voltage, Current and Temperature Power Supply Monitor 34 2892fa For more information www.linear.com/LTM2892 INTERRUPT SCLIN ENABLE SDA SHUTDOWN 5V 10k VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 ISOLATION BARRIER VCC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 J6 J5 J4 J3 H3 J2 H2 J1 H1 H4 H5 H6 3.3V -48V AGND SHDN PHY (NETWORK PHYSICAL LAYER CHIP) RESET SDAIN SCL SDAOUT AUTO INT AD0 AD1 AD2 AD3 DGND SMAJ58A 100k 1F VEE For more information www.linear.com/LTM2892 * * * * * * * T1 Q1 BYP * * * * OUT 0.1F S1B DETECT1 SENSE GATE 0.25 1/4 LTC4266 VDO 0.1F FB1 0.22F S1B 10nF 10nF FB2 CMPD3003 75 75 1nF 75 75 10nF 10nF 2892 F22 RJ45 CONNECTOR 1 2 3 4 5 6 7 8 Typical Applications * Figure 30. One Complete Isolated Power Over Ethernet (PoE) Port Q1: FAIRCHILD IRFM120A OR PHILIPS PHT6NQ10T FB1, FB2: TDK MPZ2012S601A T1: PULSE H6096NL OR COILCRAFT ETH1-230LD 10k A6 A5 A4 B3 A3 B2 A2 B1 A1 B4 B5 B6 LTM2892-I LTM2892 2892fa 35 For more information www.linear.com/LTM2892 aaa Z 0.5 0.025 O 24x 4 E 2.5 1.5 2.5 SUGGESTED PCB LAYOUT TOP VIEW 0.000 PACKAGE TOP VIEW 0.5 PIN "A1" CORNER 0.5 36 1.5 Y 3.875 2.875 0.000 2.875 3.875 X D aaa Z // bbb Z SYMBOL A A1 A2 b b1 D E e F G H1 H2 aaa bbb ccc ddd eee H1 SUBSTRATE A1 NOM 2.91 0.50 2.41 0.60 0.50 9.00 6.25 1.00 7.75 5.00 0.41 2.00 A2 A 0.46 2.05 0.15 0.10 0.20 0.15 0.08 MAX 3.11 0.60 2.51 0.70 0.55 NOTES DETAIL B PACKAGE SIDE VIEW TOTAL NUMBER OF BALLS: 24 0.36 1.95 MIN 2.71 0.40 2.31 0.50 0.45 b1 DIMENSIONS ddd M Z X Y eee M Z DETAIL A Ob (24 PLACES) DETAIL B H2 MOLD CAP ccc Z Z F e b 6 b 5 4 G 3 e 2 PACKAGE BOTTOM VIEW DETAIL A 1 PIN 1 3 SEE NOTES J H G F E D C B A DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE 4 TRAY PIN 1 BEVEL BGA 24 0911 REV A PACKAGE IN TRAY LOADING ORIENTATION LTMXXXXXX Module 6. SOLDER BALL COMPOSITION IS 96.5% Sn/3.0% Ag/0.5% Cu 5. PRIMARY DATUM -Z- IS SEATING PLANE BALL DESIGNATION PER JESD MS-028 AND JEP95 3 2. ALL DIMENSIONS ARE IN MILLIMETERS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 COMPONENT PIN "A1" (Reference LTC DWG # 05-08-1898 (Reference LTC DWG # 05-08-1898 Rev A)Rev A) Package BGABGA Package 24-Lead (9mm x 6.25mm x 2.91mm) 24-Lead (9mm x 6.25mm x 2.91mm) LTM2892 Package Description Please refer to http://www.linear.com/product/LTM2892#packaging for the most recent package drawings. 2892fa LTM2892 Revision History REV DATE DESCRIPTION A 08/16 Addd UL-CSA File # PAGE NUMBER Revised propagation delay when SDA2 SDA1, and I2C Data Hold Time 1 5, 21 2892fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. For more information www.linear.com/LTM2892 37 LTM2892 Typical Application 5V 13 RSL 10 17 1 14 * * * * D1 4 D3 1 5 SCL 3 1 1F 4 5 VCC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 A6 A5 A4 B3 A3 B2 A2 B1 A1 B4 B5 B6 J6 J5 J4 J3 H3 J2 H2 J1 H1 H4 H5 H6 VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 D6 3 1F LT1761-5 2 GND OUT BYP GND 2 4 5 4 LTM2892-I ISOLATION BARRIER SDA 5k VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 * * D5 LTM2892-I ISOLATION BARRIER 5k A6 A5 A4 B3 A3 B2 A2 B1 A1 B4 B5 B6 T3 1:1 D4 LT1761-5 2 OUT BYP GND LTM2892-I 5V * * 1F LT1761-5 D1-D6: MBR0520 T1: MURATA 782485/55C T2-3: MURATA 78615/9C * * D2 1 3 3.4k 16 T2 1:1 IN SHDN COL B PGND GND 16.9k GND 5 SYNC 6 CT 7 RT 150pF * * OUT BYP SHDN LT3439 T1 1:1.5 3 VCC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 A6 A5 A4 B3 A3 B2 A2 B1 A1 B4 B5 B6 J6 J5 J4 J3 H3 J2 H2 J1 H1 H4 H5 H6 VCC1 VL1 ON1 OUTC INA SDA1 SDA1 OUTB SCLIN GND1 GND1 GND1 ISOLATION BARRIER COL A PGND 11 IN SHDN VIN IN SHDN 10F VCC2 VL2 ON2 INC OUTA SDA2 SDA2 INB SCLOUT GND2 GND2 GND2 5M 5M 5M 5M 5M 5M 1nF 1nF 1nF 1nF 1nF 1nF J6 J5 J4 J3 H3 J2 H2 J1 H1 H4 H5 H6 SCL3 SDA3 SCL2 SDA2 SCL1 SDA1 2892 F23 Figure 31. Series Multi-Zone Isolated I2C Interface, Working Voltage Multiplier Related Parts PART NUMBER DESCRIPTION COMMENTS LTM2881 Isolated RS485/RS422 Module Transceiver with Integrated DC/DC Converter 20Mbps 2500VRMS Isolation and Integrated Termination with Power in LGA/BGA Package LTM2882 Dual Isolated RS232 Module Transceiver with Integrated DC/DC Converter 2500VRMS Isolation with Power in LGA/BGA Package LTM2883 SPI/Digital or I2C Isolated Module with Adjustable 5V, and 12.5V Nominal Voltage Rails 2500VRMS Isolation with Power in BGA Package LTC1535 Isolated RS485 Transceiver 2500VRMS Isolation with External Transformer Drive LTC4310 Hot-Swappable I2C Isolators Isolation with External Transformer or Capacitors LTC6803 Multistack Battery Monitor Individual Battery Cell Monitoring of High Voltage Battery Stacks, Multiple Devices Interconnected via SPI LTC2990 Quad I2C Temperature, Voltage and Current Monitor Remote and Internal Temperatures, 14-Bit Voltages and Current, Internal 10ppm/C Reference 38 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTM2892 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTM2892 2892fa LT 0816 REV A * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2013