LMZ31710RVQR - NATIONAL SEMICONDUCTOR

LMZ31710

PWRGD

SENSE+

VOUT

PVIN

VIN

INH/UVLO

RT/CLK

VADJ

SS/TR

STSEL

AGND PGND

SET

OUT

SYNC_OUT

ISHARE

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Documents

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Design

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMZ31710

SNVS987F –JULY 2013–REVISED MAY 2020

LMZ31710 10-A Power Module With 2.95-V to 17-V Input and Current Sharing

in QFN Package

1 Features

1• Complete integrated power solution

– Small footprint, low-profile design

– Pin compatible with LMZ31707 and LMZ31704

– 10-mm × 10-mm × 4.3-mm package

• Efficiencies up to 95%

• Eco-Mode™ and light load efficiency (LLE)

• Wide-output voltage adjust

0.6 V to 5.5 V, With 1% reference accuracy

• Supports parallel operation for higher current

• Optional split power rail allows

input voltage down to 2.95 V

• Adjustable switching frequency

(200 kHz to 1.2 MHz)

• Synchronizes to an external clock

• Provides 180° out-of-phase clock signal

• Adjustable slow start

• Output voltage sequencing and tracking

• Power-good output

• Programmable undervoltage lockout (UVLO)

• Overcurrent and overtemperature protection

• Prebias output start-up

• Operating temperature range: –40°C to +85°C

• Enhanced thermal performance: 13.3°C/W

• Meets EN55022 Class B emissions

- integrated shielded inductor

• Create a custom design using the LMZ31710 with

the WEBENCH® Power Designer

2 Applications

•Broadband and communications infrastructure

•Automated test and medical equipment

•Compact PCI / PCI Express / PXI express

•DSP and FPGA point-of-load applications

3 Description

The LMZ31710 power module is an easy-to-use

integrated power solution that combines a 10-A

DC/DC converter with power MOSFETs, a shielded

inductor, and passives into a low-profile QFN

package. This total power solution allows as few as

three external components and eliminates the loop

compensation and magnetics part selection process.

The 10 × 10 × 4.3 mm QFN package is easy to

solder onto a printed circuit board and allows a

compact point-of-load design. The device achieves

greater than 95% efficiency and excellent power

dissipation capability with a thermal impedance of

13.3°C/W. The LMZ31710 offers the flexibility and the

feature set of a discrete point-of-load design and is

ideal for powering a wide range of ICs and systems.

Advanced packaging technology affords a robust and

reliable power solution compatible with standard QFN

mounting and testing techniques.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LMZ31710 RVQ (42) 10.00 mm × 10.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Application

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings ............................................................ 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics.......................................... 6

6.6 Typical Characteristics (PVIN = VIN = 12 V) .............. 8

6.7 Typical Characteristics (PVIN = VIN = 5 V) ............... 9

6.8 Typical Characteristics (PVIN = 3.3 V, VIN = 5 V) ... 10

7 Detailed Description............................................ 11

7.1 Overview................................................................. 11

7.2 Functional Block Diagram....................................... 11

7.3 Feature Description................................................. 12

7.4 Device Functional Modes........................................ 24

8 Application and Implementation ........................ 26

8.1 Application Information............................................ 26

8.2 Typical Application.................................................. 26

8.3 Additional Application Schematics.......................... 27

9 Power Supply Recommendations...................... 28

10 Layout................................................................... 29

10.1 Layout Considerations .......................................... 29

10.2 Layout Examples................................................... 29

11 Device and Documentation Support................. 31

11.1 Device Support...................................................... 31

11.2 Documentation Support ........................................ 31

11.3 Receiving Notification of Documentation Updates 31

11.4 Support Resources ............................................... 31

11.5 Trademarks........................................................... 31

11.6 Electrostatic Discharge Caution............................ 32

11.7 Glossary................................................................ 32

12 Mechanical, Packaging, and Orderable

Information........................................................... 32

12.1 Tape and Reel Information ................................... 32

4 Revision History

Changes from Revision E (December 2019) to Revision F Page

• Updated Table 7 with correct values ................................................................................................................................... 23

Changes from Revision D (April 2019) to Revision E Page

• Added VOUT Range values under different IOUT conditions in Table 7.................................................................................. 23

Changes from Revision C (April 2018) to Revision D Page

• Corrected TBD values in Synchronization Frequency vs Output Voltage Table.................................................................. 23

Changes from Revision B (June 2017) to Revision C Page

• Added WEBENCH® design links for the LMZ31710 ............................................................................................................. 1

• Increased the peak reflow temperature and maximum number of reflows to JEDEC specifications for improved

manufacturability..................................................................................................................................................................... 5

Changes from Revision A (July 2013) to Revision B Page

• Changed Device Information and Pin Configuration and Functions sections, ESD Rating table, Feature Description,

Device Functional Modes,Application and Implementation,Power Supply Recommendations,Layout,Device and

Documentation Support , and Mechanical, Packaging, and Orderable Information sections................................................ 1

• Added peak reflow and maximum number of reflows information ........................................................................................ 5

11 12 13 14 15 16 17 18 19 20 21

3233343536373839

INH/UVLO

PWRGD

OCP_SEL

DNC

RT/CLK

VIN

SS/TR

STSEL

ISHARE

ILIM

SYNC_OUT

PVIN

SENSE+

VADJ

AGND

PVIN

PGND

VOUT

PGND

VOUT

PGND

DNC

PGND

DNC

PVIN

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5 Pin Configuration and Functions

RVQ Package

42-Pin B3QFN

(Top View)

Pin Functions

PIN TYPE DESCRIPTION

NAME NO.

AGND 2-Zero volt reference for the analog control circuit. These pins are not connected together internal to the

device and must be connected to one another using an AGND plane of the PCB. These pins are

associated with the internal analog ground (AGND) of the device. Keep AGND separate from PGND,

as a single connection is made internal to the device. See Layout.

PGND

-This is the return current path for the power stage of the device. Connect these pins to the load and to

the bypass capacitors associated with PVIN and VOUT. Keep PGND separate from AGND, as a single

connection is made internal to the device.

VIN 3 I Input bias voltage pin. Supplies the control circuitry of the power converter. Connect this pin to the

input bias supply. Connect bypass capacitors between this pin and PGND.

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Pin Functions (continued)

PIN TYPE DESCRIPTION

NAME NO.

PVIN

IInput switching voltage. Supplies voltage to the power switches of the converter. Connect these pins to

the input supply. Connect bypass capacitors between these pins and PGND.

VOUT

OOutput voltage. These pins are connected to the internal output inductor. Connect these pins to the

output load and connect external bypass capacitors between these pins and PGND.

OPhase switch node. These pins must be connected to one another using a small copper island under

the device for thermal relief. Do not place any external component on these pins or tie them to a pin of

another function.

DNC 5-Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage.

These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.

ISHARE 25 O Current share pin. Connect this pin to the ISHARE pin of the other LMZ31710 when paralleling multiple

LMZ31710 devices. When unused, treat this pin as a Do Not Connect (DNC) and leave it isolated from

all other signals or ground.

OCP_SEL 4 I Overcurrent protection select pin. Leave this pin open for hiccup mode operation. Connect this pin to

AGND for cycle-by-cycle operation. See the Overcurrent Protection section for more details.

ILIM 6 I Current limit pin. Leave this pin open for full current limit threshold. Connect this pin to AGND to reduce

the current limit threshold by approximately 3 A.

SYNC_OU

T7 O Synchronization output pin. Provides a 180° out-of-phase clock signal.

PWRGD 8 O Power Good flag pin. This open drain output asserts low if the output voltage is more than

approximately ±6% out of regulation. A pullup resistor is required.

RT/CLK 22 I This pin is connected to an internal frequency setting resistor which sets the default switching

frequency. An external resistor can be connected from this pin to AGND to increase the frequency.

This pin can also be used to synchronize to an external clock.

VADJ 26 I Connecting a resistor between this pin and AGND sets the output voltage.

SENSE+ 27 O Remote sense connection. This pin must be connected to VOUT at the load or at the device pins.

Connect this pin to VOUT at the load for improved regulation.

SS/TR 28 I Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise

time. A voltage applied to this pin allows for tracking and sequencing control.

STSEL 29 I Slow start or track feature select. Connect this pin to AGND to enable the internal SS capacitor. Leave

this pin open to enable the TR feature.

INH/UVLO 30 I Inhibit and UVLO adjust pin. Use an open drain or open collector logic device to ground this pin to

control the INH function. A resistor divider between this pin, AGND, and PVIN/VIN sets the UVLO

voltage.

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) See the temperature derating curves in the Typical Characteristics section for thermal information.

(3) For soldering specifications, refer to the Soldering Requirements for BQFN Packages application note.

(4) Devices with a date code prior to week 14 2018 (1814) have a peak reflow case temperature of 240°C with a maximum of one reflow.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Input voltage VIN, PVIN –0.3 20 V

INH/UVLO, PWRGD, RT/CLK, SENSE+ –0.3 6 V

ILIM, VADJ, SS/TR, STSEL, SYNC_OUT, ISHARE, OCP_SEL –0.3 3 V

Output voltage PH –1.0 20 V

PH 10ns Transient –3.0 20 V

VOUT –0.3 10 V

Source current RT/CLK, INH/UVLO ±100 µA

PH current limit A

Sink current PH current limit A

PVIN current limit A

PWRGD –0.1 2 mA

Operating junction temperature –40 125(2) °C

Storage temperature, Tstg –65 150 °C

Peak Reflow Case Temperature(3) 245(4) °C

Maximum Number of Reflows Allowed(3) 3(4)

Mechanical shock Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted 1500 G

Mechanical vibration Mil-STD-883D, Method 2007.2, 20-2000 Hz 20

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic

discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

Input switching voltage, PVIN 2.95 17 V

Input bias voltage, VIN 4.5 17 V

Output voltage, VOUT 0.6 5.5 V

Switching frequency, ƒSW 200 1200 kHz

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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) The junction-to-ambient thermal resistance, RθJA, applies to devices soldered directly to a 100 mm × 100 mm double-sided PCB with

2 oz. copper and natural convection cooling. Additional airflow reduces RθJA.

(3) The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a

procedure described in JESD51-2A (sections 6 and 7). TJ=ψJT × Pdis + TT; where Pdis is the power dissipated in the device and TTis

the temperature of the top of the device.

(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a

procedure described in JESD51-2A (sections 6 and 7). TJ=ψJB × Pdis + TB; where Pdis is the power dissipated in the device and TBis

the temperature of the board 1 mm from the device.

6.4 Thermal Information

THERMAL METRIC(1) LMZ31710

UNITRVQ (B3QFN)

42 PINS

RθJA Junction-to-ambient thermal resistance(2) 13.3 °C/W

RθJB Junction-to-board thermal resistance(3) 1.6 °C/W

ψJT Junction-to-top characterization parameter(4) 5.3 °C/W

(1) See Light Load Efficiency (LLE) for more information for output voltages < 1.5 V.

(2) The minimum PVIN is 2.95 V or (VOUT + 0.7 V), whichever is greater. See Table 7 for more details.

(3) The maximum PVIN voltage is 17 V or (22 x VOUT), whichever is less. See Table 7 for more details.

(4) The maximum output voltage may be limited by the power dissipation. The maximum power dissipation of this device is 4.5 W.

(5) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal

adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor.

6.5 Electrical Characteristics

Over –40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 10 A,

CIN = 0.1 µF + 2 × 22 µF ceramic + 100 µF bulk, COUT = 4 × 47 µF ceramic (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IOUT Output current TA= 85°C, natural convection 0(1) 10 A

VIN Input bias voltage range Over output current range 4.5 17 V

PVIN Input switching voltage range Over output current range 2.95(2) 17(3) V

UVLO VIN undervoltage lockout VIN Increasing 4 4.5 V

VIN Decreasing 3.5 3.85

VOUT(adj) Output voltage adjust range Over output current range 0.6 5.5(4) V

VOUT

Set-point voltage tolerance TA= 25°C, IOUT = 0 A ±1%(5)

Temperature variation –40°C ≤TA≤+85°C, IOUT = 0 A ±0.2%

Line regulation Over input voltage range ±0.1%

Load regulation Over output current range ±0.2%

Total output voltage variation Includes set-point, line, load, and temperature variation ±1.5%(5)

ηEfficiency

PVIN = VIN = 12 V

IO= 5 A

VOUT = 5 V, fSW = 1 MHz 93%

VOUT = 3.3 V, fSW = 750 kHz 92%

VOUT = 2.5 V, fSW = 750 kHz 90%

VOUT = 1.8 V, fSW = 500 kHz 89%

VOUT = 1.2 V, fSW = 300 kHz 86%

VOUT = 0.9 V, fSW = 250 kHz 84%

VOUT = 0.6 V, fSW = 200 kHz 81%

PVIN = VIN = 5 V

IO= 5 A VOUT = 3.3 V, fSW = 750 kHz 94%

VOUT = 2.5 V, fSW = 750 kHz 93%

VOUT = 1.8 V, fSW = 500 kHz 92%

VOUT = 1.2 V, fSW = 300 kHz 89%

VOUT = 0.9 V, fSW = 250 kHz 87%

VOUT = 0.6 V, fSW = 200 kHz 83%

Output voltage ripple 20 MHz bandwidth 14 mVP-P

ILIM Current limit threshold ILIM pin open 15 A

ILIM pin to AGND 12 A

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Electrical Characteristics (continued)

Over –40°C to 85°C free-air temperature, PVIN = VIN = 12 V, VOUT = 1.8 V, IOUT = 10 A,

CIN = 0.1 µF + 2 × 22 µF ceramic + 100 µF bulk, COUT = 4 × 47 µF ceramic (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(6) Value when no voltage divider is present at the INH/UVLO pin. This pin has an internal pullup. If it is left open, the device operates when

input power is applied. A small, low-leakage MOSFET is recommended for control. Do not tie this pin to VIN.

(7) A minimum of 44 µF of external ceramic capacitance is required across the input (VIN and PVIN connected) for proper operation. An

additional 100 µF of bulk capacitance is recommended. It is also recommended to place a 0.1 µF ceramic capacitor directly across the

PVIN and PGND pins of the device. Locate the input capacitance close to the device. When operating with split VIN and PVIN rails,

place 4.7 µF of ceramic capacitance directly at the VIN pin. See Table 4 for more details.

(8) The amount of required output capacitance varies depending on the output voltage (see Table 3). The amount of required capacitance

must include at least 1 × 47 µF ceramic capacitor. Locate the capacitance close to the device. Adding additional capacitance close to

the load improves the response of the regulator to load transients. See Table 3 and Table 4 more details.

(9) The maximum output capacitance of 5000 µF includes the combination of both ceramic and non-ceramic capacitors. It may be

necessary to increase the slow-start time when turning on into the maximum capacitance. See the Slow Start (SS/TR) section for

information on adjusting the slow-start time.

Transient response 1 A/µs load step from

25 to 75% IOUT(max)

Recovery time 100 µs

VOUT over/undershoot 80 mV

VINH Inhibit threshold voltage Inhibit High Voltage 1.3 open(6) V

Inhibit Low Voltage –0.3 1.1

IINH INH Input current VINH < 1.1 V -1.15 μA

INH Hysteresis current VINH > 1.3 V -3.3 μA

II(stby) Input standby current INH pin to AGND 2 10 µA

Power

Good PWRGD Thresholds

VOUT rising Good 95%

Fault 108%

VOUT falling Fault 91%

Good 104%

PWRGD Low Voltage I(PWRGD) = 0.5 mA 0.3 V

ƒSW Switching frequency RRT = 169 kΩ400 500 600 kHz

ƒCLK Synchronization frequency

CLK Control

200 1200 kHz

VCLK-H CLK High-Level 2 5.5 V

VCLK-L CLK Low-Level 0.5 V

DCLK CLK Duty Cycle 20% 50% 80%

Thermal Shutdown Thermal shutdown 175 °C

Thermal shutdown hysteresis 10 °C

CIN External input capacitance Ceramic 44(7) µF

Non-ceramic 100(7)

COUT External output capacitance

VOUT = 0.6 V to 5.5 V Ceramic 47(8) 200 1500 µF

VOUT = 0.6 V to 5.5 V Non-ceramic 220(8) 5000(9)

Equivalent series resistance (ESR) 35 mΩ

0 2 4 6 8 10

Ambient Temperature (ƒC)

Output Current (A)

9R”9IVZ N+]

Vo = 2.5V, fsw = 750kHz

Vo = 3.3V, fsw = 750kHz

Vo = 5.0V, fsw = 1MHz

C001

Airflow = 0 LFM

0 2 4 6 8 10

Ambient Temperature (ƒC)

Output Current (A)

9R”9IVZ N+]

Vo = 2.5V, fsw = 750kHz

Vo = 3.3V, fsw = 750kHz

Vo = 5.0V, fsw = 1MHz

C001

Airflow = 200 LFM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 2 4 6 8 10

Power Dissipation (W)

Output Current (A)

Vo = 5.0V, fsw = 1MHz

Vo = 3.3V, fsw = 750kHz

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

C004

±120

±90

±60

±30

120

±40

±30

±20

±10

1000 10k 100k

Phase (ƒ)

Gain (dB)

Frequency (Hz)

Gain

Phase

C006

400k

100

0 1 2 3 4 5 6 7 8 9 10

Efficiency (%)

Output Current (A)

Vo = 5.0V, fsw = 1MHz

Vo = 3.3V, fsw = 750kHz

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

C001

0 2 4 6 8 10

Output Ripple Voltage (mV)

Output Current (A)

Vo = 5.0V, fsw = 1MHz

Vo = 3.3V, fsw = 750kHz

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

C004

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6.6 Typical Characteristics (PVIN = VIN = 12 V)

The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for

the converter. Applies to Figure 1,Figure 2, and Figure 3. The temperature derating curves represent the conditions at which

internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices

soldered directly to a 100-mm × 100-mm double-sided PCB with 2-oz. copper. Applies to Figure 5 and Figure 6.

Figure 1. Efficiency versus Output Current Figure 2. Voltage Ripple versus Output Current

Figure 3. Power Dissipation versus Output Current Figure 4. VOUT = 1.8 V, IOUT = 10 A, COUT1 = 200 Μf Ceramic,

FSW = 500 Khz

Figure 5. Safe Operating Area Figure 6. Safe Operating Area

0 2 4 6 8 10

Ambient Temperature (ƒC)

Output Current (A)

All Output Voltages

C001

Airflow = 0 LFM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 2 4 6 8 10

Power Dissipation (W)

Output Current (A)

Vo = 3.3V, fsw = 750kHz

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

Vo = 0.6V, fsw = 200kHz

C004

±120

±90

±60

±30

120

±40

±30

±20

±10

1000 10k 100k

Phase (ƒ)

Gain (dB)

Frequency (Hz)

Gain

Phase

C006

400k

100

0 1 2 3 4 5 6 7 8 9 10

Efficiency (%)

Output Current (A)

Vo = 3.3V, fsw = 750kHz

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

Vo = 0.6V, fsw = 200kHz

C001

0 2 4 6 8 10

Output Voltage Ripple (mV)

Output Current (A)

Vo = 3.3V, fsw = 750kHz

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

Vo = 0.6V, fsw = 200kHz

C004

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6.7 Typical Characteristics (PVIN = VIN = 5 V)

The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for

the converter. Applies to Figure 7,Figure 8, and Figure 9. The temperature derating curves represent the conditions at which

internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices

soldered directly to a 100-mm × 100-mm double-sided PCB with 2-oz. copper. Applies to Figure 11.

Figure 7. Efficiency versus Output Current Figure 8. Voltage Ripple versus Output Current

Figure 9. Power Dissipation versus Output Current Figure 10. VOUT = 1.8 V, IOUT = 10 A, COUT1 = 200 Μf Ceramic,

FSW = 500 Khz

Figure 11. Safe Operating Area

0 2 4 6 8 10

Ambient Temperature (ƒC)

Output Current (A)

All Output Voltages

C001

Airflow = 0 LFM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 2 4 6 8 10

Power Dissipation (W)

Output Current (A)

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

Vo = 0.6V, fsw = 200kHz

C004

±120

±90

±60

±30

120

±40

±30

±20

±10

1000 10k 100k

Phase (ƒ)

Gain (dB)

Frequency (Hz)

Gain

Phase

C006

400k

100

0 1 2 3 4 5 6 7 8 9 10

Efficiency (%)

Output Current (A)

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

Vo = 0.6V, fsw = 200kHz

C001

0 2 4 6 8 10

Output Ripple Voltage (mV)

Output Current (A)

Vo = 2.5V, fsw = 750kHz

Vo = 1.8V, fsw = 500kHz

Vo = 1.2V, fsw = 300kHz

Vo = 0.9V, fsw = 250kHz

Vo = 0.6V, fsw = 200kHz

C004

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6.8 Typical Characteristics (PVIN = 3.3 V, VIN = 5 V)

The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for

the converter. Applies to Figure 12,Figure 13, and Figure 14. The temperature derating curves represent the conditions at

which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to

devices soldered directly to a 100-mm × 100-mm double-sided PCB with 2-oz. copper. Applies to Figure 16.

Figure 12. Efficiency versus Output Current Figure 13. Voltage Ripple versus Output Current

Figure 14. Power Dissipation versus Output Current Figure 15. VOUT = 1.8 V, IOUT = 10 A, COUT1 = 200 Μf Ceramic,

FSW = 500 Khz

Figure 16. Safe Operating Area

PWRGD

VIN

PVIN

PGND

VOUT

RT/CLK

AGND

VADJ

INH/UVLO

STSEL

SS/TR

SENSE+

LMZ31710

PWRGD

Logic

VREF Comp Power

Stage

and

Control

Logic

Thermal

Shutdown

Logic

OCP

VIN

UVLO

Oscillator

with PLL

SYNC_OUT

ILIM

Current

ISHARE

OCP_SEL

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7 Detailed Description

7.1 Overview

The LMZ31710 is a full-featured 2.95-V to 17-V input, 10-A, synchronous step-down converter with PWM,

MOSFETs, inductor, and control circuitry integrated into a low-profile, overmolded package. This device enables

small designs by integrating all but the input and output capacitors, while still leaving the ability to adjust key

parameters to meet specific design requirements. The LMZ31710 provides a wide output voltage range of 0.6 V

to 5.5 V. In most applications, a single external resistor is used to adjust the output voltage. The switching

frequency is also adjustable by using an external resistor or a synchronization pulse to accommodate various

input/output voltage conditions and to optimize efficiency. The device provides accurate voltage regulation for a

variety of loads by using an internal voltage reference that is ±1% accurate over temperature. The INH/UVLO pin

can be pulled low to put the device in standby mode to reduce input quiescent current. The input undervoltage

lockout can be adjusted using a resistor divider on the IN/UVLO pin of the device. The device provides a power-

good signal to indicate when the output is within ±5% of its nominal voltage. The ability to parallel the LMZ31710

allows it to be used in higher current applications. Thermal shutdown and current limit features protect the device

during an overload condition. Automatic pulse skip mode improves light-load efficiency. A 42-pin, QFN, package

that includes exposed bottom pads provides a thermally enhanced solution for space-constrained applications.

7.2 Functional Block Diagram

RSET VOUT

0.6

1.43

=)( (k)

( )- 1

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7.3 Feature Description

7.3.1 VIN and PVIN Input Voltage

The LMZ31710 allows for a variety of applications by using the VIN and PVIN pins together or separately. The

VIN voltage supplies the internal control circuits of the device. The PVIN voltage provides the input voltage to the

power converter system.

If tied together, the input voltage for the VIN pin and the PVIN pin can range from 4.5 V to 17 V. If you are using

the VIN pin separately from the PVIN pin, the VIN pin must be greater than 4.5 V, and the PVIN pin can range

from as low as 2.95 V to 17 V. When operating from a split rail, it is recommended to supply VIN from 5 V to 12

V for best performance. A voltage divider connected to the INH/UVLO pin can adjust either input voltage UVLO

appropriately. See the Programmable Undervoltage Lockout (UVLO) section for more information.

7.3.2 3.3-V PVIN Operation

Applications operating from a PVIN of 3.3 V must provide at least 4.5 V for VIN. It is recommended to supply VIN

from 5 V to 12 V for best performance. See the Powering LMZ3 SIMPLE SWITCHER Power Modules From 3.3 V

Application Note for help creating 5 V from 3.3 V using a small, simple charge pump device.

7.3.3 Adjusting the Output Voltage (0.6 V to 5.5 V)

The VADJ control sets the output voltage of the LMZ31710. The output voltage adjustment range of the

LMZ31710 is from 0.6 V to 5.5 V. The adjustment method requires the addition of RSET, which sets the output

voltage, the connection of SENSE+ to VOUT, and in some cases, RRT which sets the switching frequency. The

RSET resistor must be connected directly between the VADJ (pin 26) and AGND (pin 23). The SENSE+ pin (pin

27) must be connected to VOUT either at the load for improved regulation or at VOUT of the device. The RRT

resistor must be connected directly between the RT/CLK (pin 22) and AGND (pin 23). Table 1 gives the standard

external RSET resistor for a number of common bus voltages, along with the recommended RRT resistor for that

output voltage.

Table 1. Standard RSET Resistor Values for Common Output Voltages

RESISTORS OUTPUT VOLTAGE VOUT (V)

0.9 1.0 1.2 1.8 2.5 3.3 5.0

RSET (kΩ)2.87 2.15 1.43 0.715 0.453 0.316 0.196

RRT (kΩ)1000 1000 487 169 90.9 90.9 63.4

For other output voltages, the value of the required resistor can either be calculated using the following formula,

or simply selected from the range of values given in Table 2.

(1)

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Table 2. Standard RSET Resistor Values

VOUT (V) RSET (kΩ) RRT(kΩ) fSW(kHz) VOUT (V) RSET (kΩ) RRT(kΩ) fSW(kHz)

0.6 open OPEN 200 3.1 0.348 90.9 750

0.7 8.66 OPEN 200 3.2 0.332 90.9 750

0.8 4.32 OPEN 200 3.3 0.316 90.9 750

0.9 2.87 1000 250 3.4 0.309 90.9 750

1.0 2.15 1000 250 3.5 0.294 90.9 750

1.1 1.74 1000 250 3.6 0.287 90.9 750

1.2 1.43 487 300 3.7 0.280 90.9 750

1.3 1.24 487 300 3.8 0.267 90.9 750

1.4 1.07 487 300 3.9 0.261 90.9 750

1.5 0.953 487 300 4.0 0.255 90.9 750

1.6 0.866 487 300 4.1 0.243 63.4 1000

1.7 0.787 487 300 4.2 0.237 63.4 1000

1.8 0.715 169 500 4.3 0.232 63.4 1000

1.9 0.665 169 500 4.4 0.226 63.4 1000

2.0 0.619 169 500 4.5 0.221 63.4 1000

2.1 0.576 169 500 4.6 0.215 63.4 1000

2.2 0.536 169 500 4.7 0.210 63.4 1000

2.3 0.511 169 500 4.8 0.205 63.4 1000

2.4 0.475 169 500 4.9 0.200 63.4 1000

2.5 0.453 90.9 750 5.0 0.196 63.4 1000

2.6 0.432 90.9 750 5.1 0.191 63.4 1000

2.7 0.412 90.9 750 5.2 0.187 63.4 1000

2.8 0.392 90.9 750 5.3 0.182 63.4 1000

2.9 0.374 90.9 750 5.4 0.178 63.4 1000

3.0 0.357 90.9 750 5.5 0.174 63.4 1000

7.3.4 Capacitor Recommendations For the LMZ31710 Power Supply

7.3.4.1 Capacitor Technologies

7.3.4.1.1 Electrolytic, Polymer-Electrolytic Capacitors

When using electrolytic capacitors, high-quality, computer-grade electrolytic capacitors are recommended.

Polymer-electrolytic type capacitors are recommended for applications where the ambient operating temperature

is less than 0°C. The Sanyo OS-CON capacitor series is suggested due to the following:

• Lower ESR

• Higher rated surge

• Power dissipation

• Ripple current capability

• Small package size

Aluminum electrolytic capacitors provide adequate decoupling over the frequency range of 2 kHz to 150 kHz, and

are suitable when ambient temperatures are above 0°C.

7.3.4.1.2 Ceramic Capacitors

The performance of aluminum electrolytic capacitors is less effective than ceramic capacitors above 150 kHz.

Multilayer ceramic capacitors have a low ESR and a resonant frequency higher than the bandwidth of the

regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient

response of the output.

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7.3.4.1.3 Tantalum, Polymer-Tantalum Capacitors

Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is

less than 0°C. The Sanyo POSCAP series and Kemet T530 capacitor series are recommended rather than many

other tantalum types due to the following:

• Lower ESR

• Higher rated surge

• Power dissipation

• Ripple current capability

• Small package size

Tantalum capacitors that have no stated ESR or surge current rating are not recommended for power

applications.

7.3.4.2 Input Capacitor

The LMZ31710 requires a minimum input capacitance of 44 μF of ceramic type. An additional 100 µF of non-

ceramic capacitance is recommended for applications with transient load requirements. The voltage rating of

input capacitors must be greater than the maximum input voltage. At worst case, when operating at 50% duty

cycle and maximum load, the combined ripple current rating of the input capacitors must be at least 5 Arms.

Table 4 includes a preferred list of capacitors by vendor. It is also recommended to place a 0.1-µF ceramic

capacitor directly across the PVIN and PGND pins of the device. When operating with split VIN and PVIN rails,

place 4.7 µF of ceramic capacitance directly at the VIN pin.

7.3.4.3 Output Capacitor

The required output capacitance is determined by the output voltage of the LMZ31710. See Table 3 for the

amount of required capacitance. The effects of temperature and capacitor voltage rating must be considered

when selecting capacitors to meet the minimum required capacitance. The required output capacitance can be

comprised of all ceramic capacitors, or a combination of ceramic and bulk capacitors. The required capacitance

must include at least one 47-µF ceramic. When adding additional non-ceramic bulk capacitors, low-ESR devices

like the ones recommended in Table 4 are required. The required capacitance above the minimum is determined

by actual transient deviation requirements. See Table 5 for typical transient response values for several output

voltage, input voltage, and capacitance combinations. Table 4 includes a preferred list of capacitors by vendor.

(1) Minimum required must include at least one 47-µF ceramic capacitor.

Table 3. Required Output Capacitance

VOUT RANGE (V) MINIMUM REQUIRED COUT (µF)

MIN MAX

0.6 < 0.8 500 µF(1)

0.8 < 1.2 300 µF(1)

1.2 < 3.0 200 µF(1)

3.0 < 4.0 100 µF(1)

4.0 5.5 47 µF ceramic

(1) Capacitor Supplier Verification, RoHS, Lead-free, and Material Details

Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process

requirements for any capacitors identified in this table.

(2) Maximum ESR at 100 kHz, 25°C.

Table 4. Recommended Input/Output Capacitors(1)

VENDOR SERIES PART NUMBER

CAPACITOR CHARACTERISTICS

WORKING

VOLTAGE

(V)

CAPACITANCE

(µF) ESR(2)

(mΩ)

Murata X5R GRM32ER61E226K 25 22 2

TDK X5R C3225X5R0J107M 6.3 100 2

TDK X5R C3225X5R0J476K 6.3 47 2

Murata X5R GRM32ER60J107M 6.3 100 2

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Table 4. Recommended Input/Output Capacitors() (continued)

VENDOR SERIES PART NUMBER

CAPACITOR CHARACTERISTICS

WORKING

VOLTAGE

(V)

CAPACITANCE

(µF) ESR(2)

(mΩ)

Murata X5R GRM32ER60J476M 6.3 47 2

Panasonic EEH-ZA EEH-ZA1E101XP 25 100 30

Sanyo POSCAP 16TQC68M 16 68 50

Kemet T520 T520V107M010ASE025 10 100 25

Sanyo POSCAP 10TPE220ML 10 220 25

Sanyo POSCAP 6TPE100MI 6.3 100 25

Sanyo POSCAP 2R5TPE220M7 2.5 220 7

Kemet T530 T530D227M006ATE006 6.3 220 6

Kemet T530 T530D337M006ATE010 6.3 330 10

Sanyo POSCAP 2TPF330M6 2.0 330 6

Sanyo POSCAP 6TPE330MFL 6.3 330 15

7.3.5 Transient Response

Table 5. Output Voltage Transient Response

CIN1 = 3x 47-µF CERAMIC, CIN2 = 100-µF POLYMER-TANTALUM

VOUT (V) VIN (V) COUT1 CERAMIC COUT2 BULK VOLTAGE DEVIATION (mV) RECOVERY TIME

(µs)

2.5-A LOAD STEP,

(1 A/µs) 5-A LOAD STEP,

(1 A/µs)

0.6 5 500 µF 220 µF 25 60 100

12 500 µF 220 µF 30 65 100

0.9 5300 µF 220 µF 40 85 100

300 µF 470 µF 35 70 110

12 300 µF 220 µF 45 90 100

300 µF 470 µF 35 75 110

1.2 5200 µF 220 µF 55 110 110

200 µF 470 µF 45 90 110

12 200 µF 220 µF 55 110 110

200 µF 470 µF 45 90 110

1.8 5200 µF 220 µF 70 140 130

200 µF 470 µF 60 120 140

12 200 µF 220 µF 70 145 140

200 µF 470 µF 55 120 150

3.3 5 100 µF 220 µF 115 230 200

12 100 µF 220 µF 120 240 200

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7.3.5.1 Transient Response Waveforms

PVin = 12 V Vout = 0.9 V 2.5-A Load Step

Figure 17. Transient Response (12 V to 0.9 V)

PVin = 5 V Vout = 0.9 V 2.5-A Load Step

Figure 18. Transient Response (5 V to 0.9 V)

PVin = 12 V Vout = 1.2 V 2.5-A Load Step

Figure 19. Transient Response (12 V to 1.2 V)

PVin = 5 V Vout = 1.2 V 2.5-A Load Step

Figure 20. Transient Response (5 V to 1.2 V)

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PVin = 12 V Vout = 1.8 V 2.5-A Load Step

Figure 21. Transient Response (12 V to 1.8 V)

PVin = 5 V Vout = 1.8 V 2.5-A Load Step

Figure 22. Transient Response (5 V to 1.8 V)

7.3.6 Power Good (PWRGD)

The PWRGD pin is an open-drain output. Once the voltage on the SENSE+ pin is between 95% and 104% of the

set voltage, the PWRGD pin pulldown is released, and the pin floats. The recommended pullup resistor value is

between 10 kΩand 100 kΩto a voltage source that is 5.5 V or less. The PWRGD pin is in a defined state once

VIN is greater than 1 V, but with reduced current sinking capability. The PWRGD pin achieves full current sinking

capability once the VIN pin is above 4.5 V. The PWRGD pin is pulled low when the voltage on SENSE+ is lower

than 91% or greater than 108% of the nominal set voltage. Also, the PWRGD pin is pulled low if the input UVLO

or thermal shutdown is asserted, the INH pin is pulled low, or the SS/TR pin is below 1.4 V.

7.3.7 Light Load Efficiency (LLE)

The LMZ31710 operates in pulse skip mode at light load currents to improve efficiency and decrease power

dissipation by reducing switching and gate drive losses.

These pulses can cause the output voltage to rise when there is no load to discharge the energy. For output

voltages < 1.5 V, a minimum load is required. The amount of required load can be determined by Equation 2. In

most cases, the minimum current drawn by the load circuit will be enough to satisfy this load. For applications

requiring a load resistor to meet the minimum load, the added power dissipation will be ≤3.6 mW. A single 0402

size resistor across VOUT and PGND can be used.

(2)

When VOUT = 0.6 V and RSET = OPEN, the minimum load current is 600 µA.

7.3.8 SYNC_OUT

The LMZ31710 provides a 180° out-of-phase clock signal for applications requiring synchronization. The

SYNC_OUT pin produces a 50% duty cycle clock signal that is the same frequency as the switching frequency of

the device, but is 180° out-of-phase. Operating two devices 180° out-of-phase reduces input and output voltage

ripple. The SYNC_OUT clock signal is compatible with other LMZ3 devices that have a CLK input.

PVIN

LMZ31710

INH/UVLO

SS/TR

VIN

= 12V

= 1.8V

RT/CLK

VADJ

SET

22µF

220µF

100µF 330µF

715 Ω

PVIN

VIN

100µF

ISHARE

INH/UVLO

SS/TR

RT/CLK

VADJ

ISHARE

Sync Freq

500KHz

LMZ31710

169kΩ

INH

Control

Voltage

Supervisor

VOUT

SENSE+

PWRGD

AGND

PGND

STSEL

VOUT

SENSE+

PWRGD

100µF

SYNC_OUT

AGND

PGND

STSEL

0.1µF

22µF 0.1µF

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7.3.9 Parallel Operation

Up to six LMZ31710 devices can be paralleled for increased output current. Multiple connections must be made

between the paralleled devices and the component selection is slightly different than for a stand-alone

LMZ31710 device. A typical LMZ31710 parallel schematic is shown in Figure 23. Refer to the LMZ31710 Parallel

Operation Application Note for information and design help when paralleling multiple LMZ31710 devices.

Additionally, an EVM featuring two LMZ31710 devices operating in parallel can be evaluated using the

LMZ31710 Parallel User's Guide.

Figure 23. Typical LMZ31710 Parallel Schematic

7.3.10 Power-Up Characteristics

When configured as shown in the application circuit on the first page, the LMZ31710 produces a regulated output

voltage following the application of a valid input voltage. During the power-up, internal soft-start circuitry slows

the rate that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the

input source. Figure 24 shows the start-up waveforms for a LMZ31710, operating from a 5-V input (PVIN = VIN)

and with the output voltage adjusted to 1.8 V. Figure 25 shows the start-up waveforms for a LMZ31710 starting

up into a pre-biased output voltage. The waveforms were measured with a 5-A constant current load.

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Figure 24. Start-Up Waveforms Figure 25. Start-Up Into Pre-Bias

7.3.11 Pre-Biased Start-Up

The LMZ31710 has been designed to prevent the low-side MOSFET from discharging a pre-biased output.

During pre-biased startup, the low-side MOSFET does not turn on until the high-side MOSFET has started

switching. The high-side MOSFET does not start switching until the slow start voltage exceeds the voltage on the

VADJ pin. See Figure 25.

7.3.12 Remote Sense

The SENSE+ pin must be connected to VOUT at the load, or at the device pins.

Connecting the SENSE+ pin to VOUT at the load improves the load regulation performance of the device by

allowing it to compensate for any I-R voltage drop between its output pins and the load. An I-R drop is caused by

the high output current flowing through the small amount of pin and trace resistance. This must be limited to a

maximum of 300 mV.

NOTE

The remote sense feature is not designed to compensate for the forward drop of nonlinear

or frequency dependent components that can be placed in series with the converter

output. Examples include OR-ing diodes, filter inductors, ferrite beads, and fuses. When

these components are enclosed by the SENSE+ connection, they are effectively placed

inside the regulation control loop, which can adversely affect the stability of the regulator.

7.3.13 Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds

175°C typically. The device reinitiates the power-up sequence when the junction temperature drops below 165°C

typically.

7.3.14 Output On/Off Inhibit (INH)

The INH pin provides electrical on/off control of the device. Once the INH pin voltage exceeds the threshold

voltage, the device starts operation. If the INH pin voltage is pulled below the threshold voltage, the regulator

stops switching and enters low quiescent current state. The INH pin has an internal pullup current source,

allowing the user to float the INH pin for enabling the device.

If an application requires controlling the INH pin, use an open-drain/collector device, or a suitable logic gate to

interface with the pin. Using a voltage supervisor to control the INH pin allows control of the turnon and turnoff of

the device as opposed to relying on the ramp up or down if the input voltage source.

INH/UVLO

STSELAGND

INH

Control SS/TR

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Figure 26 shows the typical application of the inhibit function. Turning Q1 on applies a low voltage to the inhibit

control (INH) pin and disables the output of the supply, shown in Figure 27. If Q1 is turned off, the supply

executes a soft-start power-up sequence, as shown in Figure 28. A regulated output voltage is produced within

2 ms. The waveforms were measured with a 5-A constant current load.

Figure 26. Typical Inhibit Control

Figure 27. Inhibit Turnoff Figure 28. Inhibit Turnon

7.3.15 Slow Start (SS/TR)

Connecting the STSEL pin to AGND and leaving SS/TR pin open enables the internal SS capacitor with a slow-

start interval of approximately 1.2 ms. Adding additional capacitance between the SS pin and AGND increases

the slow-start time. Increasing the slow-start time will reduce inrush current seen by the input source and reduce

the current seen by the device when charging the output capacitors. To avoid the activation of current limit and

ensure proper start-up, the SS capacitor may need to be increased when operating near the maximum output

capacitance limit.

Table 6 shows an additional SS capacitor connected to the SS/TR pin and the STSEL pin connected to AGND.

See Table 6 for SS capacitor values and timing interval.

SS/TR

STSELAGND

(Optional)

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Figure 29. Slow-Start Capacitor (CSS) And STSEL Connection

Table 6. Slow-Start Capacitor Values And Slow-Start Time

CSS (nF) OPEN 3.3 4.7 10 15 22 33

SS Time (msec) 1.2 2.1 2.5 3.8 5.1 7.0 9.8

7.3.16 Overcurrent Protection

For protection against load faults, the LMZ31710 incorporates output overcurrent protection. The overcurrent

protection mode can be selected using the OCP_SEL pin. Leaving the OCP_SEL pin open selects hiccup mode

and connecting it to AGND selects cycle-by-cycle mode. In hiccup mode, applying a load that exceeds the

overcurrent threshold of the regulator causes the regulated output to shut down. Following shutdown, the module

periodically attempts to recover by initiating a soft-start power-up as shown in Figure 30. This is described as a

hiccup mode of operation, where the module continues in a cycle of successive shutdown and power-up until the

load fault is removed. During this period, the average current flowing into the fault is significantly reduced, which

reduces power dissipation. Once the fault is removed, the module automatically recovers and returns to normal

operation as shown in Figure 31.

In cycle-by-cycle mode, applying a load that exceeds the overcurrent threshold of the regulator limits the output

current and reduces the output voltage as shown in Figure 32. During this period, the current flowing into the

fault remains high, causing the power dissipation to stay high as well. Once the overcurrent condition is removed,

the output voltage returns to the set-point voltage as shown in Figure 33.

Figure 30. Overcurrent Limiting (Hiccup) Figure 31. Removal Of Overcurrent (Hiccup)

AGND

RT/CLK

External Clock

200 kHz to 1200 kHz

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Figure 32. Overcurrent Limiting (Cycle-By-Cycle) Figure 33. Removal Of Overcurrent (Cycle-By-Cycle)

7.3.17 Synchronization (CLK)

An internal phase locked loop (PLL) has been implemented to allow synchronization between 200 kHz and

1200 kHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect

a square wave clock signal to the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude

must transition lower than 0.5 V and higher than 2 V. The start of the switching cycle is synchronized to the

falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be

configured as shown in Figure 34.

Before the external clock is present, the device works in RT mode and the switching frequency is set by RT

resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is

pulled above the RT/CLK high threshold (2 V), the device switches from RT mode to CLK mode and the RT/CLK

pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not

recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to

100 kHz first before returning to the switching frequency set by the RT resistor (RRT).

Figure 34. RT/CLK Configuration

The switching frequency must be selected based on the output voltages of the devices being synchronized.

Table 7 shows the allowable frequencies for a given range of output voltages. The allowable switching frequency

changes based on the maximum output current (IOUT) of an application. The table shows the VOUT range when

IOUT ≤10 A, 9 A, and 8 A. For the most efficient solution, always synchronize to the lowest allowable frequency.

For example, an application requires synchronizing three LMZ31710 devices with output voltages of 1.0 V, 1.2 V,

and 1.8 V, all powered from PVIN = 12 V. Table 7 shows that all three output voltages must be synchronized to

300 kHz.

( ) ( )

= W

OUT2

0.6 R1

R2 k

V 0.6

( ) ( )

= W

OUT2

V 12.6

R1 k

0.6

STSEL

INH/UVLO

PWRGD

VOUT

OUT1

STSEL

INH/UVLO

PWRGD

VOUT

OUT2

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Table 7. Allowable Switching Frequency versus Output Voltage

SWITCHING

FREQUENCY

(kHz)

PVIN = 12 V PVIN = 5 V

VOUT RANGE (V) VOUT RANGE (V)

IOUT ≤10 A IOUT ≤9 A IOUT ≤8 A IOUT ≤10 A IOUT ≤9 A IOUT ≤8 A

200 0.6 - 1.2 0.6 - 1.6 0.6 - 2.0 0.6 - 1.5 0.6 - 2.5 0.6 - 4.3

300 0.8 - 1.9 0.8 - 2.6 0.8 - 3.5 0.6 - 4.3 0.6 - 4.3 0.6 - 4.3

400 1.0 - 2.7 1.0 - 4.0 1.0 - 5.5 0.6 - 4.3 0.6 - 4.3 0.6 - 4.3

500 1.3 - 3.8 1.3 - 5.5 1.3 - 5.5 0.6 - 4.2 0.6 - 4.2 0.6 - 4.3

600 1.5 - 5.5 1.5 - 5.5 1.5 - 5.5 0.8 - 4.1 0.8 - 4.2 0.7 - 4.2

700 1.8 - 5.5 1.8 - 5.5 1.8 - 5.5 0.9 - 4.0 0.9 - 4.1 0.8 - 4.1

800 2.0 - 5.5 2.0 - 5.5 2.0 - 5.5 1.0 - 3.9 1.0 - 4.0 1.0 - 4.0

900 2.2 - 5.5 2.2 - 5.5 2.2 - 5.5 1.2 - 3.8 1.1 - 3.9 1.1 - 3.9

1000 2.5 - 5.5 2.5 - 5.5 2.5 - 5.5 1.4 - 3.7 1.3 - 3.8 1.3 - 3.8

1100 2.7 - 5.5 2.7 - 5.5 2.7 - 5.5 1.4 - 3.6 1.4 - 3.7 1.4 - 3.7

1200 3.0 - 5.5 3.0 - 5.5 3.0 - 5.5 1.5 - 3.6 1.5 - 3.6 1.5 - 3.6

7.3.18 Sequencing (SS/TR)

Many of the common power supply sequencing methods can be implemented using the SS/TR, INH, and

PWRGD pins. The sequential method is illustrated in Figure 35 using two LMZ31710 devices. The PWRGD pin

of the first device is coupled to the INH pin of the second device, which enables the second power supply once

the primary supply reaches regulation. Figure 36 shows sequential turnon waveforms of two LMZ31710 devices.

Figure 35. Sequencing Schematic Figure 36. Sequencing Waveforms

Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2

shown in Figure 37 to the output of the power supply that needs to be tracked or to another voltage reference

source. The tracking voltage must exceed 750 mV before VOUT2 reaches its set-point voltage. The PWRGD

output of the VOUT2 device can remain low if the tracking voltage does not exceed 1.4 V. Figure 38 shows

simultaneous turnon waveforms of two LMZ31710 devices. Equation 3 and Equation 4 calculate the values of R1

and R2.

(3)

(4)

INH/UVLO

PVIN

VIN

UVLO1

UVLO2

INH/UVLO

PVIN

VIN

UVLO1

UVLO2

SS/TR

INH/UVLO

VOUT

STSEL

SS/TR

INH/UVLO

VOUT

STSEL

OUT1

OUT2

LMZ31710

SNVS987F –JULY 2013–REVISED MAY 2020

www.ti.com

Product Folder Links: LMZ31710

Figure 37. Simultaneous Tracking Schematic Figure 38. Simultaneous Tracking Waveforms

7.4 Device Functional Modes

7.4.1 Programmable Undervoltage Lockout (UVLO)

The LMZ31710 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin

voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 4.5 V(max) with a

typical hysteresis of 150 mV.

If an application requires either a higher UVLO threshold on the VIN pin or a higher UVLO threshold for a

combined VIN and PVIN, then the UVLO pin can be configured as shown in Figure 39 or Figure 40.Table 8 lists

standard values for RUVLO1 and RUVLO2 to adjust the VIN UVLO voltage up.

Figure 39. Adjustable VIN UVLO Figure 40. Adjustable VIN And Pvin Undervoltage Lockout

Table 8. Standard Resistor Values For Adjusting VIN UVLO

VIN UVLO (V) 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10

RUVLO1 (kΩ)68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1 68.1

RUVLO2 (kΩ)21.5 18.7 16.9 15.4 14.0 13.0 12.1 11.3 10.5 9.76 9.31

Hysteresis (mV) 400 415 430 450 465 480 500 515 530 550 565

INH/UVLO

VIN

PVIN

UVLO1

UVLO2

> 4.5 V

LMZ31710

www.ti.com

SNVS987F –JULY 2013–REVISED MAY 2020

Product Folder Links: LMZ31710

For a split rail application, if a secondary UVLO on PVIN is required, VIN must be ≥4.5 V. Figure 41 shows the

PVIN UVLO configuration. Use Table 9 to select RUVLO1 and RUVLO2 for PVIN. If PVIN UVLO is set for less than

3.5 V, a 5.1-V zener diode must be added to clamp the voltage on the UVLO pin below 6 V.

Figure 41. Adjustable PVIN Undervoltage Lockout, (VIN ≥4.5 V)

Table 9. Standard Resistor Values For Adjusting Pvin UVLO, (VIN ≥4.5 V)

PVIN UVLO (V) 2.9 3.0 3.5 4.0 4.5

RUVLO1 (kΩ)68.1 68.1 68.1 68.1 68.1 For higher PVIN UVLO voltages, see

Table 8 for resistor values

RUVLO2 (kΩ)47.5 44.2 34.8 28.7 24.3

Hysteresis (mV) 330 335 350 365 385

LMZ31710

PWRGD

SENSE+

VOUT

VIN

PVIN

INH/UVLO

RT/CLK

IN2

47 µF

VADJ

SS/TR

STSEL AGND PGND

IN1

100 µF

SET

1.43 k

OUT1

2x 100 µF

OUT2

220 µF

OUT

1.2 V

/ P

VIN

4.5 V to 17 V

487 k

ISHARE

SYNC_OUT

IN3

0.1 µF

LMZ31710

SNVS987F –JULY 2013–REVISED MAY 2020

www.ti.com

Product Folder Links: LMZ31710

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LMZ31710 power module is an easy-to-use integrated power solution that combines a 10-A DC/DC

converter with power MOSFETs, a shielded inductor, and passives into a low profile, QFN package. This total

power solution allows as few as three external components and eliminates the loop compensation and magnetics

part selection process.

8.2 Typical Application

A typical LMZ31710 application requires input and output capacitors, a voltage setting resistor, and a switching

frequency setting resistor. Figure 42 shows a typical LMZ31710 schematic with only the minimum required

components.

Figure 42. Typical Schematic

PVIN = VIN = 4.5 V To 17 V, VOUT = 1.2 V

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 10 and follow these design procedures:

Table 10. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE

Input voltage 11.4 V to 12.6 V

Output voltage 1.2 V

Output current 10 A

RSET VOUT

0.6

1.43

=)( (k)

( )- 1

LMZ31710

www.ti.com

SNVS987F –JULY 2013–REVISED MAY 2020

Product Folder Links: LMZ31710

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMZ31710 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Setting The Output Voltage

The output voltage of the LMZ31710 is externally adjustable using a single resistor (RSET). Select the value of

RSET from Table 2 or calculate using Equation 5.

(5)

To set the output voltage to 1.2 V, the calculated value for RSET is 1.43 kΩ.

8.2.2.3 Setting the Switching Frequency

The recommended switching frequency for 1.2-V output voltage is 300 kHz. To set the switching frequency to

300 kHz, a 487-kΩRRT resistor is required. Refer to Table 2 for recommended switching frequencies for other

output voltages.

8.2.2.4 Input Capacitance

The minimum required input capacitance for the LMZ31710 is 44 µF of ceramic capacitance. However, adding a

0.1-µF ceramic capacitor placed directly at the input pins of the device will help with high frequency bypassing.

Additionally, adding a bulk input capacitor is helpful in applications with fast changing load current.

In this application, a combination of a 100-µF bulk capacitor, a 47-µF ceramic capacitor, and a 0.1-µF ceramic

capacitor was used.

8.2.2.5 Output Capacitance

The amount of required output capacitance depends on the output voltage setting, as shown in Table 3. For an

output voltage of 1.2 V, the required minimum output capacitance is 200 µF, with a requirement that at least

47 µF must be ceramic type.

In this application, a combination of a 200 µF of ceramic capacitance and a 220-µF bulk capacitor was used. The

additional 220-µF bulk capacitor will help in applications with fast changing load current.

8.3 Additional Application Schematics

Figure 43 and Figure 44 show additional typical schematics. Figure 43 shows a typical schematic for a 3.3-V

output while PVIN and VIN are tied to the same input voltage rail. Figure 44 shows a typical schematic for a

1.0 V output, however PVIN and VIN are powered from separate input voltage rails.

4.5 V to 17 V

IN3

4.7 µF LMZ31710

PWRGD

SENSE+

VOUT

VIN

PVIN

INH/UVLO

RT/CLK

IN2

47 µF

VADJ

SS/TR

STSEL AGND PGND

IN1

100 µF

SET

2.15 k

OUT1

3x 100 µF

OUT2

220 µF

OUT

1.0 V

VIN

3.3 V

1 M

ISHARE

SYNC_OUT

IN3

0.1 µF

LMZ31710

PWRGD

SENSE+

VOUT

VIN

PVIN

INH/UVLO

RT/CLK

IN2

47 µF

VADJ

SS/TR

STSEL AGND PGND

IN1

100 µF

SET

316

OUT1

100 µF

OUT2

220 µF

OUT

3.3 V

/ P

VIN

4.5 V to 17 V

90.9 k

ISHARE

SYNC_OUT

IN3

0.1 µF

LMZ31710

SNVS987F –JULY 2013–REVISED MAY 2020

www.ti.com

Product Folder Links: LMZ31710

Additional Application Schematics (continued)

Figure 43. Typical Schematic

PVIN = VIN = 4.5 V To 17 V, Vout = 3.3 V

Figure 44. Typical Schematic

PVIN = 3.3 V, VIN = 4.5 V To 17 V, Vout = 1.0 V

9 Power Supply Recommendations

The LMZ31710 is designed to operate from an input voltage supply range between 2.95 V and 17 V. This input

supply must be well-regulated and able to withstand maximum input current and maintain a stable voltage. The

resistance of the input supply rail must be low enough that an input current transient does not cause a high

enough drop at the supply voltage that can cause a false UVLO fault triggering and system reset.

If the input supply is located more than a few inches from the LMZ31710, additional bulk capacitance can be

required at the input pins. A typical recommended amount of bulk input capacitance is 47 μF - 100 μF.

LMZ31710

www.ti.com

SNVS987F –JULY 2013–REVISED MAY 2020

Product Folder Links: LMZ31710

10 Layout

10.1 Layout Considerations

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 45 through

Figure 48 shows a typical PCB layout. Some considerations for an optimized layout are:

• Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal

stress.

• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.

• Locate additional output capacitors between the ceramic capacitor and the load.

• Keep AGND and PGND separate from one another.

• Place RSET, RRT, and CSS as close as possible to their respective pins.

• Use multiple vias to connect the power planes to internal layers.

10.2 Layout Examples

Figure 45. Typical Top-Layer Layout Figure 46. Typical Layer-2 Layout

LMZ31710

SNVS987F –JULY 2013–REVISED MAY 2020

www.ti.com

Product Folder Links: LMZ31710

Layout Examples (continued)

Figure 47. Typical Layer 3 Layout Figure 48. Typical Bottom-Layer Layout

10.2.1 EMI

The LMZ31710 is compliant with EN55022 Class B radiated emissions. Figure 49 and Figure 50 show typical

examples of radiated emissions plots for the LMZ31710 operating from 5 V and 12 V, respectively. Both graphs

include the plots of the antenna in the horizontal and vertical positions.

Figure 49. Radiated Emissions 5-V Input, 1.8-V Output, 10-

A Load (En55022 Class B) Figure 50. Radiated Emissions 12-V Input, 1.8-V Output,

10-A Load (EN55022 Class B)

LMZ31710

www.ti.com

SNVS987F –JULY 2013–REVISED MAY 2020

Product Folder Links: LMZ31710

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMZ31710 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.1.2 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation see the following:

• Texas Instruments, LMZ31710 EVM User's Guide

• Texas Instruments, LMZ31710 Parallel EVM User's Guide

• Texas Instruments, LMZ31707 (7A) Datasheet

• Texas Instruments, LMZ31704 (4A) Datasheet

• Texas Instruments, Soldering Requirements for BQFN Packages

11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

11.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

11.5 Trademarks

Eco-Mode, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

Reel Width (W1)

REEL DIMENSIONS

Dimension designed to accommodate the component length

Dimension designed to accommodate the component thickness

Overall width of the carrier tape

Pitch between successive cavity centers

Dimension designed to accommodate the component width

TAPE DIMENSIONS

K0 P1

B0 W

Cavity

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Pocket Quadrants

Sprocket Holes

Q1 Q1

Q2 Q2

Q3 Q3Q4 Q4

Reel

Diameter

User Direction of Feed

LMZ31710

SNVS987F –JULY 2013–REVISED MAY 2020

www.ti.com

Product Folder Links: LMZ31710

11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

12.1 Tape and Reel Information

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width W1

(mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMZ31710RVQR B3QFN RVQ 42 500 330.0 24.4 10.35 10.35 4.6 16.0 24.0 Q2

LMZ31710RVQT B3QFN RVQ 42 250 330.0 24.4 10.35 10.35 4.6 16.0 24.0 Q2

TAPE AND REEL BOX DIMENSIONS

Width (mm)

LMZ31710

www.ti.com

SNVS987F –JULY 2013–REVISED MAY 2020

Product Folder Links: LMZ31710

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMZ31710RVQR B3QFN RVQ 42 500 383.0 353.0 58.0

LMZ31710RVQT B3QFN RVQ 42 250 383.0 353.0 58.0

PACKAGE OPTION ADDENDUM

www.ti.com 28-Jun-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMZ31710RVQR ACTIVE B3QFN RVQ 42 500 RoHS Exempt

& Green NIPDAU Level-3-245C-168 HR -40 to 85 (54020, LMZ31710)

LMZ31710RVQT ACTIVE B3QFN RVQ 42 250 RoHS Exempt

& Green NIPDAU Level-3-245C-168 HR -40 to 85 (54020, LMZ31710)

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 28-Jun-2020

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMZ31710RVQR B3QFN RVQ 42 500 330.0 24.4 10.35 10.35 4.6 16.0 24.0 Q2

LMZ31710RVQT B3QFN RVQ 42 250 330.0 24.4 10.35 10.35 4.6 16.0 24.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 10-Mar-2021

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMZ31710RVQR B3QFN RVQ 42 500 383.0 353.0 58.0

LMZ31710RVQT B3QFN RVQ 42 250 383.0 353.0 58.0

PACKAGE MATERIALS INFORMATION

www.ti.com 10-Mar-2021

Pack Materials-Page 2

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