This is information on a product in full production.
July 2017 DocID025976 Rev 5 1/262
STM32L476xx
Ultra-low-power ARM® Cortex®-M4 32-bit MCU+FPU, 100DMIPS,
up to 1MB Flash, 128 KB SRAM, USB OTG FS, LCD, ext. SMPS
Datasheet - production data
Features
•Ultra-low-power with FlexPowerControl
– 1.71 V to 3.6 V power supply
– -40 °C to 85/105/125 °C temperature range
– 300 nA in VBAT mode: supply for RTC and
32x32-bit backup registers
– 30 nA Shutdown mode (5 wakeup pins)
– 120 nA Standby mode (5 wakeup pins)
– 420 nA Standby mode with RTC
– 1.1 µA Stop 2 mode, 1.4 µA with RTC
– 100 µA/MHz run mode (LDO Mode)
–39 A/MHz run mode (@3.3 V SMPS
Mode)
– Batch acquisition mode (BAM)
– 4 µs wakeup from Stop mode
– Brown out reset (BOR)
– Interconnect matrix
•Core: ARM® 32-bit Cortex®-M4 CPU with FPU,
Adaptive real-time accelerator (ART
Accelerator™) allowing 0-wait-state execution
from Flash memory, frequency up to 80 MHz,
MPU, 100DMIPS and DSP instructions
•Performance benchmark
– 1.25 DMIPS/MHz (Drystone 2.1)
– 273.55 CoreMark® (3.42 CoreMark/MHz @
80 MHz)
•Energy benchmark
– 220 ULPBENCH® score
•Clock Sources
– 4 to 48 MHz crystal oscillator
– 32 kHz crystal oscillator for RTC (LSE)
– Internal 16 MHz factory-trimmed RC (±1%)
– Internal low-power 32 kHz RC (±5%)
– Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
±0.25 % accuracy)
– 3 PLLs for system clock, USB, audio, ADC
•Up to 114 fast I/Os, most 5 V-tolerant, up to 14
I/Os with independent supply down to 1.08 V
•RTC with HW calendar, alarms and calibration
•LCD 8× 40 or 4× 44 with step-up converter
•Up to 24 capacitive sensing channels: support
touchkey, linear and rotary touch sensors
•16x timers: 2x 16-bit advanced motor-control,
2x 32-bit and 5x 16-bit general purpose, 2x 16-
bit basic, 2x low-power 16-bit timers (available
in Stop mode), 2x watchdogs, SysTick timer
•Memories
– Up to 1 MB Flash, 2 banks read-while-
write, proprietary code readout protection
– Up to 128 KB of SRAM including 32 KB
with hardware parity check
– External memory interface for static
memories supporting SRAM, PSRAM,
NOR and NAND memories
– Quad SPI memory interface
•4x digital filters for sigma delta modulator
•Rich analog peripherals (independent supply)
– 3× 12-bit ADC 5 Msps, up to 16-bit with
hardware oversampling, 200 µA/Msps
– 2x 12-bit DAC, low-power sample and hold
– 2x operational amplifiers with built-in PGA
– 2x ultra-low-power comparators
•20x communication interfaces
– USB OTG 2.0 full-speed, LPM and BCD
– 2x SAIs (serial audio interface)
–3x I2C FM+(1 Mbit/s), SMBus/PMBus
– 5x USARTs (ISO 7816, LIN, IrDA, modem)
– 1x LPUART (Stop 2 wake-up)
– 3x SPIs (4x SPIs with the Quad SPI)
(7 × 7)
LQFP144 (20 × 20)
LQFP100 (14 x 14)
LQFP64 (10 x 10)
UFBGA132 WLCSP72
WLCSP81
www.st.com
STM32L476xx
2/262 DocID025976 Rev 5
– CAN (2.0B Active) and SDMMC interface
– SWPMI single wire protocol master I/F
– IRTIM (Infrared interface)
•14-channel DMA controller
•True random number generator
•CRC calculation unit, 96-bit unique ID
•Development support: serial wire debug
(SWD), JTAG, Embedded Trace Macrocell™
Table 1. Device summary
Reference Part numbers
STM32L476xx
STM32L476RG, STM32L476JG, STM32L476MG, STM32L476ME, STM32L476VG,
STM32L476QG, STM32L476ZG, STM32L476RE, STM32L476JE, STM32L476VE,
STM32L476QE, STM32L476ZE, STM32L476RC, STM32L476VC
DocID025976 Rev 5 3/262
STM32L476xx Contents
6
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 ARM® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Adaptive real-time memory accelerator (ART Accelerator™) . . . . . . . . . 18
3.3 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6 Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.8 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 21
3.9 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.9.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.9.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.9.6 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.10 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.11 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.12 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.13 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.14 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.14.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 40
3.14.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 40
3.15 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.15.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.15.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.15.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.16 Digital to analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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3.17 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.18 Comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.19 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.20 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.21 Liquid crystal display controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.22 Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 45
3.23 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.24 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.24.1 Advanced-control timer (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.24.2 General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM15, TIM16,
TIM17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.24.3 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.24.4 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 49
3.24.5 Infrared interface (IRTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.24.6 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.24.7 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.24.8 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.25 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 51
3.26 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.27 Universal synchronous/asynchronous receiver transmitter (USART) . . . 53
3.28 Low-power universal asynchronous receiver transmitter (LPUART) . . . . 54
3.29 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.30 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.31 Single wire protocol master interface (SWPMI) . . . . . . . . . . . . . . . . . . . . 56
3.32 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.33 Secure digital input/output and MultiMediaCards Interface (SDMMC) . . . 57
3.34 Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 57
3.35 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 58
3.36 Quad SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.37 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.37.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.37.2 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . 114
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . 115
6.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.3.6 Wakeup time from low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
6.3.10 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.3.16 Extended interrupt and event controller input (EXTI) characteristics . . 171
6.3.17 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
6.3.18 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . 172
6.3.19 Digital-to-Analog converter characteristics . . . . . . . . . . . . . . . . . . . . . 185
6.3.20 Voltage reference buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . 190
6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.3.22 Operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
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6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
6.3.25 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.3.26 DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.3.27 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.3.28 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 203
6.3.29 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6.3.30 SWPMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
7.1 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
7.2 UFBGA132 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
7.3 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
7.4 WLCSP81 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
7.5 WLCSP72 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
7.6 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
7.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
7.7.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 253
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
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STM32L476xx List of tables
10
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32L476xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 19
Table 4. STM32L476xx modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5. Functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. STM32L476xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 8. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 9. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 10. DFSDM1 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 11. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 12. I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 13. STM32L476xx USART/UART/LPUART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 14. SAI implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 15. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 16. STM32L476xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 17. Alternate function AF0 to AF7 (for AF8 to AF15 see Table 18) . . . . . . . . . . . . . . . . . . . . . 87
Table 18. Alternate function AF8 to AF15 (for AF0 to AF7 see Table 17) . . . . . . . . . . . . . . . . . . . . . 94
Table 19. STM32L476xx memory map and peripheral register boundary addresses . . . . . . . . . . . 103
Table 20. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 21. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 22. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 23. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 24. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 25. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 26. Embedded internal voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 27. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 120
Table 28. Current consumption in Run modes, code with data processing running from Flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 29. Current consumption in Run and Low-power run modes, code with data processing
running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 30. Current consumption in Run modes, code with data processing running from Flash,
ART disable and power supplied by external SMPS (VDD12 = 1.10 V). . . . . . . . . . . . . . 123
Table 31. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 32. Current consumption in Run, code with data processing running from
SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . 125
Table 33. Typical current consumption in Run and Low-power run modes, with different codes
running from Flash, ART enable (Cache ON Prefetch OFF) . . . . . . . . . . . . . . . . . . . . . . 126
Table 34. Typical current consumption in Run, with different codes running from Flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 35. Typical current consumption in Run, with different codes running from Flash,
ART enable (Cache ON Prefetch OFF) and power supplied by external SMPS
(VDD12 = 1.05 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 36. Typical current consumption in Run and Low-power run modes, with different codes
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8/262 DocID025976 Rev 5
running from Flash, ART disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 37. Typical current consumption in Run modes, with different codes running from
Flash, ART disable and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . 128
Table 38. Typical current consumption in Run modes, with different codes running
from Flash, ART disable and power supplied by external SMPS (VDD12 = 1.05 V) . . . . 128
Table 39. Typical current consumption in Run and Low-power run modes, with different codes
running from SRAM1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 40. Typical current consumption in Run mode, with different codes running from
SRAM1 and power supplied by external SMPS (VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . 129
Table 41. Typical current consumption in Run mode, with different codes running from
SRAM1 and power supplied by external SMPS (VDD12 = 1.05 V) . . . . . . . . . . . . . . . . . 130
Table 42. Current consumption in Sleep and Low-power sleep modes, Flash ON . . . . . . . . . . . . . 131
Table 43. Current consumption in Sleep, Flash ON and power supplied by external SMPS
(VDD12 = 1.10 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 44. Current consumption in Low-power sleep modes, Flash in power-down . . . . . . . . . . . . . 132
Table 45. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 46. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 47. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 48. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 49. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 50. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 51. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 52. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 53. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 54. Wakeup time using USART/LPUART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 55. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 56. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 57. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 58. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 59. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 60. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
Table 61. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 62. PLL, PLLSAI1, PLLSAI2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 63. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 64. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 65. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 66. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 67. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 68. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 69. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 70. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 71. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 72. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 73. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 74. EXTI Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 75. Analog switches booster characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 76. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 77. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 78. ADC accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 79. ADC accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 80. ADC accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 81. ADC accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
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Table 82. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Table 83. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 84. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 85. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 86. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 87. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 88. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 89. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 90. LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 91. DFSDM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Table 92. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 93. IWDG min/max timeout period at 32 kHz (LSI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 94. WWDG min/max timeout value at 80 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 95. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 96. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 97. Quad SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 98. QUADSPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 99. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 100. SD / MMC dynamic characteristics, VDD=2.7 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 101. eMMC dynamic characteristics, VDD = 1.71 V to 1.9 V . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 102. USB OTG DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 103. USB OTG electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 104. USB BCD DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 105. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . 218
Table 106. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . 218
Table 107. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 219
Table 108. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . 220
Table 109. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 110. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 221
Table 111. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 112. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 223
Table 113. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 114. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 115. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 228
Table 116. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 117. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 118. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Table 119. SWPMI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 120. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Table 121. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Table 122. UFBGA132 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 239
Table 123. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Table 124. WLCSP81- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 125. WLCSP81 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . 245
Table 126. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip
scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 127. WLCSP72 recommended PCB design rules (0.4 mm pitch BGA) . . . . . . . . . . . . . . . . . . 248
Table 128. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
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10/262 DocID025976 Rev 5
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Table 129. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Table 130. STM32L476xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Table 131. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
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List of figures
Figure 1. STM32L476xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 4. Voltage reference buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 5. STM32L476Zx LQFP144 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 6. STM32L476Zx, external SMPS device, LQFP144 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 7. STM32L476Qx UFBGA132 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 8. STM32L476Vx LQFP100 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 9. STM32L476Mx WLCSP81 ballout(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 10. STM32L476Jx WLCSP72 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 11. STM32L476Jx, external SMPS device, WLCSP72 ballout(1) . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 12. STM32L476Rx LQFP64 pinout(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 13. STM32L476Rx, external SMPS device, LQFP64 pinout(1). . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 14. STM32L476xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 15. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 16. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 17. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 18. Current consumption measurement scheme with and without external
SMPS power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Figure 19. VREFINT versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 20. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 21. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 22. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Figure 23. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 24. HSI16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 25. Typical current consumption versus MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 26. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 27. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 28. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 29. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 30. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 31. 12-bit buffered / non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 32. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Figure 33. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 34. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 35. Quad SPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 36. Quad SPI timing diagram - DDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 37. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 38. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 39. SDIO high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 40. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 41. USB OTG timings – definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . 214
Figure 42. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 217
Figure 43. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 219
Figure 44. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 45. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 46. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Figure 47. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
List of figures STM32L476xx
12/262 DocID025976 Rev 5
Figure 48. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 49. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 50. NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 51. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 52. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 231
Figure 53. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 232
Figure 54. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 234
Figure 55. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 56. LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 57. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 58. UFBGA132 - 132-ball, 7 x 7 mm ultra thin fine pitch ball grid array
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Figure 59. UFBGA132 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Figure 60. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . 241
Figure 61. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 62. LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 63. WLCSP81 - 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level
chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 64. WLCSP81- 81-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Figure 65. WLCSP81 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 66. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip
scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Figure 67. WLCSP72 - 72-ball, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level
chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 68. WLCSP72 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 69. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 250
Figure 70. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 71. LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 72. LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
DocID025976 Rev 5 13/262
STM32L476xx Introduction
60
1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L476xx microcontrollers.
This document should be read in conjunction with the STM32L4x6 reference manual
(RM0351). The reference manual is available from the STMicroelectronics website
www.st.com.
For information on the ARM® Cortex®-M4 core, please refer to the Cortex®-M4 Technical
Reference Manual, available from the www.arm.com website.
Description STM32L476xx
14/262 DocID025976 Rev 5
2 Description
The STM32L476xx devices are the ultra-low-power microcontrollers based on the high-
performance ARM® Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz.
The Cortex-M4 core features a Floating point unit (FPU) single precision which supports all
ARM single-precision data-processing instructions and data types. It also implements a full
set of DSP instructions and a memory protection unit (MPU) which enhances application
security.
The STM32L476xx devices embed high-speed memories (Flash memory up to 1 Mbyte, up
to 128 Kbyte of SRAM), a flexible external memory controller (FSMC) for static memories
(for devices with packages of 100 pins and more), a Quad SPI flash memories interface
(available on all packages) and an extensive range of enhanced I/Os and peripherals
connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L476xx devices embed several protection mechanisms for embedded Flash
memory and SRAM: readout protection, write protection, proprietary code readout
protection and Firewall.
The devices offer up to three fast 12-bit ADCs (5 Msps), two comparators, two operational
amplifiers, two DAC channels, an internal voltage reference buffer, a low-power RTC, two
general-purpose 32-bit timer, two 16-bit PWM timers dedicated to motor control, seven
general-purpose 16-bit timers, and two 16-bit low-power timers. The devices support four
digital filters for external sigma delta modulators (DFSDM).
In addition, up to 24 capacitive sensing channels are available. The devices also embed an
integrated LCD driver 8x40 or 4x44, with internal step-up converter.
They also feature standard and advanced communication interfaces.
•Three I2Cs
•Three SPIs
•Three USARTs, two UARTs and one Low-Power UART.
•Two SAIs (Serial Audio Interfaces)
•One SDMMC
•One CAN
•One USB OTG full-speed
•One SWPMI (Single Wire Protocol Master Interface)
The STM32L476xx operates in the -40 to +85 °C (+105 °C junction), -40 to +105 °C
(+125 °C junction) and -40 to +125 °C (+130 °C junction) temperature ranges from a 1.71 to
3.6 V VDD power supply when using internal LDO regulator and a 1.05 to 1.32V VDD12
power supply when using external SMPS supply. A comprehensive set of power-saving
modes allows the design of low-power applications.
Some independent power supplies are supported: analog independent supply input for
ADC, DAC, OPAMPs and comparators, 3.3 V dedicated supply input for USB and up to 14
I/Os can be supplied independently down to 1.08V. A VBAT input allows to backup the RTC
and backup registers. Dedicated VDD12 power supplies can be used to bypass the internal
LDO regulator when connected to an external SMPS.
The STM32L476xx family offers six packages from 64-pin to 144-pin packages.
DocID025976 Rev 5 15/262
STM32L476xx Description
60
Table 2. STM32L476xx family device features and peripheral counts
Peripheral STM32
L476Zx
STM32
L476Qx
STM32
L476Vx
STM32
L476Mx
STM32
L476Jx
STM32
L476Rx
Flash memory 512
KB 1MB 512
KB 1MB 256
KB
512
KB 1MB 512
KB 1MB 512
KB 1MB 256
KB
512
KB 1MB
SRAM 128KB
External memory
controller for static
memories
Yes Yes Yes(1) No No No
Quad SPI Yes
Timers
Advanced
control 2 (16-bit)
General
purpose
5 (16-bit)
2 (32-bit)
Basic 2 (16-bit)
Low -power 2 (16-bit)
SysTick
timer 1
Watchdog
timers
(indepen-
dent,
window)
2
Comm.
interfaces
SPI 3
I2C3
USART
UART
LPUART
3
2
1
SAI 2
CAN 1
USB OTG
FS Yes
SDMMC Yes
SWPMI Yes
Digital filters for sigma-
delta modulators Yes (4 filters)
Number of channels 8
RTC Yes
Tamper pins 3 2 2 2
LCD
COM x SEG
Yes
8x40 or
4x44
Yes
8x40 or
4x44
Yes
8x40 or 4x44
Yes
8x30 or
4x32
Yes
8x28 or
4x32
Yes
8x28 or 4x32
Description STM32L476xx
16/262 DocID025976 Rev 5
Random generator Yes
GPIOs(2)
Wakeup pins
Nb of I/Os down to
1.08 V
114
5
14
109
5
14
82
5
0
65
4
6
57
4
6
51
4
0
Capacitive sensing
Number of channels 24 24 21 12 12 12
12-bit ADCs
Number of channels
3
24
3
19
3
16
3
16
3
16
3
16
12-bit DAC channels 2
Internal voltage
reference buffer Yes No
Analog comparator 2
Operational amplifiers 2
Max. CPU frequency 80 MHz
Operating voltage
(VDD)1.71 to 3.6 V
Operating voltage
(VDD12)1.05 to 1.32 V
Operating temperature Ambient operating temperature: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C
Junction temperature: -40 to 105 °C / -40 to 125 °C / -40 to 130 °C
Packages LQFP144 UFBGA
132 LQFP100 WLCSP81 WLCSP72 LQFP64
1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory
using the NE1 Chip Select.
2. In case external SMPS package type is used, 2 GPIO's are replaced by VDD12 pins to connect the SMPS power supplies
hence reducing the number of available GPIO's by 2.
Table 2. STM32L476xx family device features and peripheral counts (continued)
Peripheral STM32
L476Zx
STM32
L476Qx
STM32
L476Vx
STM32
L476Mx
STM32
L476Jx
STM32
L476Rx
DocID025976 Rev 5 17/262
STM32L476xx Description
60
Figure 1. STM32L476xx block diagram
Note: AF: alternate function on I/O pins.
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Functional overview STM32L476xx
18/262 DocID025976 Rev 5
3 Functional overview
3.1 ARM® Cortex®-M4 core with FPU
The ARM® Cortex®-M4 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The ARM® Cortex®-M4 with FPU 32-bit RISC processor features exceptional code-
efficiency, delivering the high-performance expected from an ARM core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded ARM core, the STM32L476xx family is compatible with all ARM tools
and software.
Figure 1 shows the general block diagram of the STM32L476xx family devices.
3.2 Adaptive real-time memory accelerator (ART Accelerator™)
The ART Accelerator™ is a memory accelerator which is optimized for STM32 industry-
standard ARM® Cortex®-M4 processors. It balances the inherent performance advantage of
the ARM® Cortex®-M4 over Flash memory technologies, which normally requires the
processor to wait for the Flash memory at higher frequencies.
To release the processor near 100 DMIPS performance at 80MHz, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 64-bit Flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from Flash memory at a CPU frequency up to 80 MHz.
3.3 Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
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STM32L476xx Functional overview
60
3.4 Embedded Flash memory
STM32L476xx devices feature up to 1 Mbyte of embedded Flash memory available for
storing programs and data. The Flash memory is divided into two banks allowing read-
while-write operations. This feature allows to perform a read operation from one bank while
an erase or program operation is performed to the other bank. The dual bank boot is also
supported. Each bank contains 256 pages of 2 Kbyte.
Flexible protections can be configured thanks to option bytes:
•Readout protection (RDP) to protect the whole memory. Three levels are available:
– Level 0: no readout protection
– Level 1: memory readout protection: the Flash memory cannot be read from or
written to if either debug features are connected, boot in RAM or bootloader is
selected
– Level 2: chip readout protection: debug features (Cortex-M4 JTAG and serial
wire), boot in RAM and bootloader selection are disabled (JTAG fuse). This
selection is irreversible.
•Write protection (WRP): the protected area is protected against erasing and
programming. Two areas per bank can be selected, with 2-Kbyte granularity.
•Proprietary code readout protection (PCROP): a part of the flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
One area per bank can be selected, with 64-bit granularity. An additional option bit
(PCROP_RDP) allows to select if the PCROP area is erased or not when the RDP
protection is changed from Level 1 to Level 0.
Table 3. Access status versus readout protection level and execution modes
Area Protection
level
User execution Debug, boot from RAM or boot
from system memory (loader)
Read Write Erase Read Write Erase
Main
memory
1 Yes Yes Yes No No No
2 Yes Yes Yes N/A N/A N/A
System
memory
1 Yes No No Yes No No
2 Yes No No N/A N/A N/A
Option
bytes
1 Yes Yes Yes Yes Yes Yes
2 Yes No No N/A N/A N/A
Backup
registers
1YesYesN/A
(1)
1. Erased when RDP change from Level 1 to Level 0.
No No N/A(1)
2 Yes Yes N/A N/A N/A N/A
SRAM2
1 Yes Yes Yes(1) No No No(1)
2 Yes Yes Yes N/A N/A N/A
Functional overview STM32L476xx
20/262 DocID025976 Rev 5
The whole non-volatile memory embeds the error correction code (ECC) feature supporting:
•single error detection and correction
•double error detection.
•The address of the ECC fail can be read in the ECC register
3.5 Embedded SRAM
STM32L476xx devices feature up to 128 Kbyte of embedded SRAM. This SRAM is split into
two blocks:
•96 Kbyte mapped at address 0x2000 0000 (SRAM1)
•32 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2).
This block is accessed through the ICode/DCode buses for maximum performance.
These 32 Kbyte SRAM can also be retained in Standby mode.
The SRAM2 can be write-protected with 1 Kbyte granularity.
The memory can be accessed in read/write at CPU clock speed with 0 wait states.
3.6 Firewall
The device embeds a Firewall which protects code sensitive and secure data from any
access performed by a code executed outside of the protected areas.
Each illegal access generates a reset which kills immediately the detected intrusion.
The Firewall main features are the following:
•Three segments can be protected and defined thanks to the Firewall registers:
– Code segment (located in Flash or SRAM1 if defined as executable protected
area)
– Non-volatile data segment (located in Flash)
– Volatile data segment (located in SRAM1)
•The start address and the length of each segments are configurable:
– Code segment: up to 1024 Kbyte with granularity of 256 bytes
– Non-volatile data segment: up to 1024 Kbyte with granularity of 256 bytes
– Volatile data segment: up to 96 Kbyte with a granularity of 64 bytes
•Specific mechanism implemented to open the Firewall to get access to the protected
areas (call gate entry sequence)
•Volatile data segment can be shared or not with the non-protected code
•Volatile data segment can be executed or not depending on the Firewall configuration
The Flash readout protection must be set to level 2 in order to reach the expected level of
protection.
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STM32L476xx Functional overview
60
3.7 Boot modes
At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:
•Boot from user Flash
•Boot from system memory
•Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART, I2C, SPI, CAN or USB OTG FS in Device mode through DFU (device
firmware upgrade).
3.8 Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link-
time and stored at a given memory location.
3.9 Power supply management
3.9.1 Power supply schemes
•VDD = 1.71 to 3.6 V: external power supply for I/Os (VDDIO1), the internal regulator and
the system analog such as reset, power management and internal clocks. It is provided
externally through VDD pins.
•VDD12 = 1.05 to 1.32 V: external power supply bypassing internal regulator when
connected to an external SMPS. It is provided externally through VDD12 pins and only
available on packages with the external SMPS supply option. VDD12 does not require
any external decoupling capacitance and cannot support any external load.
•VDDA = 1.62 V (ADCs/COMPs) / 1.8 (DACs/OPAMPs) to 3.6 V: external analog power
supply for ADCs, DACs, OPAMPs, Comparators and Voltage reference buffer. The
VDDA voltage level is independent from the VDD voltage.
•VDDUSB = 3.0 to 3.6 V: external independent power supply for USB transceivers. The
VDDUSB voltage level is independent from the VDD voltage.
•VDDIO2 = 1.08 to 3.6 V: external power supply for 14 I/Os (PG[15:2]). The VDDIO2
voltage level is independent from the VDD voltage.
•VLCD = 2.5 to 3.6 V: the LCD controller can be powered either externally through VLCD
pin, or internally from an internal voltage generated by the embedded step-up
converter.
•VBAT = 1.55 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Note: When the functions supplied by VDDA, VDDUSB or VDDIO2 are not used, these supplies
should preferably be shorted to VDD.
Functional overview STM32L476xx
22/262 DocID025976 Rev 5
Note: If these supplies are tied to ground, the I/Os supplied by these power supplies are not 5 V
tolerant (refer to Table 19: Voltage characteristics).
Note: VDDIOx is the I/Os general purpose digital functions supply. VDDIOx represents VDDIO1 or
VDDIO2, with VDDIO1 = VDD. VDDIO2 supply voltage level is independent from VDDIO1.
Figure 2. Power supply overview
3.9.2 Power supply supervisor
The device has an integrated ultra-low-power brown-out reset (BOR) active in all modes
except Shutdown and ensuring proper operation after power-on and during power down.
The device remains in reset mode when the monitored supply voltage VDD is below a
specified threshold, without the need for an external reset circuit.
The lowest BOR level is 1.71V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An
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STM32L476xx Functional overview
60
interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
In addition, the device embeds a Peripheral Voltage Monitor which compares the
independent supply voltages VDDA, VDDUSB, VDDIO2 with a fixed threshold in order to ensure
that the peripheral is in its functional supply range.
Functional overview STM32L476xx
24/262 DocID025976 Rev 5
3.9.3 Voltage regulator
Two embedded linear voltage regulators supply most of the digital circuitries: the main
regulator (MR) and the low-power regulator (LPR).
•The MR is used in the Run and Sleep modes and in the Stop 0 mode.
•The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is
also used to supply the 32 Kbyte SRAM2 in Standby with SRAM2 retention.
•Both regulators are in power-down in Standby and Shutdown modes: the regulator
output is in high impedance, and the kernel circuitry is powered down thus inducing
zero consumption.
The ultralow-power STM32L476xx supports dynamic voltage scaling to optimize its power
consumption in run mode. The voltage from the Main Regulator that supplies the logic
(VCORE) can be adjusted according to the system’s maximum operating frequency.
There are two power consumption ranges:
•Range 1 with the CPU running at up to 80 MHz.
•Range 2 with a maximum CPU frequency of 26 MHz. All peripheral clocks are also
limited to 26 MHz.
The VCORE can be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode.
•Low-power run mode with the CPU running at up to 2 MHz. Peripherals with
independent clock can be clocked by HSI16.
When the MR is in use, the STM32L476xx with the external SMPS option allows to force an
external VCORE supply on the VDD12 supply pins.
When VDD12 is forced by an external source and is higher than the output of the internal
LDO, the current is taken from this external supply and the overall power efficiency is
significantly improved if using an external step down DC/DC converter.
3.9.4 Low-power modes
The ultra-low-power STM32L476xx supports seven low-power modes to achieve the best
compromise between low-power consumption, short startup time, available peripherals and
available wakeup sources.
STM32L476xx Functional overview
DocID025976 Rev 5 25/262
Table 4. STM32L476xx modes overview
Mode Regulator
(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time
Run
MR
range 1
Yes ON(4) ON Any
All
N/A
112 µA/MHz
N/A
SMPS
range 2
High
40 µA/MHz(5)
MR
range2
All except OTG_FS, RNG
100 µA/MHz
SMPS
range 2
Low
39 µA/MHz(6)
LPRun LPR Yes ON(4) ON
Any
except
PLL
All except OTG_FS, RNG N/A 136 µA/MHz to Range 1: 4 µs
to Range 2: 64 µs
Sleep
MR range
1
No ON(4) ON(7) Any
All
Any interrupt or
event
37 µA/MHz
6 cycles
SMPS
range 2
High
13 µA/MHz(5)
MR
range2
All except OTG_FS, RNG
35 µA/MHz
6 cycles
SMPS
range 2
Low
15 µA/MHz(6)
LPSleep LPR No ON(4) ON(7)
Any
except
PLL
All except OTG_FS, RNG Any interrupt or
event 40 µA/MHz 6 cycles
Functional overview STM32L476xx
26/262 DocID025976 Rev 5
Stop 0
Range 1(8)
No Off ON LSE
LSI
BOR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1,2)
DACx (x=1,2)
OPAMPx (x=1,2)
USARTx (x=1...5)(9)
LPUART1(9)
I2Cx (x=1...3)(10)
LPTIMx (x=1,2)
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1..2)
USARTx (x=1...5)(9)
LPUART1(9)
I2Cx (x=1...3)(10)
LPTIMx (x=1,2)
OTG_FS(11)
SWPMI1(12)
108 µA 0.7 µs in SRAM
4.5 µs in Flash
Range 2(8)
Stop 1 LPR No Off ON LSE
LSI
BOR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1,2)
DACx (x=1,2)
OPAMPx (x=1,2)
USARTx (x=1...5)(9)
LPUART1(9)
I2Cx (x=1...3)(10)
LPTIMx (x=1,2)
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1..2)
USARTx (x=1...5)(9)
LPUART1(9)
I2Cx (x=1...3)(10)
LPTIMx (x=1,2)
OTG_FS(11)
SWPMI1(12)
6.6 µA w/o RTC
6.9 µA w RTC
4 µs in SRAM
6 µs in Flash
Table 4. STM32L476xx modes overview (continued)
Mode Regulator
(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time
STM32L476xx Functional overview
DocID025976 Rev 5 27/262
Stop 2 LPR No Off ON LSE
LSI
BOR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1..2)
I2C3(10)
LPUART1(9)
LPTIM1
***
All other peripherals are
frozen.
Reset pin, all I/Os
BOR, PVD, PVM
RTC, LCD, IWDG
COMPx (x=1..2)
I2C3(10)
LPUART1(9)
LPTIM1
1.1 µA w/o RTC
1.4 µA w/RTC
5 µs in SRAM
7 µs in Flash
Standby
LPR
Powered
Off Off
SRAM2
ON
LSE
LSI
BOR, RTC, IWDG
***
All other peripherals are
powered off.
***
I/O configuration can be
floating, pull-up or pull-down
Reset pin
5 I/Os (WKUPx)(13)
BOR, RTC, IWDG
0.35 µA w/o RTC
0.65 µA w/ RTC
14 µs
OFF Powered
Off
0.12 µA w/o RTC
0.42 µA w/ RTC
Shutdown OFF Powered
Off Off Powered
Off LSE
RTC
***
All other peripherals are
powered off.
***
I/O configuration can be
floating, pull-up or pull-
down(14)
Reset pin
5 I/Os (WKUPx)(13)
RTC
0.03 µA w/o RTC
0.33 µA w/ RTC 256 µs
1. LPR means Main regulator is OFF and Low-power regulator is ON.
2. All peripherals can be active or clock gated to save power consumption.
3. Typical current at VDD = 1.8 V, 25°C. Consumptions values provided running from SRAM, Flash memory Off, 80 MHz in Range 1, 26 MHz in Range 2, 2 MHz in
LPRun/LPSleep.
4. The Flash memory can be put in power-down and its clock can be gated off when executing from SRAM.
5. Theoretical value based on VDD = 3.3 V, DC/DC Efficiency of 85%, VCORE = 1.10 V
6. Theoretical value based on VDD = 3.3 V, DC/DC Efficiency of 85%, VCORE = 1.05 V
7. The SRAM1 and SRAM2 clocks can be gated on or off independently.
Table 4. STM32L476xx modes overview (continued)
Mode Regulator
(1) CPU Flash SRAM Clocks DMA & Peripherals(2) Wakeup source Consumption(3) Wakeup time
Functional overview STM32L476xx
28/262 DocID025976 Rev 5
8. SMPS mode can be used in STOP0 Mode, but no significant power gain can be expected.
9. U(S)ART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or received frame event.
10. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
11. OTG_FS wakeup by resume from suspend and attach detection protocol event.
12. SWPMI1 wakeup by resume from suspend.
13. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
14. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode.