HARRIS SEMICOND SECTOR tg] HARRIS CMOS Liquid-Crystal Display Drivers High-Voltage Types (20-Volt Rating) CD4054B ~ 4-Segment Display Driver CD4055B BCD to 7-Segment Decoder/Driver with Display-Frequency Output CD4056B BCD to 7-Segment Decoder/Driver with Strobed-Latch Function m@ CD40558 and. CD4056B types are single-digit BCD-to-7-segment decoder/driver circults that provide level-shifting functions on the chip, This feature permits the BCD input-signal swings (Vpp to Vsg) to be the same as or different from the 7-segment output-signal swings (Vpp to VEE). For example, the BCD input-signal swings (Vpp to Vgg) may be as small as 0 to 3 V, where- as the output-display drive-signal swing 'Vop to Veg) may be as.large as from 0 to 15V. If Vpp to Veg exceeds 15 V, Vpp toVgs should be at least 4V (0 to 4V). The 7-seqment outputs are controlled by the. DISPLAY-FREQUENCY (DF) input which causes the selected segment outputs to be low, high, or a square-wave output {for liquid-crystal displays). When the DF input is low the. output segments will be high when selected by the BCD: inputs. When the DF input is high, the output segments will be Jow when selected by the BCD inputs, When a square-wave is present at the DF input, the selected segments will have a square-wav output that is 180 out of phase with the DF input. Those.segments which are not selected will have a square- wave output that is.in phase with the input. DF square-wave repetition rates for liquid- crystal displays usually range from 30 Hz (welt aboye flicker rate) to 200 Hz (well below the upper limit of the liquid-crystal frequency response}. The CD4055B pro- vides a level-shifted high-amplitude DF out- put which is required for driving thecommon electrode in liquid-crystal displays. The CD40568 provides a strobed-latch function at the BCD inputs, Decoding of all input combinations on the CD4055B and CD40568 provides displays of 0 to 9 as well as L, P, H, A, -, and a blank position, The CD4054B provides level shifting similar to the CD40558 and CD40568 independently strobed latches, and common DF control on 4 signal. lines. The CD4054B is intended to provide drive-signal compatibility- with the CD4055B and CD40568 7-segment decoder types for the decimal point, colon, polarity, and similar display lines. A level-shifted high-amplitude DF gutput can. be obtained from: any CD4054B output line by connect- SUE D HM 4302271 0037472 O MBHAS. TS(-17 CD4054B, CD4055B, CD4056B Types Features: m Operation of liquid crystals with CMOS circuits. provides ultra-low-power displays Equivalent ac output drive for liquid- STROBE i@ crystal displays no external capacitor required a [2 a Voltage doubling across display, e.g. weurs 3s a Vpp VEE = 18 V results in effective each : 36 V p-p drive across selected display as rae 7 segments ss ]8 @ Low- or high-output level de drive for #* 7-SEGHENT other types of displays sureurs s2es-24ea7 = On-chip logic-level conversion for different input- and output-level swings Full decoding of all input combinations: cp40s6B 0-9, L, H, P, A,=, and blank positions Strobed-latch functionCD4054B Series and CD4056B Series DISPLAY-FREQUENGY (DF) output for liquid-crystal common-line drive signal- CD4055B Series (CD4054B Series also: see introductory text) Maximum input current of 1A at 18 V over full package temperature range; 100 nA at 18 V and 25C Noise margin (over full package temper- ature range): 1VatVpp=5V 2VatVpp=10V 2.5 Vat Vpp = 15 V = 5-V, 10-V, and 15-V parametric ratings Applications Goneral-purpose displays Calculators and meters = Wall and table clocks = Industrial contro! panels | Portable lab instruments = Panel meters Auto dashboard displays . Appliance control panels ing the corresponding input and strobe lines to a low and high level, respectively and applying a square wave to DFiy. The CD40548 may also be utilized for logic-level up conversion or down conversion", For example, input-signal swings (Vpp to Vss) frum +5 to 0 V can he converted to output- signal swings (Vpp to Veg) of +5 to -5 V. The level-shifted function on all three types Permits the use of different input: and out- put-signal swings. The input swings from a low level of Vsg to a high level of Vpp while the output swings fram alow level of VEE to the same high level of Vpp. Thus, the input and output swings can be selected indepen- dently of each other over a 3-to-18 V Tange, Vssg may be connected to VEE when no level-shift function is required, For the CD4054B and CD4056B, data are 3-153 100% tested for quiescent current at 20 V Terminal Assignment STROBE 4 lle Yoo DISPLAY FREQ.IN {2 Ine . ours 13 STROBE 3 OUTS 4 INS ourz l5 STROBE2 ourt 6 NZ Vee 47 STROBE t Yss a INT 92C5-24485 CD40548 Terminal Assignment DISPLAY FREQ.OUT 22 aco ja INPUTS ) 23 20 DISPLAY FREQ. IN VEE Ys "(C7-seeMent ouTeuts - wns ar ry gecs-24496 CD40558 Terminal Assignment transferred from input to output by placing a high voltage level at. the strobe input. A low voltage level at the strobe input latches the data input and the corresponding output segments remain selected {or non-selected) while the strobe is low. Whenever the level-shifting function is re- quired, the CD4055B can be used by itself to drive a liquid-crystal display (Figlt6 and Fig.20). The CD40568, however, must be used together with a CD40548 to provide the common DF output (Fig.19}). The capa- bility of extending the voltage swing on: the negative end (this voltage cannot be extended on the positive end) can be used to advantage in the setup of Fig.18, Fig.17 is common to all three types. The CD4054B-, CD4055B-, and Cb40568- series types are available in 16-lead ceramic dual-In-line packages (D and F SUffixes), 16- lead plastic packages (E suffix), andin chip form (H suffix). COMMERCIAL CMOS HIGH VOLTAGE ICsHARRIS SEMICOND SECTOR ~ N85 Q_LVEOL =u ce means man net nat te tat eA eNO REE, ne tee ea 44UE D BM 4302271 0037473 2 BMHAS CD4054B, CD40558, CD4056B Types ~~ s/ -/ Yd ots r vss @) a TEMPERATURE (Ty stroae 4(1) 2) G)o & 11 3@ a 2 2@ 2 @> staoBe 3@@) : $ 5a z & a = 2@ 3 s.r] 2 e In 2) - x a as = . 2ifez BO] s Has S Osten STROBE 2(2) 4 a 4 eoly & a DISPLAY, io 2 a sn @1Garen) FREQ.IN iS a a STROBE | Go) (15) Facet Oi cosas4 s % OISPLAY- LOAD CAPACITANCE (L) pF ra L @FRea.our TANCE CO PE eg caane an " Fig.4 Typical propagation delay time vs. ALL INPUTS ARE load capacitance for CD4054B, : PROTECTED AY = i CMOS PROTECTION . NETWORK ALL INPUTS ARE PROTECTED BY AMGIENT TEMPERATURE {Ty CHOS PROTECTION NETWORK ss 92CS-20080R3 . Fig.t CD4054B functional diagram. 920S-20092A2 Fig.2 - CD40558 functional diagram. Bco INPUTS. & = & z a my a > fy J DISPLAY = FREQ. IN BCD-To- TSEGMENT 7 EGMENT OUTPUTS BECOCER DISPLAY DRIVERS ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK Yoo oo rr Fig.2 CD40568 functional diagram. CD4054B. TRUTH TABLE X = Don't Care. *Depends upon the Input mode previously applied when ST = 1, nN o TRUTH TABLE FOR CD4055B and CD4056B INPUT CODE 22} 2! b mlojs/alalolol/ofajo a}el[-[-[4]-l=/ololololofolaloe 9 1 9 1 0 1 Q 1 0 1 0 1 0 1 mlaft-|[elofojoloj- elofes|alolofa}ofo]a OUTPUT STATE c -lfofea Of, H/Ool;-$(/o/ofo]/|/ol;ajs e/olafalalealal[-loji=la|[ololojolal=- OL OolO Sopot [apm lore ofo]/-f-| =/ 3-154 sees ase oe LOAD CAPACITANCE {C.) pF S2CS-28488 Fig.5 Typical propagation delay time vs. load capacitance for CD4055 and CD40568. AMBIENT TEMPERATURE (Ta)*25* TRANSITION TIME trig. pq ne DISPLAY CHARAC- LOAD CAPACITANCE (C, }pF 92s-2849081 Filg.6 Typical transition time ys Joad capacitance. ~ TEMPERATURE* FULL = - 0 0? to + to* INPUT CLOCK FREQUENCY (Fey } tz 92C$-26392A1 Fig.7 Typical input clock frequency ys. power dissipation.HARRIS SEMICOND SECTOR CD4054B, CD4055B, CD4056B Types MAXIMUM RATINGS, Absolute-Maximum Values: DG SUPPLY-VOLTAGE RANGE, (Vpp) Vollages raferanced to Vgg Terminal) ........00c0.06 te eseee dteeesceeee o INPUT VOLTAGE RANGE, ALLINPUTS ... DG INPUT CURRENT, ANY ONE INPUT ............00ceeae POWER DISSIPATION PER PACKAGE (Pp): Fot Ta -5C 10 +1009C ocala ceeseeee cease beeen eenene deneenees detect teen eteneeeees eaeee soomw ForTa = +100C to +#125C,., dee teeeeeeeseenn baeeaees Derate Linearity at 12mW/C to 200mW DEVICE: DISSIPATION PER OUTPUT TRANSISTOR . e000 OSV to +20V FOR Ta 3 FULL PACKAGE-TEMPERATURE RANGE (All Package Types)....... Poeteee ve. 100mW OPERATING-TEMPERATURE RANGE (Ta). .....0ceeeeveuecucees 55C to +125C STORAGE TEMPERATURE RANGE (Tgtgh ss seseccecnneee tte e eens +, 65C to +150C LEAD TEMPERATURE (OURING SOLDERING): At distance 1/16 & 1/32 Inch (1.69 2 0.79mm)} from case for 108 max ......... eevneees dn vneeeess +6 $265G STATIC ELECTRICAL CHARACTERISTICS CONDITIONS LIMITS AT INDICATED TEMPERATURES (C} Characteristic. (VeE}Vss! Vo | Vin (Vpp Units iv) | it vi} ivi | wv) +26C - 559| 409 | +8591+4259/ Min, Typ. | Max, Quiescent Device |-5 | 0 5 5 150] 150} - | 0.04] 5 | ya Curgent, Ipp 0}; 0 10 10 300 | 300 - 0.04] 10 MAX.{ 0] 0 15 20 600] 600] 0.04| 20 of; a 20 100 3000} 3000} 0.08 | 100 Output Voltage: QO] 0 05 | 5 0.05 = Q 0.05 Low Level, Vo. | 010 0,10{ 10 0.05 = 0 {0.05 MAX. | O70 0,15] 15 005. | = 0 [0.05 Oo}; 0 05] 5 4.95 4.95 5 = v High Level, Von|_ 0 | 0 O,10f 10 9.95 9.95 10 =~ MIN. Qo; 0 O,1S| 15 14,95 14.95] 15. - 0.5, rete oO} o| 45 5 1.5 = | = }15 VIL MAX. 401 0-19 10 3 == f3 | 0] 0 16,135 15 4 = - 4 Input High =5. | 0 0645 | 5 35 38 |= v Voltage, CE) 10 7 7 > = ViH MIN. [0 [0 15,135 15 u el i Output Low (Sink) -5 | 0 | -4.5 5. | 0.98] 0.92 | 0.67/0.55!/ 08 1.6 = Current, lor{ Of Of o5 10 | 0.98| 0.92 | 0.67 | 0.55 | 0.8 1.6 = 0; 0 LS} 15 3.6 | 3.4 | 2.4 2 29 | 58 mA OutputHigh [|-5 | 0 | 45 | -0.6|-0.55| -0.35| -0.3 |-048|o9 | . (Source) of o} 35 10 | - 0.6} -055| -0.35| -0.3|-045] -o9 | Current, oH 0} 0 | 13:5 15 | -1.9|-18 [-12[-11]-15 7 ~3 ~ Input Current, lin} 9} Of 10,18] 18] 20.1) s0.17 2 | st f [et0-8] 204 pA Yoo Veo f \ _(NPUTS oD Vss tj iNPUTS | gutrurs vin tm tJ Se Lam @ iL i - NOTE: : Vs "Test any couamation ss 8203-27441R1 925-2791R1 Fig. 11 Quiescent-device-current test circuit. Fig. 12 Input-voltage test circuit. 3-155. HUE D MM 4302271 0037474 4 BEHAS T- S/-17 current characteristics. TO E Fig.9 Minimum n-channel output low {sink} current characteristics. 92s-3s9as Fig.8 ~ Typical n-channel output law (sink) s2cs-Ss982 ORAIN-TO-SOURCE VOLTAGE Yog)- Fig.10 Typical p-channel output high fsource) current characteristics. QRAIN-TO-SOURCE VOLTAGE (Vog)V 3 & 3 2 OUTPUT Fig. 13 Minimum p-channel output high (source) current characteristics. COMMERCIAL CMOS HIGH VOLTAGE ICsHARRIS SEMICOND SECTOR WUE D MM 4302271) 0037475 b MMHAS CD4054B, CD4055B8, CD4056B Types TS) ~) 2 DYNAMIC ELECTRICAL CHARACTERISTICS at Ta = 25C, Cy = 50 pF, Input ty,t = 20 ns, Ry = 200 kQ . t : INPUTS - LIMITS v | Nore: CONDITIONS xo CHARACTERIST Vee | Ves] Von ALL PACKAGE TvPEs_| ae Seourwnauly. RACTERISTIC NITS ss _ TO BOTH Vag AND V. CD4064_ | CD4055,CD4056 |. A UNUSED wv} (vit () Typ. Max} Typ Max = murs oie . . . . Van OF Yeg- Propagation Delay Time, 5 | 0 5 | 400 | 800 650 | 1300 Vss - teHL,"PLH Qa} 0 10 | 340 | 680 575 | 1150 ns 9268-27402 (Any Input to Any Output) 0 0 15 | 250 | soo 376 | 750 Fig. 14 Input-current test circuit. Transition Time, tru t =5 | 0 | 5 | 100 | 200 100 | 200 (Any Output THLATLH [9-19 [10 | 100 | 200 | 160 | 200 ns ny Vutpu o|{o | is | 75 | 150 75 | 150 Teas -5 [| o | 5 [110] 220 110 | 220 Minimum D. Time te Setup 0 | 0 | 10 | 60 |100 | 50 | 100 ns us 1s | 35 | 70 35 | 70 sof Ne OATA - : -5 [ o | 5 | 110[ 220 110 | 220 - Minimum Strobe Pul With tt o | o | 10 | 60 | 100 | 60 | 100 ns gino : Ww 0 15 | 35 | 70 35 | 70 as Input Capacitance, Cjy sensrazas (Any Input) -~|-|;- ]5 | 75 5 | 25 pF ~ * CD4054 and CD4056 only. RECOMMENDED OPERATING CONDITIONS at Tg = 25C (Uniess otherwise specified) For maximum reliability, nominal operating conditions should be selected so that operation is always within the following ranges. Vee | Vss | Vob LIMITS (v) (Vv) (v) | Min, | Max. CHARACTERISTIC UNITS Supply. Voltage Range: (At Ta =Full Package 3 18 Vv Temperature Range) =5 0 6 | 220 | - Setup Time (t,}* 0 0 10 100 - ns 0 0 15 70 | -5 0 5 | 220 | - Strobe Pulse Width (tw) [_ 0 0 10_| 100 = ns i 0 0 15 | 70 = For CD4054 and CD4056 only. LIQUID + CAYSTAL COMMON ELECTRODE 92C$~20095R2 Fig. 18 Clock display: Vpp = 6 V, Vsg =-8 V, Veg =-18 V, DF iy = 30 Hz square wave. 3-156 Fig. 1 . Data setup time and strabe pulse duration, LeveL- SHIFTED oF, Woot OUT ry er CT Bites DISPLAY i} yo SEGMENT ORIVER ouTe SEGMENT {a 109) INPUT rm [pun te 109) {HIGH*SELECT) ~) Four 92$-20033RI Yoo OF, PLLA A IN vgs: Vo rot ved LLU LULU VEE. Vo OFour LALLA Yee v sequent in 0? : vee! l . J | v secuentour \? veg +(Vo0-Vee? * ov. ~(on-Yee! # RESULTANT LIQUID-CRYSTAL SEGMENT WAVEFOR) APPLIED To LIQUIDCRYSTAL COMMON TINE YY OFour |S DFiy *CHSPLAY-FREQUENCY INPUT DFgur= LEVEL- SHIFTED O1SPLAY- FREQUENCY OUTPUT 92C3-20094A1 tb) Fig.17 Display-driver circuit for one segment fine and waveforms.WUE D MM 430ee27) O03747b & MMHAS HARRIS SEMICOND SECTOR . CD4054B, CD4055B, CD4056B Types ar ANALOG INPUTS (E5V> 5 Yoo*$ g5t0 VegteS ANALOG OUTPUTS (45 ) 928-z00g6R2 Fig. 18 Digital (0 ta +8 V} to bidirectional analog control {#8 to 5 V) leval shifter. so fy Four _ 04055 SEGMENT ELECTROOES ds bee =30 Hz SQUARE WAVE, OF dee rruce ISPLAY~ FREQUENCY CFour BRP Ley AMPLITUDE 92C8~ 20009 R2 Fig.20 Single-digit liquid-crystal display. Dimensions ja parentheses ara in millimeters and ara derived from the basic inch dimensions as indicated. Grid graduations are in mits (10-3 inch). ops + 5 co40s4 Veg *-SV 7-S5/-17 S08 . Ror See Noa No.3 STROBE stRoaE co4054 92M> 21859RF Fig. 19 Typical 3%-digit liquid-crystal display: Vop = +5 V, Vsg=0 Vv, VEE=-10V, DF 1x = 30 Hz square wave. COMMON ELECTRODE COMMERCIAL CMOS HIGH VOLTAGE ICs 925-2708 Fig.21 Conversion of H" display to F"' display. In addition to the letters L, H, P, and A (See the truth table), five other letters can be displayed through the use of simple logic circuits preceding and following the CD4055B or CD4056B devices. Fig.21 is an example of a circuit that converts an H display (code 1011) to an F" display. One condition that must be met is that VEE=Vsgs. If Vee#Vgg, the CD4054B must be used to level shift in the appropriate places. 9 19 2 30 40 60 7075 celal et tT Tt 6o cote PAP SP GO 70 89 Som 50 To: 0- 40 62-70 0 . 30 (575-1778) 1986-8359) 20 fe Tee rk 0 1o : 5 1 zo Py 3 lo-| o as Loi (0.102-0.264) 90-98, 72-80 12.207-2.489) 92eu-sio8 (1.829-~-2.932) 92c8-27062 Dimensions and pad layout for CD4054B8H. Dimensions and pad layout for CD40558H 3-157 tn a similar manner the letters C, E, J, and U can be displayed, These circuits can also be used to drive LED displays provided the exclusive-OR gates have sufficient output- current drive. The letters B, D, G, 1, O, and.S may be rep- resented by the codes for numbers 8, 0, 6, 1, 0, and 5, respectively, when there is pre- knowledge that. only letters are to be dis- played. 10-| qk ry 45 7 [one (alo2-0.254) 2, __J 12286-2489) 92eu-35107 Dimensions and pad layout for CD40568H