1
LTC4301L
4301lf
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
Hot Swappable 2-Wire
Bus Buffer with Low Voltage
Level Translation
■
Level Translates 1V Signals to Standard 3.3V and
5V Logic Rails
■
Allows Bus Pull-Up Voltages as Low as 1V on
SDAIN and SCLIN
■
Bidirectional Buffer* for SDA and SCL Lines
Increases Fanout
■
Prevents SDA and SCL Corruption During Live Board
Insertion and Removal from Backplane
■
Isolates Input SDA and SCL Line from Output
■
10kV Human Body Model ESD Protection
■
Supports Clock Stretching, Arbitration and
Synchronization
■
High Impedance SDA, SCL Pins for V
CC
= 0V
■
CS Gates Connection from Input to Output
■
Compatible with I
2
C
TM
, I
2
C Fast Mode and SMBus
Standards (Up to 400kHz Operation)
■
Small 8-Pin MSOP and DFN (3mm × 3mm) Packages
■
Hot Board Insertion
■
Servers
■
Capacitance Buffer/Bus Extender
■
Desktop Computers
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LTC
®
4301L hot swappable, 2-wire bus buffer allows
I/O card insertion into a live backplane without corruption
of the data and clock busses. In addition, the LTC4301L
SDAIN and SCLIN pins are compatible with systems with
pull-up voltages as low as 1V. Control circuitry prevents
the backplane from being connected to the card until a
stop bit or a bus idle is present. When the connection is
made, the LTC4301L provides bidirectional buffering,
keeping the backplane and card capacitances isolated.
When driven low, the CS input pin allows the part to
connect after a stop bit or bus idle occurs. Driving CS high
breaks the connection between SCLIN and SCLOUT and
between SDAIN and SDAOUT. A logic high on READY
indicates that the backplane and card sides are connected
together.
The LTC4301L is offered in 8-pin DFN (3mm × 3mm) and
MSOP packages.
Input-Output Connection
OUTPUT
SIDE
20pF
INPUT
SIDE
55pF
4301 TA01b
1µs/DIV
0.5V/DIV
µP
SDA
SCL
V
CC
GND
SDAIN
SCLIN
CS
SDAOUT
SCLOUT
READY
LTC4301L
V
CC
GND
2k 10k2k 10k
0.01µF
SDA
SCL
1.2V 3.3V
4301l TA01a
I
2
C is a trademark of Philips Electronics N.V.
*Patent Pending
2
LTC4301L
4301lf
ORDER PART
NUMBER
V
CC
to GND ................................................. –0.3V to 7V
SDAIN, SCLIN, SDAOUT, SCLOUT, CS ........ –0.3V to 7V
READY ........................................................ –0.3V to 6V
Operating Temperature Range
LTC4301LC ............................................. 0°C to 70°C
LTC4301LI.......................................... – 40°C to 85°C
LTC4301LCDD8
LTC4301LIDD8
T
JMAX
= 125°C, θ
JA
= 43°C/W
EXPOSED PAD (PIN 9) IS GND
PCB CONNECTION OPTIONAL
ABSOLUTE MAXIMUM RATINGS
W
WW
U
PACKAGE/ORDER INFORMATION
W
UU
DD8 PART
MARKING
LBHS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Storage Temperature Range
MSOP ............................................... –65°C to 150°C
DFN .................................................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
(Note 1)
ORDER PART
NUMBER
LTC4301LCMS8
LTC4301LIMS8
MS8 PART
MARKING
LTBHQ
TOP VIEW
9
DD8 PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
5
6
7
8
4
3
2
1CS
SCLOUT
SCLIN
GND
V
CC
SDAOUT
SDAIN
READY
T
JMAX
= 125°C, θ
JA
= 200°C/W
1
2
3
4
CS
SCLOUT
SCLIN
GND
8
7
6
5
V
CC
SDAOUT
SDAIN
READY
TOP VIEW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
V
CC
Positive Supply Voltage ●2.7 5.5 V
I
CC
Supply Current V
CC
= 5.5V, V
SDAIN
= V
SCLIN
= 0V ●4.5 6.2 mA
V
CC
= 5.5V, CS = 5.5V 300 µA
Start-Up Circuitry
V
PRE
Precharge Voltage SDAOUT, SCLOUT Floating ●0.85 1.05 1.25 V
t
IDLE
Bus Idle Time ●60 95 175 µs
RDY
VOL
READY Output Low Voltage I
PULLUP
= 3mA ●0.4 V
V
THRCS
Connection Sense Threshold 0.8 1.4 2 V
I
CS
CS Input Current CS from 0V to V
CC
±0.1 ±1µA
V
THR
SDAIN, SCLIN Logic Input Threshold Voltage Rising Edge 0.45 0.6 0.75 V
SDAOUT, SCLOUT Logic Input Threshold Voltage Rising Edge 1.55 1.8 2.0 V
V
HYS
SDAIN, SCLIN Logic Input Threshold Hysteresis (Note 3) 85 mV
SDAOUT, SCLOUT Logic Input Threshold Hysteresis (Note 3) 50 mV
t
PLH
CS Delay On-Off 10 ns
READY Delay Off-On 10 ns
t
PHL
CS Delay Off-On 95 µs
READY Delay On-Off 10 ns
I
OFF
Ready Off Leakage Current ±0.1 µA
3
LTC4301L
4301lf
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Input-Output Connection
V
OS
Input-Output Offset Voltage 10k to V
CC
on SDA, SCL, V
CC
= 3.3V, ●0 100 175 mV
SDA or SCL = 0.2V (Note 2)
C
IN
Digital Input Capacitance SDAIN, SDAOUT, (Note 3) 10 pF
SCLIN, SCLOUT
I
LEAK
Input Leakage Current SDA, SCL Pins ±5µA
V
OL
Output Low Voltage, Input = 0V SDA, SCL Pins, I
SINK
= 3mA, V
CC
= 2.7V ●0 0.4 V
SDA, SCL Pins, I
SINK
= 1mA, V
CC
= 2.7V 0 0.2 V
Timing Characteristics
f
I2C,MAX
I
2
C Maximum Operating Frequency (Note 3) 400 600 kHz
t
BUF
Bus Free Time Between Stop and Start (Note 3) 1.3 µs
Condition
t
HD,STA
Hold Time After (Repeated) Start Condition (Note 3) 100 ns
t
SU,STA
Repeated Start Condition Set-Up Time (Note 3) 0 ns
t
SU,STO
Stop Condition Set-Up Time (Note 3) 0 ns
t
HD,DATI
Data Hold Time Input (Note 3) 0 ns
t
SU,DAT
Data Set-Up Time (Note 3) 100 ns
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The connection circuitry always regulates its output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pull-up resistor and V
CC
voltage is shown in the Typical Performance
Characteristics section.
Note 3: Determined by design, not tested in production.
4
LTC4301L
4301lf
UU
U
PI FU CTIO S
CS (Pin 1): The connection sense pin is a 1.4V threshold
digital input pin. For normal operation CS is grounded.
Driving CS above the 1.4V threshold isolates SDAIN from
SDAOUT and SCLIN from SCLOUT and asserts READY
low.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
the SCL bus on the card.
SCLIN (Pin 3): Serial Clock Input. Connect this pin to SCL
on the bus backplane.
GND (Pin 4, 9): Ground. Connect this pin to a ground plane
for best results. Exposed pad (DFN package) is ground.
READY (Pin 5): The READY pin is an open drain N-channel
MOSFET output which pulls down when CS is high or
when the start-up sequence described in the Operation
section has not been completed. READY goes high when
CS is low and a start-up is complete.
SDAIN (Pin 6): Serial Data Input. Connect this pin to the
SDA bus on the backplane.
SDAOUT (Pin 7): Serial Data Output. Connect this pin to
the SDA bus on the card.
V
CC
(Pin 8): Main Input Supply. Place a bypass capacitor
of at least 0.01µF close to V
CC
for best results.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
ICC vs Temperature
Input – Output High to Low
Propagation Delay vs
Temperature Connection Circuitry VOUT – VIN
–50 –25 0 25 50 75 100
TEMPERATURE (°C)
TIME (ns)
4301 G02
100
80
60
40
20
0
V
CC
= 2.7V
V
CC
= 3.3V
V
CC
= 5.5V
C
IN
= C
OUT
= 100pF
R
PULLUPIN
= R
PULLUPOUT
= 10k
R
PULLUP
(Ω)
010,000 20,000 30,000 40,000
V
OUT
– V
IN
(mV)
4301 G03
300
250
200
150
100
50
0
V
CC
= 3.3V
V
CC
= 5V
T
A
= 25°C
V
IN
= 0V
TEMPERATURE (°C)
–80
I
CC
(mA)
4.9
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
3.9 –40 020 100
4301 G01
–60 –20 40 60 80
V
CC
= 5.5V
V
CC
= 3.3V
V
CC
= 2.7V
5
LTC4301L
4301lf
BLOCK DIAGRA
W
CONNECT PRECHARGE
CONNECT
CONNECT
1
R1
200k R2
200k
PRECHARGE
LOGIC PRECHARGE
CONNECT
95µs
DELAY
UVLO
1.4V
CS
0.6V
3SCLIN
6SDAIN
1.8V
CONNECT
CONNECT
7
SDAOUT
8
V
CC
2
SCLOUT
READY 5
GND
4301l BD
4
LTC4301L Supply Independent 2-Wire Bus Buffer
6
LTC4301L
4301lf
OPERATIO
U
Start-Up
When the LTC4301L first receives power on its V
CC
pin,
either during power-up or live insertion, it starts in an
undervoltage lockout (UVLO) state, ignoring any activity
on the SDA or SCL pins until V
CC
rises above 2.5V. This is
to ensure that the part does not try to function until it has
enough voltage to do so.
During this time, the 1V precharge circuitry is active and
forces 1V through 200k nominal resistors to the SDAOUT
and SCLOUT pins. Precharging the SCLOUT and SDAOUT
pins to 1V minimizes the worst-case voltage differential
these pins will see at the moment of connection, therefore
minimizing bus disturbances.
Once the LTC4301L comes out of UVLO, it assumes that
SDAIN and SCLIN have been inserted into a live system
and that SDAOUT and SCLOUT are being powered up at
the same time as itself. Therefore, it looks for either a stop
bit or bus idle condition on the backplane side to indicate
the completion of a data transaction. When either one
occurs, the part also verifies that both the SDAOUT and
SCLOUT voltages are high. When all of these conditions
are met, the input-to-output connection circuitry is acti-
vated, joining the SDA and SCL busses on the I/O card with
those on the backplane.
Connection Circuitry
Once the connection circuitry is activated, the functional-
ity of the SDAIN and SDAOUT pins is identical. A low
forced on either pin at any time results in both pin voltages
being low. For proper operation, logic low input voltages
should be no higher than 0.4V with respect to the ground
pin voltage of the LTC4301L. SDAIN and SDAOUT enter a
logic high state only when all devices on both SDAIN and
SDAOUT release high. The same is true for SCLIN and
SCLOUT. This important feature ensures that clock stretch-
ing, clock synchronization, arbitration and the acknowl-
edge protocol always work, regardless of how the devices
in the system are tied to the LTC4301L.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms as
described here.
Input-to-Output Offset Voltage
When a logic low voltage, V
LOW1
, is driven on any of the
LTC4301L’s data or clock pins, the LTC4301L regulates
the voltage on the other side of the device (call it V
LOW2
)
at a slightly higher voltage, as directed by the following
equation:
V
LOW2
= V
LOW1
+ 75mV + (V
CC
/R) • 70Ω (typical)
where R is the bus pull-up resistance in ohms. For ex-
ample, if a device is forcing SDAOUT to 10mV where V
CC
= 3.3V and the pull-up resistor R on SDAIN is 10k, then the
voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70 =
108mV(typical). See the Typical Performance Character-
istics section for curves showing the offset voltage as a
function of V
CC
and R.
Propagation Delays
During a rising edge, the rise time on each side is deter-
mined by the bus pull-up resistor and the equivalent
capacitance on the line. In Figure 1, V
CC
= 3.3V, SDAOUT
and SCLOUT are pulled-up to 3.3V with 10k resistor (20pF
on this side) and SDAIN and SCLIN are pulled-up to 1.2V
with a 2k resistor (55pF on this side). Lower pull-up
resistor values are used on the input side to allow the
output side to be released sooner.
Figure 1. Input-Output Connection
There is a finite high to low propagation delay through the
connection circuitry for falling waveforms. Figure 2 shows
the falling edge waveforms for the same pull-up resistors
and equivalent capacitance conditions as used in Figure 1.
An external N-channel MOSFET device pulls down the
voltage on the side with 55pF capacitance; LTC4301L pulls
down the voltage on the opposite side with a delay of 60ns.
OUTPUT
SIDE
20pF
INPUT
SIDE
55pF
4301 TA01b
1µs/DIV
0.5V/DIV
7
LTC4301L
4301lf
OPERATIO
U
This delay is always positive and is a function of supply
voltage, temperature and the pull-up resistors and equiva-
lent bus capacitances on both sides of the bus. The Typical
Performance Characteristics section shows the high to
low propagation delay as a function of temperature and
voltage for 10k pull-up resistors pulled-up to V
CC
and
100pF equivalent capacitance on both sides of the part.
Larger output capacitances translate to longer delays (up
to 150ns). Users must quantify the difference in propaga-
Figure 2. Input-Output Connection
High to Low Propagation Delay
tion times for a rising edge versus a falling edge in their
systems and adjust setup and hold times accordingly.
Ready Digital Output
This pin provides a digital flag which is low when either CS
is high or the start-up sequence described earlier in this
section has not been completed. READY goes high when
CS is low and start-up is complete. The pin is driven by an
open-drain pull-down capable of sinking 3mA while hold-
ing 0.4V on the pin. Connect a resistor of 10k to V
CC
to
provide the pull-up.
Connection Sense
When the CS pin is driven above 1.4V with respect to the
LTC4301L’s ground, the backplane side is disconnected
from the card side and the READY pin is internally pulled
low. When the pin voltage is low, the part waits for data
transactions on both the backplane and card sides to be
complete (as described in the Start-Up section) before
reconnecting the two sides. At this time the internal
pulldown on READY releases.
Live Insertion and Capacitance Buffering Application
Figure 3 illustrates applications of the LTC4301L with
different bus pull-up and V
CC
voltages, demonstrating its
ability to recognize and buffer bus data levels that are
above or below its V
CC
supply. All of these applications
take advantage of the LTC4301L’s Hot Swap
TM
controlling,
capacitance buffering and precharge features. If the I/O
cards were plugged directly into the backplane without the
LTC4301L buffer, all of the backplane and card capaci-
tances would add directly together, making rise- and fall-
time requirements difficult to meet. Placing an LTC4301L
on the edge of each card, however, isolates the card
capacitance from the backplane. For a given I/O card, the
LTC4301L drives the capacitance of everything on the card
and the backplane must drive only the capacitance of the
LTC4301L, which is less than 10pF.
APPLICATIO S I FOR ATIO
WUUU
In most applications the LTC4301L will be used with a
staggered connector where V
CC
and GND will be long pins.
SDA and SCL are medium length pins to ensure that the
V
CC
and GND pins make contact first. This will allow the
precharge circuitry to be activated on SDA and SCL before
they make contact. CS is a short pin that is pulled up when
not connected. This is to ensure that the connection
between the backplane and the cards data and clock
busses is not enabled until the transients associated with
live insertion have settled.
Figure 4 shows the LTC4301L in an application where all
of the pins have the same length. In this case, an RC filter
circuit on the I/O card with a product of 10ms provides a
filter to prevent the LTC4301L from becoming activated
until the transients associated with live insertion have
settled. Connect the capacitor between V
CC
and CS, and
the resistor from CS to GND.
Hot Swap is a trademark of Linear Technology Corporation.
4301 F02
INPUT
SIDE
55pF
OUTPUT
SIDE
20pF
0.5V/DIV
20ns/DIV
8
LTC4301L
4301lf
STAGGERED CONNECTOR
CS
SDAIN
SCLIN
V
CC
GND
SDAOUT
SCLOUT
READY
10k 10k
LTC4301L CARD_SCL
CARD_SDA
0.01µF
10k
2k2k
BACKPLANE
CONNECTOR
5V
1.2V
SDA
SCL
STAGGERED CONNECTOR
CS
SDAIN
SCLIN
V
CC
GND
SDAOUT
SCLOUT
READY
10k 10k
LTC4301L CARD_SCL
CARD_SDA
0.01µF
10k
2k2k
BACKPLANE
CONNECTOR
3.3V
1.2V
SDA
SCL
STAGGERED CONNECTOR
CS
SDAIN
SCLIN
V
CC
GND
SDAOUT
SCLOUT
READY
4301l F03
10k
3V
10k
LTC4301L CARD_SCL
CARD_SDA
0.01µF
10k
2k2k
BACKPLANE
CONNECTOR
CARD
CARD
CARD
3.3V
1V
SDA
SCL
Figure 3. Typical Supply Independent Applications
APPLICATIO S I FOR ATIO
WUUU
9
LTC4301L
4301lf
2k2k
3.3V
BACK_SCL
BACKPLANE
CONNECTOR
CARD
BACK_SDA
1.2V
10k
3.3V
CS
CARD_SCL
CARD_SDA
SCLOUTSCLIN
SDAOUTSDAIN
GND
V
CC
LTC4301L
READY
0.01µF
4301l F05
10k 10k
STAGGERED CONNECTOR
FROM
MICROPROCESSOR
Figure 4. Inserting Multiple I/O Cards into a Live Backplane Using a Connector with All the Pins the Same Length
APPLICATIO S I FOR ATIO
WUUU
10
LTC4301L
4301lf
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
U
PACKAGE DESCRIPTIO
3.00 ±0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
0.38 ± 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 ± 0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
2.38 ±0.10
(2 SIDES)
14
85
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
0.00 – 0.05
(DD8) DFN 1203
0.25 ± 0.05
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 ±0.05
(2 SIDES)2.15 ±0.05
0.50
BSC
0.675 ±0.05
3.5 ±0.05
PACKAGE
OUTLINE
0.25 ± 0.05 0.50 BSC
11
LTC4301L
4301lf
U
PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
MSOP (MS8) 0204
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.18
(.007)
0.254
(.010)
1.10
(.043)
MAX
0.22 – 0.38
(.009 – .015)
TYP
0.127 ± 0.076
(.005 ± .003)
0.86
(.034)
REF
0.65
(.0256)
BSC
0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
12
34
4.90 ± 0.152
(.193 ± .006)
8765
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
0.52
(.0205)
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.42 ± 0.038
(.0165 ± .0015)
TYP
0.65
(.0256)
BSC
12
LTC4301L
4301lf
LINEAR TECHNOLOGY CORPORATION 2003
LT/TP 0304 1K • PRINTED IN THE USA
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
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U
TYPICAL APPLICATIO
2k2k
3.3V
BACK_SCL
BACKPLANE
CONNECTOR
CARD
BACK_SDA
1.2V
10k
3.3V
CS
CARD_SCL
CARD_SDA
SCLOUTSCLIN
SDAOUTSDAIN
GND
V
CC
LTC4301L
READY
0.01µF
4301l F05
10k 10k
STAGGERED CONNECTOR
FROM
MICROPROCESSOR
System with Active Connection Control
