GS832132AD-250V - GSI Technology - Datasheet.Directory

GS832118/32/36AD-xxxV

2M x 18, 1M x 32, 1M x 36

36Mb Sync Burst SRAMs

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

333 MHz–150 MHz

2.5 V or 3.3 V VDD

2.5 V or 3.3 V I/O

165-B ump BGA

Commercial Temp

Industrial Temp

Features

• IEEE 1149.1 JTAG-compatible Boundary Scan

• 1.8 V or 2.5 V core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 165-bump BGA package

• RoHS-compliant 165-bump BGA package available

Functional Description

Applications

The GS832118/32/36AD-xxx V is a 37,748,736-bit high

performance synchronous SRAM with a 2-bit burst address

counter. Although of a type originally developed for Level 2

Cache applications supporting high performance CPUs, th e

device now finds application in synchronous SRAM

applications, ranging from DSP main store to networking chip

set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control

inputs (ADSP, ADSC, ADV) and write control inputs (Bx,

BW, GW) are synchronous and are controlled by a positive-

edge-triggered clock input (CK). Output enable (G) and power

down control (ZZ) are asynchronous inputs. Burst cycles can

be initiated with either ADSP or ADSC inputs. In Burst mode,

subsequent burst addresses are generated internally and are

controlled by ADV. The burst address counter may be

configured to count in either linear or interleave order with the

Linear Burst Order (LBO) input. The Burst fu nctio n need not

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Flow Through/Pipe line Reads

The function of the Data Output register can be controlled by

the user via the FT mo de pin (Pi n 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Outpu t Register. Holdi ng FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

SCD Pipelined Reads

The GS832118/32/36AD-xxxV is a SCD (Single Cycle

Deselect) pipelined synchronou s SRAM. DCD (Dual Cycle

Deselect) versions are also available. SCD SRAMs pipeline

deselect commands one stage less than read commands. SCD

RAMs begin turning off their outputs immediately after the

deselect command has been captured in the input registers.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS832118/32/36AD-xxxV operates on a 1.8 V or 2.5 V

power supply. All inputs are 1.8 V or 2.5 V compatible.

Separate output power (VDDQ) pins are used to decouple

output noise from the internal circuits and are 1.8 V or 2.5 V

compatible.

Parameter Synopsis

-333 -250 -200 -150 Unit

Pipeline

3-1-1-1

tKQ

tCycle 3.0

3.0 3.0

4.0 3.0

5.0 3.8

6.7 ns

Curr (x18)

Curr (x32/x36) 365

425 290

345 250

290 215

240 mA

Flow

Through

2-1-1-1

tKQ

tCycle 5.0

5.0 5.5

5.5 6.5

6.5 7.5

7.5 ns

Curr (x18)

Curr (x32/x36) 270

315 245

280 210

250 200

230 mA

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

165 Bump BGA—x18 Commom I/O—Top View (Package D)

12345678910 11

ANC AE1 BB NC E3 BW ADSC ADV A A A

BNC AE2 NC BA CK GW GADSP ANC B

CNC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPA C

DNC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA D

ENC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA E

FNC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA F

GNC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA G

HFT MCL NC VDD VSS VSS VSS VDD NC NC ZZ H

JDQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC J

KDQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC K

LDQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC L

MDQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC M

NDQPB NC VDDQ VSS NC ANC VSS VDDQ NC NC N

PNC NC A A TDI A1 TDO A A A A P

RLBO A19 A A TMS A0 TCK A A A A R

11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

165 Bump BGA—x32 Common I/O—Top View (Package D)

12345678910 11

ANC AE1 BC BB E3 BW ADSC ADV ANC A

BNC AE2 BD BA CK GW GADSP ANC B

CNC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC NC C

DDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB D

EDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB E

FDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB F

GDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB G

HFT MCL NC VDD VSS VSS VSS VDD NC NC ZZ H

JDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA J

KDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K

LDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L

MDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M

NNC NC VDDQ VSS NC ANC VSS VDDQ NC NC N

PNC NC A A TDI A1 TDO A A A A P

RLBO AAATMS A0 TCK A A A A R

11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

165 Bump BGA—x36 Common I/O—Top View (Package D)

12345678910 11

ANC AE1 BC BB E3 BW ADSC ADV ANC A

BNC AE2 BD BA CK GW GADSP ANC B

CDQPC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPB C

DDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB D

EDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB E

FDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB F

GDQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB G

HFT MCL NC VDD VSS VSS VSS VDD NC NC ZZ H

JDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA J

KDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K

LDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L

MDQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M

NDQPD NC VDDQ VSS NC ANC VSS VDDQ NC DQPA N

PNC NC A A TDI A1 TDO A A A A P

RLBO AAATMS A0 TCK A A A A R

11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch

GS832118/32/36AD-xxxV 165-Bump BGA Pin Description

Symbol Type Description

A0, A1IAddress field LSBs and Address Counter Preset Inputs

A I Address Inputs

DQA

DQB

DQC

DQD

I/O Data Input and Output pins

BA, BB, BC, BDIByte Write Enable for DQA, DQB, DQC, DQD I/Os; active low

CK IClock Input Signal; active high

BW IByte Write—Writes all enabled bytes; active low

GW IGlobal Write Enable—Writes all bytes; active low

E1IChip Enable; active low

E3IChip Enable; active low

E2IChip Enable; active high

G I Output Enable; active low

ADV IBurst address counter advance enable; active l0w

ADSC, ADSP IAddress Strobe (Processor, Cache Controller); active low

ZZ ISleep mode control; active high

FT IFlow Through or Pipeline mode; active low

LBO ILinear Burst Order mode; active low

TMS IScan Test Mode Select

TDI IScan Test Data In

TDO OScan Test Data Out

TCK IScan Test Clock

MCL —Must Connect Low

VDD ICore power supply

VSS II/O and Core Ground

VDDQ IOutput driver power supply

NC —No Connect

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

A0 A0

A1 D0

D1 Q1

Counter

Load

A0–An

LBO

ADV

ADSC

ADSP

ZZ Power Down

Control

Memory

Array

36 36

DQx1–DQx9

Note: Only x36 version shown for simplicity.

GS832118/32/36AD-xxxV Block Diagram

Mode Pin Functions

Mode Name Pin Name State Function

Burst Order Control LBO LLinear Burst

HInterleaved Burst

Output Register Control FT LFlow Through

H or NC Pipeline

Power Down Control ZZ L or NC Active

H Standby, IDD = ISB

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Note:

There is a pull-up device on the FT pin and a pull-down device on the ZZ pin , so this input pin can be unconnected and the chip will operate in

the default states as specified in the above tables.

Note:

The burst counter wraps to initial state on the 5th clock. Note:

The burst counter wraps to initial state on the 5th clock.

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 10 11 00

3rd address 10 11 00 01

4th address 11 00 01 10

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address 00 01 10 11

2nd address 01 00 11 10

3rd address 10 11 00 01

4th address 11 10 01 00

Burst Counter Sequences

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Byte Write Truth Table

Function GW BW BABBBCBDNotes

Read H H X X X X 1

Write No Bytes H L H H H H 1

Write byte a H L L H H H 2, 3

Write byte b H L H L H H 2, 3

Write byte c H L H H L H 2, 3, 4

Write byte d H L H H H L 2, 3, 4

Write all bytes H L L L L L 2, 3, 4

Write all bytes L X X X X X

Notes:

1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs, BA, BB, BC and/or BD.

2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes.

3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.

4. Bytes “C” and “D” are only available on the x32 and x36 versions.

Synchronous Truth Table

Operation Address

Used

State

Diagram

Key E1E2E3ADSP ADSC ADV WDQ3

Deselect Cycle, Power Down None X L X H X L X X High-Z

Deselect Cycle, Power Down None X L L X X L X X High-Z

Deselect Cycle, Power Down None X L X H L X X X High-Z

Deselect Cycle, Power Down None X L L X L X X X High-Z

Deselect Cycle, Power Down None X H X X X L X X High-Z

Read Cycle, Begin Burst External R L H L L X X X Q

Read Cycle, Begin Burst External R L H L H L X F Q

Write Cycle, Begin Burst External W L H L H L X T D

Read Cycle, Continue Burst Next CR X X X H H L F Q

Read Cycle, Continue Burst Next CR H X X X H L F Q

Write Cycle, Continue Burst Next CW X X X H H L T D

Write Cycle, Continue Burst Next CW H X X X H L T D

Read Cycle, Suspend Burst Current X X X H H H F Q

Read Cycle, Suspend Burst Current H X X X H H F Q

Write Cycle, Suspend Burst Current X X X H H H T D

Write Cycle, Suspend Burst Current H X X X H H T D

Notes:

1. X = Don’t Care, H = High, L = Low

2. E = T (True) if E2 = 1 and E1 = E3 = 0; E = F (False) if E2 = 0 or E1 = 1 or E3 = 1

3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.

4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown

as “Q” in the Truth Table above).

5. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish

basic synchronous or synchronous burst operations and may be avoided for simplicity.

6. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.

7. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

First Write First Read

Burst Write Burst Read

Deselect

CRCW

Simple Synchronous OperationSimple Burst Synchronous Operation

CW CR

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.

2. The upper portion of the diagram assumes active use of only the Enable (E1) and W rite (BA, BB, BC, BD, BW, and GW) control inputs, and

that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and

assumes ADSP is tied high and ADV is tied low.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Simplified State Diagram

First Write First Read

Burst Write Burst Read

Deselect

CRCW

CW CR

Notes:

1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.

2. Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing

through a deselect cycle. Dummy read cycles increment the address counter just like normal read cycles.

3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet

Data Input Set Up Time.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Simplified State Diagram with G

Absolute Maximum Ratings

(All voltages reference to VSS)

Symbol Description Value Unit

VDD Voltage on VDD Pins –0.5 to 4.6 V

VDDQ Voltage on VDDQ Pins –0.5 to VDD V

VI/O Voltage on I/O Pins –0.5 to VDD +0.5 ( 4.6 V max.) V

VIN Voltage on Other Input Pins –0.5 to VDD +0.5 ( 4.6 V max.) V

IIN Input Current on Any Pin +/–20 mA

IOUT Output Current on Any I/O Pin +/–20 mA

PDPackage Power Dissipation 1.5 W

TSTG Storage Temperature –55 to 125 oC

TBIAS Temperature Under Bias –55 to 125 oC

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Note:

Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended

Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of

this component.

Power Supply Voltage Ranges (1.8 V/2.5 V Version)

Parameter Symbol Min. Typ. Max. Unit

1.8 V Supply Voltage VDD1 1.7 1.8 2.0 V

2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V

1.8 V VDDQ I/O Supply Voltage VDDQ1 1.7 1.8 VDD V

2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 VDD V

VDDQ2 & VDDQ1 Range Logic Levels

Parameter Symbol Min. Typ. Max. Unit

VDD Input High Voltage VIH 0.6*VDD —VDD + 0.3 V

VDD Input Low Voltage VIL –0.3 —0.3*VDD V

Notes:

1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the

device.

2. VIH (max) must be met for any instantaneous value of VDD.

3. VDD needs to power-up before or at the same time as VDDQ to make sure VIH (max) is not exceeded.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Operating Temperature

Parameter Symbol Min. Typ. Max. Unit

Junction Temperature

(Commercial Range Versions) TJ025 85 C

Junction Temperature

(Industrial Range Versions)* TJ–40 25 100 C

Note:

* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications

quoted are evaluated for worst case in the temperature range marked on the device.

Thermal Impedance

Package Test PCB

Substrate

JA (C°/W)

Airflow = 0 m/s

 JA (C°/W)

Airflow = 1 m/s

 JA (C°/W)

Airflow = 2 m/s JB (C°/W)  JC (C°/W)

165 BGA 4-layer 24.4 21.0 20.0 11.6 3.7

Notes:

1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.

2. Please refer to JEDEC standard JESD51-6.

3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to

the PCB can result in cooling or heating of the RAM depending on PCB temperature.

20% tKC

VSS – 2.0 V

50%

VSS

VIH

Undershoot Measurement and Timing Overshoot Measurement and Timing

20% tKC

VDD + 2.0 V

50%

VDD

VIL

Note:

Input Under/overshoot voltage must be –2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.

Capacitance

oC, f = 1 MHZ, VDD = 2.5 V)

Parameter Symbol Test conditions Typ. Max. Unit

Input Capacitance CIN VIN = 0 V 810 pF

Input/Output Capacitance CI/O VOUT = 0 V 12 14 pF

Note:

These parameters are sample tested.

(TA = 25

AC Test Conditions

Parameter Conditions

VDDQ/2

5030pF*

Output Load 1

* Distributed Test Jig Capacitance

Figure 1

Input high level VDD – 0.2 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level VDD/2

Output reference level VDDQ/2

Output load Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

DC Electrical Characteristics

Parameter Symbol Test Conditions Min Max

Input Leakage Current

(except mode pins) IIL VIN = 0 to VDD –1 uA 1 uA

FT Input Current IIN VDD  VIN  0 V –100 uA 100 uA

Output Leakage Current IOL Output Disable, VOUT = 0 to VDD –1 uA 1 uA

1.8 V Output High Voltage VOH1 IOH = –4 mA, VDDQ = 1.7 V VDDQ – 0.4 V —

2.5 V Output High Voltage VOH2 IOH = –8 mA, VDDQ = 2.375 V 1.7 V —

1.8 V Output Low Voltage VOL1 IOL = 4 mA —0.4 V

2.5 V Output Low Voltage VOL2 IOL = 8 mA —0.4 V

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Operating Currents

Parameter Test Conditions Mode Symbol

-333 -250 -200 -150

Unit

70°C

–40

85°C

70°C

–40

85°C

70°C

–40

85°C

70°C

–40

85°C

Operating

Current

Device Selected;

All other inputs

VIH or VIL

Output open

(x32/

x36)

Pipeline IDD

IDDQ

355

70 375

70 295

50 315

50 250

40 270

40 210

30 230

30 mA

Flow Through IDD

IDDQ

270

45 290

45 240

40 260

40 215

35 235

35 200

30 220

30 mA

(x18) Pipeline IDD

IDDQ

330

35 350

35 265

25 285

25 230

20 250

20 200

15 220

15 mA

Flow Through IDD

IDDQ

245

25 265

25 225

20 245

20 195

15 215

15 185

15 205

15 mA

Standby

Current ZZ VDD – 0.2 V —Pipeline ISB 55 75 55 75 55 75 55 75 mA

Flow Through ISB 55 75 55 75 55 75 55 75 mA

Deselect

Current

Device Deselected;

All other inputs

VIH or  VIL —Pipeline IDD 100 120 100 120 100 120 100 120 mA

Flow Through IDD 100 120 100 120 100 120 100 120 mA

Notes:

1. IDD and IDDQ apply to any combination of VDD1, VDD2, VDDQ1, and VDDQ2 operation.

2. All parameters listed are worst case scenario.

AC Electrical Characteristics

Parameter Symbol -333 -250 -200 -150 Unit

Min Max Min Max Min Max Min Max

Pipeline

Clock Cycle Time tKC 3.0 —4.0 —5.0 —6.7 —ns

Clock to Output Valid tKQ —3.0 —3.0 —3.0 —3.8 ns

Clock to Output Invalid tKQX 1.5 —1.5 —1.5 —1.5 —ns

Clock to Output in Low-Z tLZ11.5 —1.5 —1.5 —1.5 —ns

Setup time tS 1.0 —1.2 —1.4 —1.5 —ns

Hold time tH 0.1 —0.2 —0.4 —0.5 —ns

Flow

Through

Clock Cycle Time tKC 5.0 —5.5 —6.5 —7.5 —ns

Clock to Output Valid tKQ —5.0 —5.5 —6.5 —7.5 ns

Clock to Output Invalid tKQX 2.0 —2.0 —2.0 —2.0 —ns

Clock to Output in Low-Z tLZ12.0 —2.0 —2.0 —2.0 —ns

Setup time tS 1.3 —1.5 —1.5 —1.5 —ns

Hold time tH 0.3 —0.5 —0.5 —0.5 —ns

Clock HIGH Time tKH 1.0 —1.3 —1.3 —1.5 —ns

Clock LOW Time tKL 1.2 —1.5 —1.5 —1.7 —ns

Clock to Output in

High-Z tHZ11.5 3.0 1.5 3.0 1.5 3.0 1.5 3.8 ns

G to Output Valid tOE —3.0 —3.0 —3.0 —3.8 ns

G to output in Low-Z tOLZ10—0—0—0—ns

G to output in High-Z tOHZ1—3.0 —3.0 —3.0 —3.8 ns

ZZ setup time tZZS25—5—5—5—ns

ZZ hold time tZZH21—1—1—1—ns

ZZ recovery tZZR 20 —20 —20 —20 —ns

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Notes:

1. These parameters are sampled and are not 100% tested

2. ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold

times as specified above.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Pipeline Mode Timing

Begin Read A Cont Cont Deselect Write B Read C Read C+1 Read C+2 Read C+3 Cont Deselect

tHZ tKQXtKQtLZtH

tOHZtOE

tHtS

Burst ReadBurst ReadSingle Write

tKCtKC

tKLtKL

tKH

Single WriteSingle Read

tKH

Single Read

Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3)

ABC

Deselected with E1

E1 masks ADSP

E2 and E3 only sampled with ADSP and ADSC

ADSC initiated read

ADSP

ADSC

ADV

A0–An

Ba–Bd

DQa–DQd

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Flow Through Mode Timing

Begin Read A Cont Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C Cont Deselect

tHZtKQX

tKQ

tLZ

tOHZtOE

tKCtKC

tKLtKL

tKHtKH

ABC

Q(A) D(B) Q(C) Q(C+1) Q(C+2) Q(C+3) Q(C)

E2 and E3 only sampled with ADSC

ADSC initiated read

Deselected with E1

Fixed High

ADSP

ADSC

ADV

A0–An

Ba–Bd

DQa–DQd

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Sleep Mode

During normal operation, ZZ must be pulled low, either by the user or by its int ernal pull down resistor. When ZZ is pulled high,

the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to

low, the SRAM operates normally after ZZ recovery time.

Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of

Sleep mode is dictated by the length of ti me the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become

disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.

When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending

operations or operations in progress may not be properly com pleted if ZZ is asserted. Therefore, Sleep mode must not be initiated

until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands

may be applied while the SRAM is recovering from Sleep mode.

Sleep Mode Timing Diagram

tZZR

tZZHtZZS

Hold

Setup

tKLtKL

tKHtKH

tKCtKC

ADSP

ADSC

Application Tips

Single and Dual Cycle Deselect

SCD devices (like this one) force the use of “dummy read cycles” (read cycles that are launched normally but that are ended with

the output drivers inactive) in a fully synchronou s environment. Dumm y read cycles waste performance but their use usually

assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste

bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at

bank address boundary crossings) but greater care must be exercised to avoid exce ssive bus contention.

JTAG Port Operation

Overview

The JTAG Port on this RAM operates in a manner that is compliant w ith IEEE St andard 1149.1-1990, a serial boun dary scan

interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output

drivers are powered by VDDQ.

Disabling the JTAG Port

It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless

clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG

Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO sh ould be left unconnected.

JTAG Pin Descriptions

Pin Pin Name I/O Description

TCK Test Clock In Clocks all T AP events. All inputs are captured on the rising edge of TCK and all outputs propagate

from the falling edge of TCK.

TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP

controller state machine. An undriven TMS input will produce the same result as a logic one input

level.

TDI Test Data In In

The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers

placed between TDI and TDO. The register placed between TDI and TDO is determined by the

state of the TAP Controller state machine and the instruction that is currently loaded in the TAP

Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce

the same result as a logic one input level.

TDO Test Data Out Out Output that is active depending on the state of the TAP state machine. Output changes in

response to the falling edge of TCK. This is the output side of the serial registers placed between

TDI and TDO.

Note:

This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is

held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Port Registers

Overview

The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s

and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the

rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the

TDI and TDO pins.

Instruction Register

The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or

the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the

TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the

controller is placed in Test-Logic-Reset state.

Bypass Register

The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through

the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.

Boundary Scan Register

The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.

The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The

Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the

device pins and the bits in the Boundary Scan Register is describ e d in the Scan Order Tab le following. The Boundary Scan

Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in

Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,

SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.

Instruction Register

ID Code Register

Boundary Scan Register

012

····

31 30 29 12

Bypass Register

TDI TDO

TMS

TCK Test Access Port (TAP) Controller

·· ······

Control Signals

* For the value of M, see the BSDL file, which is available at by contacting us at apps@gsitechnology.com.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG TAP Block Diagram

Identification (ID) Register

The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in

Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.

It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the

controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.

ID Register Contents

Not Used GSI Technology

JEDEC Vendor

ID Code

Presence Register

Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

X X X X X X X X X X X X X X X X X X X X 0 0 0 1 1 0 1 1 0 0 1 1

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Tap Controller Instruction Set

Overview

There are two classes of instructions defined in the Standard 114 9.1-1 990; the standard (Public) instruct ions, and device specific

(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Opt ional Public inst ructions must be

implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load

address, data or control signals into the RAM or to preload the I/O buffers.

When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.

When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired

instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the

TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this

device is listed in the following table.

Select DR

Capture DR

Shift DR

Exit1 DR

Pause DR

Exit2 DR

Update DR

Select IR

Capture IR

Shift IR

Exit1 IR

Pause IR

Exit2 IR

Update IR

Test Logic Reset

Run Test Idle 0

0 0

110

111

JTAG Tap Controller State Diagram

Instruction Descriptions

BYPASS

When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This

occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-

tate testing of other devices in the scan path.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is

loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and

I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and

are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because

the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents

while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will

not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the

TAPs input data captu re set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP

operation except capturing the I/O ring contents into the Boundary Scan Register . Moving the controller to Shift-DR state then

places the boundary scan register between the TDI and TDO pins.

EXTEST

EXTEST is an IEEE 1149.1 mandatory pub lic in str uction . It is to be executed whenever the instruction register is loaded with

all logic 0s. The EXTEST command does not block or override th e RAM’s input pins; therefore, the RAM’s internal state is

still determined by its input pins.



Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD comman d.

Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output

drivers on the falling edge of TCK when the controller is in the Update-IR state.



Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruc-

tion is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not asso-

ciated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TC K in the Capt ure-DR

state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associ-

ated.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and

places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction

loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-

Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR

state.

RFUThese instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.

JTAG TAP Instruction Set Summary

Instruction Code Description Notes

EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1

IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2

SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO.

Forces all RAM output drivers to High-Z. 1

RFU 011 Do not use this instruction; Reserved for Fu ture Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1

SAMPLE/

PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and

TDO. 1

GSI 101 GSI private instruction. 1

RFU 110 Do not use this instruction; Reserved for Fu ture Use.

Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1

BYPASS 111 Places Bypass Register between TDI and TDO. 1

Notes:

1. Instruction codes expressed in binary, MSB on left, LSB on right.

2. Default instruction automatically loaded at power-up and in test-logic-reset state.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Port Recommended Operating Conditions and DC Characteristics (1.8/2.5 V Version)

Parameter Symbol Min. Max. Unit Notes

1.8 V Test Port Input Low Voltage VILJ1 –0.3 0.3 * VDD1 V 1

2.5 V Test Port Input Low Voltage VILJ2 –0.3 0.3 * VDD2 V 1

1.8 V Test Port Input High Vo ltage VIHJ1 0.6 * VDD1 VDD1 +0.3 V 1

2.5 V Test Port Input High Vo ltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V 1

TMS, TCK and TDI Input Leakage Current IINHJ –300 1uA 2

TMS, TCK and TDI Input Leakage Current IINLJ –1100 uA 3

TDO Output Leakage Current IOLJ –1 1 uA 4

Test Port Output High Voltage VOHJ 1.7 —V5, 6

Test Port Output Low Voltage VOLJ —0.4 V5, 7

Test Port Output CMOS High VOHJC VDDQ – 100 mV —V5, 8

Test Port Output CMOS Low VOLJC —100 mV V5, 9

Notes:

1. Input Under/overshoot voltage must be –2 V < Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC.

2. VILJ  VIN VDDn

3. 0 V VIN VILJn

4. Output Disable, VOUT = 0 to VDDn

5. The TDO output driver is served by the VDDQ supply.

6. IOHJ = –4 mA

7. IOLJ = + 4 mA

8. IOHJC = –100 uA

9. IOLJC = +100 uA

Notes:

1. Include scope and jig capacitance.

2. Test conditions as shown unless otherwise noted.

JTAG Port AC Test Conditions

Parameter Conditions

Input high level VDD – 0.2 V

Input low level 0.2 V

Input slew rate 1 V/ns

Input reference level VDDQ/2

Output reference level VDDQ/2

VDDQ/2

5030pF*

JTAG Port AC Test Load

* Distributed Test Jig Capacitance

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

JTAG Port Timing Diagram

tTH

tTS

tTKQ

tTH

tTS

tTH

tTS

tTKLtTKLtTKHtTKHtTKCtTKC

TCK

TDI

TMS

TDO

Parallel SRAM input

JTAG Port AC Electrical Characteristics

Parameter Symbol Min Max Unit

TCK Cycle Time tTKC 50 —ns

TCK Low to TDO Valid tTKQ —20 ns

TCK High Pulse Width tTKH 20 —ns

TCK Low Pulse Width tTKL 20 —ns

TDI & TMS Set Up Time tTS 10 —ns

TDI & TMS Hold Time tTH 10 —ns

Boundary Scan (BSDL Files)

For information regarding the Boundary Scan Chain, or to obtain BSDL fi les for this part, please contact our Applications

Engineering Department at: apps@gsitechnology.com.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Package Dimensions—165-Bump FPBGA (Package D)

1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1

A1 CORNER TOP VIEW A1 CORNER

BOTTOM VIEW

1.0 1.0

10.0

1.01.0

14.0

13±0.05

15±0.05

0.20(4x)

Ø0.10

Ø0.25 C

C A B

Ø0.40~0.60 (165x)

CSEATING PLANE

0.15 C

0.36~0.46

1.40 MAX.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Ordering Information for GSI Synchronous Burst RAMs

Org Part Number1Type Voltage

Option Package Speed2

(MHz/ns) TJ3

2M x 18 GS832118AD-333V Synchronous Burst 1.8 V or 2.5 V 165 BGA 333/5.0 C

2M x 18 GS832118AD-250V Synchronous Burst 1.8 V or 2.5 V 165 BGA 250/5.5 C

2M x 18 GS832118AD-200V Synchronous Burst 1.8 V or 2.5 V 165 BGA 200/6.5 C

2M x 18 GS832118AD-150V Synchronous Burst 1.8 V or 2.5 V 165 BGA 150/7.5 C

1M x 32 GS832132AD-333V Synchronous Burst 1.8 V or 2.5 V 165 BGA 333/5.0 C

1M x 32 GS832132AD-250V Synchronous Burst 1.8 V or 2.5 V 165 BGA 250/5.5 C

1M x 32 GS832132AD-200V Synchronous Burst 1.8 V or 2.5 V 165 BGA 200/6.5 C

1M x 32 GS832132AD-150V Synchronous Burst 1.8 V or 2.5 V 165 BGA 150/7.5 C

1M x 36 GS832136AD-333V Synchronous Burst 1.8 V or 2.5 V 165 BGA 333/5.0 C

1M x 36 GS832136AD-250V Synchronous Burst 1.8 V or 2.5 V 165 BGA 250/5.5 C

1M x 36 GS832136AD-200V Synchronous Burst 1.8 V or 2.5 V 165 BGA 200/6.5 C

1M x 36 GS832136AD-150V Synchronous Burst 1.8 V or 2.5 V 165 BGA 150/7.5 C

2M x 18 GS832118AD-333IV Synchronous Burst 1.8 V or 2.5 V 165 BGA 333/5.0 I

2M x 18 GS832118AD-250IV Synchronous Burst 1.8 V or 2.5 V 165 BGA 250/5.5 I

2M x 18 GS832118AD-200IV Synchronous Burst 1.8 V or 2.5 V 165 BGA 200/6.5 I

2M x 18 GS832118AD-150IV Synchronous Burst 1.8 V or 2.5 V 165 BGA 150/7.5 I

1M x 32 GS832132AD-333IV Synchronous Burst 1.8 V or 2.5 V 165 BGA 333/5.0 I

1M x 32 GS832132AD-250IV Synchronous Burst 1.8 V or 2.5 V 165 BGA 250/5.5 I

1M x 32 GS832132AD-200IV Synchronous Burst 1.8 V or 2.5 V 165 BGA 200/6.5 I

1M x 32 GS832132AD-150IV Synchronous Burst 1.8 V or 2.5 V 165 BGA 150/7.5 I

1M x 36 GS832136AD-333IV Synchronous Burst 1.8 V or 2.5 V 165 BGA 333/5.0 I

1M x 36 GS832136AD-250IV Synchronous Burst 1.8 V or 2.5 V 165 BGA 250/5.5 I

1M x 36 GS832136AD-200IV Synchronous Burst 1.8 V or 2.5 V 165 BGA 200/6.5 I

1M x 36 GS832136AD-150IV Synchronous Burst 1.8 V or 2.5 V 165 BGA 150/7.5 I

2M x 18 GS832118AGD-333V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 333/5.0 C

2M x 18 GS832118AGD-250V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 250/5.5 C

2M x 18 GS832118AGD-200V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 200/6.5 C

2M x 18 GS832118AGD-150V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 150/7.5 C

1M x 32 GS832132AGD-333V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 333/5.0 C

1M x 32 GS832132AGD-250V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 250/5.5 C

1M x 32 GS832132AGD-200V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 200/6.5 C

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832118AD-150IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. C = Commercial Temperature Range. I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many dif ferent configurations and with a variety of dif ferent features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

1M x 32 GS832132AGD-150V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 150/7.5 C

1M x 36 GS832136AGD-333V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 333/5.0 C

1M x 36 GS832136AGD-250V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 250/5.5 C

1M x 36 GS832136AGD-200V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 200/6.5 C

1M x 36 GS832136AGD-150V Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 150/7.5 C

2M x 18 GS832118AGD-333IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 333/5.0 I

2M x 18 GS832118AGD-250IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 250/5.5 I

2M x 18 GS832118AGD-200IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 200/6.5 I

2M x 18 GS832118AGD-150IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 150/7.5 I

1M x 32 GS832132AGD-333IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 333/5.0 I

1M x 32 GS832132AGD-250IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 250/5.5 I

1M x 32 GS832132AGD-200IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 200/6.5 I

1M x 32 GS832132AGD-150IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 150/7.5 I

1M x 36 GS832136AGD-333IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 333/5.0 I

1M x 36 GS832136AGD-250IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 250/5.5 I

1M x 36 GS832136AGD-200IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 200/6.5 I

1M x 36 GS832136AGD-150IV Synchronous Burst 1.8 V or 2.5 V RoHS-compliant 165 BGA 150/7.5 I

Ordering Information for GSI Synchronous Burst RAMs

Org Part Number1Type Voltage

Option Package Speed2

(MHz/ns) TJ3

Notes:

1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832118AD-150IT.

2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each

device is Pipeline/Flow Through mode-selectable by the user.

3. C = Commercial Temperature Range. I = Industrial Temperature Range.

4. GSI offers other versions this type of device in many dif ferent configurations and with a variety of dif ferent features, only some of which are

covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.

36Mb Sync SRAM Datasheet Revision History

File Name Types of Changes

Format or Content Page;Revisions;Reason

8321xxA_V_r1 • Creation of new datasheet

8321xxA_V_r1_01 Content • Updated Absolute Maximum Ratings

• Added thermal information

8321xxA_V_r1_02 Content • Updated to reflect MP status

8321xxA_V_r1_03 Content • Updated Op current numbers

• Updated tHZ, tOE, and tOHZ to 3.0 ns for 333 and 300 MHz

GS832118/32/36AD-xxxV

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.