intel. 27C210 1M (64K x 16) CHMOS EPROM > gm JEDEC Approved EPROM Pinouts g High-Performance 40-Pin DIP _ 120 ns +10% Voce 44-Pin PLCC 50 mA Icc Active w Complete Upgrade to-Higher Densities m Fast Programming w Versatile EPROM Features Quick Pulse Programming CMOS and. TTL Compatibility gorithm . c Two Line Control . Do, Programming Times As Fast As 8 Seconds Intels 27C210 is a 5V only, 1,048,576-bit Erasable Programmable Read Only Memory, organized as 65,536 words of 16 bits each. Its standard pinouts provide for simple upgrades to 4 Mbits in the future. The 27C210 represents state-of-the-art 1 micron CMOS manufacturing technology while providing unequaled performance. Its 120 ns speed (tacc) offers no-wait-state operation with high performance CPUs in applica- tions ranging from numerical control to office automation to telecommunications. Intel offers two DIP profile options to meet your prototyping and production needs. The windowed ceramic dip (CERDIP) package provides erasability and reprogrammability for prototyping and early production. Once the design is in full production, the plastic dip (PDIP) one-time programmable part provides a lower cost alternative that is well adapted for auto insertion. In addition to the JEDEC 40-pin DIP package, Intel also offers a 44-lead PLCC version of the 27C210. This one-time-programmable surface mount device is ideal where board space consumption is a major concern or where surface mount manufacturing technology is being implemented across an entire production line. The 27C210 is equally at home in both a TTL or CMOS environment. And like Intels other 1 Mbit EPROMs, the 27C210 programs quickly using Intel's industry leading Quick-Pulse Programming algorithm. V DATA OUTPUTS cc & . 09-945 Vep o> OE f OUTPUT ENABLE PGM | CHIP ENABLE AND ~ cE > PROG LOGIC OUTPUT BUFFERS i Y 3 . =S| DECODER : GATING Ao-A1s = rots Ts] olen | 3 1,048,576-BIT s| vecovern | : CELL MATRIX P > 290193-1 Figure 1. Block Diagram September 1990 -92 Order Number: 290193-003a intel. 276210 4M 2M 27C210 2M 4M , Vpp | Vep ver C11 0 vec Voc Veco cE |. CE eqh2 39 Pow FGM Air Ow | Os %sc]s 38 Nc Ate Ate O14 FOr vcs 371s Ans Ats . Ors | O13 Weds seb Aa Ava Av Ora Ora CCS 350413 Aisa Ay Pin Names On On ond? sata Ar2 Ate Ai2 Ag-A17 | ADDRESSES Or | O10 odds asboAn An An CE | CHIPENABLE Og erde 32b0410 Ato Ato OE [OUTPUT ENABLE Os 8 acqi0 sips Ag Ag GND | GND edi 30/5 ono GND {| GND fRaaTeRoaran Or | o% | mehi2 ase | fe | Me Os Os scdis 2p? Ar Az [NC |NO INTERNAL CONNECT Os Os osc] abs he Ae 4 O %CF15 284s As As Os Os %3Ch16 ap. Ag Ag Oz | O2 Sechi7 244s Ag As 1 1 - EF 18 asf A2 Ae Ae Oo Qo oedi9 2p" Ay AY OE oe C20 2140 Ao Ao . 290199-2 Figure 2. DIP Pin Configuration mazKis! titi tiitilt itty t ell t tit 27240 (64K x 16)} 13] | O14) | 1st | cel | vept | we | [vec] |Poad | nc} {ys | Ara) YS LoCo Pa eo ea en a a et 6 5 4 3 2 44430 4204140 42 (} \ 39 | AV 911 [Is 38 il Ad PPro} [} 37 | Ate 45 [}o 36 | d= +4 [| " 44 LEAD PLCC 35 | ar lend [ 12 0.650" x 0.650" 3a 1 od . TOP VIEW Nc [hss 33 i nel - C 14 32 i ae log [ 15 31 | a +o. [| 16 30 i Ask ao, hl 17 29 | Agl~ 18 19 20 21 22 23 24 25 26 27 28 Mc ooo ooo /, 95 []oo ]] os [foo] | Sfp nc t{ Ao tt Art l az || Ast Aa THT TET TE Et 290193-3 5-93 Figure 3. PLCC Lead Configurationintel. 270210 ABSOLUTE MAXIMUM RATINGS* NOTICE: This is a production data sheet. The specifi- 0 ing T : C ec(t) cations are subject to change without notice. perating emperature seen ee eeeees 0C to 70 Cc * WARNING: Stressing the device beyond the Absolute Temperature Under Bias........ *...10C to 80C Maximum Ratings may cause permanent damage. Storage Temperature............. 65C to 125C These are stress ratings only. Operation beyond the Vol A . : Operating Conditions is not recommended and ex- oltage on Any Pin tended exposure beyond the Operating Conditions (except Ag, Vcc and Vpp) may affect device reliability. with Respect to GND ........ 0.6V to 6.5V(2, 8) Voltage on Ag with Notice: Specifications contained within the following RespecttoGND............. 0.6V to 13.0V(2) tables are subject to change. Vep Program Voltage , with Respect toGND......... -. 0.6V to t4V@2) Voc Supply Voltage with Respect toGND ......... :0.6V to 7,0V(2) READ OPERATION DC CHARACTERISTICS(1) Vcc =.5.0V +10% Symbol Parameter Notes|. Min Typ Max Unit Test Condition lu input Load Current 7 , 0.01 1.0 pA | Vin = OV to Voc lLo Output Leakage Current{) ~~ of +10 BA | Vout = OV to Voc Isp Voc Standby Current 1.0 mA | CE = Vin a _ 100 | pA | CE = Voc +0.2V loc Voc Operating 3 50 mA | CE = Vit Current - f = 5 MHz, lout = OMA Ipp Vpp Operating Current 3 10 BA | Vpp = Voc los Output Short , 4,6 100 mA Circuit Current Vit Input Low Voltage ~ -0.5 0.8 Vv Vin Input High Voltage 2.0 Voc + 0.5] V Voi Output Low-Voltage 0.45 Vi ilo. = 2.1mA Vou | Output High Voltage 2.4 V | lon = 400 pA . Vpp Vpp Operating Voltage 5 Voc 0.7 Voc v NOTES: . 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is 0.5V on input/output pins. During transitions, this level may undershoot to 2.0V for periods <20 ns. Maximum DC voltage on input/output pins is Voc + 0.5V which during transitions, may overshoot to Voc + 2.0V for periods <20 ns. . 3. Maximum active power usage is the sum Ipp + loc. Maximum current value is with outputs Og to O15 unloaded. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. Vpp may be connected directly to Voc, or may be one diode voltage drop below Voc. Voc must be applied simultaneously or before Vpp and removed simultaneously or after: Vpp. 6. Sampled, not 100% tested. 7. Typical limits are at Voc = 5V, Ta = 25C. 8. Absolute Maximum ratings apply to NC pins. 5-94intel. 276210 READ OPERATION AC CHARACTERISTICS() Vcc = 5.0v + 10% 27C210-150V10 27C6210-200V10 Versions(4) Voc + 10% 27C210-120V10 P27C210-150V10 P27C210-200V10 N27C210-150V10 | N27C210-200Vv10 | Unit Symbol Parameter Notes; Min Max Min Max Min Max tacc _| Address to Output Delay , 120 150 200 | ns tce CE to Output Delay 2 120 150 200 ns tog OE to Output Delay 2 55 60 70 ns tor OE High to Output High Z | 3 "30 50 60 ns tou Output Hold from 3 0 0 0 ns Addresses, CE or OE ChangeWhichever is First NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE may be delayed up to tce-toe after the falling edge of CE without impact on tce. 3. Sampied, not 100% tested. 4, Model Number Prefixes: no prefix = CERDIP, P = PDIP, N = PLCC. 5. Typical limits are set for Ta = 25C and nominal supply voltages. CAPACITANCE(S) T, = 25C, f = 1 MHz Parameter Max | Unit | Conditions 4 8 =0V 8 12 =O0V 18 25 =0V AC INPUT/OUTPUT REFERENCE WAVEFORM AC TESTING LOAD CIRCUIT 1.3V 24 20 4 2.0 1N914 as rut X os st POINTS <Xin OUTPUT 290199-6 RL DEVICE , UNDER OUT AC test inputs are driven at Vox (2.4 Viti) for a Logic 1 and TEST Vor (0.45 Vir) for a Logic 0. Input timing begins at Vin Co (2.0 Vey) and Vi, (0.8 Vir). Output timing ends at Vij and Vic. TL Input Rise and Fall times (10% to 90%) < 10 ns. = C. = 100 pF . 290193-7 C, Includes Jig Capacitance RL = 3.3 ko 5-95intel. 270210 AC WAVEFORMS N Vit ener : : te vu \__....4 tee > : YY oe toe + face 7 tox Vues : pom sees : . IGH WT) . maHz ouTpuTs Hen _ VAUD OUTPUT . ts MAW 7 i ><. P ADDRESS VALID 290193-8 DEVICE OPERATION The Mode Selection table lists 27C210 operating modes. Read Mode requires a single 5V power supply. All inputs, except Voc and Vpp, and Ag during intgligent Identifier Mode, are TTL or CMOS. : Table 1. Mode Selection Mode Notes | CE | OF | PGM | Ag | Ap | Vpp | Vcc | Outputs Read 1 ViL Vit Xx x X Voc | Voc Dout Output Disable | vi | Vin |X xX | X | Veco | Veco | Highz Standby Vin | xX x x | X | Veco | Voc. | Highz Program } 2 | vel] Mal Vie X X | Vpp | Vep Din Program Verify Vit ViL Vin x xX Vpp Vop Dout Program Inhibit VIH xX xX xX xX Vpp | Vop High Z intgligent | Manufacturer 23 ViL Vit xX Vio | Vic | Voo | Voc 0089 H Identifier Device Vie | Ve | xX | Vo | Vm | Voc | Veco | 11EEH NOTES: 1. X can be Vi, or Vin 2. See DC Programming Characteristics for Vop, Vpp and Vip voltages. 3. AyAg, A1o-Ats = ViLintel. 27210 Read Mode The 27C210 has two control functions; both must be enabled to obtain data at the.outputs: CE is the pow- er control and device select. .OE controls the output buffers to gate data to the outputs. With addresses stable, the address access time (tacc) equals the delay from CE to output (tcE). Outputs display valid data tog after OE's falling edge, assuming tacc and tce times are met. Vcc must be appiled simuitaneously or before Vpp and removed simultaneously or after Vpp. Two Line Output Control EPROMs are often used in larger memory arrays. Intel. provides two control inputs to accommodate multiple memory connections. Two-line control pro- vides for: a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these two control inputs, an ad- dress decoder should enable CE, while OE should be connected to all memory devices and the sys- tems READ control line. This assures that only se- lected memory devices have active outputs while deselected memory devices are in Standby Mode. Standby Mode Standby Mode substantially reduces Voc current. When CE = Vip, the outputs are in a high imped- ance state, independent of OE. Program Mode Caution: Exceeding 14V on Vpp will permanently damage the device. Initially, and after each erasure, all EPROM bits are in the 1 state. Data is introduced by selectively programming Os into the desired bit locations. Al- though only Os are programmed, the data word can contain both 1s and Os. Ultraviolet light era- sure is the only way to change Os to 1s. Program Mode is entered when Vpp is raised to 12.75V. Data is introduced by applying a 16-bit word to the output pins. Pulsing PGM low while CE = Vi_ and OE = Vjq programs that data into the device. 5-97 Program Verity A verify should be performed following a program operation-to determine that bits have been correctly programmed. With Vcc at 6.26V, a substantial: pro- gram on is ensured. The verify is performed with CE at. Vy and.PGM at Viz. Valid data i is available tog after OE falls low. Program. Inhibit Program Inhibit Mode allows parallel programming of multipte EPROMs with different data. CE-high in- fo oe ar Ee of non-targeted devices. Except E, parallel EPROMs may have common inputs. inteligent Identifier Mode The intgligent Identifier Mode will determine an EPROMs manufacturer and device type, allowing programming equipment to automatically match a device with its proper programming algorithm. This mode is activated when a programmer forces 12V +0.5V on Ag. With CE, OE, AyAg, and Ajo- Ais at Vit, Ao = Vir will present the manufacturer code and Ay = Viq the device code. This mode functions in the 25C +5C ambient temperature range required during programming. UPGRADE PATH Future upgrades to 2 Mbit and 4 Mbit densities are easily accomplished due to the standardized pin configuration of the 27C210. When the 27C210 is in Read Mode, the PGM input becomes non-functional. The PGM and NC pins may be Vi_ and Viq. This allows address lines Ayg-A 17 to be routed directly to these inputs in anticipation of future density up- grades. Systems designed for 1 Mbit program mem- ories today can be upgraded to higher densities (2 Mbit and 4 Mbit) in the future with no circuit board changes.ntel. 27C210 SYSTEM CONSIDERATIONS EPROM power switching characteristics require Careful device decoupling. System designers are in- terested in 3 supply current issues: standby current levels (gg), active current levels (icc), and transient Current. peaks. produced by falling and rising edges of CE. Transient current magnitudes depend on the device outputs capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage. peaks. Each device should have a 0.1 uF ceramic capacitor connected between its Voc and GND. This high fre- quency, low inherent-inductance capacitor should be placed as close as possible to the device. Addi- tionally, for every 8 devices, a 4.7 pF electrolytic capacitor should be placed at the arrays power sup- ply connection between Voc and GND. The bulk ca- pacitor will overcom voltage slumps.caused by PC board trace inductances. 5-98 ERASURE CHARACTERISTICS Erasure begins when EPROMs are exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). it should be noted. that sunlight and certain fluorescent lamps have wavelengths in. the 3000A-4000A range. Data shows that constant ex- Posure to room ievel fluorescent lighting can erase an EPRON in approximately 3 years, while it takes approximately 1 week when exposed to direct sun- light. If the device is exposed to these lighting condi- tions for extended periods, opaque labels should be placed over the window to prevent unintentional era- sure. The recommended erasure procedure -is exposure to ultraviolet light of wavelength 2537A. The inte- grated dose (UV intensity < exposure time) for era- sure should be a minimum of 15 Wsec/cm2. Erasure time is approximately 15 to 20 minutes using an ul- traviolet lamp with a 12000 W/cm? power rating. The EPROM should be placed within 1 inch of the lamp tubes. An EPROM can be permanently dam- aged if the integrated dose exceeds 7258 Wsec/cm? (1 week @ 12000 W/cm2).ntel. 27210 INCREMENT ADDRESS ADDRESS = FIRST LOCATION Veco = 6.25V Vpp = 12.75V PROGRAM ONE 100 ws PULSE INCREMENT X DEVICE FAILED DEVICE PASSED 290193-9 Figure 4. Quick-Pulse Programming Algorithm Quick-Pulse Programming Algorithm The Quick-Pulse Programming algorithm programs Intels 27C210. Developed to substantially reduce programming throughput, this algorithm can program the 270210 as fast as 8 seconds. Actual program- ming time depends on programmer overhead. 5-99 The Quick-Pulse Programming algorithm employs a 100 1s pulse followed by a word verification to de- termine when the addressed word has been suc- cessfully programmed. The algorithm terminates if 25 attempts fail to program a word. The entire program pulse/word verify sequence is performed with Vpp = 12.75V and Voc = 6.25V. When programming is complete, all words are com- pared to the original data with Voc = Vpp = 5.0V.intel. 270210 DC PROGRAMMING CHARACTERISTICS T, = 25C +5C Symbol Parameter Notes |; Min Typ | Max | Unit Test Condition ha Input Load Current 1 PA | Vin = Vicor Vin Icp Voc Program Current 1 50 | mA | CE = PGM = Vi Ipp Vpp Program Current 1 50 | mA | CE = PGM = Vi, Vit Input Low Voltage 0.1 0.8 Vv Vin Input High Voltage 2.4 6.5 Vv VoL Output Low Voltage (Verify) ; 0.45 Vv lo. = 2.1mA Vou Output High Voltage (Verify) 3.5 ; Vv lon = 2.5mA Vip Ag intgligent Identifier Voltage 11.5 12.0. | 12.5 Vv Vpp Vpp Program Voltage 2,3 12.5 |. 12.75 | 13.0 Vv Vop Voc Supply Voltage (Program) 2 6.0 6.25 6.5 Vv AC PROGRAMMING CHARACTERISTICS(4) T, = 25C +5C Symbol Parameter Notes Min Typ Max Unit tycs Vop Setup Time 2 2 ps tyes Vpp Setup Time 2 2 pS tces CE Setup Time 2 pS tas Address Setup Time 2 ps tos Data Setup Time 2 ps tpw PGM Program Pulse Width 95 100 105 BS toH Data Hold Time 2 ps toes GE Setup Time 2 ps toe Data Valid from OE 5 150 ns torp OEHighto OutputHighZ | 5,6 0 130 ns tAH Address Hold Time 0 ps NOTES: 1. Maximum current is with outputs O9~O15 unloaded. 2. Vcp must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 3. When programming, a 0.1 uF capacitor is required across Vpp and GND to suppress spurious voltage transients which can damage the device. : 4. See AC Input/Output Reference Waveform for timing measurements. 5. tog and tpgp are device characteristics but must be accommodated by the programmer. 6. Sampled, not 100% tested. 5-100intel. 270210 PROGRAMMING WAVEFORMS PROGRAM VERIFY vi 1 ADDRESSES . x : ADORESS STABLE Vin ze Leg AS DATA _{ DATA in STABLE panna DATA OUT . vit meg ! : tos__J Lg tov 5] tps. - CS Ld 4 L a4 Vin Veh ta Yu tow toes foe _ . SY 290193-10 REVISION HISTORY Number Description 03 Revised general datasheet structure, text to improve clarity Revised speed bin as follows: tacc was 130 ns, is now 120 ns tce was 130 ns, is now 120 ns tog was 60 ns, is now 55 ns Added PDIP package Revised Isp Text Condition from CE = Voc to CE = Voc +0.2V Revised Vo, from 0.4V to 0.45V Revised Vox from Veco 0.8V to 2.4V Deleted 8 meg DIP, 4 and 8 Meg PLCC references Deleted EXPRESS page 5-101