©2009 Silicon Storage Technology, Inc.
S71160-15-000 2/09
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
SSF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
Data Sheet
2 Mbit / 4 Mbit (x8) Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
FEATURES:
Organized as 256K x8 / 512K x8
Single Voltage Read and Write Operations
4.5-5.5V for SST29SF020/040
2.7-3.6V for SST29VF020/040
Superior Reliability
Endurance: 100,000 Cycles (typical)
Greater than 100 years Data Retention
Low Power Consumption:
Active Current: 10 mA (typical)
Standby Current:
30 µA (typical) for SST29SF020/040
1 µA (typical) for SST29VF020/040
Sector-Erase Capability
Uniform 128 Byte sectors
Fast Read Access Time:
55 ns for SST29SF020/040
70 ns for SST29VF020/040
Latched Address and Data
Fast Erase and Byte-Program:
Sector-Erase Time: 18 ms (typical)
Chip-Erase Time: 70 ms (typical)
Byte-Program Time: 14 µs (typical)
Chip Rewrite Time:
4 seconds (typical) for SST29SF/VF020
8 seconds (typical) for SST29SF/VF040
Automatic Write Timing
Internal VPP Generation
End-of-Write Detection
Toggle Bit
Data# Polling
TTL I/O Compatibility for SST29SF020/040
CMOS I/O Compatibility for SST29VF020/040
JEDEC Standard
Flash EEPROM Pinouts and command sets
Packages Available
32-lead PLCC
32-lead TSOP (8mm x 14mm)
All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST29SF020/040 and SST29VF020/040 are 256K
x8 / 512K x8 CMOS Small-Sector Flash (SSF) manufac-
tured with SST’s proprietary, high-performance CMOS
SuperFlash technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The SST29SF020/040 devices write (Program or Erase)
with a 4.5-5.5V power supply. The SST29VF020/040
devices write (Program or Erase) with a 2.7-3.6V power
supply. These devices conform to JEDEC standard pin
assignments for x8 memories.
Featuring high performance Byte-Program, the
SST29SF020/040 and SST29VF020/040 devices pro-
vide a maximum Byte-Program time of 20 µsec. To protect
against inadvertent write, they have on-chip hardware and
Software Data Protection schemes. Designed, manufac-
tured, and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of at least
10,000 cycles. Data retention is rated at greater than 100
years.
The SST29SF020/040 and SST29VF020/040 devices
are suited for applications that require convenient and eco-
nomical updating of program, configuration, or data mem-
ory. For all system applications, they significantly improve
performance and reliability, while lowering power consump-
tion. They inherently use less energy during Erase and
Program than alternative flash technologies. The total
energy consumed is a function of the applied voltage, cur-
rent, and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to pro-
gram and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less than
alternative flash technologies. They also improve flexibility
while lowering the cost for program, data, and configuration
storage applications.
The SuperFlash technology provides fixed Erase and Pro-
gram times independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
To meet high density, surface mount requirements, the
SST29SF020/040 and SST29VF020/040 devices are
offered in 32-lead PLCC and 32-lead TSOP packages. The
pin assignments are shown in Figures 2 and 3.
SST29SF/VF020 / 0402Mb / 4Mb (x8)
Byte-Program, Small-Sector flash memories
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2
Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST29SF020/040 and
SST29VF020/040 devices are controlled by CE# and
OE#, both have to be low for the system to obtain data from
the outputs. CE# is used for device selection. When CE# is
high, the chip is deselected and only standby power is con-
sumed. OE# is the output control and is used to gate data
from the output pins. The data bus is in high impedance
state when either CE# or OE# is high. Refer to the Read
cycle timing diagram in Figure 4 for further details.
Byte-Program Operation
The SST29SF020/040 and SST29VF020/040 devices
are programmed on a byte-by-byte basis. Before program-
ming, the sector where the byte exists must be fully erased.
The Program operation is accomplished in three steps. The
first step is the three-byte load sequence for Software Data
Protection. The second step is to load byte address and
byte data. During the Byte-Program operation, the
addresses are latched on the falling edge of either CE# or
WE#, whichever occurs last. The data is latched on the ris-
ing edge of either CE# or WE#, whichever occurs first. The
third step is the internal Program operation which is initi-
ated after the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once initiated, will
be completed, within 20 µs. See Figures 5 and 6 for WE#
and CE# controlled Program operation timing diagrams
and Figure 16 for flowcharts. During the Program opera-
tion, the only valid reads are Data# Polling and Toggle Bit.
During the internal Program operation, the host is free to
perform additional tasks. Any commands written during the
internal Program operation will be ignored.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The SST29SF020/
040 and SST29VF020/040 offer Sector-Erase mode. The
sector architecture is based on uniform sector size of 128
Bytes. The Sector-Erase operation is initiated by executing
a six-byte command sequence with Sector-Erase com-
mand (20H) and sector address (SA) in the last bus cycle.
The sector address is latched on the falling edge of the
sixth WE# pulse, while the command (20H) is latched on
the rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. For timing waveforms, see
Figure 9. Any commands issued during the Sector-Erase
operation are ignored.
Chip-Erase Operation
The SST29SF020/040 and SST29VF020/040 devices
provide a Chip-Erase operation, which allows the user to
erase the entire memory array to the “1s” state. This is use-
ful when the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 555H in the last
byte sequence. The internal Erase operation begins with
the rising edge of the sixth WE# or CE#, whichever occurs
first. During the internal Erase operation, the only valid read
is Toggle Bit or Data# Polling. See Table 4 for the command
sequence, Figure 10 for the timing diagram, and Figure 19
for the flowchart. Any commands written during the Chip-
Erase operation will be ignored.
Write Operation Status Detection
The SST29SF020/040 and SST29VF020/040 devices
provide two software means to detect the completion of a
Write (Program or Erase) cycle, in order to optimize the
system Write cycle time. The software detection includes
two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6).
The End-of-Write detection mode is enabled after the ris-
ing edge of WE# which initiates the internal Program or
Erase operation.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data# Poll-
ing or Toggle Bit read may be simultaneous with the
completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to pre-
vent spurious rejection, if an erroneous result occurs, the
software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
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Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
3
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
Data# Polling (DQ7)
When the SST29SF020/040 and SST29VF020/040
devices are in the internal Program operation, any
attempt to read DQ7 will produce the complement of the
true data. Once the Program operation is completed,
DQ7 will produce true data. Note that even though DQ7
may have valid data immediately following the completion
of an internal Write operation, the remaining data outputs
may still be invalid: valid data on the entire data bus will
appear in subsequent successive Read cycles after an
interval of 1 µs. During internal Erase operation, any
attempt to read DQ7 will produce a ‘0’. Once the internal
Erase operation is completed, DQ7 will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE#
(or CE#) pulse for Program operation. For Sector- or
Chip-Erase, the Data# Polling is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 7 for
Data# Polling timing diagram and Figure 17 for a flow-
chart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating ‘0’s
and ‘1’s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The device is then ready for the next operation. The
Toggle Bit is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector or Chip-
Erase, the Toggle Bit is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing dia-
gram and Figure 17 for a flowchart.
Data Protection
The SST29SF020/040 and SST29VF020/040 devices
provide both hardware and software features to protect
nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 2.5V for SST29SF020/
040. The Write operation is inhibited when VDD is less than
1.5V. for SST29VF020/040.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST29SF020/040 and SST29VF020/040 provide
the JEDEC approved Software Data Protection scheme for
all data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three- byte sequence. The three-byte load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of a six-byte load sequence. These
devices are shipped with the Software Data Protection per-
manently enabled. The specific software command codes
are shown in Table 4. During SDP command sequence,
invalid commands will abort the device to read mode, within
TRC.
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4
Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
Product Identification
The Product Identification mode identifies the devices as
SST29SF020, SST29SF040 and SST29VF020,
SST29VF040 and manufacturer as SST. This mode may
be accessed by software operations. Users may use the
Software Product Identification operation to identify the part
(i.e., using the device ID) when using multiple manufactur-
ers in the same socket. For details, see Table 4 for software
operation, Figure 11 for the Software ID Entry and Read
timing diagram, and Figure 18 for the Software ID Entry
command sequence flowchart.
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read operation.
Please note that the Software ID Exit command is ignored
during an internal Program or Erase operation. See Table 4
for software command codes, Figure 12 for timing wave-
form, and Figure 18 for a flowchart.
FIGURE 1: Functional Block Diagram
TABLE 1: Product Identification
Address Data
Manufacturer’s ID 0000H BFH
Device ID
SST29SF020 0001H 24H
SST29VF020 0001H 25H
SST29SF040 0001H 13H
SST29VF040 0001H 14H
T1.3 1160
Y-Decoder
I/O Buffers and Data Latches
1160 B1.0
Address Buffers & Latches
X-Decoder
DQ7 - DQ0
Memory
Address
OE#
CE#
WE#
SuperFlash
Memory
Control Logic
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Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
5
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
FIGURE 2: Pin Assignments for 32-lead PLCC
FIGURE 3: Pin Assignments for 32-lead TSOP (8mm x 14mm)
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
4 3 2 1 32 31 30
A12
A15
A16
NC
VDD
WE#
A17
A12
A15
A16
A18
VDD
WE#
A17
32-lead PLCC
Top View
1160 32-plcc NH P1.2
14 15 16 17 18 19 20
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
SST29SF/VF020SST29SF/VF040 SST29SF/VF020 SST29SF/VF040
SST29SF/VF020SST29SF/VF040 SST29SF/VF020 SST29SF/VF040
A11
A9
A8
A13
A14
A17
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
A17
WE#
VDD
A18
A16
A15
A12
A7
A6
A5
A4
SST29SF/VF020SST29SF/VF040 SST29SF/VF020 SST29SF/VF040
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1160 32-tsop WH P2.2
Standard Pinout
Top View
Die Up
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6
Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
TABLE 2: Pin Description
Symbol Pin Name Functions
AMS1-A0
1. AMS = Most significant address
AMS = A17 for SST29SF/VF020 and A18 for SST29SF/VF040
Address Inputs To provide memory addresses. During Sector-Erase AMS-A8 address lines will select the
sector.
DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE# Chip Enable To activate the device when CE# is low.
OE# Output Enable To gate the data output buffers.
WE# Write Enable To control the Write operations.
VDD Power Supply To provide power supply voltage: 4.5-5.5V for SST29SF020/040
2.7-3.6V for SST29VF020/040
VSS Ground
NC No Connection Pin not connected internally
T2.5 1160
TABLE 3: Operation Modes Selection
Mode CE# OE# WE# DQ Address
Read VIL VIL VIH DOUT AIN
Program VIL VIH VIL DIN AIN
Erase VIL VIH VIL X1
1. X can be VIL or VIH, but no other value.
Sector address,
XXH for Chip-Erase
Standby VIH X X High Z X
Write Inhibit X VIL X High Z/ DOUT X
XXV
IH High Z/ DOUT X
Product Identification
Software Mode VIL VIL VIH See Table 4
T3.4 1160
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Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
7
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
TABLE 4: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data
Byte-Program 555H AAH 2AAH 55H 555H A0H BA2Data
Sector-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H SAX320H
Chip-Erase 555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H
Software ID Entry4,5 555H AAH 2AAH 55H 555H 90H
Software ID Exit6XXH F0H
Software ID Exit6555H AAH 2AAH 55H 555H F0H
T4.7 1160
1. Address format A14-A0 (Hex),
Addresses A15-AMS can be VIL or VIH, but no other value, for the Command sequence for SST29SF/VF020/040.
AMS = Most significant address
AMS = A17 for SST29SF/VF020 and A18 for SST29SF/VF040.
2. BA = Program Byte address
3. SAX for Sector-Erase; uses AMS-A7 address lines for SST29SF/VF020/040
4. The device does not remain in Software Product ID mode if powered down.
5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,
SST29SF020 Device ID = 24H, is read with A0 = 1
SST29VF020 Device ID = 25H, is read with A0 = 1
SST29SF040 Device ID = 13H, is read with A0 = 1
SST29VF040 Device ID = 14H, is read with A0 = 1
6. Both Software ID Exit operations are equivalent
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8
Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Through Hole Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.
2. Outputs shorted for no more than one second. No more than one output shorted at a time.
Operating Range for SST29SF020/040
Range Ambient Temp VDD
Commercial 0°C to +70°C 4.5-5.5V
Industrial -40°C to +85°C 4.5-5.5V
Operating Range for SST29VF020/040
Range Ambient Temp VDD
Commercial 0°C to +70°C 2.7-3.6V
Industrial -40°C to +85°C 2.7-3.6V
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 55 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 70 ns
See Figures 13, 14, and 15
TABLE 5: DC Operating Characteristics VDD = 4.5-5.5V for SST29SF020/040
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDD Power Supply Current Address input=VIL/VIH, at f=1/TRC Min
VDD=VDD Max
Read 25 mA CE#=OE#=VIL, WE#=VIH, all I/Os open
Write 30 mA CE#=WE#=VIL, OE#=VIH
ISB1 Standby VDD Current (TTL input) 3 mA CE#=VIH, VDD=VDD Max
ISB2 Standby VDD Current (CMOS input) 100 µA CE#=VIHC, VDD=VDD Max
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VIH Input High Voltage 2.0 V VDD=VDD Max
VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
VOL Output Low Voltage 0.4 V IOL=2.1 mA, VDD=VDD Min
VOH Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min
T5.7 1160
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Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
9
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
TABLE 6: DC Operating Characteristics VDD = 2.7-3.6V for SST29VF020/040
Symbol Parameter
Limits
Test ConditionsMin Max Units
IDD Power Supply Current Address input=VIL/VIH, at f=1/TRC Min
VDD=VDD Max
Read 25 mA CE#=OE#=VIL, WE#=VIH, all I/Os open
Write 30 mA CE#=WE#=VIL, OE#=VIH
ISB Standby VDD Current 30 µA CE#=VIHC, VDD=VDD Max
ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max
ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max
VIL Input Low Voltage 0.8 V VDD=VDD Min
VIH Input High Voltage 0.7VDD VV
DD=VDD Max
VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max
VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min
VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min
T6.9 1160
TABLE 7: Recommended System Power-up Timings
Symbol Parameter Minimum Units
TPU-READ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Power-up to Read Operation 100 µs
TPU-WRITE1Power-up to Program/Erase Operation 100 µs
T7.1 1160
TABLE 8: Capacitance (TA = 25°C, f=1 Mhz, other pins open)
Parameter Description Test Condition Maximum
CI/O1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
I/O Pin Capacitance VI/O = 0V 12 pF
CIN1Input Capacitance VIN = 0V 6 pF
T8.1 1160
TABLE 9: Reliability Characteristics
Symbol Parameter Minimum Specification Units Test Method
NEND1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Endurance 10,000 Cycles JEDEC Standard A117
TDR1Data Retention 100 Years JEDEC Standard A103
ILTH1Latch Up 100 + IDD mA JEDEC Standard 78
T9.2 1160
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10
Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
AC CHARACTERISTICS
TABLE 10: Read Cycle Timing Parameters
VDD = 4.5-5.5V for SST29SF020/040 and 2.7-3.6V for SST29VF020/040
Symbol Parameter
SST29SF020/040-55 SST29VF020/040-70
UnitsMin Max Min Max
TRC Read Cycle Time 55 70 ns
TCE Chip Enable Access Time 55 70 ns
TAA Address Access Time 55 70 ns
TOE Output Enable Access Time 30 35 ns
TCLZ1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
CE# Low to Active Output 0 0 ns
TOLZ1OE# Low to Active Output 0 0 ns
TCHZ1CE# High to High-Z Output 20 25 ns
TOHZ1OE# High to High-Z Output 20 25 ns
TOH1Output Hold from Address Change 00ns
T10.10 1160
TABLE 11: Program/Erase Cycle Timing Parameters
VDD = 4.5-5.5V for SST29SF020/040 and 2.7-3.6V for SST29VF020/040
Symbol Parameter Min Max Units
TBP Byte-Program Time 20 µs
TAS Address Setup Time 0 ns
TAH Address Hold Time 30 ns
TCS WE# and CE# Setup Time 0 ns
TCH WE# and CE# Hold Time 0 ns
TOES OE# High Setup Time 0 ns
TOEH OE# High Hold Time 10 ns
TCP CE# Pulse Width 40 ns
TWP WE# Pulse Width 40 ns
TWPH1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
WE# Pulse Width High 30 ns
TCPH1CE# Pulse Width High 30 ns
TDS Data Setup Time 40 ns
TDH1Data Hold Time 0 ns
TIDA1Software ID Access and Exit Time 150 ns
TSE Sector-Erase 25 ms
TSCE Chip-Erase 100 ms
T11.9 1160
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Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
11
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
FIGURE 4: Read Cycle Timing Diagram
FIGURE 5: WE# Controlled Program Cycle Timing Diagram
1160 F03.1
ADDRESS AMS-0
DQ7-0
WE#
OE#
CE#
TCE
TRC TAA
TOE
TOLZ
VIH
HIGH-Z
TCLZ TOH TCHZ
HIGH-Z
DATA VALIDDATA VALID
TOHZ
Note: AMS = Most significant address
AMS = A17 for SST29SF/VF020 and A18 for SST29SF/VF040
1160 F04.1
ADDRESS AMS-0
DQ7-0
TDH
TWPH TDS
TWP
TAH
TAS
TCH
TCS
CE#
SW0 SW1 SW2
555 2AA 555 ADDR
AA 55 A0 DATA
BYTE
(ADDR/DATA)
OE#
WE#
TBP
INTERNAL
PROGRAM
OPERATION
STARTS
Note: AMS = Most significant address
AMS = A17 for SST29SF/VF020 and A18 for SST29SF/VF040
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12
Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
FIGURE 6: CE# Controlled Program Cycle Timing Diagram
FIGURE 7: Data# Polling Timing Diagram
1160 F05.1
ADDRESS AMS-0
DQ7-0
TDH
TCPH TDS
TCP
TAH
TAS
TCH
TCS
WE#
SW0 SW1 SW2
555 2AA 555 ADDR
AA 55 A0 DATA
INTERNAL PROGRAM OPERATION STARTS
BYTE
(ADDR/DATA)
OE#
CE#
TBP
Note: AMS = Most significant address
AMS = A17 for SST29SF/VF020 and A18 for SST29SF/VF040
1160 F06.1
ADDRESS AMS-0
DQ7DD# D# D
WE#
OE#
CE#
TOEH
TOE
TCE
TOES
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Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
13
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
FIGURE 8: Toggle Bit Timing Diagram
FIGURE 9: WE# Controlled Sector-Erase Timing Diagram
1160 F07.1
ADDRESS AMS-0
DQ6
WE#
OE#
CE#
TOE
TOEH
TCE
TOES
TWO READ CYCLES
WITH SAME OUTPUTS
Note: AMS = Most significant address
AMS = A17 for SST29SF/VF020 and A18 for SST29SF/VF040
1160 F08.1
ADDRESS A
MS-0
DQ
7-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
555 2AA 2AA555 555
55 2055AA 80 AA
SA
X
OE#
CE#
SIX-BYTE CODE FOR SECTOR-ERASE
T
SE
T
WP
Note: This device also supports CE# controlled Sector-Erase operation The WE# and CE# signals are interchangeable as
long as minimum timings are met. (See Table 11)
AMS = Most significant address
AMS = A17 for SST29SF/VF020 and A18 for SST29SF/VF040
SAX = Sector Address.
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14
Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
FIGURE 10: WE# Controlled Chip-Erase Timing Diagram
FIGURE 11: Software ID Entry and Read
1160 F09.1
ADDRESS AMS-0
DQ7-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
555 2AA 2AA555 555
55 1055AA 80 AA
555
OE#
CE#
SIX-BYTE CODE FOR CHIP-ERASE
TSCE
TWP
Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are interchangeable as
long as minimum timings are met. (See Table 11)
AMS = Most significant address
AMS = A17 for SST29SF/VF020 and A18 for SST29SF/VF040
1160 F10.1
ADDRESS A14-0
DQ7-0
WE#
SW1SW0 SW2
Device ID
555 2AA 555 0000 0001
OE#
CE#
Three-Byte Sequence for
Software ID Entry
TWP
TWPH TAA
BF55AA 90
TIDA
Note: Device ID = 24H for SST29SF020, 13H for SST29SF040
25H for SST29VF020, 14H for SST29VF040
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Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
15
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
FIGURE 12: Software ID Exit and Reset
1160 F11.1
ADDRESS A14-0
DQ7-0
TIDA
TWP
TWHP
WE#
SW0 SW1 SW2
555 2AA 555
Three-Byte Sequence for
Sofware ID Exit and Reset
OE#
CE#
AA 55 F0
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16
Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
FIGURE 13: AC Input/Output Reference Waveforms for SST29SF020/040
FIGURE 14: AC Input/Output Reference Waveforms for SST29VF020/040
FIGURE 15: Test Load Examples
1160 F12.0
REFERENCE POINTS OUTPUTINPUT VIT
VIHT
VILT
VOT
AC test inputs are driven at VIHT (3.0V) for a logic “1” and VILT (0V) for a logic “0”. Measurement reference points for inputs
and outputs are VIT (1.5 VDD) and VOT (1.5 VDD). Input rise and fall times (10% 90%) are <10 ns.
Note: VIT - VINPUT Te s t
VOT - VOUTPUT Tes t
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
1160 F12.0
REFERENCE POINTS OUTPUTINPUT VIT
VIHT
VILT
VOT
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns.
Note: VIT - VINPUT Te s t
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
1160 F14a.0
SST29SF040
TO TESTER
TO DUT
CLRL LOW
RL HIGH
VDD
1160 F14b.0
TO TESTER
TO DUT
CL
SST29VF040
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Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
17
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
FIGURE 16: Byte-Program Algorithm
1160 F15.0
Start
Load data: AAH
Address: 555H
Load data: 55H
Address: 2AAH
Load data: A0H
Address: 555H
Load Byte
Address/Byte
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
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18
Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
FIGURE 17: Wait Options
1160 F16.0
Wait TBP,
TSCE, or TSE
Byte-
Program/Erase
Initiated
Internal Timer Toggle Bit
Ye s
Ye s
No
No
Program/Erase
Completed
Does DQ6
match?
Read same
byte
Data# Polling
Program/Erase
Completed
Program/Erase
Completed
Read byte
Is DQ7 =
true data?
Read DQ7
Byte-
Program/Erase
Initiated
Byte-
Program/Erase
Initiated
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Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
19
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
FIGURE 18: Software ID Command Flowcharts
1160 F17.0
Load data: AAH
Address: 555H
Software ID Entry
Command Sequence
Load data: 55H
Address: 2AAH
Load data: 90H
Address: 555H
Wait TIDA
Read Software ID
Load data: AAH
Address: 555H
Software ID Exit &
Reset Command Sequence
Load data: 55H
Address: 2AAH
Load data: F0H
Address: 555H
Load data: F0H
Address: XXH
Return to normal
operation
Wait TIDA
Wait TIDA
Return to normal
operation
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20
Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
FIGURE 19: Erase Command Sequence
1160 F18.0
Load data: AAH
Address: 555H
Chip-Erase
Command Sequence
Load data: 55H
Address: 2AAH
Load data: 80H
Address: 555H
Load data: 55H
Address: 2AAH
Load data: 10H
Address: 555H
Load data: AAH
Address: 555H
Wait TSCE
Chip erased
to FFH
Load data: AAH
Address: 555H
Sector-Erase
Command Sequence
Load data: 55H
Address: 2AAH
Load data: 80H
Address: 555H
Load data: 55H
Address: 2AAH
Load data: 20H
Address: SAX
Load data: AAH
Address: 555H
Wait TSE
Sector erased
to FFH
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Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
21
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 Suffix2
SST29xFxxx - XXX -XX-XXX
Environmental Attribute
E1 = non-Pb
Package Modifier
H = 32 leads
Package Type
N = PLCC
W = TSOP (type 1, die up, 8mm x 14mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
55 = 55 ns
70 = 70 ns
Device Density
040 = 4 Mbit
020 = 2 Mbit
Function
F = Chip- or Sector-Erase
Byte-Program
Voltage
S = 4.5-5.5V
V = 2.7-3.6V
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
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22
Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
Valid combinations for SST29SF020
SST29SF020-55-4C-NHE SST29SF020-55-4C-WHE
SST29SF020-55-4I-NHE SST29SF020-55-4I-WHE
Valid combinations for SST29VF020
SST29VF020-70-4C-NHE SST29VF020-70-4C-WHE
SST29VF020-70-4I-NHE SST29VF020-70-4I-WHE
Valid combinations for SST29SF040
SST29SF040-55-4C-NH SST29SF040-55-4C-WH
SST29SF040-55-4C-NHE SST29SF040-55-4C-WHE
SST29SF040-55-4I-NH SST29SF040-55-4I-WH
SST29SF040-55-4I-NHE SST29SF040-55-4I-WHE
Valid combinations for SST29VF040
SST29VF040-70-4C-NH SST29VF040-70-4C-WH
SST29VF040-70-4C-NHE SST29VF040-70-4C-WHE
SST29VF040-70-4I-NH SST29VF040-70-4I-WH
SST29VF040-70-4I-NHE SST29VF040-70-4I-WHE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
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Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
23
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
PACKAGING DIAGRAMS
FIGURE 20: 32-lead Plastic Lead Chip Carrier (PLCC)
SST Package Code: NH
.040
.030
.021
.013
.530
.490
.095
.075
.140
.125
.032
.026
.032
.026
.029
.023
.453
.447
.553
.547
.595
.585
.495
.485 .112
.106
.042
.048
.048
.042
.015 Min.
TOP VIEW SIDE VIEW BOTTOM VIEW
1232
.400
BSC
32-plcc-NH-3
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
4. Coplanarity: 4 mils.
.050
BSC
.050
BSC
Optional
Pin #1
Identifier .020 R.
MAX. R.
x 30°
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24
Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
FIGURE 21: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm
SST Package Code: WH
32-tsop-WH-7
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
1.20
max.
1mm
Pin # 1 Identifier
12.50
12.30
14.20
13.80
0.70
0.50
8.10
7.90 0.27
0.17
0.50
BSC
1.05
0.95
0.15
0.05
0.70
0.50
0°- 5°
DETAIL
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Data Sheet
2 Mbit / 4 Mbit Small-Sector Flash
SST29SF020 / SST29SF040
SST29VF020 / SST29VF040
25
©2009 Silicon Storage Technology, Inc. S71160-15-000 2/09
TABLE 12: Revision History
Number Description Date
05 2002 Data Book May 2002
06 Removed 512 Kbit, 1 Mbit, and 2 Mbit parts
Commercial temperature and 70 ns parts removed
PH package is no longer offered
Part number changes - see page 22 for additional information
Changes to Tables 5 and 6 on page 8 and page 9:
Clarified Test Conditions for Power Supply Current and Read parameters
Clarified IDD Write to be Program and Erase
Corrected IDD Program and Erase from 20 mA to 30 mA
Corrected IDD Read from 20 mA to 25 mA
Clarified measurement reference points VIT and VOT to be 1.5V instead of 1.5VDD
Corrected the VOL test condition IOL to be 2.1 mA instead of 2.1 µA in Table 5 on page 8
Mar 2003
07 Corrected the Test Conditions for the Read Parameter in Table 5 on page 8 Apr 2003
08 Added Commercial temperatures for all packages (See page 22 for details) Aug 2003
09 2004 Data Book
Changed status to “Data Sheet”
Dec 2003
10 Added 70 ns technical data and MPNs for SST29VF040 only Feb 2004
11 Added RoHS compliance information on page 1 and in the
“Product Ordering Information” on page 21
Reinstated 512 Kbit, 1 Mbit, and 2 Mbit devices and MPNs (excluding the PDIP package)
Removed 55 ns technical data and MPNs for SST29VF040
Added non-Pb MPNs for all devices
Clarified the solder temperature profile under “Absolute Maximum Stress Ratings” on
page 8
Mar 2005
12 Removed all entries related to SST29SF/VF512 and SST29SF/VF010
Removed leaded parts for 020 products.
Nov 2005
13 Changed IDD Read from 20mA to 25mA, and Changed IDD Write from 20mA to 30mA in
Table 5 on page 8 and Table 6 on page 9
Oct 2006
14 Changed ISB from 15 to 30 µA in Table 6 on page 9. Oct 2008
15 Corrected the VOL test condition IOL to be 2.1 µA instead of 2.1 mA in Table 5 on page 8 Feb 2009
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
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