Overview
The ICS1572 is ideally suited to provide the graphics system
clock signals required by high-performance video DACs.
Ful ly pr ogram m able fe edba ck a nd r efer en ce di vi de r cap ab ilit y
allow virtually any frequency to be generated, not just simple
multiples of the reference frequency. The ICS1572 uses the
latest ge nerati on of frequency synthesis techniques develope d
by ICS and is completely suitable for the most demanding
vi de o applic at ion s.
PLL Synthesizer Description -
Ratiometric Mode
The ICS1572 generates its output frequencies using phase-
locked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency pro-
vided to the PLL (see Figure 1). The reference frequency is
generated by an on-chip crystal oscillator or the reference
frequency may be applied to the ICS1572 from an external
frequency source.
The phase-frequency detector shown in the block diagram
drives the voltage-controlled oscillator , or VCO, to a frequency
that will cause the two inputs to the phase-frequency detector
to be ma tc hed in fre quency a nd phase. T hi s occurs when:
F(XTAL1) . Fe edback Di vider
F(VCO): = Refere nce Divide r
This expression is exact; that is, the accuracy of the output
fre quen cy de pends sole ly on t he re fere nce freq uenc y provi de d
to the part (assuming correctly programmed dividers).
The VCO gain is programmable , which permits the ICS1572 to
be optimized for be st performanc e at all operating frequencies.
The reference divider may be programmed for any modulus
fro m 1 t o 128 in steps of one .
The feedback divider may be programmed for any modulus
fro m 37 throug h 391 in steps of one. Any eve n mo dul us from
392 through 782 can also be achieved by setting the “double”
bit whic h double s the fe edba ck di vider modul us. The fee dback
divider makes use of a dual-modulus prescaler technique tha t
allows the programmable counters to operate at low speed
without sacrificing resolution. This is an improvement over
conventional fixed prescaler architectures that typically im-
pose a facto r -of- four penal ty (or lar ger) in this respect .
T able 1 perm its the derivation of “A” & “M” counter program-
ming d ire c tl y from desi r ed mod ulus.
PLL Post-Scaler
A programmable post-scaler may be inserted between the VCO
and the CLK+ and CLK- outputs of the ICS1572. This is useful
in generating of lower frequencies, as the VCO has been
opt imi zed fo r hig h-fr eq ue nc y ope ra tion.
The post-scaler allows the selection of:
•VCO fre que nc y
•VCO fre que nc y di vi ded by 2
•VCO fre que nc y di vi ded by 4
•Inter na l regi ster bit (AUXCL K) va lue
Load Clock Divider
The ICS1572 has an additional programmable divider
(referred to in Figure 1 as the N1 divider) that is used to
generate the LOAD clock freque ncy for t he video DAC. The
modulus of this div ider may be set t o 3, 4, 5, 6, 8, or 10 un de r
register control. The design of this divider permi ts the output
duty factor to be 50/50, even when an odd modulus is selected.
The input frequency to this divider is the output of the PLL
post-scaler described above.
Digital Inputs - ICS1572-101 Option
The AD0-AD3 pins and the STROBE pin are used to load all
cont rol re gist ers of t he ICS1572 (-101 option). The AD0- AD3
and STROBE pins ar e each equipped with a pull-up and wil l
be at a logic HIGH level when not connected. They may be
dri ven wit h sta nda rd TTL or CMOS log ic fam il ies.
The address of the register to be loaded is latched from the
AD0-AD3 pins by a negat ive e dge on the STROBE pin . Th e
data for that register is l atched from the AD0-AD3 pins by a
positive edge on the STROBE pin. See Figure 2 for a timing
diag ra m. After power-up, th e ICS1572-101 requires 32 re gis-
ter writes for new programming to become effective. Since
onl y 13 registe rs are used at present, the program ming syste m
can perform 19 “dummy” writes to address 13 or 14 to com-
p lete the se q ue nce.
ICS1572
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