__ - Fast Logic Programmable Delay Units SERIES: PDU-16F (6-Bit) TTL Interfaced Features: Test Conditions: a Input & Output TTL buffered = Input pulse-width: m6-Bit TTL programmable delay > 150% of Max. delay. line mg Input pulse spacing: @ Two (2) Separate outputs; > 3 times of Max. delay. inverting and non-inverting. . input pulse voltage: : ogic. = Completely interfaced @ Measurements taken @ = Compact & low profile Ta- 25C: veo= BV. Specifications: = Propagation delay: Address to output (Tsua) = 7 ns typ. 2: Enable to output (Tsue) = 6 ns typ. Ge en ee ee ee ee @ Delay variation: Monotonic in one g Lead materiat direction. Bikar on ay 42 = Programmed delay tolerance: +5% or ee oS 1 ns whichever is greater. ad ee oe ml fos a Inherent delay (Too): 9 NS on pin 2 8 ns on pin 1 w Supply voltage: 5 Vdc + 5%. TARR = Operating temperature: 0-70 C. TEAL AEA as Ie. ti 008 = Temperature coefficient: 100 PPM/C. LPL ab a . a Supply current: Iccu = 74 ma. Iect = 30 ma. a Minimum pulse-width = 10% of total delay. : typical A m DC parameters: See TTL-Fast Schottky Logic Table on Page 6. TRUTH TABLE | Address Enable -- . Delay ; () | 6 | 5 4 3 $2 [21 Out {> vour bn } o | 0 | 0 | o | ofo]o} 7, a o | o | o | o fo fo]1] gf, our 0. | o | o | o0 fo }1]o] 7, + oe ms o | 0 |] of o fo}fafay 7, Loa cd o | 0 |] 0 o |1]o]o] f, o |o}fo]of1fof1] 7, 0 Pog | oO 0 1 1 0 Te | Incremental Delay Total Programmed 0 Pa o- 0 1 4 1 T; Part No. , Per Step (ns) Delay (ns) o O. 1 1} 0 o T, PDU-16-0.5 | 05 + 03 34.5 oO 0 0 1 1 1 1 Tis PDU-16F-1 ot 2 05 6s 0 _ 1 4 j o lo r PDU-16F-2 2 05 _ 126 oO 0 1 1 + 1 1 Ta PDU-16F-3 Bt 10 189 PDU-16F-4 4-410 252 0 1 0 0 0 0 0 Tap PDU-16F-5 Be toe : 316 6 1 1 1 1 1 1 Teg PDU-16F-6 6 + 1.0 378 1 $ 6 9 6] oOo] 6 0 PDU-16F-8 84 40 504 0 LogicO 1. Logic1 0 Don't care. PDU-16F-10 e418 a0 T, . Reference or inherent delay of unit. T, > T,, Multiplier of incremental delay. 3 Mt. Prospect Avenue, Clifton, New Jersey 07013 = (201) 773-2299 m FAX (201) 773-9672 43