3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit Pre-emphasis and Receive Equalization DS25CP104 Evaluation Kit USER MANUAL Part Number: DS25CP104EVK For the latest documents concerning these products and evaluation kit, visit lvds.national.com. Schematics and gerber files are also available at lvds.national.com. June 2007 Rev. 0.1 DS25CP104EVK User Manual Table of Contents Table of Contents ......................................................................................................... 2 Overview ...................................................................................................................... 3 DS25CP104EVK Description ...................................................................................... 4 Evaluation..................................................................................................................... 6 Typical Performance .................................................................................................. 12 Page 2 of 12 DS25CP104EVK User Manual Overview The DS25CP104EVK is an evaluation kit designed for demonstrating performance of DS25CP104, a 3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit Pre-emphasis and Receive Equalization. The evaluation kit is comprised of the DS25CP104 with its associated input and output SMA connectors and jumpers to manually select the desired pre-emphasis or equalization. The kit also includes an integrated USB to SMBus conversion circuit to control the SMBus with a PC, and three FR4 striplines (15" (38.1cm), 30" (76.2cm), and 60" (152.4cm) ) to exercise the devices' signal conditioning features (pre-emphasis and equalization). The purpose of this document is to familiarize the user with the DS25CP104EVK, to suggest test setup procedures and instrumentation to test the device optimally, and to guide the user through some typical measurements that demonstrate the performance of the DS25CP104 in typical applications. Figure 1. Photo of the DS25CP104EVK Page 3 of 12 DS25CP104EVK User Manual DS25CP104EVK Description Figure 2 shows the top layer drawing of the PCB with the silkscreen annotations. The 4.5 by 4.5 inch, eight-layer PCB is designed to evaluate the functions of the DS25CP104. Figure 2. Top Layer DS25CP104EVK Page 4 of 12 DS25CP104EVK User Manual For descriptive purposes the DS25CP104EVK can be broken into three parts: 1. The DS25CP104 IC with associated connectors and jumpers is the main part of the board. The block diagram of the DS25CP104 is shown in Figure 3. The receive buffers can be set to Off and Low equalization by the external pins EQ0 - EQ3; the transmit buffers has can be set to Off and Med. levels of pre-emphasis by the external pins PE0 - PE3. Since data capabilities are 3.125 Gbps, SMA connectors are used to ensure minimal loss. More information can be found about the DS25CP104 on the data sheets. 2. A USB to SMBus converter has been added to the evaluation kit to implement SMBus switch configuration to control the signal conditioning. Through the SMBus the DS25CP104 currently features four levels (Off, Low, Medium, and High) of preemphasis and two levels (Off, Low) of equalization. 3. Three channels of stripline have been added to the evaluation kit to test the preemphasis and equalization functions (15" (38.1cm), 30" (76.2cm), and 60" (152.4cm)). In practical applications, devices often drive long backplanes or cables. To help reduce jitter caused from long backplanes or cables, pre-emphasis can be used for the drivers and equalization for the receivers. Figure 3. DS25CP104 Block Diagram Page 5 of 12 DS25CP104EVK User Manual DS25CP104 Evaluation The DS25CP104 is a 3.125 Gbps LVDS Crosspoint Switch with four levels of transmit pre-emphasis and two levels of receive equalization configured in the SMBus Mode and two levels of transmit pre-emphasis and two levels of receive equalization configured via external jumpers on the evaluation board in the Pin Mode. Initial Pin Settings for Pin Mode Testing Pin SMBus Enable EQ0 - EQ 3 Setting L L PE0 - PE3 L PWDN H Note Disable SMbus Equalization off, See table Pre-Emphasis off, See table Power Down off S00 0 1 0 1 Input Selected IN0 IN1 IN2 IN3 Switch Configuration Truth Tables S01 0 0 1 1 Table 1. Input Select Pins Configuration for the Output OUT0 S11 0 0 1 1 S10 0 1 0 1 Input Selected IN0 IN1 IN2 IN3 Table 2. Input Select Pins Configuration for the Output OUT1 Page 6 of 12 DS25CP104EVK User Manual S21 0 0 1 1 S20 0 1 0 1 Input Selected IN0 IN1 IN2 IN3 Table 3. Input Select Pins Configuration for the Output OUT2 S31 0 0 1 1 S30 0 1 0 1 Input Selected IN0 IN1 IN2 IN3 Table 4. Input Select Pins Configuration for the Output OUT3 Signal Conditioning Tables Output OUTn, n={0,1,2,3} Pre-Emphasis Control Pin (PEn) State Pre-Emphasis Level 0 Off 1 Medium Table 5. Transmit Pre-emphasis Truth Table Input INn, n={0,1,2,3} Equalization Control Pin (EQn) State Equalization Level 0 Off 1 Low Table 6. Receive Equalization Truth Table Stripline Length Table (also known as Test Channels) Stripline L1 L2 L3 Length 15" (38.1cm) 30" (76.2cm) 60" (152.4cm) Table 7. Stripline length table Page 7 of 12 Loss (dB) @ 1250 MHz -3.6 -8.2 -14.5 DS25CP104EVK User Manual Jitter Performance Testing with No Signal Conditioning 1. Configure the test setup as shown in Figure 4. 2. Set the desired INn to OUTn drivers by selecting S00, S01, S10, S11, S20, S21, S30, and S31 according to Tables 1 - 4. 3. Move the PEn and EQn jumpers to 0, according to tables 5 and 6. 4. Apply + supply (3.3V typical) to the VDD and - supply (ground) to the VSS connectors. 5. Connect a signal source (signal generator, data source, or an LVDS driver) to the desired INn inputs on the board and adjust the signal parameters (VOH, VOL, VCM) so that they comply with the device input recommendations. Either AC or DC coupling may be used on the inputs of the DS25CP104. 6. Connect an oscilloscope to the selected OUTn outputs and view the output signals with an oscilloscope with the bandwidth of at least 6 GHz. For most oscilloscopes, AC coupling of the outputs will be needed to properly load the LVDS outputs of the DS25CP104. Some newer differential probes, like the P7380SMA from Tektronix will automatically adjust to the LVDS output common mode voltage and no AC coupling is required. DS25CP104 EVK 50 Microstrip 1/4 DS25CP104 L=4" 50 Microstrip L=4" PATTERN GENERATOR OSCILLOSCOPE L=4" L=4" 50 Microstrip 50 Microstrip Figure 4. Jitter Performance Test Circuit Page 8 of 12 DS25CP104EVK User Manual Pre-Emphasis Performance Testing In applications where data transmits over cables or long backplanes, the pre-emphasis feature on the DS25CP104 transmitter helps to overcome media loss and reduce bit errors; hence the DS25CP104EVK has three lengths of stripline to test the pre-emphasis function. 1. Configure the test setup as shown in figure 5; select the desired test channel lengths in Table 7. 2. Set the desired INn to OUTn drivers by selecting S00, S01, S10, S11, S20, S21, S30 and S31 according to Tables 1 - 4. 3. Move the PEn jumpers to 1 and the EQn jumpers to 0, according to Tables 5 and 6. 4. Apply + supply (3.3V typical) to the VDD and - supply (ground) to the VSS connectors. 5. Connect a signal source (signal generator, data source, or an LVDS driver) to the desired INn inputs on the board and adjust the signal parameters (VOH, VOL, VCM) so that they comply with the device input recommendations. Either AC or DC coupling may be used on the inputs of the DS25CP104. 6. Connect an oscilloscope to the selected OUTn outputs and view the output signals with an oscilloscope with a bandwidth of at least 6 GHz. For most oscilloscopes, AC coupling of the outputs will be needed to properly load the LVDS outputs of the DS25CP104. Some newer differential probes, like the P7380SMA from Tektronix will automatically adjust to the LVDS output common mode voltage and no AC coupling is required. Figure 5. Pre-Emphasis Performance Test Circuit Page 9 of 12 DS25CP104EVK User Manual Equalization Performance Testing In some applications, data transmits over cables or long backplanes. The equalization function on the DS25CP104 receivers helps to compensate for loss of certain media; hence the DS25CP104EVK has three lengths of stripline to test the equalization function. 1. Configure the test setup as shown in Figure 6; select the desired test channel, lengths in Table 7. 2. Set the desired INn to OUTn drivers by selecting S00, S01, S10, S11, S20, S21, S30, S31 according to Tables 1 - 4. 3. Select the PEn jumpers to 0 and the EQn jumpers to 1, according to Tables 5 and 6. 4. Apply + supply (3.3V typical) to the VDD and - supply (ground) to the VSS connectors. 5. Connect a signal source (signal generator, data source, or an LVDS driver) to the desired INn inputs on the board and adjust the signal parameters (VOH, VOL, VCM) so that they comply with the device input recommendations. Either AC or DC coupling may be used on the inputs of the DS25CP104. 6. Connect an oscilloscope to the selected OUTn outputs and view the output signals with an oscilloscope with a bandwidth of at least 6 GHz. For most oscilloscopes, AC coupling of the outputs will be needed to properly load the LVDS outputs of the DS25CP104. Some newer differential probes, like the P7380SMA from Tektronix will automatically adjust to the LVDS output common mode voltage and no AC coupling is required. Figure 6. Equalization Performance Test Circuit Page 10 of 12 DS25CP104EVK User Manual Pre-Emphasis and Equalization Performance Testing In some applications, data transmits over cables or long backplanes. The pre-emphasis and equalization functions on the DS25CP104 help to compensate for loss of certain media; hence the DS25CP104EVK has three lengths of stripline to test the pre-emphasis and equalization functions. 1. Configure the test setup as shown in Figure 7; select the desired test channel, lengths in Table 7. 2. Set the desired INn to OUTn drivers by selecting S00, S01, S10, S11, S20, S21, S30, and S31 according to Tables 1 - 4. 3. Select the PEn jumpers to 1 and the EQn jumpers to 1, according to Tables 5 and 6. 4. Apply + supply (3.3V typical) to the VDD and - supply (ground) to the VSS connectors. 5. Connect a signal source (signal generator, data source, or an LVDS driver) to the desired INn inputs on the board and adjust the signal parameters (VOH, VOL, VCM) so that they comply with the device input recommendations. Either AC or DC coupling may be used on the inputs of the DS25CP104. 6. Connect an oscilloscope to the selected OUTn outputs and view the output signals with an oscilloscope with a bandwidth of at least 6 GHz. For most oscilloscopes, AC coupling of the outputs will be needed to properly load the LVDS outputs of the DS25CP104. Some newer differential probes, like the P7380SMA from Tektronix will automatically adjust to the LVDS output common mode voltage and no AC coupling is required. TEST CHANNEL TEST CHANNEL DS25CP104EVK 50 Microstrip 1/4 DS25CP104 50 Microstrip L=4" L=4" L=4" L=4" 50 Microstrip 50 Microstrip PATTERN GENERATOR OSCILLOSCOPE Figure 7. Pre-emphasis and Equalization Performance Test Circuit Page 11 of 12 DS25CP104EVK User Manual SMBus Evaluation The description of the USB to SMBus function of the DS25CP104EVK will follow in future revisions of this user manual. The full range of crosspoint switch configurations are possible using the configuration control pin jumpers. Typical Performance This section of the User Manual shows typical eye diagrams you can expect to see when evaluating the DS25CP104EVK. The DS25CP104 3.125 Gbps PRBS-7 output eye diagram with no STRIPLINE connected and with PE/EQ = Off The DS25CP104 3.125 Gbps PRBS-7 output eye diagram after the STRIPLINE2 (30" FR4) and with PE/EQ = Off The DS25CP104 3.125 Gbps PRBS-7 output eye diagram after the STRIPLINE 2 (30" FR4) and with PE = Med. See Figure 5 for the Setup used. The DS25CP104 3.125 Gbps PRBS-7 output eye diagram after the STRIPLINE 1 (15" FR4) and with EQ = Low. See Figure 6 for the Setup used. Page 12 of 12 ENERCON - BILL OF MATERIALS TITLE: Main Product: NATIONAL SEMICONDUCTOR PCBA, DS25CP104EVK, ROHS Rev: Rev By: Rev Date: PL Number: Z3071-01 0 Responsible Eng/Mgr: PCBA, DS25CP104 EVK Item Part Type 1 PCB Part Number/Value Mfg P-05885R0 NoSub Description Qty DS25CP104EVK: 5.25x5.25x.060in, 8 layer 1 Released Creator: Creation Date: Arlene Fox 3/28/2007 Ref Des SMT PL Status: 3/28/2007 Notes Bd: (133.35x 133.35mm) Panel: ( 10.60x5.25in) (269.24x 133.35mm) 2 bds/panel Rev 0 2 3 IC 24LC128-I/SN MICROCHIP 128K bit Serial EEPROM 2.5V, SOIC8, PbFree 1 X U3 0 4 IC CY7C68013A-56LFXC CYPRESS EZ-USB FX2 USB Microcontroller, QFN56, Pb-Free 1 X U1 0 5 IC DS25CP104 NAT 6 IC LP38691SD-3.3/NOPB NAT Linear Regulator, 3.3V, LLP6, Pb-Free 1 X U2 0 7 IC PGB1040805 LF ESD Suppressor, 0805, Pb-Free 1 X U4 0 ERJ-3GEY0R00 PANA 0 Ohm 1/10W 5% 0603, Pb-Free 3 X R4,5,14 0 <ALT> CRCW06030000Z0EA VISHAY 0 Ohm 1/10W 5% 0603, Pb-Free <ALT> MCR03EZPJ000 ROHM 0 Ohm 1/10W 5% 0603, Pb-Free <ALT> RC0603JR-070RL YAGEO 0 Ohm 1/10W 5% 0603, Pb-Free 5 X R3,8-9,12,13 0 2 X R1-2 0 2 X R6,7 0 2 X R10-11 0 1 U5 Customer Supplied 0 8 9 RES 10 RES ERJ-3GEYJ103 PANA 10K 1/10W 5% 0603 200ppm, Pb-Free <ALT> CRCW060310K0JNEA VISHAY 10K 1/10W 5% 0603 200ppm, Pb-Free <ALT> RK73B1JTTD103J KOA 10K 1/10W 5% 0603 200ppm, Pb-Free ERJ-3GEYJ220 PANA 22 Ohm 1/10W 5% 0603 200ppm, Pb-Free CRCW060322R0JNEA VISHAY 22 Ohm 1/10W 5% 0603 200ppm, Pb-Free 11 RES <ALT> <ALT> 12 RES <ALT> <ALT> 13 RES RK73B1JTTD220J KOA 22 Ohm 1/10W 5% 0603 200ppm, Pb-Free ERJ-3GEYJ222 PANA 2.2K 1/10W 5% 0603 200ppm, Pb-Free CRCW06032K20JNEA VISHAY 2.2K 1/10W 5% 0603 200ppm, Pb-Free RK73B1JTTD222J KOA 2.2K 1/10W 5% 0603 200ppm, Pb-Free ERJ-8GEY0R00 PANA 0 Ohm 1/4W 5% 1206, Pb-Free 1:12:35 PM, 4/20/2007 Confidential and Proprietary. This document is considered uncontrolled unless stamped otherwise. Page 1 of 3 ENERCON - BILL OF MATERIALS TITLE: Main Product: NATIONAL SEMICONDUCTOR PCBA, DS25CP104EVK, ROHS Rev: Rev By: Rev Date: PL Number: Z3071-01 0 Responsible Eng/Mgr: PCBA, DS25CP104 EVK Item Part Type <ALT> Part Number/Value Mfg NoSub Description CRCW12060000Z0EA VISHAY 0 Ohm 1/4W 5% 1206, Pb-Free 0402YC103KAT AVX .01F, 16V, 10%, 0402, Ceramic, X7R, Pb-Free <ALT> C0402C103K4RAC KEMET .01F, 16V, 10%, 0402, Ceramic, X7R, Pb-Free <ALT> ECJ-0EB1C103K PANA .01F, 16V, 10%, 0402, Ceramic, X7R, Pb-Free 08055A180JAT AVX 18pF, 50V, 5%, 0805, Ceramic, NP0, PbFree <ALT> C0805C180J5GAC KEMET 18pF, 50V, 5%, 0805, Ceramic, NP0, PbFree <ALT> ECJ-2VC1H180J PANA 18pF, 50V, 5%, 0805, Ceramic, NP0, PbFree 17 CAP C0402C104K8RAC KEMET .1F, 10V, 10%, 0402, Ceramic, X7R, PbFree 18 CAP C1206C225K4RAC KEMET 2.2F, 16V, 10%, 1206, Ceramic, X7R, Pb-Free ECJ-3YB1C225K PANA 2.2F, 16V, 10%, 1206, Ceramic, X7R, Pb-Free MMZ1608R301A TDK HCM49-24.000MABJ Qty Released Creator: Creation Date: Arlene Fox 3/28/2007 Ref Des SMT PL Status: 3/28/2007 Notes Rev 14 15 CAP 2 X C15,17 0 2 X C11-12 0 10 X C1,4-8,10,1314,16 0 4 X C2,3,9,18 0 Ferrite, 300 Ohm, .5A, 0603, Pb Free 2 X FB1-2 0 CITIZEN Crystal, 24.0000MHz, SMD, 18pF, Pb-Free 1 X Y1 0 1206L050 LF .5A, Resettable, SMT, .09 Ohms, Pb Free 1 X F1 0 26 CONN 1287-ST KEYSTONE Faston, Male, .250x.032, Pb-Free 2 J25-26 0 27 CONN 142-0701-851 EMERSON SMA, Jack Receptacle, 50 OHM, Pb-Free SMA1-28 0 28 CONN 61729-0010 FCI USB-B, 4p, R/A, Pb-Free 1 J1 0 29 CONN TSW-102-07-G-S SAMTEC Header, 2p, Male, .100"sp, Gold, Pb-Free 2 J3-4 0 30 CONN TSW-103-07-G-S SAMTEC Header, 3p, Male, .100"sp, Gold, Pb-Free 18 J7-24 0 16 CAP <ALT> 19 20 FILTER 21 22 XTAL 23 24 FUSE 25 1:12:35 PM, 4/20/2007 28 Confidential and Proprietary. This document is considered uncontrolled unless stamped otherwise. Page 2 of 3 ENERCON - BILL OF MATERIALS TITLE: Main Product: NATIONAL SEMICONDUCTOR PCBA, DS25CP104EVK, ROHS Rev: Rev By: Rev Date: PL Number: Z3071-01 0 Responsible Eng/Mgr: PCBA, DS25CP104 EVK Item Part Type 31 CONN Part Number/Value Mfg NoSub Description Qty Released Creator: Creation Date: Arlene Fox 3/28/2007 Ref Des SMT PL Status: 3/28/2007 Notes J2 Rev TSW-105-07-G-S SAMTEC Header, 5p, Male, .100"sp, Gold, Pb-Free 1 0 T-05889R0 ENERCON STENCIL FABRICATION, TOP, DS25CP104EVK 1 0 T-05890R0 ENERCON STENCIL FABRICATION, BOTTOM, DS25CP104EVK 1 0 36 REF C-05886R0 ENERCON FABRICATION DWG, DS25CP104EVK 0 37 REF C-05888R0 ENERCON PALLET DWG, DS25CP104EVK 0 38 REF S-05887R0 ENERCON SCHEMATIC, DS25CP104EVK 0 32 33 STENCL 34 STENCL 35 39 40 41 Notes: DO NOT STUFF: R15,16,17,18,19 J5,6 1:12:35 PM, 4/20/2007 Confidential and Proprietary. This document is considered uncontrolled unless stamped otherwise. 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Note: This document is considered uncontrolled unless stamped otherwise. Note: This document is considered uncontrolled unless stamped otherwise. Note: This document is considered uncontrolled unless stamped otherwise.