DS25CP104EVK/NOPB - NATIONAL SEMICONDUCTOR

June 2007

Rev. 0.1

3.125 Gbps 4x4 LVDS Crosspoint Switch

with Transmit Pre-emphasis

and Receive Equalization

DS25CP104 Evaluation Kit

USER MANUAL

Part Number: DS25CP104EVK

For the latest documents concerning these products and evaluation kit, visit lvds.national.com.

Schematics and gerber files are also available at lvds.national.com.

DS25CP104EVK User Manual

Page 2 of 12

Table of Contents

Table of Contents......................................................................................................... 2

Overview...................................................................................................................... 3

DS25CP104EVK Description...................................................................................... 4

Evaluation..................................................................................................................... 6

Typical Performance.................................................................................................. 12

DS25CP104EVK User Manual

Page 3 of 12

Overview

The DS25CP104EVK is an evaluation kit designed for demonstrating performance of

DS25CP104, a 3.125 Gbps 4x4 LVDS Crosspoint Switch with Transmit Pre-emphasis

and Receive Equalization. The evaluation kit is comprised of the DS25CP104 with its

associated input and output SMA connectors and jumpers to manually select the desired

pre-emphasis or equalization. The kit also includes an integrated USB to SMBus

conversion circuit to control the SMBus with a PC, and three FR4 striplines (15”

(38.1cm), 30” (76.2cm), and 60” (152.4cm) ) to exercise the devices’ signal conditioning

features (pre-emphasis and equalization).

The purpose of this document is to familiarize the user with the DS25CP104EVK, to

suggest test setup procedures and instrumentation to test the device optimally, and to

guide the user through some typical measurements that demonstrate the performance of

the DS25CP104 in typical applications.

Figure 1. Photo of the DS25CP104EVK

DS25CP104EVK User Manual

Page 4 of 12

DS25CP104EVK Description

Figure 2 shows the top layer drawing of the PCB with the silkscreen annotations. The 4.5

by 4.5 inch, eight-layer PCB is designed to evaluate the functions of the DS25CP104.

Figure 2. Top Layer DS25CP104EVK

DS25CP104EVK User Manual

Page 5 of 12

For descriptive purposes the DS25CP104EVK can be broken into three parts:

1. The DS25CP104 IC with associated connectors and jumpers is the main part of the

board. The block diagram of the DS25CP104 is shown in Figure 3. The receive buffers

can be set to Off and Low equalization by the external pins EQ0 – EQ3; the transmit

buffers has can be set to Off and Med. levels of pre-emphasis by the external pins PE0 –

PE3. Since data capabilities are 3.125 Gbps, SMA connectors are used to ensure minimal

loss. More information can be found about the DS25CP104 on the data sheets.

2. A USB to SMBus converter has been added to the evaluation kit to implement

SMBus switch configuration to control the signal conditioning. Through the SMBus the

DS25CP104 currently features four levels (Off, Low, Medium, and High) of pre-

emphasis and two levels (Off, Low) of equalization.

3. Three channels of stripline have been added to the evaluation kit to test the pre-

emphasis and equalization functions (15” (38.1cm), 30” (76.2cm), and 60” (152.4cm)).

In practical applications, devices often drive long backplanes or cables. To help reduce

jitter caused from long backplanes or cables, pre-em phasis can be used for the drivers and

equalization for the receivers.

Figure 3. DS25CP104 Block Diagram

DS25CP104EVK User Manual

Page 6 of 12

Pin Setting Note

SMBus Enable L Disable SMbus

EQ0 – EQ 3 L Equalization off,

See table

PE0 – PE3 L Pre-Emphasis off,

See table

PWDN H Power Down off

DS25CP104 Evaluation

The DS25CP104 is a 3.125 Gbps LVDS Crosspoint Switch with four levels of transmit

pre-emphasis and two levels of receive equalization configured in the SMBus Mode and

two levels of transmit pre-emphasis and two levels of receive equalization configured via

external jumpers on the evaluation board in the Pin Mode.

Initial Pin Settings for Pin Mode Testing

Switch Configuration Truth Tables

S01 S00 Input Selected

0 0 IN0

0 1 IN1

1 0 IN2

1 1 IN3

Table 1. Input Select Pins Configuration for the Output OUT0

S11 S10 Input Selected

0 0 IN0

0 1 IN1

1 0 IN2

1 1 IN3

Table 2. Input Select Pins Configuration for the Output OUT1

DS25CP104EVK User Manual

Page 7 of 12

S21 S20 Input Selected

0 0 IN0

0 1 IN1

1 0 IN2

1 1 IN3

Table 3. Input Select Pins Configuration for the Output OUT2

S31 S30 Input Selected

0 0 IN0

0 1 IN1

1 0 IN2

1 1 IN3

Table 4. Input Select Pins Configuration for the Output OUT3

Signal Conditioning Tables

Output OUTn, n={0,1,2,3}

Pre-Emphasis Control Pin (PEn) State Pre-Emphasis Level

0 Off

1 Medium

Table 5. Transmit Pre-emphasis Truth Table

Input INn, n={0,1,2,3}

Equalization Control Pin (EQn) State Equalization Level

0 Off

1 Low

Table 6. Receive Equalization Truth Table

Stripline Length Table (also known as Test Channels)

Stripline Length Loss (dB) @ 1250 MHz

L1 15” (38.1cm) -3.6

L2 30” (76.2cm) -8.2

L3 60” (152.4cm) -14.5

Table 7. Stripl length table

ine

DS25CP104EVK User Manual

Page 8 of 12

Jitter Performance Testing with No Signal Conditioning

1. Configure the test setup as shown in Figure 4.

2. Set the d 11, S20, S21,

S30, and S31 according to Tables 1 – 4.

3. Move the PEn and EQn jumpers to 0, according to tables 5 a

4. Apply + supply (3.3V typical) to the D and – supply (ground) VSS

connectors.

5. Connect a signal source (signal generator, data source, or an LVDS driver) to the

desired IN OH, VOL,

VCM) so that they comply with the device input recommendations. Either AC or

DC coupling may be used on the inputs of the DS25CP104.

6. Connect an oscilloscope to the selected OUTn outputs and view the output signals

with an oscilloscope with the bandwidth of at least 6 GHz. For most

oscilloscopes, AC coupling of the outputs will be needed to properly load the

LVDS outputs of the DS25CP104. Some newer differential probes, like the

P7380SMA from Tektronix will auto tically adjust to the L

common mode voltage and no AC coupling is required.

esired INn to OUTn drivers by selecting S00, S01, S10, S

nd 6.

VD to the

n inputs on the board and adjust the signal parameters (V

ma VDS output

Microstrip

L=4"

¼ DS25CP104

PATTERN

GENER R OSC E

DS25CP104 EVK

ATO ILLOSCOP

Microstrip

Figure 4. Jitter Performance Test Circuit

DS25CP104EVK User Manual

Page 9 of 12

Pre-Emphasis Performance Testing

In applications where data transmits over cables or long backplanes, the pre-emphasis

feature on the DS25CP104 transmitter helps overcome media loss and reduce bit

errors; hence the DS25CP104EV ipline to test the pre-emphasis

1. Configure the test setup as shown in figure 5; select the de test channel

lengths in Table 7.

2. Set the desired INn to OUTn drivers

S30 and S31 according to Tables 1 – 4.

0, according to Tables 5 and

4. Apply upply (3.3V typical) to – supply (ground) to SS

conne s.

5. Connect a signal source (signal generator, data source, or an LVDS driver) to the

desired INn inputs on th l parameters (VOH, VOL,

endations. Either AC or

P104.

utputs and view the output signals

l probes, like the P7380SMA from

ode voltage

K has three lengths of str

nction.

sired

by selecting S00, S01, S10, S11, S20, S21,

3. Move the PEn jumpers to 1 and the EQn jumpers to

+ s the VDD and the V

ctor

e board and adjust the signa

VCM) so that they comply with the device input recomm

DC coupling may be used on the inputs of the DS25C

6. Connect an oscilloscope to the selected OUTn o

with an oscilloscope with a bandwidth of at least 6 GHz. For most oscilloscopes,

AC coupling of the outputs will be needed to properly load the LVDS outputs of

the DS25CP104. Some newer differentia

Tektronix will automatic ally adjust to the LVDS output common m

and no AC coupling is required.

Figure 5. Pre-Emphasis Performance Test Circuit

DS25CP104EVK User Manual

Page 10 of 12

Equalization Performance Testing

some applications, data transmits over cables or long backplanes. The equalization

dia;

hence the D

3. Select the PEn jum rding to Tables 5 and

4. Apply + supply (3.3V typical) to the VDD and – supply (ground) to the VSS

connectors.

5. Connect a signal source (signal generator, data source, or an LVDS driver) to the

desired INn inputs on the board and adjust the signal parameters (VOH, VOL,

VCM) so that they comply with the device input recommendations. Either AC

or DC coupling may be used on the inputs of the DS25CP104.

6. Connect an oscilloscope to the selected OUTn outputs and view the output

380SMA from Tektronix will automatically adjust to the LVDS output

common mode voltage and no AC coupling is required.

function on the DS25CP104 receivers helps to compensate for loss of certain me

S25CP104EVK has three lengths of stripline to test the equalization function.

Configure the test setup as shown in Figure 6; select the desired test channel,

lengths in Table 7.

Set the desired INn to OUTn drivers by selecting S00, S01, S10, S11, S20, S21,

S30, S31 according to Tables 1 – 4.

pers to 0 and the EQn jumpers to 1, acco

signals with an oscilloscope with a bandwidth of at least 6 GHz. For most

oscilloscopes, AC coupling of the outputs will be needed to properly load th

LVDS outputs of the DS25CP104. Some newer differential probes, like the

Figure 6. Equalization Performance Test Circuit

DS25CP104EVK User Manual

Page 11 of 12

Pre

In some

and equ

media;

and equ

1. Configure the test setup as shown in Figure 7; select the desired test channel,

lengths in Table 7.

2. Set the desired INn to OUTn drivers by selecting S00, S01, S10, S11, S20, S21,

S30, and S31 according to Tables 1 – 4.

3. Select the PEn jumpers to 1 and the EQn jumpers to 1, according to Tables 5 and

4. Apply + su d) to the VSS

connectors.

5. Connect a signal source (signal generator, data source, or an LVDS driver) to the

desired INn inputs on the board and adjust the signal parameters (VOH, VOL,

th the device input recommendations. Either AC

or DC coupling may be used on the inputs of the DS25CP104.

oscilloscopes, AC coupling of the outputs will be needed to properly load the

ktronix will automatically adjust to the LVDS output

common mode voltage and no AC coupling is required.

-Emphasis and Equalization Performance Testing

applications, data transmits over cables or long backplanes. The pre-emphasis

alization functions on the DS25CP104 help to compensate for loss of certain

hence the DS25CP104EVK has three lengths of stripline to test the pre-emphasis

alization functions.

pply (3.3V typical) to the VDD and – supply (groun

VCM) so that they comply wi

6. Connect an oscilloscope to the selected OUTn outputs and view the output

signals with an oscilloscope with a bandwidth of at least 6 GHz. For most

LVDS outputs of the DS25CP104. Some newer differential probes, like the

P7380SMA from Te

TEST

CHANNEL DS25CP104EVK TEST

CHANNEL

Microstrip

L=4"

¼ DS25CP104

PAT

GENE R OPE

TERN

RATO OSCILLOSC

Microstrip

Microstrip Microstrip

Figure 7. Pre-emphasis and Equalization Performance Test Circuit

DS25CP104EVK User Manual

Page 12 of 12

SMB

The des in

future re

are poss

Typical Performance

This section of the User Manual shows typical eye diagrams you can expect to see when

evaluating the DS25CP104EVK.

us Evaluation

cription of the USB to SMBus function of the DS25CP104EVK will follow

visions of this user manual. The full range of crosspoint switch configurations

ible using the configuration control pin jumpers.

The DS25CP104 3.125 Gbps PRBS-7 output eye

diagram with no STRIPLINE connected and with

E/EQ = Off

The DS25CP104 3.125 Gbps PRBS-7 output eye

diagram after the STRIPLINE2 (30” FR4) and with

P PE/EQ = Off

dhe DS25CP104 3.125 Gbps PRBS-7 output eye

iagr

PE =

The DS25CP104 3.125 Gbps PRBS-7 output eye

am after the STRIPLINE 2 (30” FR4) and with

Med. See Figure 5 for the Setup used. diagram after the STRIPLINE 1 (15” FR4) and with

EQ = Low. See Figure 6 for the Setup used.

Item Part Type Part Number/Value Mfg Description Qty SMTNoSub Ref Des Notes Rev

1 PCB P-05885R0 DS25CP104EVK: 5.25x5.25x.060in, 8 layer 1 0

Bd: (133.35x

133.35mm)

Panel: (

10.60x5.25in)

(269.24x

133.35mm) 2

bds/panel

3 IC 24LC128-I/SN MICROCHIP 128K bit Serial EEPROM 2.5V, SOIC8, Pb-

Free 1 X 0U3

4 IC CY7C68013A-56LFXC CYPRESS EZ-USB FX2 USB Microcontroller, QFN56,

Pb-Free 1 X 0U1

5 IC DS25CP104 NAT 1 0U5 Customer

Supplied

6 IC LP38691SD-3.3/NOPB NAT Linear Regulator, 3.3V, LLP6, Pb-Free 1 X 0U2

7 IC PGB1040805 LF ESD Suppressor, 0805, Pb-Free 1 X 0U4

9 RES ERJ-3GEY0R00 PANA 0 Ohm 1/10W ±5% 0603, Pb-Free 3 X 0R4,5,14

<ALT> CRCW06030000Z0EA VISHAY 0 Ohm 1/10W ±5% 0603, Pb-Free

<ALT> MCR03EZPJ000 ROHM 0 Ohm 1/10W ±5% 0603, Pb-Free

<ALT> RC0603JR-070RL YAGEO 0 Ohm 1/10W ±5% 0603, Pb-Free

10 RES ERJ-3GEYJ103 PANA 10K 1/10W ±5% 0603 200ppm, Pb-Free 5 X 0R3,8-9,12,13

<ALT> CRCW060310K0JNEA VISHAY 10K 1/10W ±5% 0603 200ppm, Pb-Free

<ALT> RK73B1JTTD103J KOA 10K 1/10W ±5% 0603 200ppm, Pb-Free

11 RES ERJ-3GEYJ220 PANA 22 Ohm 1/10W ±5% 0603 200ppm, Pb-Free 2 X 0R1-2

<ALT> CRCW060322R0JNEA VISHAY 22 Ohm 1/10W ±5% 0603 200ppm, Pb-Free

<ALT> RK73B1JTTD220J KOA 22 Ohm 1/10W ±5% 0603 200ppm, Pb-Free

12 RES ERJ-3GEYJ222 PANA 2.2K 1/10W ±5% 0603 200ppm, Pb-Free 2 X 0R6,7

<ALT> CRCW06032K20JNEA VISHAY 2.2K 1/10W ±5% 0603 200ppm, Pb-Free

<ALT> RK73B1JTTD222J KOA 2.2K 1/10W ±5% 0603 200ppm, Pb-Free

13 RES ERJ-8GEY0R00 PANA 0 Ohm 1/4W ±5% 1206, Pb-Free 2 X 0R10-11

1:12:35 PM, 4/20/2007 1 3

Page

Confidential and Proprietary. This document is considered uncontrolled unless stamped otherwise.

Creation Date:

3/28/2007

Responsible Eng/Mgr: Creator:

Arlene Fox

PL Number:

Z3071-01 Rev:

0Rev Date:

3/28/2007 PL Status:

Released

Rev By:

Main Product:

PCBA, DS25CP104 EVK

TITLE: NATIONAL SEMICONDUCTOR

PCBA, DS25CP104EVK, ROHS

ENERCON - BILL OF MATERIALS

Item Part Type Part Number/Value Mfg Description QtySMTNoSub Ref Des Notes Rev

<ALT> CRCW12060000Z0EA VISHAY 0 Ohm 1/4W ±5% 1206, Pb-Free

15 CAP 0402YC103KAT AVX .01µF, 16V, ±10%, 0402, Ceramic, X7R,

Pb-Free 2 X 0C15,17

<ALT> C0402C103K4RAC KEMET .01µF, 16V, ±10%, 0402, Ceramic, X7R,

Pb-Free

<ALT> ECJ-0EB1C103K PANA .01µF, 16V, ±10%, 0402, Ceramic, X7R,

Pb-Free

16 CAP 08055A180JAT AVX 18pF, 50V, ±5%, 0805, Ceramic, NP0, Pb-

Free 2 X 0C11-12

<ALT> C0805C180J5GAC KEMET 18pF, 50V, ±5%, 0805, Ceramic, NP0, Pb-

Free

<ALT> ECJ-2VC1H180J PANA 18pF, 50V, ±5%, 0805, Ceramic, NP0, Pb-

Free

17 CAP C0402C104K8RAC KEMET .1µF, 10V, ±10%, 0402, Ceramic, X7R, Pb-

Free 10 X 0

C1,4-8,10,13-

14,16

18 CAP C1206C225K4RAC KEMET 2.2µF, 16V, ±10%, 1206, Ceramic, X7R,

Pb-Free 4 X 0C2,3,9,18

<ALT> ECJ-3YB1C225K PANA 2.2µF, 16V, ±10%, 1206, Ceramic, X7R,

Pb-Free

20 FILTER MMZ1608R301A TDK Ferrite, 300 Ohm, .5A, 0603, Pb Free 2 X 0FB1-2

22 XTAL HCM49-24.000MABJ CITIZEN Crystal, 24.0000MHz, SMD, 18pF, Pb-Free 1 X 0Y1

24 FUSE 1206L050 LF .5A, Resettable, SMT, .09 Ohms, Pb Free 1 X 0F1

26 CONN 1287-ST KEYSTONE Faston, Male, .250x.032, Pb-Free 2 0J25-26

27 CONN 142-0701-851 EMERSON SMA, Jack Receptacle, 50 OHM, Pb-Free 28 0SMA1-28

28 CONN 61729-0010 FCI USB-B, 4p, R/A, Pb-Free 1 0J1

29 CONN TSW-102-07-G-S SAMTEC Header, 2p, Male, .100"sp, Gold, Pb-Free 2 0J3-4

30 CONN TSW-103-07-G-S SAMTEC Header, 3p, Male, .100"sp, Gold, Pb-Free 18 0J7-24

1:12:35 PM, 4/20/2007 2 3

Page

Confidential and Proprietary. This document is considered uncontrolled unless stamped otherwise.

Creation Date:

3/28/2007

Responsible Eng/Mgr: Creator:

Arlene Fox

PL Number:

Z3071-01 Rev:

0Rev Date:

3/28/2007 PL Status:

Released

Rev By:

Main Product:

PCBA, DS25CP104 EVK

TITLE: NATIONAL SEMICONDUCTOR

PCBA, DS25CP104EVK, ROHS

ENERCON - BILL OF MATERIALS

Item Part Type Part Number/Value Mfg Description QtySMTNoSub Ref Des Notes Rev

31 CONN TSW-105-07-G-S SAMTEC Header, 5p, Male, .100"sp, Gold, Pb-Free 1 0J2

33 STENCL T-05889R0 ENERCON STENCIL FABRICATION, TOP, DS25CP104EVK 1 0

34 STENCL T-05890R0 ENERCON STENCIL FABRICATION, BOTTOM,

DS25CP104EVK 1 0

36 REF C-05886R0 ENERCON FABRICATION DWG, DS25CP104EVK 0

37 REF C-05888R0 ENERCON PALLET DWG, DS25CP104EVK 0

38 REF S-05887R0 ENERCON SCHEMATIC, DS25CP104EVK 0

Notes:

DO NOT STUFF:

R15,16,17,18,19

J5,6

1:12:35 PM, 4/20/2007 3 3

Page

Confidential and Proprietary. This document is considered uncontrolled unless stamped otherwise.

Creation Date:

3/28/2007

Responsible Eng/Mgr: Creator:

Arlene Fox

PL Number:

Z3071-01 Rev:

0Rev Date:

3/28/2007 PL Status:

Released

Rev By:

Main Product:

PCBA, DS25CP104 EVK

TITLE: NATIONAL SEMICONDUCTOR

PCBA, DS25CP104EVK, ROHS

ENERCON - BILL OF MATERIALS

Note: This document is considered uncontrolled unless stamped otherwise.