1/10Septe mber 2002
■16 STAGE BINARY COUNTER
■LOW SYMMETR. OUTPUT RESISTANCE,
TYPIC A LLY 100Ω at VDD = 15V
■OSCILLATOR FREQUENCY RANGE :
DC to 100KHz
■AUTO OR MASTER RESET DISABLES
OSCILLATOR DURING RESET TO REDUCE
POWER DISSIPATIO N
■OPERATES WITH VERY SLOW CLOCK
RISE AND FALL TIMES
■BUILT-IN LOW-POWER RC OSCILLATOR
■EXTERNA L CLO CK (applied to pin 3) CAN
BE USED INSTEAD OF O SCILLATOR
■O PER AT ES AS 2 n FREQUENCY DIVIDER
OR AS A SINGLE-TRANSITION TIMER
■Q/Q SELECT PROVIDES OUTPUT LOGIC
LEVEL FLEXIBILITY
■CAPABLE OF DRIVING SIX LOW POWER
TTL LOAD S, THREE L OW POWER
SCHOTTKY LOADS, OR SIX HTL LOADS
OVER THE RATED TEMP. RANGE
■5V, 10V AND 15V PARAMETRIC RATINGS
■100% TESTED FOR QUIESCENT CURRENT
AT 20V
■MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRI PTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
The HCF4541B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
This device is composed of a 16-stages binary
counter, an oscillator controlled by 2 external
resistors and a capacitor, an output control logic
and an automatic power-on reset circuit. The
counter varies on positive-edge clock transition
and it can be cleared by the MASTER RESET
input. The output from this timer is the Q or Q
output from the 8th, 13th, or 16th counter stage.
The choice of the stage depends on the time
HCF4541B
PROGRAMMABLE TIMER
PIN CONNECTION
ORDER CODES
PACKAGE TUBE T & R
DIP HCF4541BEY
SOP HCF4541BM1 HCF4541M013TR
DIP SOP
HCF4541B
2/10
select inputs A or B (see frequency selection
table). The output is available in one of the two
modes that can be selected via the MODE input
pin 10 (see truth t able). The output turns out as a
con tinuos square wav e, with a f requency equ al to
the oscillator frequency divided by 2N when this
MODE input is a logic "1". When it is a logic "0"
and after a MASTER RESET is started, and Q
outpu t has been select ed, the output goes up to a
high state after 2 N-1 counts. It remains in that
state till another MASTER RESET pulse is ap ply
or the mode input is a logic "1". The process starts
by setting the AUTO RESET input (pin 5) to logic
"0" and switching power on . If pin 5 is set to logic
"1", the AUTO RESET circuit is not enabled and
counting cannot start till a positive MASTER
RESET pulse is applied, returning to a low level.
The AUTO RESET consumes a remarkable
amount of power and should not be used if low
power operation is wanted. The frequency of the
oscillator depends on the RC network. It can be
calcu lated using the follow ing formula :
f = 1 / 2.3 RTC CTC
where f is between 1KHz and 100KHz and RS >
10 KΩ and ≈2 RTC
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
RC OSCILLATOR CIRCUIT
PIN No SYMBOL NAME AND FUNCTION
12, 13 A, B Time Select Input
4, 11 NC Not Connected
1, 2 RTC, CTC External Resistor, Capaci-
tor Connection
3RSExternal Resistor Con-
nection or External Clock
Input
5 AR Auto Reset Input
6 MR Master Reset Input
10 MODE Mode Select Input
9Q/Q
SELECT Output Selector
8 Q Output
7VSS Negative Supply Voltage
14 VDD Positive Supply Voltage
HCF4541B
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FUNCTIONAL DIAGRAM
FREQUENCY SELECTION TABLE TRUTH TABLE
LOGIC DIAGRAM
A B N. of Stages N Count 2N
L L 13 8192
L H 10 1024
H L 8 256
H H 16 65536
PIN STATE
LH
5 Auto Reset On Auto Reset Disable
6 Master Reset Off Master Reset On
9Output Initially Low
After Reset (Q) Output Initially High
After Reset (Q)
10 Single Transition Mode Recycle Mode
HCF4541B
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ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All vo l tage v al ues are refe rred t o VSS pin voltage .
RECOMMENDE D OPERATING CONDITIONS
Symbol Parameter Value Unit
VDD Supply Voltage -0.5 to +22 V
VIDC Input Voltage -0.5 to VDD + 0.5 V
IIDC Input Current ± 10 mA
PDPower Dissipation per Package 200 mW
Power Dissipation per Output Transistor 100 mW
Top Operating Temperature -55 to +125 °C
Tstg Storage Temperature -65 to +150 °C
Symbol Parameter Value Unit
VDD Supply Voltage 3 to 20 V
VIInput Voltage 0 to VDD V
Top Operating Temperature -55 to 125 °C
HCF4541B
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DC SPECIFICATI ONS
Th e Noi se Ma rgi n for bot h " 1" and " 0" le vel is : 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
Symbol Parameter
Test Condition Value
Unit
VI
(V) VO
(V) |IO|
(µA) VDD
(V)
TA = 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
ILQuiescent Current 0/5 5 0.04 5 150 150
µA
0/10 10 0.04 10 300 300
0/15 15 0.04 20 600 600
0/20 20 0.08 100 3000 3000
VOH High Level Output
Voltage 0/5 <1 5 4.95 4.95 4.95 V0/10 <1 10 9.95 9.95 9.95
0/15 <1 15 14.95 14.95 14.95
VOL Low Level Output
Voltage 5/0 <1 5 0.05 0.05 0.05 V10/0 <1 10 0.05 0.05 0.05
15/0 <1 15 0.05 0.05 0.05
VIH High Level Input
Voltage 0.5/4.5 <1 5 3.5 3.5 3.5 V1/9 <1 10 7 7 7
1.5/13.5 <1 15 11 11 11
VIL Low Level Input
Voltage 4.5/0.5 <1 5 1.5 1.5 1.5 V9/1 <1 10 3 3 3
13.5/1.5 <1 15 4 4 4
IOH Output Drive
Current 0/5 2.5 <1 5 -1.55 -3.1 -1.08 -1.08
mA
0/5 4.6 <1 5 -5 -10 -3 -4.1
0/10 9.5 <1 10 -4 -8 -3.3 -3.3
0/15 13.5 <1 15 -10 -20 -8.4 -8.4
IOL Output Sink
Current 0/5 0.4 <1 5 1.55 3.1 1.08 1.08 mA0/10 0.5 <1 10 4 8 3.3 3.3
0/15 1.5 <1 15 10 20 8.4 8.4
IIInput Leakage
Current 0/18 Any Input 18 ±10-5 ±0.1 ±1±1µA
CIInput Capacitance Any Input 5 7.5 pF
HCF4541B
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DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25° C, CL = 50pF, RL = 200K Ω, tr = tf = 20 ns)
(* ) T ypical te m peratur e coef ficient for all V DD value is 0.3 %/°C.
DIGITAL TIMER APPLICATION
A positive MASTER RESET pulse clears the
counter and latch. The Output goes high and
keeps up till the number of pulses, selected by A
and B , are counted. This circuit is retriggerable
and is as accurate as the input frequency. If a
more accurate circuit is desired, an external clock
can be used on pin 3. A set-up time equal to the
width of the one shot output is required
immediately following initial power up, during
whic h tim e the outp ut w ill b e h igh
Symbol Parameter Test Cond ition Valu e (*) Unit
VDD (V) Min. Typ. Max.
(28)
tPHL tPLH
Propagation Delay Time
(CLOCK to Q) 5 3.5 10.5 µs10 1.25 3.8
15 0.9 2.9
(216)
tPHL tPLH
Propagation Delay Time
(CLOCK to Q) 5618
µ
s10 3.5 10
15 2.5 7.5
tTHL Transition Time 5 100 2 00 ns10 50 100
15 40 80
tTLH Transition Time 5 180 3 60 ns10 90 180
15 65 130
Master Reset, Clock Pulse
Width 5 900 300 ns10 300 100
15 225 85
fCL Maximum Clock Pulse
Input Frequency 51.5
MHz10 4
15 6
tr, tfMaximum Clock Pulse
Input Rise or Fall Time 5Unlimited µs10
15
HCF4541B
7/10
TEST CIRCUIT
CL = 50p F or equi valent (includes jig and probe ca pacitanc e)
RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)
HCF4541B
8/10
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 1.39 1.65 0.055 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 15.24 0.600
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 2.54 0.050 0.100
Plastic DIP-14 MECHANICAL DATA
P001A
HCF4541B
9/10
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45˚ (typ. )
D 8.55 8.75 0.336 0.344
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 7.62 0.300
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.68 0.026
S ˚ (max.)
SO-14 MECHANICAL DATA
PO13G
8
HCF4541B
10/10
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