NEC NEC Electronics Inc. uPD8255A PROGRAMMABLE PERIPHERAL INTERFACE Description The pPD8255A-2 and PD8255A-5 are general purpose programmable input/output devices designed for use with the 8080A/8085A microprocessors. Twenty-four 1/0 lines may be programmed in two groups of twelve (group | and group II) and used in three modes of operation. In the basic mode, (Mode 0), each group of twelve /O pins may be programmed in sets of 4 to input or output. In the strobed mode, (MODE 1), each group may be programmed to have 8 lines of input or output. Three of the remaining four pins in each group are used for handshaking strobes and interrupt control signals. The bidirectional bus mode, (MODE 2), uses the 8 lines of port A for a bi-directional bus, and five lines from port C for bus controt signals. Features 0 Fully compatible with the 8080A/8085 microprocessor families OC All inputs and outputs TTL compatible C1 24 programmable WO pins O Direct bit set/reset eases contro! application interfaces C] Eight Darlington drive outputs for printers and displays LS! drastically reduces system package count Ordering Information May. System Part Number Package Type Clock Frequency p#PDB255AC-2 40-pin plastic DIP 5 MHz pPD8255AC-5 40-pin plastic DIP 4 MHz Pin Configuration PA3 0 J PA PAL PAy ROO esq ond a. 400 Pc; C190 PCs 21 PCs] t2 Pc, 13 PCy CT] 14 Pci 15 PC: ] 16 PCa 1] 17 PBo EF] 18 PB; O19 PB2 C] 20 ont annean PDB255A Py PA, [) PAs ] PAg ] PA; 1] WR ) RESET ] Do D1 ] Oz 7) D3 [J Ds [J] Ds I De [1 Dy HT Vee [_] PB; L) PBs -) PBs 3 PBs (] PBs 83-002B06A Pin Identification No. Symbol Function 1-4, 37-40 PA7-PAg Port A (1/0) 5 RD Read input 6 cs Chip select input 7 GND Ground 8.9 Ay, Ag Port address inputs 10-17 PC7-PCp Port C (1/0) 18-25 PB7-PBp Port B (1/0) 26 Voc +5 V power supply 27-34 D7-Do Bidirectional data bus 35 RESET Reset input 36 WR Write input 8-69uPD8255A NEC Pin Functions D7-Dp (Data Bus Buffer) These pins form a three-state, bidirectional data bus buffer that is controlled by input and output instructions executed by the processor. Control words and status information are also transmitted via D7-Do. CS (Chip Select) A low input to this pin enables the pPD8255A for communication with the 8080A/8085A. RD (Read) A low input to this pin enables the w.PD8255A for communication with the 8080A/8085A. WR (Write) A tow input to this pin enabies the data bus buffer to receive data or control words from the processor. Ai, Ap (Port Address) These inputs are used in conjunction with CS, RB, and WR to control the selection of one of the three ports on the control word register. Ag and A; are usually connected to Ag and A; of the processor address bus. Block Diagram RESET (Reset) A high level input to this pin clears the control register and places ports A, B, and C in input mode. The input latches in ports A, B, and C are not cleared. PA7-PAo, PB7-PBo, PC7-PCo (Ports A, B, and C) These three 8-bit I/O ports can be configured to meet a variety of functional requirements through system software. The effectiveness and flexibility of the yuPD8255A are further enhanced by special features unique to each of the ports, as follows: Port A has an 8-bit data output latch/buffer, data input latch/buffer, and data input latch. Port B has an 8-bit data I/O latch/buffer and an 8-bit data input buffer. Port C has an 8-bit output latch/buffer and a data input buffer (input not latched). Port C may be divided into two independent 4-bit control and status ports for use with ports A and B. Vec +5 V power supply. GND (Ground) Connection to ground. Power +5 Group Hi Supplies - GND Group et uO rc] i A PA7-PAg Control (8) . Group l Port C lo 8-Bit Upper POPC, Internal 4} Data Bus Data Bus (4 i Data }_____h D7-0, Bus Buffer YY Group ul Port C vo Lower PCa-PCo (4) i} RD _-___-o Group WR Read! Group " write " Port Te) At "1 _ Control Control a PB7-PBo Ay >] __ Logic (8) ++ RESET -} f 83-002807B 8-70NEC uPD8255A Functional Description The read/write and control logic manages ali internal and external transfers of data, control, and status. It is through this block that the processor address and control buses control the peripheral interfaces. Through an OUT instruction in system software from the processor, a control word is transmitted to the pyPD8255A. Information such as the mode, bit set, and bit reset is used to initialize the functional configuration of each I/O port. Both group | and group II accept commands from the read/write control logic and control words from the internal data bus and in turn controls its associated 10 ports, as follows: * Group |: port A and upper port C (PC7-PC,z) Group Il: port B and lower port C (PC3-PCo) While the control word register can be written to, the contents cannot be read back to the processor. Absolute Maximum Ratings Ta = 25C 0C to +70C 65C to +150C -0.5to +7 V Operating temperature, Top Storage temperature, Tstg Voltage on any pin with respect to Vs Comment: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliabitity. DC Characteristics Ta = 0 to +70C; Veg = +5 V 10%; Vgg = OV Limits Parameter Symbo! = Min Max Unit Test Conditions Input low voltage = Vi ~0.5 0.8 Vv Input high voltage = Viy 2 Vee Vv Output low voltage Vo, 0.45 Ve (2) Output high voltage Voy 2.4 Vo (3) Darlington drive lon (} 0-1 -4 mA Veyt = 1.5V current Reyt = 7500 Power supply lec 120 MA Veo = +5 V, current output open Input leakage tH 10 vA Vin = V = Voc current Input leakage ILL -10 vA Vin = 0.4 V current Output ieakage ILou +10 vA Vout = Vec: current CS = 2.0V Output leakage ILoL -10 vA Vout = 0.4 V; current cS = 2.0V Note: (1) Any set of eight outputs from either port A, B, C can source 4 mA into 1.5 V. (2) lo. = 2.5 mA for DB port; 1.7 mA for peripheral ports. (3) lon = -400uA for DB port; 200 yA for peripheral ports. Capacitance Ta = 25C; Voc = OV Limits Test Parameter Symbol = Min Max Unit Conditions Input capacitance C 10 pF fp = 1 MHz 1/0 capacitance Cip 20 pF Unmeasured pins returned to Vs 8-71uPD8255A NEC AC Characteristics Ta = 0C to +70C; Veg = +5 V 5%; Vgg = OV 8255A-2 8255-5 Limits Limits Test Parameter Symbol Min Max Min Max Unit Conditions Address stable before READ tan 0 0 ns Address stable after READ tra 0 0 ns READ pulse width tar 200 250 ns Data valid from READ tro 140 170 ns CL = 150 pF Data float after READ tor 100 100 ns C= 100 pF 10 10 ns CG. = 15 pF Time between READS and /WRITES trv 200 850 ns (Note 2) Write Address stable before WRITE taw 0 0 ns Address stable after WRITE twa 20 20 ns WRITE pulse width tww 200 250 ns. Data valid to WRITE (T.E.) tow 100 100 ns Data valid after WRITE two 0 0 ns Other Timing WR = 0 to output twe 350 350 ns Cy = 150 pF Peripheral data before RD tir 0 0 ns Peripheral data after RD tHR 0 0 ns ACK pulse width tak 300 300 ns STB pulse width tst 350 350 ns Per. data before T.. of STB tes 0 0 ns Per. data after T.E. of STB tpy 150 150 ns ACK = 0 to output tap 300 300 ns CL = 150 pF ACK = 0 to output fioat typ 250 250 ns CL = 50 pF 20 20 CL = 15 pF WR = 1 to OBF = 0 twos 300 650 ns ACK = 0 to OBF = 1 tas 350 350 ns STB = 0 to IBF = 1 tsip 300 300 ns RD = 1 to IBF = 0 tris 300 300 ns RD = 0 to INTR = 0 tat 400 400 ns STB = 1 to INTR = 1 tsi 300 300 ns CL = 150 pF ACK = 1 to INTR = 1 tart 350 350 ns WR = 0 to INTR = 0 twit 450 850 ns Cy, = 150 pF (Note 3) Note: (1) Period of reset pulse must be at least 50 us during or after power on. Subsequent reset pulse can be 500 ns min. (2) trv j+ try tRY WR 8-72 j}+_- trv. SO 83-002806A (3) INTRt may occur as early as WRI. AC Testing Load Circuit Device Under Test *Vext is set at various voltages during testing to guarantee the specification IL C. = 150 pF Vext* 83-0028098N KE Cc uPD8255A Timing Waveforms AC Testing Input, Output Waveform 24 Test Points a Cy = 150 pF a 0.45 83-003793A, Mode 0 Input From Peripheral CS, Ay,Ag Do, D7 Basic Input (READ) Do, 07 CS, Ar, Ao Output to Peripheral Basic Output (WRITE) 43-002810C 8-73uPD8255A NEC Timing Waveforms (cont) Mode 7 OBF tNTR twos t~-taoa- ACK \ + tak tat>| Output to Peripheral STB to \ Peripheral tsT [+tsiB twe trit IBF tsiT INTR RO teH Input from { Peripheral PS trip B3-002812C 8-74uPD8255A Timing Waveforms (cont) Mode 2 Write Data from uPD&OBSA to .PD8255A WR |}+taos> OBF ert iNTR ACK from Po tan _ |} ts + STB from Peripheral V tsie {BF tes tap TT | tho Peripheral ~\ Bus . b -_ _s_OoOooOr oo K A Data trom lt, Data from t Peripheral to uPD8255A i #PDB255A to Peripheral RIB RO Read Data trom uPD8255A to PD8085A Note: (1) Any sequence where WR occurs before ACK and STB occurs before AD Is permissible (INTR = IBF MASK STB * RD + OBF MASK ACK WR). (2} When the .PD&255A is set to Mode 1 or 2, OBF Is reset to be high (logic 1). 83-0028136 8-75uPD8255A NEC The pPD8255A can be operated in modes 0, 1 or 2 which are selected by appropriate control words and are detailed below. Mode 0 Mode 0 provides basic input and output operations through each of the ports A, B, and C. Output data is latched and input data follows the peripheral. No handshaking strobes are needed. @ 16 different configurations in mode 0 @ Two 8-bit ports and two 4-bit ports @ Inputs are not latched @ Outputs are latched Mode 1 Mode 1 provides for strobed input and output opera- tions with data transferred through port A or B and handshaking through port C. @ Two I/O groups (I and Ii) Both groups contain an 8-bit data port and a 4-bit control/data port Both 8-bit data ports can be either latched input or latched output Mode 2 Mode 2 provides for strobed bidirectional operation using PAgPA.7 as the bidirectional latched data bus. PC3PC; is used for interrupts and handshaking bus flow control similar to mode 1. Note that PBgPB7 and PCoPC2 may be defined as mode 0 or 1, input or out- put in conjunction with port A in mode 2. @ An 8-bit latched bidirectional bus port (PAg-PA7) and a 5-bit control port (PC3PC7) @ Both inputs and outputs are latched @ An additional 8-bit input or output port with a 3-bit control port. 8-76 Basic Operation Input Operation (Read) Ay Ao RD wR cs 0 0 0 4 Q | PORT A DATA BUS 0 1 0 1 Q | PORT B - DATA BUS 1 0 0 1 Q | PORT C DATA BUS Output Operation (Write) Ay Ay RD WR cs DATA BUS - PORT A DATA BUS PORT B DATA BUS ~ PORT C DATA BUS CONTROL al=ajolo alafa]o Qololo|!ca Qy,o!]o|oa 0 1 0 1 Disable Function Al Ag RD WR cs x xX x x 1 DATA BUS HIGH Z STATE x x 1 1 0 DATA BUS > HIGH Z STATE Note: (1) X means DO NOT CARE (2) All conditions not listed are illegal and should be avoided.uPD8255A Formats Mode Definition, Bit/Rest Format Control Word Control Word D7 | Dg | Ds | Bq | Dg | D2 | Dy | Do [o, Dg | Ds | Dg | Dg | Dz | Dy | Group II Port C (Lower) 1 = Input 0 = Output Port B 1 = Input O = Output Mode Selection 0 = Mode 0 1 = Mode 1 xX xX X Don't Group | Care Bit Set/Reset 1 = Set Port C (Upper) 9 = Reset 1 = Input 0 = Output Bit Select Port A 1 = Input oO); 1 2/3/4/5/]6]/7 0 = Output Oo} 1 o 1 oa} 1 0] 1 | Bo Mode Selection O;a;1}1]70]0/]1 1 | By 00 = Mode 0 01 = Mode 1 ololojloji}1] 1] 4 |e 1X = Mode 2 Mode Set Flag Bit Set/Reset Flag Mode Definition 1 = Active Bit/Reset 0 = Active 83-002874B 8-77