1
®
FN6826.2
ISL59920, ISL59921, ISL59922, ISL59923
Triple Analog Video Delay Lines
The ISL59920, ISL59921, ISL59922, and ISL59923 are
triple analog delay lines that prov ide skew compensation
between three high-speed signals. These parts are ideal for
compensating for the skew introduced by a typical CAT-5,
CAT-6 or CAT-7 cable (with differing electrical lengths on
each twisted pair) when transmitting analog video.
Using a simple serial interface, the ISL59920, ISL59921,
ISL59922, and ISL59923’s delays are programmable in
steps of 2, 1.5, 1, or 2ns (respectively) for up to a total delay
of 62, 46.5, 31, or 30ns (respectively) on each channel. The
gain of the video amplifiers can be set to x1 (0dB) or x2
(6dB) for back-termination. The delay lines require a ±5V
supply.
Features
• 30, 31, 46.5, or 62ns Total Delay
• 1.0, 1.5, or 2.0ns Delay Step Increments
• Very Low Offset Voltage
• Drop-in Compatible with the EL9115
• Low Power Consumption
• 20 Ld QFN Package
• Pb-Free (RoHS Compliant)
Applications
• Skew Control for RGB Video Signals
• Generating Programmable High-speed Analog Delays
Pinout ISL59920, ISL59921, ISL59922, ISL59923
(20 LD 5X5 QFN)
TOP VIEW
Ordering Information
PART NUMBER
(Note) PART
MARKING
MAX
DELAY
(ns) DELAY STEP
SIZE (ns)
TYPICAL POWER
DISSIPATION
(mW) PACKAGE
(Pb-free) PKG.
DWG. #
ISL59920IRZ* 59 9 2 0 I R Z 62 2. 0 64 5 20 Ld 5 m m x 5 m m Q F N L2 0. 5 x 5 C
ISL59921IR* 59 9 2 1 IR Z 46.5 1. 5 64 5 20 Ld 5m mx5m m QF N L2 0 . 5 x 5C
ISL59922IRZ* 59 9 2 2 I R Z 31 1. 0 64 5 20 Ld 5 m m x 5 m m Q F N L2 0. 5 x 5 C
ISL59923IRZ* 59 9 2 3 I R Z 30 2. 0 54 0 20 Ld 5 m m x 5 m m Q F N L2 0. 5 x 5 C
*Add “-T7” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
2
3
4
15
14
13
12
6
7
8
9
20
19
18
17
VSP
RIN
GND
GIN
BIN
CENABLE
SENABLE
SDATA
X2
TESTR
TESTG
TESTB
ROUT
GNDO
GOUT
VSMO
THERMAL
PAD
5
VSM
10SCLOCK
11 BOUT
16 VSPO
Data Sheet August 31, 2010
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
2FN6826.2
August 31, 2010
Absolute Maximum Ratings (TA = +25°C) Thermal Information
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
ESD Classification
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 0 0 V
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . .1200V
Thermal Resistance (Typical, Note 1) θJA (°C/W)
20 Lead QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+135°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications VSP = VSPO = +5V, VSM = VSMP = -5V, GAIN = 2, TA = +25°C, exposed die plate = -5V, x2 = 5V,
RLOAD = 150Ω on all video outputs, unless otherwise specified.
PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT
dtNominal Delay Increment (Note 2) ISL59920 1.8 2 2.2 ns
ISL59921 1.4 1.5 1.7 ns
ISL59922 0.9 1 1.2 ns
ISL59923 1.8 2 2.3 ns
tMAX Maximum Delay ISL59920 55 62 68 ns
ISL59921 42.5 46.5 53.5 ns
ISL59922 26.5 31 38.5 ns
ISL59923 26.5 30 34.5 ns
DELDT Delay Difference Between Channels for Same
Delay Settings On All Channels 1ns
tPD Propagation Delay ISL59920, ISL59923, measured input to
output, delay setting = 0ns 10 ns
ISL59921, measured input to output, delay
setting = 0ns 8ns
ISL59922, measured input to output, delay
setting = 0ns 7ns
BW -3dB 3dB Bandwidth, 0ns Delay Time ISL59920, ISL59923 153 MHz
ISL59921 200 MHz
ISL59922 230 MHz
BW ±0.1dB ±0.1dB Bandwidth, 0ns Delay Time ISL59920, ISL59923 50 MHz
ISL59921 60 MHz
ISL59922 50 MHz
SR Slew Rate ISL59920, 20-80, delay = 0ns 550 V/µs
ISL59921, 20-80, delay = 0ns 640 V/µs
ISL59922, 20-80, delay = 0ns 700 V/µs
ISL59923; 20-80, delay = 0ns 550 V/µs
ISL59920, ISL59921, ISL59922, ISL59923
3FN6826.2
August 31, 2010
tR - tFTransient Response Time ISL59920, 20% to 80%, for any delay , 1V step
delay = 0ns 1.7 ns
ISL59921, 20% to 80%, for any delay , 1V step
delay = 0ns 1.6 ns
ISL59922, 20% to 80%, for any delay , 1V step
delay = 0ns 1.43 ns
ISL59923, 20% to 80%, for any delay , 1V step
delay = 0ns 1.7 ns
VOVER Voltage Overshoot For any delay, response to 1V step input 4 %
Settling Time Output Settling after Delay Change / Offset
Calibration Output settling time from rising edge of
SENABLE 3µs
THD Total Harmonic Distortion 1VP-P 10MHz sinewave, offset by +0.2V at
mid delay setting -43 -38 dB
X Crosstalk Stimulate G, measure R/B at 1MHz,
ISL59920, ISL59921, ISL59923 -80 -63 dB
ISL59922 -78 -59 dB
VNOutput Noise Bandwidth = 150MHz 2 mVRMS
G_0 Gain Zero Delay 1.74 1.8 1.92 V/V
G_m Gain Mid Delay 1.67 1.8 1.97 V/V
G_f Gain Full Delay 1.6 1.8 2 V/V
DG_m0 Difference in Gain, 0 to Mid -8 0.6 7.5 %
DG_f0 Difference in Gain, 0 to Full -12 -1.8 10 %
DG_fm Difference in Gain, Mid to Full -10 -1.7 7.5 %
VIN Input Voltage Range ISL59920, Gain remains > 90% of nominal,
Gain = 2 -0.7 1.1 V
ISL59921, Gain remains > 90% of nominal,
Gain = 2 -0.7 1.04 V
ISL59922, Gain remains > 90% of nominal,
Gain = 2 -0.7 1.04 V
ISL59923, Gain remains > 90% of nominal,
Gain = 2 -0.7 1.15 V
IBRIN, GIN, BIN Input Bias Current ISL59920, ISL59921 3 6 8 µA
ISL59922, ISL59923 1.5 8 µA
VOS Output Offset Voltage Post offset calibration (Note 4), Delay = 0ns
and Delay = Full -25 -4 +20 mV
ZOUT Output Impedance ISL59920, ISL59921, Enabled,
Chip enable = 5V 4.5 5.4 6.3 Ω
ISL59922, ISL59923, Enabled,
Chip enable = 5V 3.5 6.3 Ω
Disabled, Chip enable = 0V 8 MΩ
+PSRR Rejection of Positive Supply -42 -29 dB
-PSRR Rejection of Negative Supply -58 -46 dB
IOUT Output Drive Current 10Ω load, 0.5V drive 43 53 70 mA
VIH Logic High Switch high threshold 1.6 V
VIL Logic Low Switch low threshold 0.8 V
Electrical Specifications VSP = VSPO = +5V, VSM = VSMP = -5V, GAIN = 2, TA = +25°C, exposed die plate = -5V, x2 = 5V,
RLOAD = 150Ω on all video outputs, unless otherwise specified. (Continued)
PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT
ISL59920, ISL59921, ISL59922, ISL59923
4FN6826.2
August 31, 2010
POWER SUPPLY CHARACTERISTICS
V+ VSP, VSPO Positive Supply Range +4.5 +5.5 V
V- VSM, VSMO Negative Supply Range -4.5 -5.5 V
ISP Positive Supply Current (Note 3) ISL59920 98 115 127 mA
ISL59921, ISL59922 98 125 146 mA
ISL59923 74 90 106 mA
ISPO Positive Output Supply Current (Note 3) ISL59920 11.3 13 15.3 mA
ISL59921, ISL59922 11.3 13 16.3 mA
ISL59923 9.9 13 16 mA
ISM Negative Supply Current (Note 3) -35.45 -31 -26 mA
ISMO Negative Output Supply Current (Note 3) ISL59920, ISL59921, ISL59922 -15.5 -13 -11 mA
ISL59923 -17.5 -13 -9.5 mA
ΔISP Supply Current (Note 3) Increase in ISP per unit step in delay per
channel 0.9 mA
ISTANDBY Positive Supply Standby Current (Note 3) Chip enable = 0V 2.6 mA
SERIAL INTERFACE CHARACTERISTICS
tMAX Max SCLOCK Frequency Maximum programming clock speed 10 MHz
tSEN_SETUP SENABLE to SCLOCK falling edge setup time.
See Figure 33. SENABLE falling edge should occur at least
tSEN_SETUP ns after previous (ignored) clock
and tSEN_SETUP before next (desired) clock.
Clock edges occurring within t_en_ck of the
SENABLE falling edge will have
indeterminate effect.
10 ns
tSEN_CYCLE Minimum Separation Between SENABLE rising
edge and next SENABLE falling edge. See Figure 33. If SENABLE is taken low less than 3µs after it
was taken high, there is a small possibility that
an offset correction will not be initiated.
3µs
NOTES:
2. The limits for the “Nominal Delay Increment” are derived by taking the limits for the “Maximum Delay” and dividing by the number of steps for the
device. For the ISL59920, ISL59921, and ISL59922 the number of steps is 31; for the ISL59923 the number of steps is 15.
3. All supply currents measured with Delay R = 0ns, G = mid delay, B = full delay.
4. Offset measurements are referred to 75Ω load as shown in Figure 1.
Electrical Specifications VSP = VSPO = +5V, VSM = VSMP = -5V, GAIN = 2, TA = +25°C, exposed die plate = -5V, x2 = 5V,
RLOAD = 150Ω on all video outputs, unless otherwise specified. (Continued)
PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT
FIGURE 1. VOS MEASUREMENT CONDITIONS
x2 -
75ΩVOS
VIN VOUT
75Ω
ISL59920, ISL59921, ISL59922, ISL59923
5FN6826.2
August 31, 2010
Pin Descriptions
PIN NUMBER PIN NAME PIN DESCRIPTION
1V
SP +5V for delay circuitry and input amp
2R
IN Red channel video input
3 GND 0V for delay circuitry supply
4G
IN Green channel video input
5V
SM -5V for input amp
6B
IN Blue channel video input
7 CENABLE Chip Enable input, active high: logical high enables chip, low disables chip
8 SENABLE Serial Enable input, active low: logical low enables serial communication
9 SDATA Serial Data input, logic threshold 1.2V: data to be programmed into chip
10 SCLOCK Serial Clock input: Clock to enter data; logical; data written on negative edge
11 BOUT Blue channel video output
12 VSMO -5V for video output buffers
13 GOUT Green channel video output
14 GNDO 0V reference for input and output buffers
15 ROUT Red channel video output
16 VSPO +5V for video output buffers
17 TESTB Blue channel phase detector output
18 TESTG Green channel phase detector output
19 TESTR Red channel phase detector output
20 X2 Gain Select Input: logical high = 2x (+6dB), logical low = 1x (0dB)
Thermal Pad MUST be tied to -5V. For best thermal conductivity also tie to a larger -5V copper plane (inner
or bottom). Use many vias to minimize thermal resistance between thermal pad and copper
plane. Do not connect to GND - connection to GND is equivalent to shorting the -5V and GND
planes together.
ISL59920, ISL59921, ISL59922, ISL59923
6FN6826.2
August 31, 2010
Typical Performance Curves
FIGURE 2. ISL59920 FREQUENCY RESPONSE (GAIN = 1) FIGURE 3. ISL59920 FREQUENCY RESPONSE (GAIN = 2)
FIGURE 4. ISL59921 FREQUENCY RESPONSE (GAIN = 1) FIGURE 5. ISL59921 FREQUENCY RESPONSE (GAIN = 2)
FIGURE 6. ISL59922 FREQUENCY RESPONSE (GAIN = 1) FIGURE 7. ISL59922 FREQUENCY RESPONSE (GAIN = 2)
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
100k 1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
VIN = 700mVP-P
GAIN = 1
10ns
50ns
20ns
40ns
62ns
30ns
0ns
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
100k 1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED GAIN (dB)
VIN = 700mVP-P
GAIN = 2
10ns
50ns
20ns
40ns
62ns
30ns
0ns
-10
-8
-6
-4
-2
0
2
100k 1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED MAGNITUDE (dB)
VIN = 700mVP-P
GAIN = 1
46.5ns
30ns
0ns
10.5ns
21ns
-10
-8
-6
-4
-2
0
2
100k 1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED MAGNITUDE (dB)
30ns
46.5ns
0ns
21ns
10.5ns
VIN = 700mVP-P
GAIN = 2
-10
-8
-6
-4
-2
0
2
4
100k 1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED MAGNITUDE (dB)
31ns
20ns
10ns
0ns
VIN = 700mVP-P
GAIN = 1 -10
-8
-6
-4
-2
0
2
4
100k 1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED MAGNITUDE (dB)
31ns
20ns
10ns
0ns
VIN = 700mVP-P
GAIN = 2
ISL59920, ISL59921, ISL59922, ISL59923
7FN6826.2
August 31, 2010
FIGURE 8. ISL59923 FREQUENCY RESPONSE (GAIN = 1) FIGURE 9. ISL59923 FREQUENCY RESPONSE (GAIN = 2)
FIGURE 10. OFFSET CORRECTION DAC ADJUST FIGURE 11. ISL59920 NOISE SPECTRUM (10k TO 500MHz)
FIGURE 12. ISL59921 NOISE SPECTRUM (10k TO 500MHz) FIGURE 13. ISL59922 NOISE SPECTRUM (10k TO 500MHz)
Typical Performance Curves (Continued)
-10
-8
-6
-4
-2
0
2
100k 1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED MAGNITUDE (dB)
VIN = 700mVP-P
GAIN = 1
30ns 20ns
10ns
0ns
-10
-8
-6
-4
-2
0
2
100k 1M 10M 100M 1G
FREQUENCY (Hz)
NORMALIZED MAGNITUDE (dB)
VIN = 700mVP-P
GAIN = 2
30ns 20ns
10ns
0ns
SENABLE
OUTPUT
TIMEBASE: 500ns/div
SENABLE: 1V/div
OUTPUT: 100mV/div
GAIN: 1
0
50
100
150
200
250
0M 100M 200M 300M 400M 500M 600M
FREQUENCY (Hz)
SPECTRUM (nV/
√
Hz)
OUTPUT REFERRED
GAIN = 2
0
20
40
60
80
100
120
140
160
180
200
0M 100M 200M 300M 400M 500M 600M
FREQUENCY (Hz)
SPECTRUM (nV/
√
HZ)
OUTPUT REFERRED
GAIN = 2
0
50
100
150
200
250
0M 100M 200M 300M 400M 500M 600M
FREQUENCY (Hz)
SPECTRUM (nV/
√
HZ)
OUTPUT REFERRED
GAIN = 2
ISL59920, ISL59921, ISL59922, ISL59923
8FN6826.2
August 31, 2010
FIGURE 14. ISL59923 NOISE SPECTRUM (10k TO 500MHz) FIGURE 15. ISL59920 RISE/FALL TIME vs DELAY TIME
(GAIN = 2)
FIGURE 16. ISL59921 RISE/F ALL TIME vs DELAY TIME
(GAIN = 2) FIGURE 17. ISL59922 RISE/FALL TIME vs DELAY TIME
(GAIN = 2)
FIGURE 18. ISL59923 RISE/F ALL TIME vs DELAY TIME
(GAIN = 2) FIGURE 19. HARMONIC DISTORTION vs FREQUENCY
Typical Performance Curves (Continued)
0
50
100
150
200
250
0M 100M 200M 300M 400M 500M 600M
FREQUENCY (Hz)
S
PE
C
TRUM
(
nV
/√
HZ
)
OUTPUT REFERRED
GAIN = 2
FALL
RISE
0
0.5
1.0
1.5
2.0
2.5
3.0
12 16 20 24 28 32 36 40 44 48 52 56 60
DELAY (ns)
RISE/FALL TIME
048
0
0.5
1.0
1.5
2.0
2.5
3.0
12 16 20 24 28 32 36 40 44 48
DELAY (ns)
RISE/FALL TIME
04 8
FALL
RISE
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0 2 4 6 8 101214161820222426 283032
DELAY (ns)
RISE/FALL TIME
FALL
RISE
0.5
1.0
1.5
2.0
2.5
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32
DELAY (ns)
RISE/FALL TIME
0
FALL
RISE
-80
-70
-60
-50
-40
-30
-20
-10
0
2M 6M 10M 14M 18M 22M 26M 30M 34M 38M
FREQUENCY (Hz)
HARMONIC DISTORTION (dBc)
3RD HD
V+ = +5.0V, V- = -5.0V
VOUT = 1.0VP-P, SINE WAVE
RL = 150Ω
GAIN = 2
2ND HD2ND HD
ISL59920, ISL59921, ISL59922, ISL59923
9FN6826.2
August 31, 2010
FIGURE 20. ISL59920 POSITIVE SUPPLY CURRENT (VSP) vs
DELAY TIME FIGURE 21. ISL59921 POSITIVE SUPPLY CURRENT (VSP) vs
DELAY TIME
FIGURE 22. ISL59922 POSITIVE SUPPLY CURRENT (VSP) vs
DELAY TIME FIGURE 23. ISL59923 POSITIVE SUPPLY CURRENT (VSP) vs
DELAY TIME
FIGURE 24. ISL59920 ISUPPLY+ vs VSUPPLY+ FIGURE 25. ISL59920 ISUPPLY- vs VSUPPLY-
Typical Performance Curves (Continued)
60
80
100
120
140
160
180
POSITIVE SUPPLY CURRENT (mA)
3 CHANNELS
2 CHANNELS 1 CHANNEL
GAIN = 2
0 4 8 12162024283236404448525660
DELAY (ns)
60
80
100
120
140
160
180
200
220
0 12151821242730333639424548
DELAY (ns)
POSITIVE SUPPLY CURRENT (mA)
GAIN = 2
NO INPUT, NO LOAD
369
3 CHANNELS
2 CHANNELS 1 CHANNEL
60
80
100
120
140
160
180
200
220
10 12 14 16 18 20 22 24 26 28 30 32
DELAY (ns)
POSITIVE SUPPLY CURRENT (mA)
8642
0
GAIN = 2
NO INPUT, NO LOAD
2 CHANNELS 1 CHANNEL
3 CHANNELS
60
70
80
90
100
110
120
130
140
150
0 101214161820222426283032
DELAY (ns)
POSITIVE SUPPLY CURRENT (mA)
2468
GAIN = 2
NO INPUT, NO LOAD
2 CHANNELS 1 CHANNEL
3 CHANNELS
60
80
100
120
140
160
180
200
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
DELAY = 62ns
DELAY = 0ns
GAIN = 1 OR 2 -46.5
-46.0
-45.5
-44.0
-44.5
-44.0
-43.5
-43.0
-42.5
-4.0 -4.2 -4.4 -4.6 -4.8 -5.0 -5.2 -5.4 -5.6 -5.8 -6.0
SUPPLY VOLTAGE (V)
NEGATIVE SUPPLY CURRENT (mA)
DELAY = 62ns
DELAY = 0ns
GAIN = 1 OR 2
ISL59920, ISL59921, ISL59922, ISL59923
10 FN6826.2
August 31, 2010
FIGURE 26. ISL59921 ISUPPLY+ vs VSUPPLY+ FIGURE 27. ISL59921 ISUPPLY- vs VSUPPLY-
FIGURE 28. ISL59922 ISUPPLY+ vs VSUPPLY+ FIGURE 29. ISL59922 ISUPPLY- vs VSUPPLY-
ISL59923 ISUPPLY+ vs VSUPPLY+FIGURE 30. ISL59923 ISUPPLY- vs VSUPPLY-
Typical Performance Curves (Continued)
60
80
100
120
140
160
180
200
220
240
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
DELAY = 46.5ns
DELAY = 0ns
GAIN = 1 OR 2
DELAY APPLIED TO ALL
CHANNELS
NO INPUT, NO LOAD
-51.0
-50.5
-50.0
-49.5
-49.0
-48.5
-48.0
-47.5
-47.0
-46.5
-46.0
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
SUPPLY VOLTAGE (V)
NEGATIVE SUPPLY CURRENT (mA)
DELAY = 46.5ns
DELAY = 0ns
GAIN = 2
60
80
100
120
140
160
180
200
220
4.04.24.44.64.85.05.25.45.65.86.0
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
DELAY = 31ns
DELAY = 0ns
GAIN = 1 OR 2
DELAY APPLIED TO ALL
CHANNELS
NO INPUT, NO LOAD
-50.5
-50.0
-49.5
-49.0
-48.5
-48.0
-47.5
-47.0
-46.5
-46.0
-45.5
-45.0
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
SUPPLY VOLTAGE (V)
NEGATIVE SUPPLY CURRENT (mA)
DELAY = 31ns
DELAY = 0ns
GAIN = 2
60
70
80
90
100
110
120
130
140
150
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
DELAY = 30ns
DELAY = 0ns
GAIN = 1 OR 2
DELAY APPLIED TO ALL
CHANNELS
NO INPUT, NO LOAD
60
70
80
90
100
110
120
130
140
150
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
DELAY = 30ns
DELAY = 0ns
GAIN = 1 OR 2
DELAY APPLIED TO ALL
CHANNELS
NO INPUT, NO LOAD -49.5
-49.0
-48.5
-48.0
-47.5
-47.0
-46.5
-46.0
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0
SUPPLY VOLTAGE (V)
NEGATIVE SUPPLY CURRENT (mA)
DELAY = 30ns GAIN = 2
DELAY = 0ns
ISL59920, ISL59921, ISL59922, ISL59923
11 FN6826.2
August 31, 2010
Applications Information
The ISL59920, ISL59921, ISL59922, and ISL59923 are
triple analog delay lines that prov ide skew compensation
between three high-speed signals. These devices
compensate for time skew introduced by a typical CAT - 5,
CAT-6 or CAT -7 cable with dif fering electrical lengths (due to
different twist ratios) on each pair. Via their SPI interface,
these devices can be programmed to independently
compensate for the three different cable delays while
maintaining 80MHz bandwidth at their maximum setting.
There are four different variations of the ISL5992x (ISL5992x
will be used when talking about characteristics that are
common to all four devices).
FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD - QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
3.54W
θ
JA
= 31°C/W
QFN20
4.5
4.0
3.5
3.0
2.0
1.0
00 25 50 75 100 150
AMBIENT TEMPERATURE (°C)
POWER DISSIPATION (W)
12585
2.5
1.5
0.5
FIGURE 32. ISL59920, ISL59921, ISL59922, ISL59923 BLOCK DIAGRAM
+
+
+
+
+
+
DELAY LINE
DELAY LINE
DELAY LINE
18
TESTG
TESTB
TESTR
17
SENABLE
SCLOCK
SDATA X2
19
3
10
8
9
RIN
GIN
BIN
CONTROL LOGIC
BOUT
GOUT
ROUT
GND
GND
VSMO
VSM
51214
20
11
13
15
2
4
6
CENABLE 7
C
[BOTTOM PLATE]
VSPO
16
VSP
1
TABLE 1.
PART NUMBER MAX DELAY
(ns)
NOMINAL DELAY
INCREMENT
(ns)
ISL59920 62 2.0
ISL59921 46.5 1.5
ISL59922 31 1.0
ISL59923 30 2.0
ISL59920, ISL59921, ISL59922, ISL59923
12 FN6826.2
August 31, 2010
Figure 32 shows the ISL5992x block diagram. The 3 analog
inputs are ground referenced single-ended signals. After the
signal is received, the delay is introduced by switching filter
blocks into the signal path. Each filter block is an all-pass
filter introducing either 1, 1.5 or 2ns of delay. In addition to
adding delay, each fi lter block also in troduces some low
pass filtering. As a result, the bandwidth of the signal path
decreases from the 0ns delay setting to the maximum delay
setting, as shown in Figures 2 through 9 of the “Typical
Performance Curves”.
In operation, it is best to allocate the most delayed signal
0ns delay then increase the delay on the other channels to
bring them into line. This will result in delay compensation
with the lowest power and distortion.
Serial Bus Operation
The ISL5992x is programmed via 8-bit words sent through
its serial interface. The first bit (MSB) of SDAT A is latched on
the first falling clock edge after SENABLE goes low, as
shown in Figure 33. This bit should be a 0 under all
conditions. The next two bits determine the color register to
be written to: 01 = R, 02 = G, and 03 = B (00 is reserved for
the test register). The final five bits set the delay for the
specified color . Af ter 8 bits are latched, any additional clocks
are treated as a new word (data is shifted directly to the final
registers as it is clocked in). This allows the user to write (for
example) the 24 bits of data necessary for R, G, and B as a
single 24-bit word. It is the user's responsibility to send
complete multiples of 8 clock cycles. The serial state
machine is reset on the falling edge of SENABLE, so any
data corruption that may have occurred due to too many or
too few clocks can be corrected with a new word with the
correct number of clocks. The initial value of all registers on
power-up is 0.
SENABLE
SCLOCK
SDATA A1 A0 D4 D3 D2 D1 D0*0
a b v w x y z
FIGURE 33. SERIAL TIMING
*D0 is 0 when addressing the test register
tSEN_SETUP tSEN_CYCLE
TABLE 2. SERIAL BUS DATA
vwxyz ISL59920
DELAY ISL59921
DELAY ISL59922
DELAY ISL59923
DELAY
00000 0 0 0 0
00001 2 1.5 1 2
00010 4 3 2 4
00011 6 4.5 3 6
00100 8 6 4 8
00101 10 7.5 5 10
00110 12 9 6 12
00111 14 10.5 7 14
01000 16 12 8 16
01001 18 13.5 9 18
01010 20 15 10 20
01011 22 16.5 11 22
01100 24 18 12 24
01101 26 19.5 13 26
01110 28 21 14 28
01111 30 22.5 15 30
10000 32 24 16 N/A
10001 34 25.5 17 N/A
10010 36 27 18 N/A
10011 38 28.5 19 N/A
10100 40 30 20 N/A
10101 42 31.5 21 N/A
10110 44 33 22 N/A
10111 46 34.5 23 N/A
11000 48 36 24 N/A
11001 50 37.5 25 N/A
11010 52 39 26 N/A
11011 54 40.5 27 N/A
11100 56 42 28 N/A
11101 58 43.5 29 N/A
11110 60 45 30 N/A
11111 62 46.5 31 N/A
NOTE: Delay register word = 0abvwxyz; Red register - ab = 01;
Green register - ab = 10; Blue register - ab = 11; vwxyz selects
delay; ab = 00 writes to the test register to change the DAC slice
level.
TABLE 2. SERIAL BUS DATA (Continued)
vwxyz ISL59920
DELAY ISL59921
DELAY ISL59922
DELAY ISL59923
DELAY
ISL59920, ISL59921, ISL59922, ISL59923
13 FN6826.2
August 31, 2010
Offset Compensation
To counter the ef fects of offset, the ISL5992x incorporates a n
offset compensation circuit that reduces the of fset to less than
±25mV. An offset correction cycle is triggered by the rising
edge of the SENABLE pin after writing a delay word to any of
the 3 channels. The of fset calibratio n st a rt s about 50 0ns af te r
the SENABLE rising edge to allow the ISL5992x time to settle
(electrically and thermally) to the new delay setting. It lasts
about 2.5µs, for a total of fset correcti on time of 3.0µs. During
calibration, the ISL5992x’ s input s are internally shorted
together (however the characteristics of the ISL5992x’s
differentia l input p ins stay the sa me), and the of fset of th e
output st age is adjusted unti l it has been minimi zed .
In addition to automatically triggering after a delay change
(or any register write), an additional offset calibration may be
initiated at any time, such as:
• When the die temperature changes. Applying powe r to the
ISL5992x will cause the die temperature to quickly increase
then slowly settle over 20 to 30ns. Because the ISL5 992x
powers-down unused delay st ag es (to minimize power
consumption), the die temp will a lso change and settle af ter
a delay change. Initiating an offset 20ns (or longer,
depending on the thermal characteristics of the system)
after power-on or a de lay change wi ll minimize the of fse t in
normal operation thereafter.
• When the ambient temperature changes. If you are
monitoring the temperature, initia te a calibration e very time
the temperature shift s by 5 to 10 degrees. If you are not
monitoring temperature, initiate a calibration periodically, as
expected by the environment the device is in.
• After a CENABLE (Chip Enable) cycle. The CENABLE pin
may be taken low to put the ISL5992x in a low power
standby mode to conserve power when not needed. When
the CENABLE pin goes high to exit this low power mode,
the ISL5992x will recall the delay settin gs but it wil l not
recall the correct offset calibration settings, so to maintain
low offset, a write to the delay register is required after a
CENABLE cycle. Offset errors may be as large as
±200mV coming out of standby mode - recalibration is a
necessity. For best performance, initiate an additional
calibration again once the die temperature has settled (20
to 30ns after coming ou t of standby).
• After a gain change (X2 pin changes state). The syste matic
offset is dif ferent for a gain of x1 vs. a gain of x2, so an
offse t calibration is re commended after a gain change.
However in a typical application the gain is perma nently
fixed at x1 or x2, so this is not usually a concern.
Offset Calibration with Sync-On-Video
The offset correction mechanism temporarily disconnects
the input signals to perform the offset calibration. This
introduces several discontinui ties in the video signal, as
shown in Figure 10 on page 7:
• 200-300mV spike when calibration is engaged
• Successive-approximation offset null
• 200-300mV spike when calibration is disengaged
• In addition, because an offset calibration is performed any
time the delay changes, the output video signal may be
moved forward or back in time by up to 62ns.
If the video signals going through the ISL5992x contain only
video (with no sync signals), this appears as a 2µs “sparkle”
on the screen - usually it is not even visible to the eye.
However if sync signals are embedded on the video, the
spikes may be misinterpreted as a sync signal, causing the
downstream circuitry to see an asynchronous sync pulse. In
some receiving systems (typically monitors), a single
asynchronous sync pulse can cause the system to think the
video signal has changed. Dependin g on the receiveing
monitor’s design, this can initiate a new video acquisition
cycle (for example, the monitor blanks the screen while it
measures the “new” HSYNC and VSYNC timing, selects the
right mode, and optimizes the image). This can cause the
monitor to go blank for up to several seconds after a single
delay change.
Since this only happens at power-on and when the delays
are initially set, this is not a problem in normal use, but if the
monitor is blanking for several seconds every time the delay
is adjusted, it can cause calibration to take longer than
absolutely necessary. If this behavior is undesirable , it can
be eliminat ed as fo l lo w s:
1. Synchronize the rising edge of SENABLE to the sync
pulse, so that the SENABLE goes high immediately after
the trailing edge of the sync pulse. SENABLE can be
taken low and the serial data written asynchronously at
any time - it is the rising edge of SENABLE that triggers
a calibration.
2. If the Sync Processor is part of the same design as
ISL5992x, ensure that the sync processor ignores the
first x microseconds after a valid sync, where x = 3µs + the
delay between the end of a sync and rising edge of
SENABLE. This will prevent the sync processor from
generating invalid sync signals du e to the spikes.
3. If the Sync Processor is external to the design with the
ISL5992x (video with Sync-On-Green, for example), the
video signal should disconnected from the ISL59920 and
shorted to ground via an analog switch for the first x
microseconds after a valid sync, where x = 3µs + the
delay between the end of a sync and rising edge of
SENABLE. This will remove the calibration signals from
the video signal.
ISL59920, ISL59921, ISL59922, ISL59923
14 FN6826.2
August 31, 2010
These steps are only necessary if the sync signal is
embedded on the video and you want to avoid possible
monitor blanking during skew adjustment.
Test Pins
Three test pins are provided (Test R, Test G, Test B). During
normal operation, the test pins output pulses of current for a
duration of the overlap between the inpu ts, as shown in
Figure 34:
TESTR pulse = REDOUT (A) with respect to GREEN OUT (B)
TESTG pulse = GREENOUT with respect to BLUEOUT
TESTB pulse = BLUEOUT with respect to REDOUT
Averaging the current gives a direct measure of the delay
between the two edges. When A precedes B, the current
pulse is +50µA, and the outp ut voltage goes up. When B
precedes A, the pulse is -50µA.
For the logic to work correctly , A and B must have a period of
overlap while they are high (a delay longer tha n the pulse
width cannot be measured).
Signals A and B are derived from the vi deo in put by
comparing the video signal with a slicing level, which is set by
an internal DAC. This enables the delay to be measured
either from the rising edges of sync-like signal s encoded on
top of the video or from a d edicated set-up signal. The outputs
can be used to set the correct delays for the signals received.
The DAC level is set through the serial input by bits 1
through 4 directed to the test register (00).
Internal DAC Voltage
The slice level of the internal DAC may be programmed by
writing a byte to the test register (00). Table 3 shows the
values that should be written to change the DAC slice level.
Please keep in mind when writing to the test register that the
LSB should always be zero.
Referred to the input, the DAC slice ra nge for the ISL5992x
is cut in half for gain of 2 mode because the slicing occurs
after the x1/x2 stage output amplifier. (In the EL9115, the
slicing occurred before the amplifier so the range of the DAC
voltage was the same for either gain of 1 or gain of 2).
TABLE 3. DAC VOLTAGE RANGE - INPUT REFERRED
wxyz DAC RANGE [mV]
(GAIN 1) DAC RANGE [mV]
(GAIN 2)
1000 -400 -200
1001 -350 -175
1010 -300 -150
1011 -250 -125
1100 -200 -100
1101 -150 -75
1110 -100 -50
1111 -50 -25
0000 0 0
0001 50 25
0010 100 50
0011 150 75
0100 200 100
0101 250 125
0110 300 150
0111 350 175
NOTE: Test Register word = 000wxyz0. wxyz fed to DAC. z is LSB
FIGURE 34. DELAY DETECTOR
A
B
OUTPUT
4SLICING LEVEL
COMPARATORS
A
B
INTERNAL DAC
000wxyz0
TESTR
A
BTESTG
A
BTESTB
REDOUT
GREENOUT
BLUEOUT
ISL59920, ISL59921, ISL59922, ISL59923
15 FN6826.2
August 31, 2010
Power Dissipation
As the delay setting increases, additional filter blocks turn on
and insert into the signal path. When the delay per channel
increments, VSP current increases by 0.9mA while VSM
does not change significantly. U nder the extreme settings,
the positive supply current reaches 141mA and the negative
supply current can be 41mA. Operating at ±5V power supply ,
the worst-case ISL5992x power dissipation is:
The minimum θJA required for long term reliable operation of
the ISL5992x is calculated using Equatio n 2:
Where:
TJ is the maximum junction temperature (+135°C)
TA is the maximum ambient temperature (+85°C)
For a 20 Ld package on a well laid-out PCB with good
connectivity between the QFN’s pad and the PCB copper
area, 31°C/W θJA thermal resistance can be achieved. This
yields a much higher power dissipation of 3.54W usin g
Equation 2 (see Figure 31). To disperse the heat, the bottom
heat spreader must be soldered to the PCB. Heat flows
through the heat spreader to th e circuit board copper then
spreads and convects to air. Thus, the PCB copper pla ne
becomes the heatsink (see TB389). This has proven to be a
very eff ec ti v e te ch niq u e. A separate application note, which
details the 20 Ld QFN PCB design considerations, is
available.
PD 5 141mA 5 41mA•910mW=+•=(EQ. 1)
θJA TJ
(TA)PD 55°=⁄CW⁄–= (EQ. 2)
ISL59920, ISL59921, ISL59922, ISL59923
16
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN6826.2
August 31, 2010
ISL59920, ISL59921, ISL59922, ISL59923
Quad Flat No-Lead Plastic Package (QFN)
AB
E
1
2
3
N
(N-1)
(N-2)
PIN #1
I.D. MARK
(N/2)
0.075
(2X)
C
0.075
(2X)
C
TOP VIEW
SIDE VIEW
C
SEATING
PLANE
0.08 C
N LEADS AND
EXPOSED PAD
SEE DETAIL “X”
e0.10 C
L
b
N
(N-1)
(N-2)
1
2
3
PIN #1 I.D.
0.01 BA
MC
3
NE 5
7
(N/2)
(D2)
(E2)
C(c)
A1
A2
BOTTOM VIEW
DETAIL “X”
(L)
N LEADS
N LEADS
D
L20.5x5C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220)
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.80 0.90 1.00 -
A1 0.00 0.02 0.05 -
b 0.28 0.30 0.32 -
c0.20 REF-
D 5.00 BASIC -
D2 3.70 REF 8
E 5.00 BASIC -
E2 3.70 REF 8
e 0.65 BASIC -
L 0.35 0.40 0.45 -
N204
ND 5 REF 6
NE 5 REF 5
Rev. 0 6/06
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7. Inward end of terminal may be square or circular in shape with
radius (b/2) as shown.
8. If two values are listed, multiple exposed pad options are
available. Refer to device-specific datasheet.
9. One of 10 packages in MDP0046
