TECHNICAL NOTE
High-performance Regulator IC Series for PCs
Ultra Low Dropout
Linear Regulators for PC Chipsets
BD3508EKN
● Description
The BD3508EKN ultra low-dropout linear chipset regulator operates from a very low input supply, and offers ideal
performance in low input voltage to low output voltage applications. It incorporates a built-in N-MOSFET power transistor to
minimize the input-to-output voltage differential to the ON resistance (RON=65mΩ) level. By lowering the dropout voltage in
this way, the regulator realizes high current output (Iomax=3.0A) with reduced conversion loss, and thereby obviates the
switching regulator and its power transistor, choke coil, and rectifier diode. Thus, the BD3508EKN is designed to enable
significant package profile downsizing and cost reduction. An external resistor allows the entire range of output voltage
configurations between 0.65 and 2.7V, while the NRCS (soft start) function enables a controlled output voltage ramp-up,
which can be programmed to whatever power supply sequence is required.
● Features
1) Internal high-precision reference voltage circuit(0.65V±1%)
2) Built-in VCC under voltage lock out circuit (VCC=3.80V)
3) NRCS (soft start) function reduces the magnitude of in-rush current
4) Internal Nch MOSFET driver offers low ON resistance (65mΩ typ)
5) Built-in current limit circuit(3.0A min)
6) Built-in thermal shutdown (TSD) circuit
7) Variable output (0.65～2.7V)
8) Incorporates high-power HQFN20V package: 4.2×4.2×0.9(mm)
● Applications
Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances
● Model Lineup
Oct. 2008
●Absolute Maximum Ratings
◎BD3508EKN
○Absolute Maximum Ratings(Ta=100℃)
PARAMETER SYMBOL RATING UNIT
Input Voltage 1 VCC 6.0 *1 V
Input Voltage 2 VIN 6.0 *1 V
Enable Input Voltage Ven 6.0 V
Power Dissipation 1 Pd1 0.5 *2 W
Power Dissipation 2 Pd2 0.75 *3 W
Power Dissipation 3 Pd3 1.75 *4 W
Power Dissipation 4 Pd4 2.0 *5 W
Operating Temperature Range Topr -10～+100 ℃
Storage Temperature Range Tstg -55～+125 ℃
Maximum Junction Temperature Tjmax +150 ℃
*1 Should not exceed Pd.
*2 Reduced by 4mW/℃ for each increase in Ta≧25℃(no heat sink)
*3 Reduced by 6mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board,
with no copper foil on the bottom surface)
*4 Reduced by 14mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board,
with 60mm X 60 mm copper foil on the bottom surface…1-layer)
*5 Reduced by 16mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board,
with 60mm X 60 mm copper foil on the bottom surface…2-layer)
●Operating Conditions
○Operating Voltage(Ta=25℃)
PARAMETER SYMBOL MIN. MAX. UNIT
Input Voltage 1 VCC 4.3 5.5 V
Input Voltage 2 VIN 0.75 VCC-1 *6 V
Output Voltage Setting Range Vo VFB 2.7 V
Enable Input Voltage Ven -0.3 5.5 V
NRCS Capacity CNRCS 0.001 1 uF
*6 VCC and VIN do not have to be implemented in the order listed.
★This product is not designed for use in radioactive environments.
●Electrical Characteristics (Unless otherwise specified, Ta=25℃ VCC=5V Ven=3V VIN=1.8V R1=3.9KΩ R2=3.3KΩ)
Parameter Symbol Limit Unit Condition
Min. Typ. Max.
Bias Current ICC - 0.7 1.4 mA
VCC Shutdown Mode Current IST - 0 10 uA Ven=0V
Output Voltage VOUT - 1.200 - V
Maximum Output Current Io 3.0 - - A
Output Short Circuit Current Iost 3.0 - - A Vo=0V
Output Voltage Temperature
Coefficient Tcvo - 0.01 - %/℃
Feedback Voltage 1 VFB1 0.643 0.650 0.657 V
Feedback Voltage 2 VFB2 0.630 0.650 0.670 V Io=0 to 3A
Ta=-10 to 100℃ *
7
Line Regulation 1 Reg.l1 - 0.1 0.5 %/V VCC=4.3V to 5.5V
Line Regulation 2 Reg.l2 - 0.1 0.5 %/V VIN=1.2V to 3.3V
Load Regulation Reg.L - 0.5 10 mV Io=0 to 3A
Minimum Input-Output Voltage
Differential dVo - 65 100 mV
Io=1A,VIN=1.2V
Ta=-10 to 100℃ *
7
Standby Discharge Current Iden 1 - - mA Ven=0V, Vo=1V
[ENABLE]
Enable Pin
Input Voltage High Enhi 2 - - V
Enable Pin
Input Voltage Low Enlow -0.2 - 0.8 V
Enable Input Bias Current Ien - 7 10 uA Ven=3V
[FEEDBACK]
Feedback Pin Bias Current IFB -100 0 100 nA
[NRCS]
NRCS Charge Current Inrcs 14 20 26 uA Vnrcs=0.5V
NRCS Standby Voltage VSTB - 0 50 mV Ven=0V
[UVLO]
VCC Under voltage Lock out
Threshold Voltage VccUVLO 3.5 3.8 4.1 V VCC:Sweep-up
VCC Under voltage Lock out
Hysteresis Voltage Vcchys 100 160 220 mV VCC:Sweep-down
[AMP]
Gate Source Current IGSO - 1.6 - mA VFB=0, VGATE=2.5V
Gate Sink Current IGSI - 4.7 - mA VFB=VCC, VGATE=2.5V
*7 Design targets
● Reference Data
Fig.1 Transient response (0→3A)
Co=150μF×2
Fig.2 Transient response (0→3A)
Co=150μF
Fig.3 Transient response (0→3A)
Co=47μF
Fig.4 Transient response (3→0A)
Co=150μF×2
Fig.5 Transient response (3→0A)
Co=150μF
Fig.6 Transient response (3→0A)
Co=47μF
Fig.7 Waveform at output start Fig.8 Waveform at output OFF Fig.9 Input sequence
Fig.10 Input sequence Fig.11 Input sequence Fig.12 Input sequence
45mV
3.0A
Vo
50mV/di
v
Io
2A/di
v
64mV
3.0A
Vo
50mV/di
v
Io
2A/di
v
91mV
3.0A
Vo
100mV/di
v
Io
2A/di
v
Vo
50mV/di
v
Io
2A/di
v
55mV
3.0A
Io=0A→3A/3μsec t(5μsec/div) Io=0A→3A/3μsec t(5μsec/div) Io=0A→3A/3μsec t(5μsec/div)
Io=3A→0A/3μsec t(5μsec/div)
Vo
50mV/di
v
Io
2A/di
v
79mV
3.0A
Io=3A→0A/3μsec t(5μsec/div)
Vo
100mV/di
v
Io
2A/di
v
87mV
3.0A
Io=3A→0A/3μsec t(5μsec/div)
Ven
2V/di
v
VNRCS
2V/di
v
Vo
1V/di
v
Ven
2V/di
v
t(200μsec/div) t(2msec/div)
VCC
Ven
VIN
Vo
VCC
Ven
VIN
Vo
VCC
Ven
VIN
Vo
VCC
Ven
VIN
Vo
VCC→VIN→Ven
VIN→VCC→Ven Ven→VCC→VIN VCC→Ven→VIN
VNRCS
2V/di
v
Vo
1V/di
v
1.15
1.17
1.19
1.21
1.23
1.25
-101030507090
Ta(℃)
Vo(V)
Fig.13 Input sequence Fig.14 Input sequence
VCC
Ven
VIN
Vo
VCC
Ven
VIN
Vo
VIN→Ven→VCC Ven→VIN→VCC
Fig.15 Ta-Vo (Io=0mA)
Fig.16 Ta-ICC
0.50
0.55
0.60
0.65
0.70
0.75
0.80
0.85
0.90
0.95
1.00
-101030507090
Ta(℃)
ICC(mA)
0
0.2
0.4
0.6
0.8
1
1.2
-60 -30 0 30 60 90 120 150
Ta(℃)
ICC(uA)
Fig.17 Ta-ISTB
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
-101030507090
Ta(℃)
IIN(mA)
Fig.18 Ta-IIN
Fig.19 Ta-IINSTB
0
5
10
15
20
25
30
-60 -30 0 30 60 90 120 150
Ta(℃)
IIN(uA)
15
16
17
18
19
20
21
22
23
24
25
-101030507090
Ta(℃)
INRCS(uA)
Fig.20 Ta-INRCS
-20
-15
-10
-5
0
5
10
15
20
-101030507090
Ta(℃)
IFB(nA)
Fig.21 Ta-IFB
Fig.22 Ta-Ien
0
1
2
3
4
5
6
7
8
9
10
-101030507090
Ta(℃)
Ien(uA)
Fig.23 Ta-RON
(VCC=5V/Vo=1.2V)
Fig.24 VCC-RON
100
100 100
100 100
100
25
30
35
40
45
50
55
60
24 68
Vcc(V)
RON(mΩ)
0
10
20
30
40
50
60
-101030507090
Ta(℃)
RON(mΩ)
2.5V
100
1.8V
1.2V
● Block Diagram
● Pin Function Table ● Pin Layout
PIN
No.
PIN
Name PIN Function
1 GND1 Ground pin 1
2 GND2 Ground pin 2
3 N.C. No connection (empty) pin
4 N.C. No connection (empty) pin
5 N.C. No connection (empty) pin
6 VCC Power supply pin
7 EN Enable input pin
8 VIN1 Input pin 1
9 VIN2 Input pin 2
10 VIN3 Input pin 3
11 GATE Gate pin
12 N.C. No connection (empty) pin
13 N.C. No connection (empty) pin
14 N.C. No connection (empty) pin
15 N.C. No connection (empty) pin
16 Vo1 Output voltage pin 1
17 Vo2 Output voltage pin 2
18 Vo3 Output voltage pin 3
19 FB Reference voltage feedback pin
20 NRCS
In-rush current protection (NRCS)
capacitor connection pin
reverse FIN Connected to heatsink and GND
* Please short N.C to the GND
Enable
7
6
VCC
VCC
Reference
Block
Thermal
Shutdown
NRCS
20 1
EN
NRCS GND
19
18
17
9
Current
Limit
VCC
UVLO CL
CL
UVLO
TSD
EN
VIN3
Vo1
FB
R2
R1
VIN
Vo
TSD
2
11
GATE
16
Vo2
Vo3
10
8
VIN2
VIN1
VCC
16
17
18
19
20
1 2 3 4 5
10
9
8
7
6
15 14 13 12 11
N.C N.C N.C N.C
GATE
N.C N.C N.C GND2 GND1
VIN3
VIN2
VIN1
EN
VCC
Vo1
Vo2
Vo3
FB
NRCS
FIN
● Operation of Each Block
・AMP
This is an error amp that functions by comparing the reference voltage (0.65V) with Vo to drive the output Nch FET
(Ron=65mΩ). Frequency optimization helps to realize rapid transit response, and to support the use of functional polymer
output capacitors. AMP input voltage ranges from GND to 2.7V, while the AMP output ranges from GND to VCC. When EN
is OFF, or when UVLO is active, output goes LOW and the output NchFET switches OFF.
・EN
The EN block controls the regulator ON/OFF pin by means of the logic input pin. In OFF position, circuit voltage is
maintained at 0μA, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the
NRCS pin Vo, thereby draining the excess charge and preventing the load IC from malfunctioning. Since no electrical
connection is required (such as between the VCC pin and the ESD prevention Di), module operation is independent of the
input sequence.
・UVLO
To prevent malfunctions that can occur when there is a momentary decrease in VCC supply voltage, the UVLO circuit
switches output OFF, and, like the EN block, discharges the NRCS Vo. Once the UVLO threshold voltage (TYP3.80V) is
exceeded, the power-on reset is triggered and output begins.
・CURRENT LIMIT
With output ON, the current limit function monitors internal IC output current against the parameter value (3.0A). When
current exceeds this level, the current limit module lowers the output current to protect the load IC. When the overcurrent
state is eliminated, output voltage is restored at the parameter value.
・NRCS
The soft start function is realized by connecting an NRCS pin external capacitor to the target ground. Output ramp-up can
be set for any period up to the time the NRCS pin reaches VFB (0.65V). During startup, the NRCS pin serves as the 20μA
(TYP) constant current source and charges the externally connected capacitor.
・TSD (Thermal Shut Down)
The shutdown (TSD) circuit automatically switches output OFF when the chip temperature gets too high, thus serving to
protect the IC against “thermal runaway” and heat damage. Because the TSD circuit is provided to shut down the IC in the
presence of extreme heat, in order to avoid potential problems with the TSD, it is crucial that the Tj (max) parameter not be
exceeded in the thermal design.
・VIN
The VIN line is the major current supply line, and is connected to the output NchFET drain. Since no electrical connection
(such as between the VCC pin and an ESD protective Di) is necessary, VIN operates independent of the input sequence.
However, since there is an output NchFET body Di between VIN and Vo, a VIN-Vo electric (Di) connection is present. Note,
therefore, that when output is switched ON or OFF, reverse current may flow to the VIN from Vo.
●Timing Chart
EN ON/OFF
VCC ON/OFF
VIN
VCC
Ven
NRCS
Vo
VIN
VCC
Ven
NRCS
Vo
t
t
Startup
Hysteresis
UVLO
Startup
0.65V(typ)
0.65V(typ)
●Evaluation Board
Component Rating Manufacturer Product Name Component Rating Manufacturer Product Name
U1 - ROHM BD3508EKN C5 47uF ROHM MCH318CN476K
C1 1uF ROHM MCH184CN105K C4 10uF ROHM MCH218CN106K
C10 0.01uF ROHM MCH185CN103K R1 3.9k ROHM MCR03EZPF3301
R8 0Ω - Jumper R2 3.3k ROHM MCR03EZPF3901
■
■
BD3508EKN Evaluation Board Schematic
■
■
BD3508EKN Evaluation Board Layout
■
■
BD3508EKN Evaluation Board Standard Component List
TOP Laye r Bottom Layer Silkscreen
● Recommended Circuit Example
Component Recommended
Value Programming Notes and Precautions
R1/R2 3.9k/3.3k IC output voltage can be set with a configuration formula using the values for the internal
reference output voltage (VFB)and the output voltage resistors (R1, R2). Select resistance
values that will avoid the impact of the VFB current (±100nA). The recommended total
resistance value is 10KΩ.
C3 47μF To assure output voltage stability, please be certain the Vo1, Vo2, and Vo3 pins and the
GND pins are connected. Output capacitors play a role in loop gain phase compensation
and in mitigating output fluctuation during rapid changes in load level. Insufficient
capacitance may cause oscillation, while high equivalent series reisistance (ESR) will
exacerbate output voltage fluctuation under rapid load change conditions. While a 47μF
ceramic capacitor is recomended, actual stability is highly dependent on temperature and
load conditions. Also, note that connecting different types of capacitors in series may
result in insufficient total phase compensation, thus causing oscillation. In light of this
information, please confirm operation across a variety of temperature and load
conditions.
C1 1μF Input capacitors reduce the output impedance of the voltage supply source connected to
the (VCC) input pins. If the impedance of this power supply were to increase, input
voltage (VCC) could become unstable, leading to oscillation or lowered ripple rejection
function. While a low-ESR 1μF capacitor with minimal susceptibility to temperature is
recommended, stability is highly dependent on the input power supply characteristics and
the substrate wiring pattern. In light of this information, please confirm operation across a
variety of temperature and load conditions.
C2 10μF Input capacitors reduce the output impedance of the voltage supply source connected to
the (VCC) input pins. If the impedance of this power supply were to increase, input
voltage (VCC) could become unstable, leading to oscillation or lowered ripple rejection
function. While a low-ESR 10μF capacitor with minimal susceptibility to temperature is
recommended, stability is highly dependent on the input power supply characteristics and
the substrate wiring pattern. In light of this information, please confirm operation across a
variety of temperature and load conditions.
C4 0.01μF The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush
current from going through the load (VIN to Vo) and impacting output capacitors at power
supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the
UVLO function is deactivated. The temporary reference voltage is proportionate to time,
due to the current charge of the NRCS pin capacitor, and output voltage start-up is
proportionate to this reference voltage. Capacitors with low susceptibility to temperature
are recommended, in order to assure a stable soft-start time.
R3/C5
- This component is employed when the C3 capacitor causes, or may cause, oscillation. It
provides more precise internal phase correction.
16
17
18
19
20
12345
15 14 13 12 11
10
9
8
7
6
C2 VIN
VEN
VCC C1
Option
R3
C5
C3
C4
R1
R2
Vo (1.2V/3A)
● Heat Loss
Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed
temperature limits, and thermal design should allow sufficient margin from the limits.
1. Ambient temperature Ta can be no higher than 100 ℃.
2. Chip junction temperature (Tj) can be no higher than 150℃.
Chip junction temperature can be determined as follows:
It is recommended to layout the VIA for heat radiation in the GND pattern of reverse (of IC) when there is the GND pattern in
the inner layer (in using multiplayer substrate). This package is so small (size: 4.2mm×4.2mm) that it is not available to
layout the VIA in the bottom of IC. Spreading the pattern and being increased the number of VIA like the figure below).
enable to get the superior heat radiation characteristic. (This figure is the image. It is recommended that the VIA size and
the number is designed suitable for the actual situation.).
Most of the heat loss that occurs in the BD3508EKN is generated from the output Nch FET. Power loss is determined by
the total VIN-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current
conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in mind that heat
dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the
BD3508EKN) make certain to factor conditions such as substrate size into the thermal design.
Power consumption (W) = Input voltage (VIN)- output voltage (Vo) ×Io (Ave)
Example) VIN=1.5V, Vo=1.2V, Io(Ave) = 3A
Power consumption (W) = 1.5(V)-1.2(V) ×3.0(A)
= 0.9(W)
① Calculation based on ambient temperature (Ta)
Tj=Ta+θj-a×W
Bare (unmounted) IC
1-layer substrate (top layer copper foil less than 3%)
1-layer substrate (bottom layer surface copper foil area 60×60mm2)
2-layer substrate (top layer copper foil area 60×60mm2)
Substrate size: 70×70×1.6mm3 (substrate with thermal via)
θj-a:HQFN20V 250.0℃/W
166.7℃/W
71.4℃/W
62.5℃/W
＜Reference values＞
● Input-Output Equivalent Circuit Diagram
●Reference landing pattern
(Unit : mm)
Lead pitch
e
landing pitch
MIE
landing length
≧l2
landing pitch
b2
0.50 2.60 1.10 0.25
central pad length
central pad pitch thermal via
D3 E3 Diameter
1.60 1.60 Φ0.30
*It is recommended to design suitable for the actual application.
350kΩ
10kΩ
EN
NRCS
VCC
1kΩ
10kΩ
1kΩ
1kΩ
1kΩ
1kΩ
VCC
VCC
FB 1kΩ
100kΩ
100kΩ
20pF
b2
thermal via
b2
e
e
MIE L2
MID L2
E3
D3
10kΩ
VIN1 1kΩ
VIN2
VIN3
VCC
VO1
VO2 50kΩ
1kΩ
1kΩ
VO3
●Operation Notes
1. Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as
fuses.
2. Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.
3. Output pin
In the event that load containing a large inductance component is connected to the output terminal, and generation of
back-EMF at the start-up and when output is turned OFF is assumed, it is requested to insert a protection diode.
4. GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
5. Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
8. ASO
When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.
9. Thermal shutdown circuit
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed
only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not
continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is
assumed.
TSD on temperature [°C] (typ.) Hysteresis temperature [°C] (typ.)
BD3508EKN 175 15
10. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.
OUTPUT PIN
(Example)
11. Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
12. Ground Wiring Pattern
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing
a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations
caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND
wiring pattern of any external components, either.
● Heat Dissipation Characteristics
◎HQFN20V
(1) IC unit
θj-a=250℃/W
(2) Substrate (Bottom surface copper foil area: none)
θj-a=166.7℃/W
(3) Substrate (Bottom surface copper foil area: 60mm×
60mm…1 layer)
θj-a=71.4℃/W
(4) Substrate (Bottom surface copper foil area: 60mm×
60mm…2 layers)
θj-a=62.5℃/W
Power Dissipation [Pd]
[W]
0 25 75 100 125 150 50
[℃]
Ambient Temperature [Ta]
1.0
0.5
0
2.0
2.5
1.5
(1) 0.5W
(2) 0.75W
(3) 1.75W
(4) 2.0W
Resistor Transistor (NPN)
N
N N P+ P
+
P
P substrate
GND
Parasitic element
Pin A
N
N P+ P+
P
P substrate
GND
Parasitic element
Pin B C B
E
N
GND
Pin A
P
aras
iti
c
element
Pin B
Other adjacent elements
E
B C
GND
P
aras
iti
c
element
● Type Designations (Ordering Information)
● Package specification
B D 35 0 8- E 2E
Product Name Package Type E2 Emboss tape reel opposite draw-out side: 1 pin
・BD3508
・EKN : HQFN20V
K N
Catalog No.08T431A '08.10 ROHM ©
Note: Please order by the number of reels desired
(With reel in left hand, unreeling with the right, the index
[number 1] pin is at the top left)
Packing
Pieces/Reel
Unreeling
Direction
Embossed tape (moisture-proof packing)
2500pcs
E2
Packing Specs
Reel Draw-out side
#1 Pin
1234
1234
1234
1234
1234
HQFN20V
(Unit: mm)
External View
4.2
±
0.1
(1.1)
0.22
±
0.05
4.0
±
0.1
4.0
±
0.1
4.2
±
0.1
20
16
15 11
10
6
5
1
0.05
0.95MAX
0.22
±
0.05
0.05
0.02
+
0.03
−
0.02
(0.5)
3−(0.35)
(0.22)
0.5
(2.1)
(2.1)
0.6
+
0.1
−
0.3
1234
Appendix1-Rev3.0
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Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM
CO.,LTD.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no respon-
sibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or
exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility
whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
appliances and amusement devices).
The Products are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your
use of any Product outside of the prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system
which requires an extremely high level of reliability the failure or malfunction of which may result in a direct
threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment,
aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no
responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended
to be used for any such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under
the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
