LTC3852
1
3852f
TYPICAL APPLICATION
FEATURES DESCRIPTION
Low Input Voltage,
Synchronous Step-Down
DC/DC Controller
The LTC
®
3852 is a constant frequency, current mode
step-down DC/DC controller which can be powered by an
onboard charge pump. Input supplies as low as 2.7V, when
doubled by the charge pump, provide 5V to the LTC3852’s
control logic and gate drives, supporting a wide selection
of logic-level N-channel power MOSFETs.
The constant-frequency current mode architecture allows for
a phase-lockable fi xed frequency of up to 750kHz. The RUN
pin provides a precision enable threshold while the TRACK/SS
pin combines tracking and adjustable soft-start features.
The MODE/PLLIN pin selects among Burst Mode
®
oper-
ation, pulse-skipping mode, and continuous current mode.
Current foldback limits MOSFET power dissipation during
short-circuit conditions. Reverse current and current
foldback functions are disabled during soft-start. A power
good output pin indicates when the output is within ±10%
of its designed set point.
Effi ciency and Power Loss
vs Load Current
APPLICATIONS
n Charge Pump Input Range: 2.7V to 5.5V
n Controller Input Range: 4V to 38V
n Integrated Charge Pump Provides 5V Gate Drive to
Logic Level MOSFETs
n RSENSE or DCR Current Sensing
n ±1.25% Output Voltage Accuracy Over Temperature
n Phase-Lockable Fixed Frequency: 250kHz to 750kHz
n Power Good Output Voltage Monitor
n Adjustable Soft-Start Voltage Ramping
n Current Foldback Disabled During Start-Up
n No Reverse Current During Soft-Start
n Selectable Constant Frequency, Pulse-Skipping, or
Burst Mode Operation
n Output Overvoltage Protection
n Very Low Dropout Operation: 99% Duty Cycle
n Available in a 24-Lead (3mm ¥ 5mm) QFN Package
n General Purpose 3.3V Systems
n Lithium-Ion Powered Devices
n Distributed DC Power Systems
L, LT, LTC, LTM, Linear Technology, Burst Mode and the Linear logo are registered trademarks
and No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 5408150, 5481178,
5705919, 6498466, 6580258, 6611131.
PGO0D
C+
C–
RUN
SHDN
TRACK/SS
ITH
MODE/PLLIN
FREQ/PLLFLTR
VIN1
INTVCC
TG
SW
INTVCC
BG
SENSE+
SENSE–
VFB
VPUMP
VIN2
GND2
GND1
0.1µF
0.1µF
4.7µF
2.1k
LTC3852
22µF
VIN
2.7V TO 5.5V
VOUT
1.2V
20A
3852 TA01
0.36µH
100pF
CHARGE PUMP
2.2µF
1nF
0.1µF
100k
470µF
×2
BOOST
12.1k
40.2k
1%
20k
1%
95.3k
+
ONOFF
High Effi ciency Synchronous Step-Down Converter
LOAD CURRENT (A)
12010
0
EFFICIENCY (%)
POWER LOSS (W)
100
90
80
70
60
50
40
30
20
10
0
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
3852 TA01a
EFFICIENCY
POWER LOSS
LTC3852
2
3852f
ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage (VIN1) .........................6V to –0.3V
Top Side Driver Voltage (BOOST) ...............46V to –0.3V
Switch Voltage (SW) ..................................40V to –0.3V
VPUMP .......................................................5.5V to –0.3V
SHDN, RUN ..................................................6V to –0.3V
VPUMP Short-Circuit Duration .......................... Indefi nite
VIN2 ............................................................40V to –0.3V
INTVCC, (BOOST-SW), RUN, PGOOD ...........6V to –0.3V
INTVCC, Peak Output Current .................................50mA
SENSE+, SENSE– ..........................................6V to –0.3V
MODE/PLLIN, TRACK/SS .....................INTVCC to –0.3V
FREQ/PLLFLTR .....................................INTVCC to –0.3V
ITH, VFB ........................................................3V to –0.3V
Operating Junction Temperature (Note 2) ............. 125°C
Storage Temperature Range ..................–65°C to 125°C
(Note 1)
TOP VIEW
UDD PACKAGE
24-LEAD
(
3mm s 5mm
)
PLASTIC QFN
SENSE–
SENSE+
PGOOD
GND2
BG
NC
C+
C–
FREQ/PLLFLTR
MODE/PLLIN
SW
TG
BOOST
VIN2
INTVCC
VPUMP
NC
SHDN
GND1
VIN1
VFB
ITH
TRACK/SS
RUN
6
5
4
3
2
1
7
8
15
16
17
18
19
20
14
13
9101112
24 23 22 21
25
GND
TJMAX = 125°C, qJA = 38°C/W
EXPOSED PAD (PIN 25) IS GND, MUST BE SOLDERED TO PCB
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3852EUDD#PBF LTC3852EUDD#TRPBF LFRJ 24-Lead (3mm ¥ 5mm) Plastic QFN –40°C to 125°C
LTC3852IUDD#PBF LTC3852IUDD#TRPBF LFRJ 24-Lead (3mm ¥ 5mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi
cations, go to: http://www.linear.com/tapeandreel/
LTC3852
3
3852f
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop (Step-Down Regulator)
VIN2 Controller Input Voltage Range l438V
VFB Regulated Feedback Voltage (Note 3); ITH Voltage = 1.2V l0.790 0.800 0.810 V
IFB Feedback Current (Note 3) –10 –50 nA
VREFLNREG Reference Voltage Line Regulation (Notes 3, 9); VIN2 = 6V to 38V 0.002 0.02 %/V
VLOADREG Output Voltage Load Regulation (Note 3)
Measured in Servo Loop;
DITH Voltage = 1.2V to 0.7V
l0.01 0.1 %
Measured in Servo Loop;
DITH Voltage = 1.2V to 1.6V
l–0.01 –0.1 %
gmTransconductance Amplifi er gm(Note 3); ITH = 1.2V;
Sink/Source 5µA
2 mmho
IQ(VIN2) Controller Input DC Supply Current (Note 4) VFB = 0.9V
(RUN = 3.3V)
1.4 mA
Shutdown Supply Current RUN = 0V 25 50 µA
IQ(VIN1) Total Input DC Supply Current (Notes 4, 7) VFB = 0.9V
(RUN = SHDN = 3.3V)
7mA
Shutdown Supply Current (Note 7) RUN = SHDN = 0V 5 µA
UVLO Undervoltage Lockout INTVCC Ramping Down 3.25 V
Undervoltage Hysteresis 0.4 V
VOVL Feedback Overvoltage Lockout Measured at VFB l0.86 0.88 0.90 V
ISENSE SENSE Pins Current –2.0 2.0 µA
ITRACK/SS Soft-Start Charge Current VTRACK/SS = 0V 0.5 1 2 µA
VRUN RUN Pin On Threshold VRUN Rising l1.1 1.22 1.35 V
VRUN(HYS) RUN Pin On Hysteresis 130 mV
VSENSE(MAX) Maximum Current Sense Threshold VFB = 0.7V, VSENSE– = 3.3V l40 53 68 mV
TG RUP TG Driver Pull-Up On-Resistance TG High 2.2
TG RDOWN TG Driver Pull-Down On-Resistance TG Low 1.2
BG RUP BG Driver Pull-Up On-Resistance BG High 2.1
BG RDOWN BG Driver Pull-Down On-Resistance BG Low 1.1
TG tr
TG tf
Top Gate Rise Time
Top Gate Fall Time
CLOAD = 3300pF (Note 5) 25
25
ns
ns
BG tr
BG tf
Bottom Gate Rise Time
Bottom Gate Fall Time
CLOAD = 3300pF (Note 5) 25
25
ns
ns
TG/BG t1D Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
CLOAD = 3300pF (Note 5) 30 ns
BG/TG t1D Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
CLOAD = 3300pF (Note 5) 30 ns
tON(MIN) Minimum On-Time (Note 6) 90 ns
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C (Note 2), VIN1 = 3.3V, VIN2 = 15V, VRUN = 3.3V, SHDN = 0V,
MODE/PLLIN = 0V unless otherwise noted.
LTC3852
4
3852f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Oscillator and Phase-Locked Loop (Step-Down Regulator)
fNOM1 Nominal Frequency RFREQ = 60k 460 500 540 kHz
fLOW1 Lowest Frequency RFREQ = 160k 205 235 265 kHz
fHIGH1 Highest Frequency RFREQ = 36k 690 750 810 kHz
fNOM2 Nominal Frequency RFREQ = 60k (Note 7) 460 500 540 kHz
fLOW2 Lowest Frequency RFREQ = 160k (Note 7) 205 235 265 kHz
fHIGH2 Highest Frequency RFREQ = 36k (Note 7) 690 750 810 kHz
fMODE MODE/PLLIN Minimum Input Frequency
MODE/PLLIN Maximum Input Frequency
MODE/PLLIN = External Clock 250
750
kHz
kHz
RMODE/PLLIN MODE/PLLIN Input Resistance 100 k
IFREQ Phase Detector Output Current
Sinking Capability
Sourcing Capability
fMODE > fOSC
fMODE < fOSC
–90
75
µA
µA
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA
VPG PGOOD Trip Level VFB with Respect to Regulated Voltage
VFB Ramping Negative
VFB Ramping Positive
–12
8
–10
10
–8
12
%
%
VPUMP Charge Pump Supply (VIN1 = 3.3V; VSHDN = 3.3V, VRUN = 0); CVIN1 = 4.7μF, CFLY = 2.2μF, CVPUMP = 4.7μF
VIN1 Input Voltage Range 2.7 5.5 V
VPUMP Charge Pump Doubler Output Voltage CFLY = 2.2µF
2.7V < VIN1 < 5.5V; IVPUMP = 1mA l4.8 5.05 5.3 V
ISHDN Shutdown Pin Current SHDN = 0V; VPUMP = 0V 1 µA
VRIPPLE Output Ripple at VPUMP IVPUMP = 50mA (Note 10) 20 mVP-P
fPUMP Charge Pump Frequency 0.6 1.2 1.8 MHz
VIH SHDN Input Threshold l1.3 V
VIL SHDN Input Threshold l0.4 V
IIH SHDN Input Current –1 1 µA
IIL SHDN Input Current –1 1 µA
ROL Effective Open-Loop Output Resistance
(Note 8)
VIN1 = 2.7V, VPUMP = 4.5V 6
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C (Note 2), VIN1 = 3.3V, VIN2 = 15V, VRUN = 3.3V, SHDN = 0V,
MODE/PLLIN = 0V unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: The LTC3852 is tested under pulsed load conditions such that
TJ ≈ TA. The LTC3852E is guaranteed to meet specifi cations from
0°C to 85°C junction temperature. Specifi cations over the –40°C to
125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC3852I is guaranteed over the –40°C to 125°C operating junction
temperature range. TJ is calculated from the ambient temperature, TA and
power dissipation PD according to the following formula:
T
J = TA + (PD • 38°C/W)
Note 3: The LTC3852 is tested in a feedback loop that servos VITH to a
specifi ed voltage and measures the resultant VFB.
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications information.
Note 5: Rise and fall times are measured using 10% and 90% levels. Delay
times are measured using 50% levels. Rise and fall times are assured by
design, characterization and correlation with statistical process controls.
Note 6: The minimum on-time condition is specifi ed for an inductor
peak-to-peak ripple current equal to 40% of IMAX (see Minimum On-Time
Considerations in the Applications Information Section).
Note 7: VIN1 = 3.3V; Connect VPUMP, VIN2 and INTVCC together.
Note 8: ROL = (2VIN - VOUT)/IOUT
Note 9: VIN2 swept while not connected to VPUMP or INTVCC.
Note 10: Guaranteed by design, not tested in production.
LTC3852
5
3852f
TYPICAL PERFORMANCE CHARACTERISTICS
Load Step
Load Step
(Burst Mode Operation)
Load Step
(Forced Continuous Mode)
Load Step
(Pulse-Skipping Mode) Inductor Current at Light Load
Start-Up with Prebiased Output
at 0.5V
Effi ciency vs Output Current
and Mode
LOAD CURRENT (A)
0.01
40
EFFICIENCY(%)
60
80
0.1 1 10 100
3852 G02
20
0
100
CCM
PULSE-SKIPPING
Burst Mode OPERATION
FIGURE 16 CIRCUIT
ILOAD
10A/DIV
1A TO 12A
VOUT
100mV/DIV
AC-COUPLED
IL
10A/DIV
20µs/DIVVOUT = 1.2V
VIN1 = 3.3V
FIGURE 17 CIRCUIT
3852 G05
ILOAD
10A/DIV
5A TO 15A
VOUT
100mV/DIV
AC-COUPLED
IL
10A/DIV
50µs/DIV 3852 G04
VOUT = 1.5V
VIN1 = 3.3V
FIGURE 16 CIRCUIT
ILOAD
10A/DIV
1A TO 12A
VOUT
100mV/DIV
AC-
COUPLED
IL
10A/DIV
20µs/DIVVOUT = 1.2V
VIN1 = 3.3V
FIGURE 17 CIRCUIT
3852 G06
ILOAD
10A/DIV
1A TO 12A
VOUT
100mV/DIV
AC-
COUPLED
IL
10A/DIV
20µs/DIVVOUT = 1.2V
VIN1 = 3.3V
FIGURE 17 CIRCUIT
3852 G07
FORCED
CONTINOUS
MODE
5A/DIV
PULSE-
SKIPPING
MODE 5A/DIV
Burst Mode
OPERATION
5A/DIV
1µs/DIVVOUT = 1.5V
VIN2 = 3.3V
ILOAD = 500mA
FIGURE 17 CIRCUIT
3852 G08
VOUT
1V/DIV
VFB
0.5V/DIV
0V
20ms/DIV 3852 G09
TRACK/SS
0.5V/DIV
FIGURE 16 CIRCUIT
Coincident Tracking with Master
Supply
Ratiometric Tracking with Master
Supply
VMASTER
0.5V/DIV
VOUT
2A LOAD
0.5V/DIV
100ms/DIV 3852 G10
FIGURE 16 CIRCUIT
0V
VMASTER
0.5V/DIV
VOUT
2A LOAD
0.5V/DIV
10ms/DIV 3852 G11
FIGURE 16 CIRCUIT
0V
LTC3852
6
3852f
TYPICAL PERFORMANCE CHARACTERISTICS
Controller Maximum Current
Sense Threshold
vs Common Mode Voltage
Controller Maximum Peak Current
Sense Threshold vs ITH Voltage
Controller Burst Mode Peak
Current Sense Threshold
vs ITH Voltage
Controller Maximum Current
Sense Threshold vs Duty Cycle
Controller Maximum Current
Sense Threshold vs Feedback
Voltage (Current Foldback)
Controller Input DC Supply
Current vs Input Voltage (VIN2)
Controller TRACK/SS Pull-Up
Current vs Temperature
INPUT VOLTAGE (V)
4
SUPPLY CURRENT (mA)
12 20 24 40
3852 G12
816 28 32 36
3.0
2.5
2.0
1.5
1.0
0.5
0
VSENSE COMMON MODE VOLTAGE (V)
0
0
VSENSE THRESHOLD (mV)
3 3.5 4 4.5
90
80
70
60
50
40
30
20
10
3852 G14
0.5 1 1.5 2 2.5 5
VITH (V)
0 0.2 0.4 0.6
VSENSE (mV)
0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
3852 G15
2.4
90
80
70
60
50
40
30
20
10
0
–10
–20
DUTY CYCLE RANGE: 0% TO 100%
VITH (V)
VSENSE (mV)
60
50
40
30
20
10
0
0.8 1.2 1.6 2.0
3852 G16
2.40.60.4 1.0 1.4 1.8 2.2
BURST COMPARATOR FALLING THRESHOLD:
VITH = 0.4V
MAXIMUM
MINIMUM
DUTY CYCLE (%)
0
0
CURRENT SENSE THRESHOLD (mV)
10
30
40
50
40 80 100
90
3852 G17
20
20 60
60
70
80
FEEDBACK VOLTAGE (V)
0
MAXIMUM VSENSE (mV)
0.8
3852 G18
0
0.2 0.4 0.6
0.1 0.3 0.5 0.7
90
80
70
60
50
40
30
20
10
TEMPERATURE (°C)
–50
0.5
TRACK/SS CURRENT (µA)
0.6
0.8
0.9
1.0
1.5
1.2
050 75
3852 G19
0.7
1.3
1.4
1.1
–25 25 100 125
Controller Shutdown (RUN)
Threshold vs Temperature
Controller Regulated Feedback
Voltage vs Temperature
TEMPERATURE (°C)
–50 –25
0.9
RUN PIN VOLTAGE (V)
1.1
1.4
050 75
3852 G20
1.0
1.3
1.2
25 100 125
RUN RISING THRESHOLD (ON)
RUN FALLING THRESHOLD (OFF)
TEMPERATURE (°C)
–50
REGULATED FEEDBACK VOLTAGE (mV)
802
804
806
25 75
3852 G21
800
798
–25 0 50 100 125
796
794
LTC3852
7
3852f
TYPICAL PERFORMANCE CHARACTERISTICS
Controller Oscillator Frequency
vs Temperature
Controller Undervoltage Lockout
Threshold (INTVCC) vs Temperature
Shutdown Input DC Supply Current
vs Input Voltage Controller Only
Shutdown Input DC Supply Current
vs Temperature Controller Only
Input DC Supply Current
vs Temperature Controller Only
TEMPERATURE (°C)
–50
600
700
900
25 75
3852 G22
500
400
–25 0 50 100 125
300
200
800
FREQUENCY (kHz)
RFREQ = 36k
RFREQ = 60k
RFREQ = 160k
TEMPERATURE (°C)
–50 –25
0
INTVCC VOLTAGE AT UVLO THRESHOLD (V)
2
5
050 75
3852 G24
1
4
3
25 100 125
INTVCC RAMPING UP
INTVCC RAMPING DOWN
INPUT VOLTAGE (V)
0 5 10 15 20 25 30 35
SHUTDOWN SUPPLY CURRENT (µA)
20
30
40
3852 G25
10
0
40
15
25
5
35
TEMPERATURE (°C)
–50
SHUTDOWN INPUT DC SUPPLY CURRENT (µA)
35
25
3852 G26
20
10
–25 0 50
5
0
40
30
25
15
75 100 125
TEMPERATURE (°C)
–50
INPUT DC SUPPLY CURRENT (mA)
2.0
2.5
3.0
25 75
3852 G27
1.5
1.0
–25 0 50 100 125
0.5
0
Maximum Current Sense
Threshold vs INTVCC Voltage
INTVCC VOLTAGE(V)
3.2 3.4 3.6
0
CURRENT SENSE THRESHOLD (mV)
10
30
40
50
4.4 4.6 4.8
90
3852 G28
20
3.8 4.0 4.2 5.0
60
70
80
Charge Pump Oscillator
Frequency vs Supply Voltage
SUPPLY VOLTAGE (V)
1.5
FREQUENCY (MHz)
1.50
1.25
1.00
0.75
0.50
0.25
02.0 2.5 3.0 3.5 4.0 4.5
3852 G29
Charge Pump Oscillator
Frequency vs Temperature
TEMPERATURE (oC)
–50
FREQUENCY (MHz)
1.4
1.3
1.2
1.1
1.0
0.9
0.8 –20 10 40 70 100 130
3852 G30
VIN = 4.5V
VIN = 2.4V
Charge Pump SHDN
Threshold
Voltage vs Supply Voltage
THRESHOLD VOLTAGE (V)
0.7
0.8
0.6
0.5
0.9
SUPPLY VOLTAGE (V)
1.5 2.0 2.5 3.0 3.5 4.0 4.5
3852 G31
HIGH-TO-LOW THRESHOLD
LOW-TO-HIGH THRESHOLD
LTC3852
8
3852f
TYPICAL PERFORMANCE CHARACTERISTICS
Charge Pump
SHDN LO-to-HI Threshold
vs Temperature
Charge Pump
SHDN HI-to-LO Threshold
vs Temperature
Charge Pump Short-Circuit
Current vs Supply Voltage
TEMPERATURE (oC)
–50 150
050 100
3852 G32
SHDN THRESHOLD LO-TO-HI (V)
0.7
0.8
0.6
0.5
0.9
VIN = 3.2V
VIN = 2.4V
TEMPERATURE (oC)
–50 150
3852 G33
050 100
SHDN THRESHOLD HI-TO-LO (V)
0.6
0.7
0.5
0.4
0.8
VIN = 3.2V
VIN = 2.4V
SUPPLY VOLTAGE (V)
SHORT-CIRCUIT CURRENT (mA)
350
300
250
200
150
100
50
0
3852 G34
1.5 2.0 2.5 3.0 3.5 4.0 4.5
DEVICE CYCLES
IN AND OUT OF
THERMAL SHUTDOWN
Charge Pump Load Regulation
Charge Pump Output Load
Capability at 4% Below Regulation Charge Pump Effective Open-Loop
Output Resistance vs Temperature
3852 G35
LOAD CURRENT (mA)
0
5.20
5.10
5.00
4.90
4.80
4.70
4.60
4.50
300
100 200 400 500
OUTPUT VOLTAGE (V)
VIN = 4.2V
VIN = 2.7V
VIN = 3.6V
3852 G36
SUPPLY VOLTAGE (V)
2.4
OUTPUT LOAD (mA)
2.9 3.4 3.9
500
450
400
350
300
250
200
150
100
50
0
125°C
85°C
25°C
–45°C
TEMPERATURE
(
oC
)
EFFECTIVE OPEN-LOOP OUTPUT RESISTANCE ()
100
050
VIN = 2.7V
VOUT = 4.5V
–50
8
7
6
5
4
LTC3852
9
3852f
TYPICAL PERFORMANCE CHARACTERISTICS
Charge Pump Output Ripple
Charge Pump Load Transient
Response
1µs/DIVVIN1 = 3.3V
IPUMP = 25mA
CVPUMP = 4.7µF
VPUMP
20mV/DIV
(AC-COUPLED)
3852 G38 10µs/DIVVIN = 3.3V
IPUMP = 25mA TO 50mA STEP
IPUMP
50mA/DIV
VPUMP
50mV/DIV
(AC-COUPLED)
3852 G39
3852 G40
VIN1 (V)
1.8
VPUMP (V)
2.8 3.8 4.8
5.5
5
4.5
4
3.5
3
125°C
85°C
25°C
–45°C
Charge Pump Line Regulation
with 25mA Load
PIN FUNCTIONS
SENSE– (Pin 1): The (–) Input to the Current Sense
Comparators. Kelvin connect to VOUT at the current sense
resistor or, if DCR sensing is used, at the inductor.
SENSE+ (Pin 2): Current Sense Comparator Noninverting
Input. The (+) input to the current comparator is normally
connected to the DCR sensing network or current sensing
resistor.
PGOOD (Pin 3): Power Good Indicator Output. Open drain
logic out that is pulled to ground when the output voltage
exceeds the ±10% regulation window, after the internal
17s power bad mask timer expires.
GND2 (Pin 4): Buck Controller Ground. All small-signal
components and compensation components should be
Kelvin connected to this ground. The (–) terminal of CINTVCC
should be closely connected to this pin. The exposed pad
must be soldered to the PCB to provide electrical contact
for the IC and for optimum thermal performance.
BG (Pin 5): Bottom Gate Driver Output. This pin drives
the gate of the bottom N-channel MOSFET between GND
and INTVCC.
C+ (Pin 7): Flying Capacitor Positive Terminal.
2.7 4.5
3.0 3.3 3.6 3.9 4.2
3852 G41
SUPPLY VOLTAGE (VIN1)
EFFICIENCY (%)
100
90
80
70
60
50
40
30
20
10
0
IPUMP = 1mA
THEORETICAL MAX
IPUMP = 10mA
IPUMP = 100mA
Effi ciency vs Supply Voltage
LTC3852
10
3852f
PIN FUNCTIONS
C– (Pin 8): Flying Capacitor Negative Terminal.
SHDN (Pin 10): Active Low Shutdown Input. A low on
SHDN disables the charge pump. This pin must not be
allowed to fl oat.
GND1 (Pin 11): Charge Pump Ground. The (–) terminals of
CIN and CVPUMP should be closely connected to this pin.
VIN1 (Pin 12): Input Supply Voltage to Charge Pump. VIN1
should be bypassed with a 1F to 4.7F low ESR ceramic
capacitor.
VPUMP (Pin 13): Regulated Output Voltage from Charge
Pump. For best performance, VPUMP should be bypassed
with a low ESR ceramic capacitor providing at least 2.2F
of capacitance as close to the pin as possible.
INTVCC (Pin 14): Gate Drive Supply. The MOSFET drivers
and internal logic are powered from this voltage. Bypass
this pin to GND with a minimum 2.2F low ESR tantalum
or ceramic capacitor, CINTVCC.
VIN2 (Pin 15): Main Supply Pin for Step-Down Controller.
A bypass capacitor should be tied between this pin and
the GND2 pin.
BOOST (Pin 16): Boosted Floating Driver Supply. The
(+) terminal of the booststrap capacitor is connected to
this pin. This pin swings from a diode voltage drop below
INTVCC up to VIN1 + INTVCC.
TG (Pin 17): Top Gate Driver Output. This is the output
of a fl oating driver with a voltage swing equal to INTVCC
superimposed on the switch node voltage.
SW (Pin 18): Switch Node Connection to the Inductor. Vol-
tage swing at this pin is from a diode (external) voltage drop
below ground to the buck regulator power stage VIN.
MODE/PLLIN (Pin 19): Forced Continuous Mode, Burst
Mode operation or Pulse-Skipping Mode Selection Pin
and External Synchronization Input to Phase Detector
Pin. Connect this pin to INTVCC to force continuous
conduction mode of operation. Connect to GND2 to enable
pulse-skipping mode of operation. To select Burst Mode
operation, tie this pin to INTVCC through a resistor no less
than 50k, but no greater than 250k. A clock on the pin
will force the controller into forced continuous mode of
operation and synchronize the internal oscillator.
FREQ/PLLFLTR (Pin 20): The phase-locked loop’s lowpass
fi lter is tied to this pin. Alternatively, a resistor can be
connected between this pin and GND2 to vary the frequency
of the internal oscillator.
RUN (Pin 21): Run Control Input. Forcing the pin below
1.25V shuts down the step-down controller. There is a
2µA pull-up current on this pin.
TRACK/SS (Pin 22): Output Voltage Tracking and Soft-Start
Input. A capacitor to ground at this pin sets the ramp rate
for the output voltage. An internal soft-start current of 1A
charges this capacitor.
ITH (Pin 23): Error Amplifi er Output and Switching
Regulator Compensation Point. The current comparator
input threshold increases with this control voltage.
VFB (Pin 24): Error Amplifi er Feedback Input. This pin
receives the remotely sensed feedback voltage from an
external resistive divider across the output.
GND (Exposed Pad Pin 25): Ground. Must be soldered to
PCB, providing a local ground for the IC.
LTC3852
11
3852f
FUNCTIONAL DIAGRAM
–+
–+
–
+
2µA
SLOPE COMPENSATION
UVLO
OSC S
RQ
5k
RUN
SWITCH
LOGIC
AND
ANTI-
SHOOT
THROUGH
BG
ON
PULSE SKIP
0.8V
OV
1
100k
1.25V0.64V
RC
INTVCC
ITHB
ICMP
CC1
EA
SS
R1
0.88V
R2
GND2
SW
TG CB
VIN2 SLEEP
BOOST
BURSTEN
–
+
–
+
UV
OV
CINTVCC
VOUT
COUT
M2
M1
L1
–
+
IREV
DB
MODE/PLLIN
BUCK REGULATOR
100k
SENSE+
SENSE–
0.8V
REF
TRACK/SS
0.4V
–+
VFB
FREQ/
PLLFLTR
PLL-SYNC
5V REG
MODE/SYNC
DETECT
+
1µA
CSS
+
PGOOD
–+
0.72V
VIN
38V MAX
–
+
VPUMP
RUN
CPUMP
VIN1
VIN1
2.7V to 5.5V
CIN
SHDN
C+
C–
CHARGE
PUMP
1.2MHz
OSCILLATO
CHARGE PUMP
R
GND1
ON/OFF
CFLY
3852 FD
INTVCC
ITH
VIN2
FAULT
LOGIC
RUN
–+
SOFT-START
AND
SWITCH CONTROL
LTC3852
12
3852f
OPERATION
Main Control Loop
The LTC3852 is a constant frequency, current mode
step-down DC/DC controller which can be powered by
an onboard charge pump. Supplies as low as 2.7V, when
doubled by the charge pump, provide 5V to the LTC3852’s
control logic and gate drives, supporting a wide selection
of logic-level MOSFETs.
During normal operation, the controller’s top MOSFET is
turned on when the clock sets the RS latch, and is turned
off when the main current comparator, ICMP
, resets the
RS latch. The peak inductor current at which ICMP resets
the RS latch is controlled by the voltage on the ITH pin,
which is the output of the error ampli fi er EA. The VFB pin
receives the voltage feedback signal, which is compared
to the internal reference voltage by the EA. When the
load current increases, it causes a slight decrease in VFB
relative to the 0.8V reference, which in turn causes the
ITH voltage to increase until the average inductor current
matches the new load current. After the top MOSFET has
turned off, the bottom MOSFET is turned on until either
the inductor current starts to reverse, as indicated by the
reverse current comparator, IREV, or the beginning of the
next cycle.
The charge pump section uses a switched capacitor doubler
to boost VIN1 to 2 ¥ VIN1, with a regulated maximum of
5V. Regulation is achieved by sensing the output voltage
through an internal resistor divider and modulating the
charge pump output current based on the error signal. A
2-phase nonoverlapping clock activates the charge pump
switches. The fl ying capacitor is charged from VIN1 on
the fi rst phase of the clock. On the second phase of the
clock it is stacked in series with VIN1 and connected to
VPUMP. This sequence of charging and discharging the
fl ying capacitor continues at a free running frequency of
1.2MHz (typ).
Two confi gurations address most LTC3852 applications.
Figure 1a covers the single low input voltage case, typically
3.3V. The input to the charge pump, VIN1, is connected to
the same input voltage as the drain of the top MOSFET.
VPUMP, VIN2 and INTVCC are tied together, so that the
charge pump’s 5V output provides all power to the buck
controller section.
The alternative arrangement in Figure 1b allows the
LTC3852 to step down from as high as 38V, while powering
itself from an available 3.3V bus. The input to the charge
pump, VIN1, is connected to 3.3V instead of the drain of
the top MOSFET. It is not necessary to step the high input
voltage down to 5V through a linear regulator. Logic level
MOSFETs are usable in both cases.
VIN 3.3V
3852 F01a
VIN1
VPUMP
VIN2
INTVCC
TG
BG
Figure 1a
VIN ≤ 38V
3852 F01b
VIN1
VPUMP
VIN2
INTVCC
TG
BG
3.3V
Figure 1b
INTVCC Power
Power for the top and bottom MOSFET drivers and most
other internal circuitry is derived from the INTVCC pin. Peak
current drawn from INTVCC should not exceed 50mA.
The top MOSFET driver is biased from the fl oating boot-
strap capacitor, CB, which normally recharges during each
off cycle through an external diode when the top MOSFET
turns off. If VIN decreases to a voltage close to VOUT, the
loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detec tor detects this
and forces the top MOSFET off for about 1/10 of the clock
period every tenth cycle to allow CB to recharge. However, it
LTC3852
13
3852f
is recommended that there is always a load present during
the drop-out transition to ensure CB is recharged.
Shutdown and Start-Up (RUN, SHDN and TRACK/SS)
The switching regulator section of the LTC3852 can be
shut down using the RUN pin. Pulling this pin below 1.1V
disables the controller and most of the internal circuitry.
Releasing the RUN pin allows an internal 2µA current to
pull up the pin and enable the controller. Alternatively, the
RUN pin may be externally pulled up or driven directly by
logic. Be careful not to exceed the absolute maximum
rating of 6V on this pin.
The start-up of the controller’s output voltage, VOUT
, is
controlled by the voltage on the TRACK/SS pin. When the
voltage on the TRACK/SS pin is less than the 0.8V internal
reference, the LTC3852 regulates the VFB voltage to the
TRACK/SS pin voltage instead of the 0.8V reference. This
allows the TRACK/SS pin to be used to program a soft-start
by connecting an external capacitor from the TRACK/SS
pin to GND. An internal 1µA pull-up current charges this
capacitor, creating a voltage ramp on the TRACK/SS pin.
As the TRACK/SS voltage rises linearly from 0V to 0.8V
(and beyond), the output voltage VOUT rises smoothly from
zero to its fi nal value. Alternatively, the TRACK/SS pin can
be used to cause the start-up of VOUT to “track” another
supply. Typically, this requires connecting to the TRACK/SS
pin an external resistor divider from the other supply to
ground (see the Applica tions Information section). When
the RUN pin is pulled low to disable the controller, or when
INTVCC drops below its undervoltage lockout threshold
of 3.2V, the TRACK/SS pin is pulled low by an internal
MOSFET. When in undervoltage lockout, the controller is
disabled and the external MOSFETs are held off.
The charge pump is separately controlled by SHDN. In
shutdown mode, all charge pump circuitry is turned off and it
draws only leakage current from the VIN1 supply. Furthermore,
VPUMP is disconnected from VIN1. The SHDN pin is a CMOS
input with a threshold voltage of approximately 0.7V. The
charge pump is in shutdown when a logic low is applied to
the SHDN pin. Since the SHDN pin is a very high impedance
CMOS input, it should never be allowed to fl oat. To ensure
that its state is defi ned, it must always be driven with a valid
logic level not exceeding VIN1, even if it is tied to RUN.
OPERATION
Since the output voltage of the charge pump can go above
the input voltage, special circuitry is required to control the
internal logic. Detection logic will draw an input current
of 5µA when in shutdown. However, this current will
be eliminated if the output voltage (VPUMP) is less than
approximately 0.8V.
The charge pump has built-in soft-start circuitry to prevent
excessive current fl ow during start-up. The soft-start is
achieved by charging an internal capacitor with a very weak
current source. The voltage on this capacitor, in turn, slowly
ramps the amount of current available to the output storage
capacitor from zero to a value of 50mA over a period of
approximately 125µs. The soft-start circuit is reset in the
event of a commanded shutdown or thermal shutdown.
Light Load Current Operation (Burst Mode Operation,
Pulse skipping or Continuous Conduction)
The LTC3852 can be enabled for high effi ciency Burst
Mode operation, constant frequency pulse skipping mode
or forced continuous conduction mode. To select forced
continuous operation, tie the MODE/PLLIN pin to INTVCC.
To select pulse skipping mode of operation, fl oat the
MODE/PLLIN pin or tie it to GND2. To select Burst Mode
operation, tie MODE/PLLIN to INTVCC through a resistor
no less than 50k, but no greater than 250k.
When the controller is enabled for Burst Mode operation,
the peak current in the inductor is set to approximately
one-fourth of the maximum sense voltage even though
the voltage on the ITH pin indicates a lower value. If the
average inductor current is higher than the load current,
the error amplifi er, EA, will decrease the voltage on the ITH
pin. When the ITH voltage drops below 0.4V, the internal
sleep signal goes high (enabling sleep mode) and both
external MOSFETs are turned off.
In sleep mode, the load current is supplied by the output
capacitor. As the output voltage decreases, the EA’s output
begins to rise. When the output voltage drops enough, the
sleep signal goes low, and the controller resumes normal
operation by turning on the top external MOSFET on the
next cycle of the internal oscillator. When the controller is
enabled for Burst Mode operation, the inductor current is
not allowed to reverse. The reverse current comparator,
IREV, turns off the bottom external MOSFET just before the
LTC3852
14
3852f
inductor current reaches zero, preventing it from revers-
ing and going negative. Thus, the controller operates in
discontinuous operation. In forced continuous operation,
the inductor current is allowed to reverse at light loads
or under large transient conditions. The peak inductor
cur rent is determined by the voltage on the ITH pin, just
as in normal operation. In this mode the effi ciency at light
loads is lower than in Burst Mode operation. However,
continuous mode has the advantages of lower output
ripple and constant frequency operation.
When the MODE/PLLIN pin is connected to GND2, the
LTC3852 operates in PWM pulse skipping mode at light
loads. At very light loads the current comparator, ICMP
, may
remain tripped for several cycles and force the external top
MOSFET to stay off for the same number of cycles (i.e.,
skipping pulses). The inductor current is not allowed to
reverse (discontinuous operation). This mode, like forced
continuous operation, exhibits low output ripple as well as
low audio noise and reduced RF interference as compared
to Burst Mode operation. It provides higher low current
effi ciency than forced continuous mode, but not as high
as Burst Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ/PLLFLTR and MODE/PLLIN Pins)
The selection of a switching frequency is a trade-off between
effi ciency and component size. Low frequency operation
increases effi ciency by reducing MOSFET switching losses, but
requires larger inductance and/or capacitance to main tain low
output ripple voltage. The switching frequency of the LTC3852’s
controller can be selected using the FREQ/PLLFLTR pin. If
the MODE/PLLIN pin is not being driven by an external clock
source, the FREQ/PLLFLTR pin can be used to program the
controller’s operating frequency from 250kHz to 750kHz.
A phase-locked loop (PLL) is available on the LTC3852
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
controller operates in forced continuous mode of operation
when it is synchronized. A series RC should be connected
between the FREQ/PLLFLTR pin and GND to serve as the
PLL’s loop fi lter.
It is suggested that the external clock be applied before
enabling the controller unless a second resistor is
OPERATION
connected in parallel with the series RC loop fi lter network.
The second resistor prevents low switching frequency
operation if the controller is enabled before the clock.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious con-
ditions that may overvoltage the output of the step-down
controller. In such cases, the top MOSFET is turned off
and the bottom MOSFET is turned on until the overvoltage
condition is cleared.
Power Good (PGOOD) Pin
The PGOOD pin is connected to an open drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when the VFB pin voltage is not within
±10% of the 0.8V reference voltage. The PGOOD pin is
also pulled low when the RUN pin is low (shut down)
or when the LTC3852’s controller is in the soft-start or
tracking phase. When the VFB pin voltage is within the
±10% requirement, the MOSFET is turned off and the
pin is allowed to be pulled up by an external resistor to
a source of up to 6V (abs max). The PGOOD pin will fl ag
power good immediately when the VFB pin is within the
±10% window. However, there is an internal 17µs power
bad mask when VFB goes out of the ±10% window.
Short-Circuit/Thermal Protection
The charge pump has built-in short-circuit current limit as
well as over-temperature protection. During a short-circuit
condition, it will automatically limit VPUMP output current
to approximately 300mA. At higher temperatures, or if the
input voltage is high enough to cause excessive self-heating
of the part, the thermal shutdown circuitry will shut down
the charge pump once the junction temperature exceeds
approximately 160°C. It will enable the charge pump once its
junction temperature drops back to approximately 150°C.
The charge pump will cycle in and out of thermal shutdown
indefi nitely until the short-circuit condition on VPUMP is
removed. The maximum rated junction temperature will
be exceeded when this thermal shutdown protection is
active. Continuous operation above the specifi ed absolute
maximum operating junction temperature may impair
device reliability or permanently damage the device.
LTC3852
15
3852f
The Typical Application on the fi rst page of this data sheet
is a basic LTC3852 application circuit. The LTC3852 can
be confi gured to use either DCR (inductor resistance)
sensing or low value resistor sensing. The choice of the
two current sensing schemes is largely a design trade-off
between cost, power consumption and accuracy. DCR
sensing is popular because it saves expensive current
sensing resis tors and is more power effi cient, especially
in high current applications. However, current sensing
resistors provide the most accurate current limits for the
controller. Other external component selection is driven
by the load require ment, and begins with the selection of
RSENSE (if RSENSE is used) and the inductor value. Next,
the power MOSFETs and Schottky diodes are selected.
Finally, input and output capacitors are selected.
SENSE+ and SENSE– Pins
The SENSE+ and SENSE– pins are the inputs to the current
comparators. The common mode input voltage range of
the current comparators is 0V to 5.5V. Both SENSE pins
are high impedance inputs with small base currents of
less than 1A. When the SENSE pins ramp up from 0V
to 1.4V, the small base currents fl ow out of the SENSE
pins. When the SENSE pins ramp down from 5V to 1.1V,
the small base currents fl ow into the SENSE pins. The
high impedance inputs to the current comparators allow
accurate DCR sensing. However, care must be taken not
to fl oat these pins during normal operation.
Low Value Resistors Current Sensing
A typical sensing circuit using a discrete resistor is shown
in Figure 2. RSENSE is chosen based on the required
output current. For simplicity, the charge pump section
is omitted.
The current comparator has a maximum threshold,
VMAX = 50mV. The current comparator threshold sets the
maximum peak of the inductor current, yielding a maximum
average output current, IMAX, equal to the peak value less
APPLICATIONS INFORMATION
half the peak-to-peak ripple current, DIL. Allowing a margin
of 20% for variations in the IC and external component
values yields:
RSENSE =0.8•VMAX
IMAX +ΔIL/2
VIN2 VIN
INTVCC
BOOST
TG
SW
BG
GND2
FILTER COMPONENTS
PLACED NEAR SENSE PINS
SENSE+
SENSE–
LTC3852
VOUT
RSENSE
3852 F02
Inductor DCR Sensing
For applications requiring the highest possible effi ciency,
the LTC3852 is capable of sensing the voltage drop across
the inductor DCR, as shown in Figure 3. The DCR of the
inductor represents the small amount of DC winding
resis tance of the copper, which can be less than 1mW for
today’s low value, high current inductors. If the external
R1||R2 • C1 time constant is chosen to be exactly equal
to the L/DCR time constant, the voltage drop across the
external capacitor is equal to the voltage drop across the
inductor DCR multiplied by R2/(R1 + R2). Therefore, R2
may be used to scale the voltage across the sense terminals
when the DCR is greater than the target sense resistance.
Check the manufacturer’s data sheet for specifi cations
regarding the inductor DCR, in order to properly dimension
the external fi lter components. The DCR of the inductor
can also be measured using a good RLC meter.
Figure 2. Using a Resistor to Sense Current with the LTC3852
LTC3852
16
3852f
APPLICATIONS INFORMATION
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant
frequency architectures by preventing sub-harmonic
oscillations at high duty cycles. It is accomplished inter nally
by adding a compensating ramp to the inductor current
signal. Normally, this results in a reduction of maximum
inductor peak cur rent for duty cycles >40%. However, the
LTC3852 uses a novel scheme that allows the maximum
inductor peak current to remain unaffected throughout
all duty cycles.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use of
smaller inductor and capacitor values. A higher frequency
generally results in lower effi ciency because of MOSFET
gate charge losses. In addition to this basic trade-off, the
effect of inductor value on ripple current and low current
operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current DIL decreases with higher
inductance or frequency and increases with higher VIN:
ΔIL=1
f•LVOUT 1– VOUT
VIN
⎛
⎝
⎜⎞
⎠
⎟
VIN2 VIN
INTVCC
BOOST
TG
SW
BG
GND2
INDUCTOR
DCRL
SENSE+
SENSE–
LTC3852 VOUT
3852 F03
R1**
R2
*PLACE C1 NEAR SENSE+, SENSE– PINS
**PLACE R1 NEAR INDUCTOR
C1*
R1||R2 • C1 =
RSENSE(EQ) = DCR
L
DCR
R2
R1 + R2
Accepting larger values of DIL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is DIL = 0.3(IMAX). The maximum
DIL occurs at the maximum input voltage.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
≈10% of the current limit determined by RSENSE. Lower
inductor values (higher DIL) will cause this to occur at
lower load currents, which can cause a dip in effi ciency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to increase.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High effi ciency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
fi xed inductor value, but it is very dependent on inductance
selected. As inductance increases, core losses go down.
Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode (Optional)
Selection
Two external power MOSFETs must be selected for the
LTC3852 controller: one N-channel MOSFET for the top
(main) switch, and one N-channel MOSFET for the bottom
(synchronous) switch.
Figure 3. Current Mode Control Using the Inductor DCR
LTC3852
17
3852f
APPLICATIONS INFORMATION
The peak-to-peak drive levels are set by the VPUMP voltage.
This voltage is typically 5V when the charge pump is active.
Consequently, logic-level threshold MOSFETs may be used
in most applications.
Selection criteria for the power MOSFETs include the on-
resistance, RDS(ON), Miller capacitance, CMILLER, input
voltage and maximum output current. Miller capacitance,
CMILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. CMILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
fl at divided by the specifi ed change in VDS. This result is
then multiplied by the ratio of the application applied VDS
to the gate charge curve specifi ed VDS. When the IC is
operating in continuous mode, the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle = VOUT
VIN
Synchronous Switch Duty Cycle = VIN –V
OUT
VIN
The MOSFET power dissipations at maximum output
current are given by:
P
MAIN =VOUT
VIN
IMAX
()
21+δ
()
RDS(ON) +
VIN
()
2IMAX
2
⎛
⎝
⎜⎞
⎠
⎟RDR
()
CMILLER
()
•
1
VINTVCC –V
TH(MIN)
+1
VTH(MIN)
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥(f)
PSYNC =VIN –V
OUT
VIN
IMAX
()
21+δ
()
RDS(ON)
where d is the temperature dependency of RDS(ON) and
RDR (approximately 2W) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. VTH(MIN) is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I2R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For VIN < 20V,
the high current effi ciency generally improves with larger
MOSFETs, while for VIN > 20V, the transition losses rapidly
increase to the point that the use of a higher RDS(ON) device
with lower CMILLER actually provides higher effi ciency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
short-circuit when the synchronous switch is on close to
100% of the period.
The term (1 + d) is generally given for a MOSFET in the
form of a normalized RDS(ON) vs Temperature curve, but
d = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diode conducts during the dead time
between the conduction of the two power MOSFETs. This
prevents the body diode of the bottom MOSFET from turning
on, storing charge during the dead time and requiring a
reverse recovery period that could cost as much as 2%
in effi ciency at high VIN. A 1A to 3A Schottky is generally
a good size due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance.
Soft-Start and Tracking
The LTC3852 has the ability to either soft-start by itself
with a capacitor or track the output of another channel
or external supply. When the LTC3852 is confi gured to
soft-start by itself, a capacitor should be connected to
the TRACK/SS pin. The LTC3852 is in the shutdown state
if the RUN pin voltage is below 1.25V. TRACK/SS pin is
actively pulled to ground in this shutdown state.
Once the RUN pin voltage is above 1.25V, the LTC3852 powers
up. A soft-start current of 1A then starts to charge its soft-
start capacitor. Note that soft-start or tracking is achieved
not by limiting the maximum output current of the controller
but by controlling the output ramp voltage according to the
ramp rate on the TRACK/SS pin. Current foldback is disabled
during this phase to ensure smooth soft-start or tracking. The
soft-start or tracking range is 0V to 0.8V on the TRACK/SS
pin. The total soft-start time can be calculated as:
tSOFT-START =0.8•CSS
1.0µA
LTC3852
18
3852f
Regardless of the mode selected by the MODE/PLLIN pin,
the regulator will always start in pulse skipping mode up
to TRACK/SS = 0.64V. Between TRACK/SS = 0.64V and
0.72V, it will operate in forced continuous mode and revert
to the selected mode once TRACK/SS > 0.72V. The output
ripple is minimized during the 80mV forced continuous
mode window.
When the regulator is confi gured to track another supply,
the feedback voltage of the other supply is duplicated
by a resistor divider and applied to the TRACK/SS pin.
Therefore, the voltage ramp rate on this pin is determined
by the ramp rate of the other supply’s voltage. Note that
the small soft-start capacitor charging current is always
fl owing, producing a small offset error. To minimize this
error, one can select the tracking resistive divider value to
be small enough to make this error negligible.
In order to track down another supply after the soft-start
phase expires, the LTC3852 must be confi gured for forced
continuous operation by connecting MODE/PLLIN to
INTVCC.
Output Voltage Tracking
The LTC3852 allows the user to program how its output
ramps up and down by means of the TRACK/SS pins.
Through this pin, the output can be set up to either
coincidentally or ratiometrically track with another supply’s
output, as shown in Figure 4. In the following discussions,
VMASTER refers to a master supply and VOUT refers to the
LTC3852’s output as a slave supply. To implement the
coincident tracking in Figure 4a, connect a resistor divider
to VMASTER and connect its midpoint to the TRACK/SS pin
of the LTC3852. The ratio of this divider should be selected
the same as that of the LTC3852’s feedback divider as
shown in Figure 5a. In this tracking mode, VMASTER must
be higher than VOUT. To implement ratiometric tracking,
the ratio of the resistor divider connected to VMASTER is
determined by:
VOUT
VMASTER
=R2
R4
R3 +R4
R1+R2
⎛
⎝
⎜⎞
⎠
⎟
APPLICATIONS INFORMATION
So which mode should be programmed? While either
mode in Figure 5 satisfi es most practical applications,
the coincident mode offers better output regulation. This
concept can be better understood with the help of Figure 6.
At the input stage of the LTC3852’s error amplifi er, two
common anode diodes are used to clamp the equivalent
reference voltage and an additional diode is used to match
the shifted common mode voltage. The top two current
sources are of the same amplitude. In the coincident
mode, the TRACK/SS voltage is substantially higher than
0.8V at steady-state and effectively turns off D1. D2 and
D3 will therefore conduct the same current and offer
tight matching between VFB and the internal precision
0.8V reference. In the ratiometric mode, however, TRACK/SS
equals 0.8V at steady-state. D1 will divert part of the bias
current to make VFB slightly lower than 0.8V.
Figure 4. Two Different Modes of Output Voltage Tracking
(
4a
)
Coincident Trackin
g
TIME
VMASTER
VOUT
OUTPUT VOLTAGE
3852 F04a
(4b) Ratiometric Tracking
VMASTER
VOUT
TIME 3852 F04b
OUTPUT VOLTAGE
LTC3852
19
3852f
APPLICATIONS INFORMATION
Although this error is minimized by the exponential I-V
characteristic of the diode, it does impose a fi nite amount
of output voltage deviation. Furthermore, when the master
supply’s output experiences dynamic excursion (under
load transient, for example), the slave channel output will
be affected as well. For better output regulation, use the
coincident tracking mode instead of ratiometric.
Topside MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor CB connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFET. Capacitor CB in the Functional Diagram is charged
though external diode DB from INTVCC when the SW pin
is low. When the topside MOSFET is to be turned on, the
driver places the CB voltage across the gate source of the
MOSFET. This enhances the MOSFET and turns on the
topside switch. The switch node voltage, SW, rises to VIN
(5a) Coincident Tracking Setup
R3
VOUT
R4
TO
VFB
PIN
R3
VMASTER
R4
TO
TRACK/SS
PIN
3852 F05a
(5b) Ratiometric Tracking Setup
R1 R3
VOUT
R4R2
3852 F05b
TO
VFB
PIN
TO
TRACK/SS
PIN
VMASTER
Figure 5. Setup for Coincident and Ratiometric Tracking
–
+
II
D1
TRACK/SS
0.8V
VFB
D2
D3
3852 F06
EA
Figure 6. Equivalent Input Circuit of Error Amplifi er
and the BOOST pin follows. With the topside MOSFET on,
the boost voltage is above the input supply:
V
BOOST = VIN + VINTVCC
The value of the boost capacitor CB needs to be 100 times
that of the total input capa citance of the topside MOSFET.
The reverse break down of the external Schottky diode
must be greater than VIN(MAX).
Undervoltage Lockout
The LTC3852 has two functions that help protect the
controller in case of undervoltage conditions. A precision
UVLO comparator constantly monitors the INTVCC voltage
to ensure that an adequate gate-drive voltage is present. It
locks out switching action when INTVCC falls below 3.25V.
To prevent oscillation when there is a disturbance on the
INTVCC, the UVLO comparator has 400mV of preci sion
hysteresis.
Another way to detect an undervoltage condition is to
monitor the VIN supply. Because the RUN pin has a precision
turn-on reference of 1.25V, one can use a resistor divider
to VIN to turn on the IC when VIN is high enough.
CIN Selection
In continuous mode, the source current of the top N-channel
MOSFET is a square wave of duty cycle VOUT/VIN. To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
IRMS ≅IO(MAX)
VOUT
VIN
VIN
VOUT
–1
⎛
⎝
⎜⎞
⎠
⎟
1/ 2
This formula has a maximum at VIN = 2VOUT, where IRMS =
IO(MAX)/2. This simple worst-case condition is com monly
used for design because even signifi cant deviations do not
offer much relief. Note that capacitor manufacturers’ ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to meet
size or height requirements in the design. Always consult
the manufacturer if there is any question.
LTC3852
20
3852f
COUT Selection
The selection of COUT is primarily determined by the effec-
tive series resistance, ESR, to minimize voltage ripple. The
output ripple, DVOUT, in continuous mode is determined by:
ΔVOUT ≅ΔILESR +1
8fCOUT
⎛
⎝
⎜⎞
⎠
⎟
where f = operating frequency, COUT = output capaci tance
and DIL = ripple current in the inductor. The output ripple
is highest at maximum input voltage since DIL increases
with input voltage. Typically, once the ESR requirement
for COUT has been met, the RMS current rating gener-
ally far exceeds the IRIPPLE(P-P) requirement. With DIL =
0.3IOUT(MAX) and allowing 2/3 of the ripple to be due to
ESR, the output ripple will be less than 50mV at maximum
VIN and:
COUT Required ESR < 2.2RSENSE
COUT >1
8fRSENSE
The fi rst condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran tees
that the output capacitance does not signifi cantly discharge
during the operating frequency period due to ripple current.
The choice of using smaller output capaci tance increases
the ripple voltage due to the discharging term but can be
compensated for by using capacitors of very low ESR to
maintain the ripple voltage at or below 50mV. The ITH pin
OPTI-LOOP compensation compo nents can be optimized
to provide stable, high perfor mance transient response
regardless of the output capaci tors selected.
The selection of output capacitors for applications with
large load current transients is primarily determined by the
voltage tolerance specifi cations of the load. The resistive
component of the capacitor, ESR, multiplied by the load
current change, plus any output voltage ripple must be
within the voltage tolerance of the load.
The required ESR due to a load current step is:
RESR ≤ΔV
ΔI
APPLICATIONS INFORMATION
where
D
I is the change in current from full load to zero load
(or minimum load) and
D
V is the allowed voltage devia-
tion (not including any droop due to fi nite capacitance).
The amount of capacitance needed is determined by the
maximum energy stored in the inductor. The capacitance
must be suffi cient to absorb the change in inductor
current when a high current to low current transition
occurs. The opposite load current transition is generally
determined by the control loop OPTI-LOOP components,
so make sure not to over compensate and slow down
the response. The minimum capacitance to assure the
inductors’ energy is adequately absorbed is:
COUT >LΔI
()
2
2ΔV
()
VOUT
where DI is the change in load current.
Manufacturers such as Nichicon, United Chemi-Con and
Sanyo can be considered for high performance through-
hole capacitors. The OS-CON semiconductor electrolyte
capacitor available from Sanyo has the lowest (ESR)(size)
product of any aluminum electrolytic at a somewhat
higher price. An additional ceramic capacitor in parallel
with OS-CON capacitors is recommended to reduce the
inductance effects.
In surface mount applications, ESR, RMS current han dling
and load step specifi cations may require multiple capacitors
in parallel. Aluminum electrolytic, dry tantalum and
special polymer capacitors are available in surface mount
packages. Special polymer surface mount capaci tors offer
very low ESR but have much lower capacitive density per
unit volume than other capacitor types. These capacitors
offer a very cost-effective output capacitor solution and are
an ideal choice when combined with a controller having
high loop bandwidth. Tantalum capaci tors offer the highest
capacitance density and are often used as output capacitors
for switching regulators having controlled soft-start.
Several excellent surge-tested choices are the AVX TPS,
AVX TPSV or the KEMET T510 series of surface mount
tantalums, available in case heights rang ing from 1.5mm
to 4.1mm. Aluminum electrolytic capaci tors can be used
in cost-driven applications, provided that consideration
LTC3852
21
3852f
APPLICATIONS INFORMATION
is given to ripple current ratings, tempera ture and long-
term reliability. A typical application will require several
to many aluminum electrolytic capacitors in parallel. A
combination of the above mentioned capaci tors will often
result in maximizing performance and minimizing overall
cost. Other capacitor types include Nichicon PL series, NEC
Neocap, Panasonic SP and Sprague 595D series. Consult
manufacturers for other specifi c recommendations.
Like all components, capacitors are not ideal. Each
ca pacitor has its own benefi ts and limitations. Combina-
tions of different capacitor types have proven to be a very
cost effective solution. Remember also to include high
frequency decoupling capacitors. They should be placed
as close as possible to the power pins of the load. Any
inductance present in the circuit board traces negates
their usefulness.
Setting Output Voltage
The LTC3852 output voltage is set by an external feedback
resistive divider carefully placed across the output,
as shown in Figure 7. The regulated output volt age is
determined by:
VOUT =0.8V1+RB
RA
⎛
⎝
⎜⎞
⎠
⎟
To improve the transient response, a feed-forward ca-
pacitor, CFF , may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
LTC3852
VFB
VOUT
RBCFF
RA
3852 F07
Figure 7. Settling Output Voltage
Fault Conditions: Current Limit and Current Foldback
The LTC3852 includes current foldback to help limit load
current when the output is shorted to ground. If the output
falls below 40% of its nominal output level, the maximum
sense voltage is progressively lowered from its maximum
programmed value to about 25% of the that value. Foldback
current limiting is disabled during soft-start or tracking.
Under short-circuit conditions with very low duty cycles,
the LTC3852 will begin cycle skipping in order to limit the
short-circuit current. In this situation the bottom MOSFET
will be dissipating most of the power but less than in normal
operation. The short-circuit ripple current is determined
by the minimum on-time tON(MIN) of the LTC3852 (≈90ns),
the input voltage and inductor value:
ΔIL(SC) =tON(MIN) •VIN
L
The resulting short-circuit current is:
ISC =1/4MaxVSENSE
RSENSE
–1
2ΔIL(SC)
Programming Switching Frequency
To set the switching frequency of the LTC3852, connect
a resistor, RFREQ, between FREQ/PLLFLTR and GND. The
relationship between the oscillator frequency and RFREQ
is shown in Figure 8. A 0.1µF bypass capacitor should be
connected in parallel with RFREQ.
RFREQ (k)
20
250
OSCILLATOR FREQUENCY (kHz)
300
400
450
500
750
600
60 100 120
3852 F08
350
650
700
550
40 80 140 160
Figure 8. Relationship Between Oscillator Frequency
and Resistor Connected Between FREQ/PLLFLTR and GND
LTC3852
22
3852f
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
The LTC3852 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the top MOSFET to
be locked to the rising edge of an external clock signal
applied to the MODE/PLLIN pin. This phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen tary
current sources that charge or discharge the external fi lter
network connected to the FREQ/PLLFLTR pin. Note that
the LTC3852 can only be synchronized to an external clock
whose frequency is within range of the LTC3852’s internal
VCO.This is guaranteed to be between 250kHz and 750kHz.
A simplifi ed block diagram is shown in Figure 9.
DIGITAL
PHASE/
FREQUENCY
DETECTOR VCO
2.7V RLP
CLP
3852 F09
FREQ/PLLFLTR
EXTERNAL
OSCILLATOR
MODE/
PLLIN
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC , then current is sunk con-
tinuously from the phase detector output, pulling down
the FREQ/PLLFLTR pin. When the external clock frequency
is less than fOSC , current is sourced continuously, pulling
up the FREQ/PLLFLTR pin. If the external and internal
frequencies are the same but exhibit a phase difference, the
current sources turn on for an amount of time corresponding
to the phase difference. The voltage on the FREQ/PLLFLTR
pin is adjusted until the phase and frequency of the internal
and external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and the
fi lter capacitor CLP holds the voltage.
Figure 9. Phase-Locked Loop Block Diagram
The loop fi lter components, CLP and RLP , smooth out
the current pulses from the phase detector and provide
a stable input to the voltage-controlled oscillator. The
fi lter components CLP and RLP determine how fast the
loop acquires lock. Typically RLP is 1k to 10k and CLP is
2200pF to 0.01F.
When the external oscillator is active before the LTC3852
is enabled, the internal oscillator frequency will track the
external oscillator frequency as described in the preceding
paragraphs. In situations where the LTC3852 is enabled
before the external oscillator is active, a low free-running
oscillator frequency of approximately 50kHz will result. It is
possible to increase the free-running, pre-synchronization
frequency by adding a second resistor in parallel with
RLP and CLP
. The second resistor will also cause a phase
difference between the internal and external oscillator
signals. The magnitude of the phase difference is inversely
proportional to the value of the second resistor.
The external clock (on MODE/PLLIN pin) input high
threshold is nominally 1.6V, while the input low thres hold
is nominally 1.2V.
Maximum Available Charge Pump Current
For the charge pump, the maximum available output
current and voltage can be calculated from the effective
open-loop output resistance, ROL, and the effective input
voltage, 2VIN1(MIN).
+
–
ROL
IOUT VPUMP
2VIN1
3852 F10
+
–
From Figure 10, the available current is given by:
IPUMP =2V
IN1 –V
PUMP
ROL
The actual current (into VIN2 and INTVCC) should not
exceed 50mA.
Figure 10. Equivalent Open-Loop Circuit
LTC3852
23
3852f
Effective Open Loop Output Resistance (ROL)
The effective open loop output resistance (ROL) of a charge
pump is a very important parameter which determines the
strength of the charge pump. The value of this parameter
depends on many factors such as the oscillator frequency
(fOSC), value of the fl ying capacitor (CFLY), the nonoverlap
time, the internal switch resistances (RS), and the ESR of
the external capacitors. A fi rst order approximation for
ROL is given below:
ROL ≅2R
S
∑+1
fOSC •C
FLY
Typical ROL values as a function of temperature are shown
in Figure 11.
APPLICATIONS INFORMATION
S=1 TO 4
Charge Pump Capacitor Selection
The style and value of capacitors used with the charge
pump determine several important parameters such as
regulator control loop stability, output ripple, charge pump
strength and minimum start-up time.
To reduce noise and ripple, it is recommended that low
ESR (<0.1W) ceramic capacitors be used for both CIN
and CPUMP. These capacitors should be 2.2µF or greater.
Tantalum and aluminum capacitors are not recommended
because of their high ESR.
The value of CPUMP directly controls the amount of
output ripple for a given load current. Increasing the size
of CPUMP will reduce the output ripple at the expense of
3852 F11
TEMPERATURE (oC)
100
050
EFFECTIVE OPEN-LOOP OUTPUT RESISTANCE (7)
VIN = 2.7V
VPUMP = 4.5V
–50
8
7
6
5
4
Figure 11. Typical ROL vs Temperature
higher minimum turn-on time. The peak-to-peak output
ripple of a charge pump is approximately given by the
expression:
VRIPPLE(P−P) ≅IPUMP
2fOSC •C
PUMP
where fOSC is the charge pump frequency (typically 1.2MHz)
and CPUMP is the value of the VPUMP storage capacitor.
Also, the value and style of the CPUMP capacitor can
signifi cantly affect the stability of the charge pump. As
shown in the Functional Diagram, the charge pump
uses a linear control loop to adjust the strength of the
charge pump to match the current required at the output.
The error signal of this loop is stored directly on the
output storage capacitor. This output capacitor also
serves to form the dominant pole of the control loop.
To prevent ringing or instability on the charge pump,
it is important to maintain at least 1µF of capacitance over
all conditions.
Excessive ESR on the CPUMP capacitor can degrade the
loop stability of the charge pump. Its closed loop output
resistance is designed to be 0.5W. For a 50mA load current
change, the output voltage will change by about 25mV. If
the output capacitor has 0.5W or more of ESR, the closed
loop frequency response will cease to roll off in a simple
one-pole fashion and poor load transient response or
instability could result. Ceramic capacitors typically have
exceptional ESR performance and combined with a good
board layout should yield very good stability and load
transient performance.
As the value of CPUMP controls the amount of output ripple,
the value of CIN controls the amount of ripple present at
the input pin (VIN1). The input current to the charge pump
will be relatively constant during the input charging phase
or the output charging phase but will drop to zero during
the nonoverlap times. Since the nonoverlap time is small
(~25ns), these missing notches will result in only a small
perturbation on the input power supply line. Note that a
higher ESR capacitor such as tantalum will have higher
input noise due to the voltage drop in the ESR. Therefore,
ceramic capacitors are again recommended for their
exceptional ESR performance.
LTC3852
24
3852f
Further input noise reduction can be achieved by powering
VIN1 through a very small series inductor as shown in
Figure 12. A 10nH inductor will reject the fast current
notches, thereby presenting a nearly constant current
load to the input power supply. For economy, the 10nH
inductor can be fabricated on the PC board with about
1cm (0.4") of PC board trace.
APPLICATIONS INFORMATION
LTC3852
0.22µF 2.2µF
VIN1
GND1
1cm OF PCB TRACE
10nH
VIN
11
12
3852 F12
Flying Capacitor Selection
Warning: A polarized capacitor such as tantalum or
aluminum should never be used for the fl ying capacitor
since its voltage can reverse upon start-up of the
charge pump. Low ESR ceramic capacitors should always
be used for the fl ying capacitor.
The fl ying capacitor controls the strength of the charge
pump. In order to achieve the rated output current, it is
necessary to have at least 1µF of capacitance for the fl y ing
capacitor.
Ceramic Capacitors
Ceramic capacitors of different materials lose their capac-
itance with higher temperature and voltage at different rates.
For example, a capacitor made of X5R or X7R material
will retain most of its capacitance from –40°C to 85°C
whereas a Z5U or Y5V style capacitor will lose considerable
capacitance over that range. Z5U and Y5V capacitors
may also have a poor voltage coeffi cient causing them
to lose 60% or more of their capacitance when the rated
voltage is applied. Therefore when comparing different
capacitors, it is often more appropriate to compare the
amount of achievable capacitance for a given case size
rather than discussing the specifi ed capacitance value. For
example, over rated voltage and temperature conditions,
a 1µF 10V Y5V ceramic capacitor in a 0603 case may not
Figure 12. 10nH Inductor Used for
Additional Input Noise Reduction
provide any more capacitance than a 0.22µF 10V X7R
capacitor available in the same 0603 case. In fact, for the
charge pump, these capacitors can be considered roughly
equivalent. The capacitor manufacturer’s data sheet should
be consulted to ensure the desired capacitance at all temp-
eratures and voltages.
Table 1 shows a list of ceramic capacitor manufacturers
and how to contact them:
Table 1.
AVX www.avx.com
Kemet www.kemet.com
Murata www.murata.com
Taiyo Yuden www.t-yuden.com
TDK www.component.tdk.com
Vishay www.vishay.com
Effi ciency Considerations
The percent effi ciency of a switching regulator is equal to
the output power divided by the input power times 100. It
is often useful to analyze the individual loss components
to determine what limits the effi ciency and which change
would produce the biggest improvement. The effi ciency
can be expressed as:
% Effi ciency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, there are fi ve main sources of power loss in
LTC3851 circuits: 1) I2R losses, 2) transition losses in the
top MOSFET, 3) gate charge losses within the controller
due to the input capacitance of the power MOSFETs,
4) the DC bias current of the controller (VIN2), and 5) the
effi ciency of the charge pump.
1. I2R losses are predicted from the DC resistances of the
fuse (if used), top and bottom MOSFET on-resistances,
the inductor DCR and the current sense resistor (if used).
In continuous conduction mode (CCM), the average
output current fl ows through the inductor (L) and sense
resistor (RSENSE), but is “chopped” between the top
and bottom MOSFETs. Since the two MOSFETs rarely
have the same RON, an effective MOSFET resistance
LTC3852
25
3852f
can be computed using the duty cycle (D = VOUT/VIN).
The effective MOSFET DC resistance is therefore:
R
ON(EFF) = D • RON(TOP) + (1-D) • RON(BOT)
The effective MOSFET resistance can then be summed
with the DCR of the inductor and the sense resistor
to obtain the overall series resistance. For example,
consider a DC/DC converter with a 3.3V input voltage
and a 1.2V/15A output. The nominal duty cycle of this
converter is 36% (1.2V/3.3V). For a design with RON(TOP)
= 8m and RON(BOT) = 2m, the effective MOSFET DC
resistance is (0.36) • 0.008 + (1-0.36) • 0.002 = 4.2m.
For an inductor DCR = 1m and a 2m sense resistor,
the total series resistance is 7.2m. For an output
current range of 5A to 15A, the total I2R losses range
from 1% to 9% for a 1.2V output. It is worth noting that
the losses due to the sense resistor at full load (15A)
are 450mW, or 2.5%. If the same application used
a DCR current sensing scheme, the peak effi ciency
would be 2.5% higher, an expensive component would
be eliminated from the bill of materials, and the
solution size would be smaller. The effi ciency varies
as the inverse square of VOUT for the same external
components and output power level. The combined
effects of increasingly lower output voltages and higher
currents required by high performance digital systems
is not doubling but quadrupling the importance of loss
terms in the switching regulator system!
2. Since the LTC3852 was optimized for low supply voltage
applications, the transition losses for the top MOSFET
can normally be neglected. Transition losses for the
top MOSFET only become signifi cant when operating
at high input voltages (typically 15V or greater). This
condition can occur, however, when the input to the
charge pump is not the same voltage as the input to the
DC/DC converter power stage. For example, an auxiliary,
low current 3.3V supply could be connected to the input
of the charge pump (VIN1), while the DC/DC converter
power stage could draw power from a high current 12V
supply. Transition losses for the upper power MOSFET
can be estimated from the following equation:
Transition Loss = (1.7)VDS(MAX)2 • IO(MAX)
• CRSS • fSW
APPLICATIONS INFORMATION
3. The INTVCC current is the sum of the MOSFET driver and
DC bias requirements of the internal circuitry. The gate
drive current results from charging the gate capacitance
of the power MOSFETs. Each time a MOSFET gate is
switched on, a packet of charge QG moves from INTVCC
to the MOSFET gate. The resulting dQ/dt is a current
into INTVCC that is typically much larger than the DC
bias current for the internal control circuitry. In CCM
operation, IGATE = fSW • (QG(TOP) + QG(BOT)), where
QG(TOP) and QG(BOT) are the gate charges of the top
and bottom MOSFETs respectively. These parameters
are listed on most power MOSFET datasheets.
4. The DC bias current for the controller is specifi ed in the
Electrical Characteristics table, and is typically 1.2mA.
This current is almost always much smaller than the
gate charge current associated with the power MOSFETs
in CCM operation.
5. In most LTC3852 applications, the output of the charge
pump will be connected to the VIN2 and INTVCC pins of
the controller. The DC bias current into the controller
VIN2 pin, as well as the gate charge current associated
with the power MOSFETs, will typically be supplied by
the charge pump. Because the charge pump has a fi nite
power effi ciency, the input current will be higher that
the output current when the charge pump is active.
For a 3.3V input application where the output of the
charge pump is 5.1V, this effi ciency is approximately
72%, as shown in the graph in the Typical Performance
Characteristics. As a result, for every 1mA of current
required by the controller, about 1.4mA will be drawn
from the VIN1 pin.
The DC bias current of the charge pump within the LTC3852
is typically only 60µA. For the purposes of power losses, this
bias current is typically 2 orders of magnitude lower than
the gate drive current, and can therefore be neglected.
Other “hidden” losses such as copper trace and the battery
internal resistance can account for an additional several
percent effi ciency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
CIN has adequate charge storage and very low ESR at the
switching frequency. A 25W supply will typically require
LTC3852
26
3852f
a minimum of 20F to 40F of capacitance having a
maximum of 20m to 50m of ESR. Other losses
including Schottky conduction losses during dead time
and inductor core losses generally account for less than
2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, VOUT shifts by an
amount equal to DILOAD (ESR), where ESR is the effective
series resistance of COUT. DILOAD also begins to charge or
discharge COUT generating the feedback error signal that
forces the regulator to adapt to the current change and
return VOUT to its steady-state value. During this recovery
time VOUT can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the ITH pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC fi ltered closed-loop response test point. The DC step,
rise time and settling at this test point truly refl ects the
closed-loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
pin. The bandwidth can also be estimated by examining the
rise time at the pin. The ITH external components shown
in the Typical Application circuit will provide an adequate
starting point for most applications.
The ITH series RC-CC fi lter sets the dominant pole-zero
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1s to 10s will
produce output voltage and ITH pin waveforms that will
give a sense of the overall loop stability without break ing
the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
APPLICATIONS INFORMATION
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this
signal cannot be used to determine phase margin. This
is why it is better to look at the ITH pin signal which is in
the feedback loop and is the fi ltered and compensated
control loop response. The midband gain of the loop will
be in creased by increasing RC and the bandwidth of the
loop will be increased by decreasing CC. If RC is increased
by the same factor that CC is decreased, the zero frequency
will be kept the same, thereby keeping the phase shift the
same in the most critical frequency range of the feedback
loop. The output voltage settling behavior is related to the
stability of the closed-loop system and will demonstrate
the actual overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with COUT, causing a rapid drop in VOUT. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
CLOAD to COUT is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • CLOAD. Thus a 10F capacitor would
require a 250s rise time, limiting the charging current
to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3852. These items are also illustrated graphically
in the layout diagram of Figure 13. Check the following
in your layout:
1. Are the board signal and power grounds segregated?
The LTC3852 ground pins should connect to the ground
plane close to the output capacitor(s). The low current
or signal ground lines should make a single point tie
directly to the GND1 and GND2 pins. The synchronous
MOSFET source pins should connect to the input
capacitor(s) ground.
2. Does the VFB pin connect directly to the feedback
resistors? The resistive divider R1, R2 must be
connected between the (+) plate of COUT and signal
LTC3852
27
3852f
LTC3852
CS
CC1
CC2
CFF
CINTVCC
CFLY
RB
RS1
CSS
CFLTR
RFREQ
RPGOOD
VPULL-UP
RC
RA
COUT1
CIN2
COUT2
CB
DB
RSENSE
D1
M2
M1
C
IN1
+
–
L1
VIN
–
+
VOUT
3852 F13
PGOOD
FREQ/PLLFLTR
MODE/PLLIN
RUN
SHDN
TRACK/SS
ITH
VFB
SENSE–
SENSE+
SW
TG
BOOST
VIN2
VIN1
INTVCC
VPUMP
BG
GND1, 2
C–
C+
RS2
+
+
ONOFF
Figure 13. LTC3852 Switching Regulator Layout Diagram
APPLICATIONS INFORMATION
ground. The 47pF to 100pF capacitor should be as
close as possible to the LTC3852. Be careful locating
the feedback resistors too far away from the LTC3852.
The VFB line should not be routed close to any other
nodes with high slew rates.
3. Are the SENSE– and SENSE+ leads routed together
with minimum PC trace spacing? The fi lter capacitor
between SENSE+ and SENSE– should be as close as
possible to the LTC3852. Ensure accurate current
sensing with Kelvin connections as shown in Figure 14.
Series resistance can be added to the SENSE lines to
increase noise rejection and to compensate for the ESL
of RSENSE.
4. Does the (+) terminal of CIN connect to the drain of
the topside MOSFET(s) as closely as possible? This
capacitor provides the AC current to the MOSFET(s).
5. Is the INTVCC ceramic decoupling capacitor connected
closely between INTVCC and GND2? This capacitor
carries the MOSFET driver peak currents.
6. Keep the switching node (SW), top gate node (TG) and
boost node (BOOST) away from sensitive small-signal
SENSE+SENSE–
HIGH
CURRENT
PATH
3852 F14
CURRENT SENSE
RESISTOR
(RSENSE)
nodes, especially from the voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and therefore should be kept on
the “output side” of the LTC3852 and occupy minimum
PC trace area.
Figure 14. Kelvin Sensing RSENSE
Layout Considerations (Charge Pump)
Due to the high switching frequency and high transient
currents produced by the charge pump, careful board layout
is necessary for optimum performance. A true ground
plane and short connections to all the external capacitors
LTC3852
28
3852f
will improve performance and ensure proper regulation
under all conditions. Figure 15 shows an example layout
for the charge pump.
APPLICATIONS INFORMATION
sensing pins needs to be placed immediately adjacent to
the pins of the IC. This capacitor helps to minimize the
effects of differential noise injection due to high frequency
capacitive coupling. If problems are encountered with
high current output loading at lower input voltages, look
for inductive coupling between CIN, the Schottky and the
top MOSFET to the sensitive current and voltage sensing
traces. In addition, investigate common ground path
voltage pickup between these components and the GND
pin of the IC.
Design Example
As a design example, assume VIN = 3.3V (nominal), VIN =
5.5V (maximum), VOUT = 1.5V, IMAX = 15A, and f = 400kHz
(refer to Figure 16).
The inductance value is chosen fi rst based on a 30%
ripple current assumption. The highest value of ripple
current occurs at the maximum input voltage. Connect
a 68.1k resistor between the FREQ/PLLFLTR and GND
pins, generating 400kHz op eration. The inductance for
30% ripple current is:
L=1
ΔILf
()
VOUT 1−VOUT
VIN
⎛
⎝
⎜⎞
⎠
⎟
=1
4.5A 400kHz
()
1.5V 1−1.5V
3.3V
⎛
⎝
⎜⎞
⎠
⎟=454nH
A 400nH inductor will produce 34% ripple current.The peak
inductor current will be the maximum DC value (15A) plus
one-half the ripple current (2.5A), or 17.5A. The minimum
on-time occurs at maximum VIN:
tON(MIN) =VOUT
VIN(MAX) f
()
=1.5V
5.5V 400kHz
()
=682ns
which is greater than the 90ns minimum on-time.
The RSENSE resistor value can be calculated by using the
minimum current sense voltage specifi cation with a 20%
increase for current limit.
RSENSE ≤VSENSE(MIN)
IPEAK •1.2 ≤40mV
17.5A •1.2 =1.9mΩ
Choosing 1% resistors: R1 = 20k and R2 = 37.4k yields
an output voltage of 1.496V.
Figure 15. Recommended Charge Pump Layout
3852 F15
CIN
0603
CPUMP
0603
VPUMP
VIN1
CFLY
0603
GND1
LTC3852EUDD
C+
C–
PC Board Layout Debugging
It is helpful to use a DC-50MHz current probe to monitor
the current in the inductor while testing the circuit. Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator and probe the actual
output voltage as well. Check for proper performance
over the operating voltage and current range expected
in the application. The frequency of operation should be
maintained over the input voltage range down to dropout
and until the output load drops below the low current
operation threshold—typically 10% of the maximum
designed cur rent level in Burst Mode operation.
The duty cycle percentage should be maintained from cycle
to cycle in a well designed, low noise PCB imple mentation.
Variation in the duty cycle at a subharmonic rate can suggest
noise pick-up at the current or voltage sensing inputs or
inadequate loop compensation. Overcompensation of the
loop can be used to tame a poor PC layout if regulator
bandwidth optimization is not required.
Investigate whether any problems exist only at higher out-
put currents or only at higher input voltages. If problems
coincide with high input voltages and low output currents,
look for capacitive coupling between the BOOST, SW, TG
and possibly BG connections and the sensitive voltage
and current pins. The capacitor placed across the current
LTC3852
29
3852f
The power dissipation on the topside MOSFET can be easily
estimated. Choosing Vishay SIR438DP MOSFETs results
in: RDS(ON) = 0.0023W, CMILLER = 445pF. At maximum
input voltage with T (estimated) = 50°C:
P
MAIN =1.5V
5.5V 15
()
21+0.005
()
50°C−25°C
()
⎡
⎣⎤
⎦
• 0.0023Ω
()
+5.5V
()
215A
2
⎛
⎝
⎜⎞
⎠
⎟2Ω
()
445pF
()
•1
5−1+1
1
⎡
⎣
⎢⎤
⎦
⎥400kHz
()
=108mW
A short-circuit to ground will result in a folded back current of:
ISC =
14
()
65mV
0.003Ω–1
2
90ns 5.5V
()
400nH
⎛
⎝
⎜⎞
⎠
⎟=4.8A
APPLICATIONS INFORMATION
with a typical value of RDS(ON) and d = (0.005/°C)(25°C)
= 0.125. The resulting power dissipated in the bottom
MOSFET is:
PSYNC =5.5V–1.5V
5.5V 15A
()
21.125
()
0.0023Ω
()
=423mW
which is less than under full-load conditions.
CIN is chosen for an RMS current rating of at least 9A at
temperature. COUT is chosen with an ESR of 0.02W for
low output ripple. The output ripple in continuous mode
will be highest at the maximum input voltage. The output
voltage ripple due to ESR is approximately:
V
ORIPPLE = RESR (DIL) = 0.02W (5.1A) = 102mVP-P
TYPICAL APPLICATIONS
Figure 16. High Effi ciency 1.5V/15A Step-Down Converter From Design Example
C8
2200pF
1
2
3
JP1
RUN
R9
5.9k
C5
0.1µF
2.2µF
10V
0603
C1
JP2
MODE
1
2
3
4R5
68.1k
1%
R16
100k
R17
100k
C9
150pF
C11
0.01µF
VIN
INTVCC
100k
PGOOD
ON
OFF
CCM
BURST
PS
+
GND
VIN
2.7V TO 5.5V
CIN1
220µF
6.3V
L1
0.4µH
CIN1: SANYO 6TPE220MI
COUT1: AVX 12106D107MAT2A
COUT2: SANYO 4TPE330MI
D1: CENTRAL SEMI CMDSH-3
L1: VITEC 59PR9875N
Q1, Q3: VISHAY SILICONIX SiR438DP
CIN5
10µF
16V
1206
×2
COUT1
100µF
6.3V
COUT2
330µF
4V
×2
VOUT
1.5V/15A
Q1
D1
Q3
C15
4.7µF
10V
C6
0.1µF
C12
1000pF
RS1
0.002
1%
+
GND
R11
100
R20
17.4k
1%
R19
20k
1%
R12
100
24
GND1 GND2
FB
BG
TG
BOOST
SW
INTVCC
VIN2
VIN1
VPUMP
SENSE–
SENSE+
C–
C+
MODE/
PLLIN
FREQ/PLLFLTR
RUN
TRACK/SS
PGOOD
SHDN
ITH
GND
LTC3852
3852 F16
LTC3852
30
3852f
TYPICAL APPLICATIONS
VIN = 7V
VOUT = 5V
INTVCC
5V
2V/DIV
10ms 3852 F17a
INTVCC During Line Transient
(VIN1 < 5V)
C8
2200pF
R9
3.6k
C5
0.1µF
2.2µF
10V
0603
C1
R5
82.5k
1%
R16
100k
C9
150pF
C11
0.1µF
INTVCC
PGOOD
+
VIN
4V TO 36V
CIN1
56µF
50V
L1
3.6µH
CIN5
3.3µF ×4
50V
C1
4.7µF
10V
COUT1
47µF
10V
COUT2
220µF
6.3V
VOUT
5V/10A
(VIN > 5V)
Q1
Q2
2N3904
D1
D3
BAT85
Q3
C15
4.7µF
10V
C6
0.1µF
C12
1000pF
RS1
0.003
1%
+
GND
R11
100
R1
1k
D2
4.7V
R20
42.2k
1%
R19
8.06k
1%
R12
100
GND1 GND2
FB
BG
BOOST
SW
TG
INTVCC
VIN2
VIN1
VPUMP
SENSE–
SENSE+
C–
C+
MODE/
PLLIN
FREQ/
PLLFLTR
RUN
TRACK/SS
PGOOD
SHDN
ITH
GND
3V
0V
LTC3852
3852 F18
ONOFF
CIN1: SUNCON 50HVP56M
CIN5: TDK C3225X7R1H335
COUT1: TDK C3225X5ROJ476
COUT2: SANYO 6TPE220MI
D1: CENTRAL SEMI CMDSH-3
L1: COILTRONICS HC1-3R6-R
Q1: RENESAS RJK0451DPB
Q3: RENESAS RJKO453DPB
JP2
MODE
1
2
3
4
INTVCC
100k
CCM
BURST
PS
Figure 17. 5V/10A Converter Providing 5V Drive to MOSFETs for 4V < VIN < 36V
LTC3852
31
3852f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
3.00 ± 0.10 1.50 REF
5.00 ± 0.10
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
23 24
1
2
BOTTOM VIEW—EXPOSED PAD
3.50 REF
0.75 ± 0.05
R = 0.115
TYP
PIN 1 NOTCH
R = 0.20 OR 0.25
s 45° CHAMFER
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UDD24) QFN 0808 REV Ø
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
3.50 REF
4.10 ± 0.05
5.50 ± 0.05
1.50 REF
2.10 ± 0.05
3.50 ± 0.05
PACKAGE OUTLINE
R = 0.05 TYP
1.65 ± 0.10
3.65 ± 0.10
1.65 ± 0.05
UDD Package
24-Lead Plastic QFN (3mm s 5mm)
(Reference LTC DWG # 05-08-1833 Rev Ø)
3.65 ± 0.05
0.50 BSC
LTC3852
32
3852f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
” LINEAR TECHNOLOGY CORPORATION 2010
LT 1010 • PRINTED IN USA
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC3736/LTC3736-1/
LTC3736-2
Dual, 2-Phase Synchronous Step-Down Controller 2.75V ≤ VIN ≤ 9.8V, No RSENSE™
LTC3772/LTC3772B Micropower, No RSENSE Constant Frequency Step-Down
DC/DC Controller
2.75V ≤ VIN ≤ 9.8V, No RSENSE, 40µA No-Load IQ
LTC3776 Dual 2-Phase, No RSENSE Synchronous Controller for DDR/
QDR Memory Termination
2.75V ≤ VIN ≤ 9.8V, VOUT2 Tracks 1/2 VREF
LT3808 No RSENSE, Low EMI, Synchronous DC/DC Controller with
Output Tracking
2.75V ≤ VIN ≤ 9.8V, Spread Spectrum Modulation for Low Noise
LTC3809/LTC3809-1 No RSENSE, Low Input Voltage, Synchronous DC/DC
Controller
2.75V ≤ VIN ≤ 9.8V, Output Tracking (LTC3809-1) or Spread
Spectrum Modulation
LTC3822/LTC3822-1 Low Input Voltage Synchronous Step-Down Controller 2.75V ≤ VIN ≤ 4.5V, No RSENSE
LTC3836 Dual, Low Input Voltage Synchronous Step-Down Controller 2.75V ≤ VIN ≤ 4.5V, No RSENSE
TYPICAL APPLICATIONS
Figure 18. 1.2V/20A Low Ripple DCR Sense Application
C8
1nF
1
2
3
JP1
RUN
R9
12.1k
C5
0.1µF
2.2µF
10V
0603
C1
R5
95.3k
1%
R16
100k
R17
100k
C9
100pF
C11
0.1µF
VIN
INTVCC
PGOOD
ON
OFF
+
VIN
2.7V TO 5.5V
CIN1
220µF
6.3V
s2
L1
0.36µH
CIN5
10µF
16V
1206
COUT1
100µF
6.3V
s5
COUT3
470µF/4V
s2
VOUT
1.2V/20A
Q1
D1
Q3
C15
4.7µF
10V
C6
0.1µF
C12
0.1µF
+
GND
R8
2.1k
R20
20k
1%
R19
40.2k
1%
GND1 GND2
FB
BG
BOOST
SW
TG
INTVCC
VIN2
VIN1
VPUMP
SENSE–
SENSE+
C–
C+
MODE/
PLLIN
FREQ/PLLFLTR
RUN
TRACK/SS
PGOOD
SHDN
ITH
GND
LTC3852EUDD
3852 F17
CIN1: SANYO 6TPE220MI
COUT1: AVX 12106D107MAT2A
COUT3: SANYO 4TPF470ML
D1: CENTRAL SEMI CMDSH-3
L1: VISHAY IHLP4040DZ-01
Q1, Q3: VISHAY SILICONIX SiR438DP