19-4093; Rev 1; 4/11 KIT ATION EVALU E L B A AVAIL 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter The MAX7057 frequency-programmable UHF transmitter is designed to transmit ASK/FSK data at a wide range of frequencies from 300MHz to 450MHz. The MAX7057 has internal tuning capacitors at the output of the power amplifier that are programmable for matching to an antenna or load. This allows the user to change to a new frequency and match the antenna at the new frequency simultaneously. The MAX7057 transmits at a data rate up to 100kbps nonreturn-to-zero (NRZ) (50kbps Manchester coded). Typical transmitted power into a 50 load is +9.2dBm with a +2.7V supply. The device operates from +2.1V to +3.6V and typically draws under 12.5mA of current in FSK mode (8.5mA in ASK mode) when the antenna-matching network is designed to operate over the 315MHz to 433.92MHz frequency range. For narrower operating frequency ranges, the matching network can be redesigned to improve efficiency. The standby current is less than 1A at room temperature. The MAX7057 reference frequency from the crystal oscillator is multiplied by a fully integrated fractional-N phase-locked loop (PLL). The multiplying factor of the PLL is set by a 16-bit number, with 4 bits for integer and 12 bits for fraction; the multiplying factor can be anywhere between 19 and 28. The 12-bit fraction in the synthesizer sets a tuning resolution equal to the reference frequency divided by 4096; frequency deviation can be set as low as 2kHz and as high as 100kHz. The fractional-N synthesizer eliminates the problems associated with oscillator-pulling FSK signal generation. The MAX7057 has a serial peripheral interface (SPITM) for selecting all the necessary settings. The MAX7057 is available in a 16-pin SO package and is specified to operate in the -40C to +125C automotive temperature range. Applications RF Remote Controls Garage Door Openers Home Automation Automotive Wireless Sensors Features o Programmable Frequency Operation with Single Crystal o Internal Variable Capacitor for Antenna Tuning with Single-Matching Network o 100kbps Data Rate (NRZ) o +2.1V to +3.6V Single-Supply Operation o < 12.5mA (FSK), < 8.5mA (ASK) DC Current Drain o < 1A Standby Current o ASK/FSK Modulation o 47% Carrier Tuning Range Using One Crystal Ordering Information PART TEMP RANGE MAX7057ASE+ PIN-PACKAGE -40C to +125C 16 SO +Denotes a lead(Pb)-free package/RoHs-compliant package. Pin Configuration TOP VIEW CS 1 + 16 DVDD 15 GPO SDI 2 MAX7057 SCLK 3 14 DGND PAGND 4 13 DIN PAOUT 5 12 ENABLE ROUT 6 11 AGND PAVDD 7 10 XTAL1 AVDD 8 9 XTAL2 Wireless Game Consoles Wireless Computer Peripherals Security Systems Typical Application Circuit and Functional Diagram appear at end of data sheet. SPI is a trademark of Motorola, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX7057 General Description MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter ABSOLUTE MAXIMUM RATINGS Supply Voltage, PAVDD, AVDD, DVDD to AGND, DGND, PAGND ...................................................-0.3V to +4.0V All Other Pins..................................._GND - 0.3V to _VDD + 0.3V Continuous Power Dissipation (TA = +70C) 16-Pin SO (derate 8.7mW/C above +70C)...............695.7mW Operating Temperature .....................................-40C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C Soldering Temperature (reflow) .......................................+260C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (Typical Application Circuit, 50 system impedance, tuned for 315MHz to 433.92MHz operation, VAVDD = VDVDD = VPAVDD = +2.1V to +3.6V, fRF = 300MHz to 450MHz, fCRYSTAL = 16MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VPAVDD = +2.7V, TA = +25C, unless otherwise noted. All min and max values are 100% tested at TA = +125C, and guaranteed by design and characterization over temperature, unless otherwise noted.) PARAMETER Supply Voltage SYMBOL VDD CONDITIONS PAVDD, AVDD, and DVDD connected to power supply, VDD PA off, VDIN at 0% duty cycle (ASK) Supply Current IDD ISTDBY TYP MAX UNITS 2.1 2.7 3.6 V 3.9 6.5 fRF = 315MHz fRF = 433.92MHz 4.5 7.5 VDIN at 50% duty cycle fRF = 315MHz (ASK) (Notes 1, 2, 3) fRF = 433.92MHz 8.1 15.1 8.5 15.0 VDIN at 100% duty cycle (FSK) (Note 1) Standby Current MIN VENABLE < VIL fRF = 315MHz 12.2 23.7 fRF = 433.92MHz 12.4 22.4 TA = +25C (Note 3) 0.8 TA < +85C (Note 3) TA < +125C 1 6.4 6.2 20.1 mA A DIGITAL I/O Input High Threshold VIH Input Low Threshold VIL 0.9 x VDVDD V 0.1 x DVDD V Input Pulldown Sink Current 13 A Input Pullup Source Current 9 A Output-Voltage High VOH ISINK = 500A (GPO) VDD 0.37 V Output-Voltage Low VOL ISOURCE = 500A (GPO) 0.36 V 2 _______________________________________________________________________________________ 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter (Typical Application Circuit, 50 system impedance, tuned for 315MHz to 433.92MHz operation, VAVDD = VDVDD = VPAVDD = +2.1V to +3.6V, fRF = 300MHz to 450MHz, fCRYSTAL = 16MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VPAVDD = +2.7V, TA = +25C, unless otherwise noted. All min and max values are 100% tested at TA = +125C, and guaranteed by design and characterization over temperature, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 450 MHz GENERAL CHARACTERISTICS Frequency Range 300 ENABLE transition low-to-high, frequency settled to within 50kHz of the desired carrier Power-On Time tON 120 s ENABLE transition low-to-high, frequency settled to within 5kHz of the desired carrier ASK mode Maximum Data Rate FSK mode 260 Manchester encoded 50 Nonreturn-to-Zero 100 Manchester encoded 50 Nonreturn-to-Zero 100 Time from end of SPI write to frequency settled to within 5kHz of desired carrier Frequency Switching Time kbps 70 s 320 MHz/V PHASE-LOCKED LOOP (PLL) VCO Gain KVCO fRF = 315MHz PLL Phase Noise fRF = 433.92MHz 10kHz offset -78 1MHz offset -98 10kHz offset -73 1MHz offset -98 dBc/Hz Loop Bandwidth 300 kHz Reference Frequency Input Level 500 mVP-P Frequency-Divider Range 19 28 Frequency Deviation (FSK) 2 100 kHz 23.68 MHz CRYSTAL OSCILLATOR Crystal Frequency fXTAL 10.71 Frequency Pulling by VDD Crystal Load Capacitance POWER AMPLIFIER (PA) Output Power (Note 1) (Note 4) POUT 4 ppm/V 10 pF TA = +25C (Note 3) 3.8 9.2 TA = +125C, VAVDD = VDVDD = VPAVDD = +2.1V 2.4 5.2 TA = -40C, VAVDD = VDVDD = VPAVDD = +3.6V (Note 3) Modulation Depth 12.6 71 Maximum Carrier Harmonics Reference Spur 16 With output matching network fRF = 315MHz -29 fRF = 433.92MHz -44 -45 16.4 dBm 17.0 dB dBc dBc _______________________________________________________________________________________ 3 MAX7057 AC ELECTRICAL CHARACTERISTICS MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter AC ELECTRICAL CHARACTERISTICS (continued) (Typical Application Circuit, 50 system impedance, tuned for 315MHz to 433.92MHz operation, VAVDD = VDVDD = VPAVDD = +2.1V to +3.6V, fRF = 300MHz to 450MHz, fCRYSTAL = 16MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VPAVDD = +2.7V, TA = +25C, unless otherwise noted. All min and max values are 100% tested at TA = +125C, and guaranteed by design and characterization over temperature, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SERIAL INTERFACE (SPI) TIMING CHARACTERISTICS (Figure 1) Minimum SCLK Low to FallingEdge of CS Setup Time tSC 10 ns Minimum CS Low to Rising-Edge of SCLK Setup Time tCSS 5 ns Minimum SCLK Low to RisingEdge of CS Setup Time tHCS 20 ns Minimum SCLK Low After RisingEdge of CS Hold Time tHS 5 ns Minimum Data Valid to SCLK Rising-Edge Setup Time tDS 10 ns Minimum Data Valid to SCLK Rising-Edge Hold Time tDH 5 ns Minimum SCLK High Pulse Width tCH 40 ns Minimum SCLK Low Pulse Width tCL 40 ns Minimum CS High Pulse Width Maximum Transition Time from Falling-Edge of CS to Valid GPO Maximum Transition Time from Falling-Edge of SCLK to Valid GPO Note 1: Note 2: Note 3: Note 4: tCSH 40 ns tCSG CL = 10pF load capacitance from GPO to DGND 50 ns tCG CL = 10pF load capacitance from GPO to DGND 50 ns Supply current and output power are greatly dependent on board layout and PAOUT match. 50% duty cycle at 10kHz ASK data (Manchester coded). Guaranteed by design and characterization, not production tested. Dependent on PCB trace capacitance. tCSH CS tSC tHCS tCSS SCLK tCL tDS tCH tHS tDH SDI tCSG tCG GPO Figure 1. SPI Timing Diagram 4 _______________________________________________________________________________________ 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter MAX7057 Typical Operating Characteristics (50 system impedance, VAVDD = VDVDD = VPAVDD = +2.1V to +3.6V, fRF = 300MHz to 450MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VPAVDD = +2.7V, TA = +25C, unless otherwise noted.) 13 TA = +25C 12 11 TA = -40C 10 8 TA = +25C 7 2.7 3.0 3.3 TA = +25C 3.5 3.0 TA = -40C 2.5 2.0 2.1 2.4 2.7 3.0 3.3 2.1 3.6 2.4 2.7 3.0 3.3 SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE 11 10 TA = +125C 9 TA = +25C 8 7 8 3.0 3.3 5.0 4.5 3.0 2.7 TA = +25C 4.0 5 2.4 TA = +125C 5.5 3.5 2.1 TA = +85C 6.0 6 3.6 fRF = 433.92MHz PA OFF 6.5 TA = -40C 9 2.7 10 TA = +85C 3.0 3.3 3.6 7.0 MAX7057 toc05 11 TA = -40C 2.4 fRF = 433.92MHz 50% DUTY CYCLE SUPPLY CURRENT (mA) TA = +25C 12 12 SUPPLY CURRENT (mA) TA = +125C 13 TA = -40C 2.1 3.6 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) OUTPUT POWER vs. SUPPLY VOLTAGE OUTPUT POWER vs. SUPPLY VOLTAGE SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR TA = -40C 10 8 TA = +85C 6 TA = +125C 4 2 0 2.4 2.7 3.0 SUPPLY VOLTAGE (V) 14 3.3 3.6 fRF = 433.92MHz PA ON TA = -40C, +25C 12 10 8 TA = +85C 6 TA = +125C 4 SUPPLY VOLTAGE (V) 3.3 3.6 SUPPLY CURRENT -5 6 -10 4 0 3.0 10 0 8 0 2.7 15 5 10 2 2.4 OUTPUT POWER 12 2 2.1 MAX7057 toc09 14 SUPPLY CURRENT (mA) TA = +25C OUTPUT POWER (dBm) fRF = 315MHz PA ON MAX7057 toc07 14 2.1 4.0 SUPPLY CURRENT vs. SUPPLY VOLTAGE TA = +85C 12 4.5 SUPPLY VOLTAGE (V) 15 2.1 TA = +85C SUPPLY VOLTAGE (V) 16 14 TA = +125C SUPPLY VOLTAGE (V) fRF = 433.92MHz PA ON 17 3.6 MAX7057 toc04 18 2.4 5.0 TA = -40C 5 2.1 SUPPLY CURRENT (mA) 8 6 9 OUTPUT POWER (dBm) TA = +125C 9 fRF = 315MHz PA OFF -15 -20 fRF = 315MHz PA ON 0.1 1 10 100 1000 -25 10,000 EXTERNAL RESISTOR () _______________________________________________________________________________________ 5 OUTPUT POWER (dBm) TA = +125C 10 5.5 MAX7057 toc06 14 TA = +85C SUPPLY CURRENT (mA) 15 MAX7057 toc02 TA = +85C 6.0 MAX7057 toc08 SUPPLY CURRENT (mA) 16 fRF = 315MHz 50% DUTY CYCLE 11 SUPPLY CURRENT (mA) fRF = 315MHz PA ON 17 12 MAX7057 toc01 18 SUPPLY CURRENT vs. SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX7057 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE Typical Operating Characteristics (continued) (50 system impedance, VAVDD = VDVDD = VPAVDD = +2.1V to +3.6V, fRF = 300MHz to 450MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VPAVDD = +2.7V, TA = +25C, unless otherwise noted.) SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR SUPPLY CURRENT (mA) 8 10 14 5 12 7 0 6 5 -5 4 -10 3 OUTPUT POWER -15 SUPPLY CURRENT (mA) SUPPLY CURRENT OUTPUT POWER (dBm) MAX7057 toc10 9 MAX7057 toc11 15 SUPPLY CURRENT 10 5 10 0 8 -5 6 -10 OUTPUT POWER 4 -15 2 fRF = 315MHz 50% DUTY CYCLE 0 0.1 1 10 100 1000 2 -25 10,000 0 0.1 1 SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR -60 5 -70 0 -80 -5 5 -10 4 -15 OUTPUT POWER fRF = 433.92MHz 50% DUTY CYCLE 0 0.1 10 100 1000 -25 10,000 fRF = 315MHz 1000 -90 -100 -110 -20 -120 -25 -130 -30 10,000 -140 100 1k 10k 100k 1M EXTERNAL RESISTOR () OFFSET FREQUENCY (Hz) PHASE NOISE vs. OFFSET FREQUENCY REFERENCE SPUR MAGNITUDE vs. SUPPLY VOLTAGE -60 -70 -80 -90 -100 -110 -120 10M -30 MAX7057 toc15 fRF = 433.92MHz REFERENCE SPUR MAGNITUDE (dBc) MAX7057 toc14 -50 1 PHASE NOISE (dBc/Hz) 6 OUTPUT POWER (dBm) SUPPLY CURRENT (mA) 7 2 -35 fRF = 433.92MHz -40 -45 -50 fRF = 315MHz -55 -60 -130 100 1k 10k 100k OFFSET FREQUENCY (Hz) 6 10 SUPPLY CURRENT 1 100 PHASE NOISE vs. OFFSET FREQUENCY MAX7057 toc12 9 3 10 EXTERNAL RESISTOR () EXTERNAL RESISTOR () 8 -20 fRF = 433.92MHz PA ON MAX7057 toc13 1 -20 1M 10M 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ OUTPUT POWER (dBm) SUPPLY CURRENT AND OUTPUT POWER vs. EXTERNAL RESISTOR PHASE NOISE (dBc/Hz) MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter FREQUENCY STABILITY vs. SUPPLY VOLTAGE 6 fRF = 315MHz PA ON TA = -40C 30 TA = +25C MAX7057 toc17 8 fRF = 315MHz 4 EFFICIENCY (%) FREQUENCY STABILITY (ppm) 35 MAX7057 toc16 10 EFFICIENCY vs. SUPPLY VOLTAGE 2 0 fRF = 433.92MHz -2 25 20 TA = +85C -4 -6 TA = +125C 15 -8 -10 10 2.7 3.0 3.3 2.1 3.0 3.3 EFFICIENCY vs. SUPPLY VOLTAGE EFFICIENCY vs. SUPPLY VOLTAGE fRF = 315MHz 50% DUTY CYCLE TA = -40C TA = +25C 35 19 17 15 TA = +85C TA = +25C 3.6 25 20 TA = +85C 13 TA = +125C 15 TA = +125C 11 fRF = 433.92MHz PA ON TA = -40C 30 EFFICIENCY (%) 9 10 2.1 2.4 2.7 3.0 3.3 2.1 3.6 SUPPLY VOLTAGE (V) 3.0 3.3 3.6 TA = +25C FSK SPECTRUM +24 MAX7057 toc20 23 fRF = 433.92MHz 50% DUTY CYCLE TA = -40C 2.7 SUPPLY VOLTAGE (V) EFFICIENCY vs. SUPPLY VOLTAGE 21 2.4 +14 +4 19 RBW = 10kHz VBW = 10kHz VIDEO AVG ON MAX7057 toc21 EFFICIENCY (%) 2.7 SUPPLY VOLTAGE (V) 21 -6 17 (dBm) EFFICIENCY (%) 2.4 SUPPLY VOLTAGE (V) 25 23 3.6 MAX7057 toc19 2.4 MAX7057 toc18 2.1 15 -16 -26 -36 -46 13 TA = +85C 11 -56 TA = +125C -66 -76 9 2.1 2.4 2.7 3.0 3.3 100kHz DEVIATION, 4kHz SQUARE-WAVE MODULATION. SPAN = 1.00MHz 3.6 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 7 MAX7057 Typical Operating Characteristics (continued) (50 system impedance, VAVDD = VDVDD = VPAVDD = +2.1V to +3.6V, fRF = 300MHz to 450MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at VAVDD = VDVDD = VPAVDD = +2.7V, TA = +25C, unless otherwise noted.) MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Pin Description PIN NAME FUNCTION 1 CS Serial Interface Active-Low Chip Select. Internally pulled up to DVDD. 2 SDI Serial Interface Data Input. Internally pulled down to GND. 3 SCLK Serial Interface Clock Input. Internally pulled down to GND. 4 PAGND Power Amplifier Ground 5 PAOUT Power Amplifier Output. Requires a pullup inductor to the supply voltage or ROUT. The pullup inductor can be part of the output-matching network. 6 ROUT 7 PAVDD Power Amplifier Supply Voltage. Bypass to ground with 0.01F and 220pF capacitors placed as close as possible to the pin. 8 AVDD Analog Positive Supply Voltage. Bypass to ground with 0.1F and 0.01F capacitors placed as close as possible to the pin. 9 XTAL2 Crystal Input 2. XTAL2 can be driven from an AC-coupled external reference. Envelope-Shaping Output. ROUT controls the power amplifier envelope's rise and fall times. Connect ROUT to the PA pullup inductor or to an optional power-adjust resistor. Bypass the inductor to GND as close as possible to the inductor with 680pF and 220pF capacitors. 10 XTAL1 Crystal Input 1. Bypass to ground if XTAL2 is driven from an AC-coupled external reference. 11 AGND Analog Ground 12 ENABLE Enable Pin. Drive high for normal operation; drive low or leave unconnected to put the device in standby mode. Internally pulled down to GND. 13 DIN ASK/FSK Data Input. Use the control register (address: 0x00) to select the type of modulation. Internally pulled down to GND. 14 DGND 15 GPO 16 DVDD Digital Ground General-Purpose Output. Can be configured to output various digital signals (SPI serial data output--SDO, CLKOUT--reference oscillator frequency divided by 1, 2, 4, or 8 for microprocessor clock, etc). Digital positive supply voltage. Bypass to ground with 0.1F and 0.01F capacitors placed as close as possible to the pin. Detailed Description The MAX7057 is frequency programmable from 300MHz to 450MHz, by using a fractional-N phase-locked loop (PLL), and transmits data using either ASK or FSK modulation. The MAX7057 has integrated tuning capacitors at the output of the power amplifier (PA) to ensure highpower efficiency at various programmable frequencies with a single-matching network. The crystal-based architecture of the MAX7057 eliminates many of the common problems with SAW transmitters by providing greater modulation depth, faster frequency settling, tighter transmit frequency tolerance, and reduced temperature dependence. In particular, the tighter transmit frequency tolerance means that a superheterodyne receiver with a narrower IF bandwidth (therefore lower noise bandwidth) can be used. The payoff is better overall receiver performance when using 8 a superheterodyne receiver such as the MAX1471, MAX1473, MAX7033, MAX7034, or MAX7042. Frequency Programming The MAX7057 is a crystal-referenced phased-locked loop (PLL) VHF/UHF transmitter that transmits data over the frequency range of 300MHz to 450MHz in ASK or FSK mode. The transmit frequency is set by the crystal frequency and the programmable divider in the PLL; the programmable-divide ratios can be set anywhere from 19 to 28, which means that with a crystal frequency of 16MHz, the output frequency range can be from 304MHz to 448MHz. The fractional-N architecture of the PLL in the MAX7057 allows the FSK signal to be programmed for exact frequency deviations and rapid, transient-free frequency settling time. This modulation method completely elimi- _______________________________________________________________________________________ 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter The MAX7057 supports data rates up to 100kbps NRZ in both ASK and FSK modes. In FSK mode, the frequency deviation can be programmed as low as 2kHz and as high as 100kHz. Power Amplifier (PA) The PA of the MAX7057 is a high-efficiency, open-drain switching-mode amplifier. In a switching-mode amplifier, the gate of the final-stage FET is driven with a very sharp 25% duty-cycle square wave at the transmit frequency. This square wave is derived from the synthesizer circuit. When the matching network is tuned correctly, the output FET resonates the attached matching circuit with a minimum amount of power dissipated in the FET. With a proper output-matching network, the PA can drive a wide range of antenna impedances, which include a small-loop PCB trace and a 50 antenna. The output-matching network suppresses the carrier harmonics and transforms the antenna impedance to an optimal impedance at PAOUT, which is from 125 to 250. When the output-matching network is properly tuned, the PA transmits power with a high overall efficiency of up to 25%. The efficiency of the PA itself is more than 39%. The output power can be adjusted by changing the impedance seen by the PA or by adjusting the value of an external resistor at PAOUT. Variable Capacitor The MAX7057 has a set of internal variable shunt capacitors that can be switched in and out to present different capacitor values at the PA output. The capacitors are connected from the PA output to ground. This allows changing the tuning network along with the synthesizer divide ratio each time the transmitted frequency changes, making it possible to maintain maximum transmitter power while moving rapidly from one frequency to another. When the particular capacitance control bit is high, the corresponding amount of shunt capacitance is added at PAOUT. The 32 capacitor values are selected using the SPI; the capacitance resolution is 0.25pF. The total capacitance can vary from 0 to 7.75pF. For example, if cap[1] and cap[3] are high, and cap[4], cap[2], and cap[0] are low, this circuit will add 2.5pF at PAOUT. See Table 1 for variable capacitor values and control bits. Fractional-N Phase-Locked Loop (PLL) The MAX7057 utilizes a fully integrated fractional-N PLL for its transmit frequency synthesizer. All PLL components, including the loop filter, are included on-chip. The loop bandwidth is programmable to either 300kHz or 600kHz. See Tables 2, 3, and 4 for "pllbw" bit description. The 16-bit fractional-N topology allows the transmit frequency to be adjusted in increments of fXTAL/4096. The allowable range of the fRF/fXTAL ratio is approximately 19 to 28. The fractional-N topology also allows exact FSK frequency deviations to be programmed, completely eliminating the problems associated with generating frequency deviations by crystal oscillator pulling. The integer and fractional portions of the PLL divider ratio set the transmit frequency. The following example shows how to determine the correct values to be loaded to registers HIFREQ1, HIFREQ0, LOFREQ1, and LOFREQ0. See Tables 2, 3, and 7-10 for a detailed description of these registers. Table 1. Variable Capacitor Values and Control Bits SPI REGISTER BITS INCREMENTAL SHUNT CAPACITANCE (pF) Envelope Shaping cap[0] 0.25 The MAX7057 features an internal envelope-shaping resistor for ASK modulation, which connects between PAVDD and ROUT. When connected to the PA pullup inductor, the envelope-shaping resistor slows the turnon/-off time of the PA and results in a smaller spectral width of the modulated PA output signal. cap[1] 0.5 cap[2] 1.0 cap[3] 2.0 cap[4] 4.0 _______________________________________________________________________________________ 9 MAX7057 nates the problems associated with crystal-pulling FSK signal generation. The multiplying factor of the PLL is set by a 16-bit number, with 4 bits for integer and 12 bits for fraction. The 12-bit fraction in the synthesizer results in a tuning resolution that is equal to the reference frequency divided by 4096. The MAX7057 has an internal variable shunt capacitor connected at the PA output. This capacitor is controlled using the SPI to maintain highly efficient transmission at any frequency within a 1.47 to 1 (28/19) tuning range. This means that it is possible to change the frequency and retune the antenna to the new frequency in a very short time. The combination of rapid-antenna tuning ability with rapid-synthesizer tuning makes the MAX7057 a true frequency-agile transmitter. The tuning capacitor has a resolution of 0.25pF. The MAX7057 also features adjustable output power through an external resistor to nearly +10dBm into a 50 load at +2.7V. MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Due to the nature of the transmit PLL frequency divider, a fixed offset of 16 must be subtracted from the transmit PLL divider ratio for programming the MAX7057's transmit frequency registers. To determine the value to program the MAX7057's transmit frequency registers, convert the decimal value of the following equation to the nearest hexadecimal value: fRF -16 x 4096 = Decimal value to program f XTAL transmit frequency registers Assume that the ASK transmit frequency = 315MHz and fXTAL = 16MHz. In this example, the rounded decimal value is 15,104, or 0x3B00 hexadecimal. The upper 2 bytes (0x3B) are loaded into the LOFREQ1 register, and the low 2 bytes (0x00) are loaded into the LOFREQ0 register. In ASK mode, the transmit frequency equals the lower frequency programmed into the MAX7057's transmit frequency registers (see Tables 2, 3, and 9-12). In FSK mode, the transmit frequencies equal the upper (HIFREQ1 and HIFREQ0) and lower (LOFREQ1 and LOFREQ0) frequencies programmed into the MAX7057's transmit frequency registers. Calculate the upper and lower frequency in the same way as shown above. FSK deviations as low as 2kHz and as high as 100kHz are programmable (see Tables 2, 3, and 8-12). The exact min and max values for the transmit frequency registers (HIFREQ1/0, LOFREQ1/0) are 2.9596 (0x2F42) and 12.0220 (0xC05A), yielding a synthesizer ratio of 18.9596 and 28.0220, respectively. These limits MUST be followed to prevent the delta-sigma modulator from overflowing. Whenever all of the fractional bits in the HIFREQ1/0 and LOFREQ1/0 registers are zero (fhi[11:0] and flo[11:0]), only an integer divider is used, and the delta-sigma modulator is not in operation. This allows lower current operation. The 600kHz PLL bandwidth should be used in this mode to reduce phase noise. Any change to the transmit frequency registers must be followed by writing a "1" to the self-reset frequency load register (see Tables 2, 3, and 12). Crystal (XTAL) Oscillator The crystal (XTAL) oscillator in the MAX7057 is designed to present a capacitance of approximately 10 6pF between XTAL1 and XTAL2. In most cases, this corresponds to an 8pF load capacitance applied to the external crystal when typical PCB parasitics are added. The MAX7057 is designed to operate with a typical 10pF load capacitance crystal. It is very important to use a crystal with a load capacitance that is equal to the capacitance of the MAX7057 crystal oscillator plus PCB parasitics and optional external load capacitors. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, introducing an error in the reference frequency. A crystal designed to operate at a higher load capacitance than the value specified for the oscillator is always pulled higher in frequency. Adding capacitance to increase the load capacitance on the crystal increases the start-up time and can prevent oscillation altogether. In actuality, the oscillator pulls every crystal. The crystal's natural frequency is below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is already accounted for in the specification of the load capacitance. Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by: fp = Cm 1 2 Ccase + Cload - 1 6 x 10 Ccase + Cspec where: fp is the amount the crystal frequency is pulled in ppm Cm is the motional capacitance of the crystal Ccase is the case capacitance Cspec is the specified load capacitance Cload is the actual load capacitance When the crystal is loaded as specified (i.e., Cload = Cspec), the frequency pulling equals zero. Communication Protocol The MAX7057 registers are programmed through an SPI interface. Figure 2 shows the timing diagram of the SPI. The GPO must be properly configured to act as an SPI data output (SDO) by setting the configuration 1 register (see Tables 2, 3, 15, and 16). The SPI operates on a byte format, according to Figure 2. ______________________________________________________________________________________ 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter MAX7057 CS SCLK SDI D7 D6 D5 D4 D3 D2 D1 D0 D7 DATA 1 D6 D5 D4 D3 D2 D1 D0 DATA N Figure 2. SPI Format CS SCLK A7 SDI WRITE COMMAND (0x01) A6 A5 A4 A3 A2 A1 INITIAL ADDRESS (A[7:0]) A0 D7 D6 D5 D4 D3 D2 D1 D0 DATA 0 D7 D0 DATA N Figure 3. SPI Write Command Format Depending on the command, byte 1 through byte N may assume different functions. They may either be a direct command (write, read, read all, reset), or an address or data contents. The commands available in the MAX7057 SPI are described in detail below: Write: The write command (0x01) is used to program the MAX7057 registers (see Tables 2 and 3). The format shown in Figure 3 must be followed, allowing all the registers to be programmed within one CS cycle. Using a byte descriptive notation, the write command can be viewed as the following sequence: SDI: <0x01> <Initial Address> <Data 0> <Data 1> ... <Data N> Data 0 is then written to the register addressed by <Initial Address>, Data 1 is written to <Initial Address + 1>, and so on. Read: To execute an SPI read operation, the generalpurpose output (GPO) pin must be configured to either a CKOUT_SDO or SDO function (see Tables 15 and 16 for details). ______________________________________________________________________________________ 11 MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter CS SCLK A7 A6 A5 A4 A3 A2 A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 SDI READ COMMAND (0x02) ADDRESS 0 GPO A0 A7 ADDRESS N ADDRESS 1 D7 D6 D5 D4 D3 D2 D1 D0 D0 D7 D7 DATA N-1 DATA 0 0x00 D0 DATA N Figure 4. SPI Read Command Format CS SCLK SDI A7 A6 A5 A4 A3 A2 A1 A0 READ ALL COMMAND (0x03) ADDRESS N GPO D7 D6 D5 D4 D3 D2 D1 D0 D7 DATA N D0 DATA N+1 D7 D0 DATA N+n Figure 5. SPI Read-All Command Format Using a byte descriptive notation, the read command can be viewed as the following sequence, within the same CS cycle: SDI : <0x02> <Address 0> <Address 1> <Address2> ... < Address N > < 0x00 > GPO: < XX > < XX > < Data 0 > < Data 1 > ... < Data N - 1 > <Data N> With this command, all the registers can be read within the same cycle of CS. The addresses can be given in any order. Read-All: To execute an SPI read-all operation, GPO must be configured to either a CKOUT_SDO or SDO 12 function (see Tables 15 and 17 for details). Using a byte descriptive notation, the read command can be viewed as the following sequence, within two CS cycles: CS cycle 1 SDI : <0x03> <Address N> GPO: CS cycle 2 < XX > < XX > < XX >...< XX > <Data N> <DataN + 1> <DataN + 2>...<Data N + n> Reset: The MAX7057 can be reset to its power-up state through the reset command. ______________________________________________________________________________________ 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter CS SCLK SDI RESET COMMAND (0x04) Figure 6. Reset Command Format Using a byte descriptive notation, the reset command can be viewed as the following sequence, within the same CS cycle: SDI: <0x04> Features and Settings Values and parameters are set through registers in the MAX7057 that are addressable through the SPI. These registers contain bits that either turn functions on and off or program numerical settings. The following settings are controlled through the SPI. Clock Output The MAX7057 has a buffered clock output that can serve as a clock for a microprocessor. The divide ratio is set through the configuration 0 register (see Tables 5 and 6). The divide settings are 1 (no division), 2, 4, 8, or 16; the original undivided frequency is based on the reference frequency generated by the external crystal. The buffered clock output is available at GPO when enabled by setting the configuration 1 register (see Tables 2, 3, 15, and 16). Mode Select and Crystal Shutdown The transmission mode is selected by writing to a register. The default mode is ASK and the mode can be changed to FSK by writing a 1 to the mode bit in the control register. This register is also used to keep the crystal circuit powered up in the shutdown mode. Registers The following tables provide information on the MAX7057 registers. Table 2. Register Summary ADDRESS REGISTER NAME DESCRIPTION 0x00 CONTRL Control register. Controls the mode (ASK/FSK), crystal clock output, envelope-shaping, PLL bandwidth, and SPI enable. 0x01 CONFIG0 Configuration 0 register. Controls the capacitance at the PA output and clock output frequency divider. 0x02 HIFREQ1 High-frequency 1 register (upper byte). Sets the high frequency in FSK transmission. 0x03 HIFREQ0 High-frequency 0 register (lower byte). Sets the high frequency in FSK transmission. 0x04 LOFREQ1 Low-frequency 1 register (upper byte). Sets the low frequency in FSK transmission, or carrier frequency in ASK transmission. 0x05 LOFREQ0 Low-frequency 0 register (lower byte). Sets the low frequency in FSK transmission, or carrier frequency in ASK transmission. 0x06 FLOAD Frequency load register. Performs the frequency load function. 0x07 DATAIN Data in register. SPI equivalent of DIN pin. 0x08 EN 0x09 CONFIG1 0x0C STATUS Enable register. SPI equivalent of ENABLE pin. Configuration 1 register. GPO selector. Status register. ______________________________________________________________________________________ 13 MAX7057 Variable Capacitor The internal variable shunt capacitor, which is instrumental in matching the PA to the antenna, is controlled by setting 5 bits in the configuration 0 register. This allows for 32 levels of shunt capacitance control. Since the control of these 5 bits is independent of the other settings, any capacitance value can be chosen at any frequency, making it possible to maintain maximum transmitter efficiency while moving rapidly from one frequency to another. MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Table 3. Register Configuration NAME ADDRESS DATA BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 MODE CONTRL 0x00 0 0 spioffsht pllbw shape ckouts ckouton mode R/W CONFIG0 0x01 ckdiv[2] ckdiv[1] ckdiv[0] cap[4] cap[3] cap[2] cap[1] cap[0] R/W HIFREQ1 0x02 fhi[15] fhi[14] fhi[13] fhi[12] fhi[11] fhi[10] fhi[9] fhi[8] R/W HIFREQ0 0x03 fhi[7] fhi[6] fhi[5] fhi[4] fhi[3] fhi[2] fhi[1] fhi[0] R/W LOFREQ1 0x04 flo[15] flo[14] flo[13] flo[12] flo[11] flo[10] flo[9] flo[8] R/W LOFREQ0 0x05 flo[7] flo[6] flo[5] flo[4] flo[3] flo[2] flo[1] flo[0] R/W FLOAD 0x06 -- -- -- -- -- -- -- fload R/W DATAIN 0x07 -- -- -- -- -- -- -- datain_bit R/W EN 0x08 -- -- -- -- -- -- -- enable_bit R/W CONFIG1 0x09 0 0 0 0 0 gposel[2] gposel[1] gposel[0] R/W STATUS 0x0C fhi/lo[15] fhi/lo[14] X 0 TxREADY NoXTAL R fhi/lo[13] fhi/lo[12] Table 4. Control Register (Address: 0x00) BIT NAME 0 mode FUNCTION 1 ckouton 2 ckouts Crystal clock output enable(1) while part is in shutdown mode 3 shape Disable(0) or enable(1) transmitter envelope-shaping resistor 4 pllbw PLL bandwidth setting, low(0) = 300kHz or high(1) = 600kHz; 300kHz is recommended for fractional-N and 600kHz for fixed-N 5 spioffsht ASK(0) or FSK(1) Crystal clock output enable(1) on GPO output Enable(0) or disable(1) SPI communication during shutdown Table 5. Configuration 0 Register (Address: 0x01) 14 BIT NAME 4-0 cap[4:0] 7-5 ckdiv[2:0] FUNCTION 5-bit capacitor setting 3-bit clock output frequency divider ______________________________________________________________________________________ 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter MAX7057 Table 6. ckdiv[2:0] of Configuration 0 Register (Address: 0x01) DECIMAL BINARY CRYSTAL FREQUENCY DIVIDED BY 0 000 1 1 001 2 2 010 4 3 011 8 4-7 1XX 16 Table 7. High-Frequency 1 Register (Address: 0x02) BIT NAME 7-0 fhi[15:8] FUNCTION 8-bit upper byte of high-frequency divider for FSK The 4 MSBs of HIFREQ1 (fhi[15:12]) are the integer portion of the divider, excluding offset of 16. The 12 LSBs (fhi[11:0]) are the fractional part of the divider. Table 8. High-Frequency 0 Register (Address: 0x03) BIT NAME 7-0 fhi[7:0] FUNCTION 8-bit lower byte of high-frequency divider for FSK Table 9. Low-Frequency 1 Register (Address: 0x04) BIT NAME 7-0 flo[15:8] FUNCTION 8-bit upper byte of low-frequency divider for FSK/ASK The 4 MSBs of LOFREQ1 (flo[15:12]) are the integer portion of the divider, excluding offset of 16. The 12 LSBs (flo[11:0]) are the fractional part of the divider. Valid values for the divider are shown in Table 11. Table 10. Low-Frequency 0 Register (Address: 0x05) BIT NAME 7-0 flo[7:0] FUNCTION 8-bit lower byte of low-frequency divider for FSK/ASK Table 11. Maximum and Minimum Values for Frequency Divide DECIMAL VALUE fhi[15:12], flo[15:12] fhi[11:0], flo[11:0] 12.0220 0xC 0x05A 2.9536 0x2 0xF42 ______________________________________________________________________________________ 15 MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter These values are internally summed with 16, and thus, the min and max divider becomes approximately 19 and 28. These limits MUST be followed, to prevent the delta-sigma number generator from overflowing. Whenever all of the fhi[11:0] and flo[11:0] are zero, only an integer divider is used, and the delta-sigma modulator is not in operation. This allows lower current operation. The 600kHz PLL bandwidth could be used in this mode to reduce phase noise. Table 12. Frequency Load Register (Address: 0x06) BIT 0 NAME fload FUNCTION Effectively changes the PLL frequency to the ones written in registers 2-5. This is a self-reset bit, and is reset to zero after the operation is completed. Table 13. Data In Register (Address: 0x07) BIT NAME 0 datain_bit FUNCTION SPI equivalent of DIN, where the transmitted data can be controlled through the SPI interface. It should be kept low (0) if only the external DIN pin is used. The external DIN pin should also be kept low (0) if the SPI datain_bit is used. Table 14. Enable Register (Address: 0x08) BIT 0 NAME enable_bit FUNCTION SPI equivalent of ENABLE. It should be kept low (0) if the external ENABLE pin is used. The external ENABLE pin should also be kept low (0) if the SPI enable_bit is used. Table 15. Configuration 1 Register (Address: 0x09) BIT NAME 2-0 gposel[2:0] 7-3 FUNCTION 3-bit GPO selector RESERVED "0" RESERVED. Set to 0 for normal operation. Table 16. General-Purpose Output Selector (gposel[2:0]) for Configuration 1 Register DECIMAL BINARY GPO 0 000 CKOUT_SDO 1 001 SDO 16 DESCRIPTION Clock/SDO Output. Outputs clock when CS is high and clock output is enabled; outputs SDO when CS is low. SPI Serial Data Output (SDO) 2 010 CKOUT 3 011 RESERVED RESERVED Clock Output 4 100 RESERVED RESERVED 5 101 NoXTAL Internal Crystal Oscillator Status. High means oscillator is NOT in operation. 6 110 TxREADY Transmitter Ready Status. High means PLL is locked and MAX7057 is ready to transmit data. 7 111 datain_bit A copy of datain_bit ______________________________________________________________________________________ 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter MAX7057 Table 17. Status Register (Address: 0x0C) BIT NAME 0 NoXTAL 1 TxREADY 2 RESERVED "0" 3 X 7-4 FUNCTION Internal Crystal Oscillator Status. High means oscillator is not in operation. Transmitter Ready Status. High means PLL is locked and MAX7057 is ready to transmit data. RESERVED. Set to 0 for normal operation. RESERVED fhi/lo[15]-fhi/lo[12] ASK mode: Outputs flo[15:12]. FSK mode: when datain pin/bit is high, outputs fhi[15:12]; when datain pin/bit is low, outputs flo[15:12]. Applications Information Output Matching to 50 When matched to a 50 system, the MAX7057's PA is capable of delivering +9.2dBm of output power at PAVDD = +2.7V with a broadband match. The output of the PA is an open-drain transistor, which has internal selectable shunt tuning capacitors (see the Variable Capacitor section) for impedance matching. It is connected to PAVDD or ROUT through a pullup inductor for proper biasing. The internal selectable shunt capacitors make it easy for tuning when changing the output frequency. The pullup inductor from the PA to PAVDD or ROUT serves three main purposes: resonating the capacitive PA output, providing biasing for the PA, and acting as a high-frequency choke to prevent RF energy from coupling onto the supply voltage. The pi network between the PA output and the antenna also forms a lowpass filter that provides attenuation for the higherorder harmonics. Output Matching to PCB Loop Antenna In many applications, the MAX7057 must be impedance-matched to a small-loop antenna. The antenna is usually fabricated out of a copper trace on a PCB in a rectangular, circular, or square pattern. The antenna has an impedance that consists of a lossy component and a radiative component. To achieve high radiating efficiency, the radiative component should be as high as possible, while minimizing the lossy component. In addition, a loop antenna has an inherent loop inductance associated with it (assuming the antenna is terminated to ground). In a typical application, the inductance of the loop antenna is approximately 50nH to 100nH. The radiative and lossy impedances can be anywhere from a few tenths of an ohm to 5 or 10. Layout Considerations A properly designed PCB is an essential part of any RF/microwave circuit. At high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. At high frequencies, trace lengths that are in the order of /10 or longer act as antennas, where is the wavelength. Keeping the traces short also reduces parasitic inductance. Generally, 1in of PCB trace adds about 20nH of parasitic inductance. The parasitic inductance can have a dramatic effect on the effective inductance of a passive component. For example, a 0.5in trace connecting to a 100nH inductor adds an extra 10nH of inductance, or 10%. To reduce parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. Using a solid ground plane can reduce the parasitic inductance from approximately 20nH/in to 7nH/in. Also, use low-inductance connections to the ground plane, and place decoupling capacitors as close as possible to all VDD pins. ______________________________________________________________________________________ 17 MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Typical Application Circuit SCLK SDI CS 3 4 C1 L1 RFOUT C3 5 2 1 SDI CS VDD DVDD SCLK C12 PAOUT GPO MAX7057 L2 DGND C5 C4 6 ROUT DIN VDD ENABLE 7 C7 C13 PAGND C2 R1 16 AGND PAVDD AVDD 8 C6 VDD C9 XTAL2 9 C15 GPO 14 13 12 DIN ENABLE 11 XTAL1 10 C10 C8 15 C11 Y1 C14 Component List DESIGNATION 18 QTY DESCRIPTION C1, C2 1 10pF 5%, 50V C0G ceramic capacitors (0603) Murata GRM1885C1H100J C3 1 6.8pF 5%, 50V C0G ceramic capacitor (0603) Murata GRM1885C1H6R8J C4, C7 2 220pF 5%, 50V C0G ceramic capacitors (0603) Murata GRM1885C1H221J C5 1 680pF 5%, 50V C0G ceramic capacitor (0603) Murata GRM1885C1H681J C6, C9, C12 3 10nF 10%, 50V X7R ceramic capacitors (0603) Murata GRM188R71H103K C8, C13 2 100nF 10%, 50V X7R ceramic capacitors (0603) Murata GRM188R71H104K C10, C11 2 100pF 5%, 50V C0G ceramic capacitors (0603) Murata GRM1885C1H101J C14, C15 2 4pF 5%, 50V C0G ceramic capacitors (0603) Murata GRM1885C1H4R0C L1 1 22nH 5% wire-wound inductor (0603) Murata LQW18AN22NJ00 L2 1 13nH 5% wire-wound inductor (0603) Murata LQW18AN13NJ00 R1 1 0 resistor (0603) Y1 1 16MHz crystal Crystek 17466, Suntsu SCX284 ______________________________________________________________________________________ 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter SCLK 3 SDI 2 CS 1 DVDD 16 14 DGND MAX7057 SERIAL INTERFACE AND DIGITAL CONTROL PAGND 4 13 DIN 12 ENABLE DELTA-SIGMA MODULATOR FREQUENCY DIVIDER PAOUT 5 PA VCO ROUT 6 15 GPO ENVELOPE SHAPING LOOP FILTER PFD CHARGE PUMP 7 8 PAVDD AVDD CRYSTAL OSCILLATOR 9 11 AGND 10 XTAL2 XTAL1 Package Information Chip Information PROCESS: CMOS For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 16 SO S16+3 21-0041 90-0097 ______________________________________________________________________________________ 19 MAX7057 Functional Diagram MAX7057 300MHz to 450MHz Frequency-Programmable ASK/FSK Transmitter Revision History REVISION NUMBER REVISION DATE 0 5/08 Initial release 4/11 Added reflow soldering information to Absolute Maximum Ratings, added bandwidth notation to TOC21, and corrected SPI format in Figure 2 1 DESCRIPTION PAGES CHANGED -- 2, 7, 11 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.