Application Information
SIMPLE NEGATIVE VOLTAGE CONVERTER
The main application of LM2662/LM2663 is to generate a
negative supply voltage. The voltage inverter circuit uses
only two external capacitors as shown in the Basic Applica-
tion Circuits. The range of the input supply voltage is 1.5V to
5.5V. For a supply voltage less than 3.5V, the LV pin must be
connected to ground to bypass the internal regulator cir-
cuitry. This gives the best performance in low voltage appli-
cations. If the supply voltage is greater than 3.5V, LV may be
connected to ground or left open. The choice of leaving LV
open simplifies the direct substitution of the LM2662/
LM2663 for the LMC7660 Switched Capacitor Voltage Con-
verter.
The output characteristics of this circuit can be approximated
by an ideal voltage source in series with a resistor. The
voltage source equals −(V+). The output resistance R
out
is a
function of the ON resistance of the internal MOS switches,
the oscillator frequency, and the capacitance and ESR of C
1
and C
2
. Since the switching current charging and discharg-
ing C
1
is approximately twice as the output current, the effect
of the ESR of the pumping capacitor C
1
is multiplied by four
in the output resistance. The output capacitor C
2
is charging
and discharging at a current approximately equal to the
output current, therefore, its ESR only counts once in the
output resistance. A good approximation is:
where R
SW
is the sum of the ON resistance of the internal
MOS switches shown in
Figure 2
.
High value, low ESR capacitors will reduce the output resis-
tance. Instead of increasing the capacitance, the oscillator
frequency can be increased to reduce the 2/(f
osc
xC
1
) term.
Once this term is trivial compared with R
SW
and ESRs,
further increasing in oscillator frequency and capacitance will
become ineffective.
The peak-to-peak output voltage ripple is determined by the
oscillator frequency, and the capacitance and ESR of the
output capacitor C
2
:
Again, using a low ESR capacitor will result in lower ripple.
POSITIVE VOLTAGE DOUBLER
The LM2662/LM2663 can operate as a positive voltage dou-
bler (as shown in the Basic Application Circuits). The dou-
bling function is achieved by reversing some of the connec-
tions to the device. The input voltage is applied to the GND
pin with an allowable voltage from 2.5V to 5.5V. The V+ pin
is used as the output. The LV pin and OUT pin must be
connected to ground. The OSC pin can not be driven by an
external clock in this operation mode. The unloaded output
voltage is twice of the input voltage and is not reduced by the
diode D
1
’s forward drop.
The Schottky diode D
1
is only needed for start-up. The
internal oscillator circuit uses the V+ pin and the LV pin
(connected to ground in the voltage doubler circuit) as its
power rails. Voltage across V+ and LV must be larger than
1.5V to insure the operation of the oscillator. During start-up,
D
1
is used to charge up the voltage at V+ pin to start the
oscillator; also, it protects the device from turning-on its own
parasitic diode and potentially latching-up. Therefore, the
Schottky diode D
1
should have enough current carrying
capability to charge the output capacitor at start-up, as well
as a low forward voltage to prevent the internal parasitic
diode from turning-on. A Schottky diode like 1N5817 can be
used for most applications. If the input voltage ramp is less
than 10V/ms, a smaller Schottky diode like MBR0520LT1
can be used to reduce the circuit size.
SPLIT V+ IN HALF
Another interesting application shown in the Basic Applica-
tion Circuits is using the LM2662/LM2663 as a precision
voltage divider. Since the off-voltage across each switch
equals V
IN
/2, the input voltage can be raised to +11V.
CHANGING OSCILLATOR FREQUENCY
For the LM2662, the internal oscillator frequency can be
selected using the Frequency Control (FC) pin. When FC is
open, the oscillator frequency is 20 kHz; when FC is con-
nected to V+, the frequency increases to 150 kHz. A higher
oscillator frequency allows smaller capacitors to be used for
equivalent output resistance and ripple, but increases the
typical supply current from 0.3 mA to 1.3 mA.
The oscillator frequency can be lowered by adding an exter-
nal capacitor between OSC and GND (See typical perfor-
mance characteristics). Also, in the inverter mode, an exter-
nal clock that swings within 100 mV of V+ and GND can be
used to drive OSC. Any CMOS logic gate is suitable for
driving OSC. LV must be grounded when driving OSC. The
maximum external clock frequency is limited to 150 kHz.
The switching frequency of the converter (also called the
charge pump frequency) is half of the oscillator frequency.
Note: OSC cannot be driven by an external clock in the voltage-doubling
mode.
TABLE 1. LM2662 Oscillator Frequency Selection
FC OSC Oscillator
Open Open 20 kHz
V+ Open 150 kHz
Open or V+ External Capacitor See Typical
Performance
Characteristics
N/A External Clock External Clock
(inverter mode only) Frequency
TABLE 2. LM2663 Oscillator Frequency Selection
OSC Oscillator
Open 150 kHz
External
Capacitor See Typical Performance
Characteristics
External Clock External Clock Frequency
(inverter mode only)
SHUTDOWN MODE
For the LM2663, a shutdown (SD) pin is available to disable
the device and reduce the quiescent current to 10 µA. Ap-
plying a voltage greater than 2V to the SD pin will bring the
device into shutdown mode. While in normal operating
mode, the SD pin is connected to ground.
LM2662/LM2663
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