SEMICONDUCTOR
10-12
August 1997
HI-565A
High Speed, Monolithic D/A
Converter with Reference
Features
• 12-Bit DAC and Reference on a Single Chip
• Pin Compatible With AD565A
• Very High Speed: Settles to ±0.5 LSB in 250ns (Max)
Full Scale Switching Time 30ns (Typ)
• Guaranteed For Operation With ±12V Supplies
• Monotonicity Guaranteed Over Temperature
• Nonlinearity Guaranteed Over Temp (Max) . . ±0.5 LSB
• Low Gain Drift (Max, DAC Plus Ref) . . . . . . 25ppm/oC
• Low Power Dissipation . . . . . . . . . . . . . . . . . . . .250mW
Applications
• CRT Displays
• High Speed A/D Converters
• Signal Reconstruction
• Waveform Synthesis
Description
The HI-565A is a f ast, 12-bit, current output, digital-to-analog
converter. The monolithic chip includes a precision voltage
reference, thin-film R2R ladder, reference control amplifier
and twelve high speed bipolar current switches.
The Harris dielectric isolation process provides latch free
operation while minimizing stray capacitance and leakage
currents, to produce an excellent combination of speed and
accuracy. Also, ground currents are minimized to produce a
low and constant current through the ground terminal, which
reduces error due to code dependent ground currents.
HI-565A dice are laser trimmed for a maximum integral
non-linearity error of ±0.5 LSB at 25oC. In addition, the low
noise buried zener reference is trimmed both for absolute
value and temperature coefficient. Power dissipation is
typically 250mW, with ±15V supplies.
The HI-565A is offered in both commercial and military
grades. See Ordering Information.
Ordering Information
PART NUMBER LINEARITY (INL) LINEARITY (DNL) TEMP. RANGE (oC) PACKAGE PKG. NO.
HI1-565AJD-5 0.50 LSB 0.75 LSB 0 to 75 24 Ld SBDIP D24.6
HI1-565AKD-5 0.25 LSB 0.50 LSB 0 to 75 24 Ld SBDIP D24.6
HI1-565ASD-2 0.50 LSB 0.75 LSB -55 to 125 24 Ld SBDIP D24.6
HI1-565ATD-2 0.25 LSB 0.50 LSB -55 to 125 24 Ld SBDIP D24.6
HI1-565ASD/883 0.50 LSB 0.50 LSB -55 to 125 24 Ld SBDIP D24.6
HI1-565ATD/883 0.25 LSB 0.50 LSB -55 to 125 24 Ld SBDIP D24.6
Pinout
HI-565A (SBDIP)
TOP VIEW
Functional Diagram
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
VCC
REF OUT (+10V)
REF GND
REF IN
-VEE
BIPOLAR R IN
IDAC OUT
10V SPAN R
20V SPAN R
POWER GND
16
17
18
19
20
21
22
23
24
15
14
13
BIT 1 (MSB) IN
BIT 3 IN
BIT 4 IN
BIT 5 IN
BIT 6 IN
BIT 8 IN
BIT 10 IN
BIT 11 IN
BIT 12 (LSB) IN
BIT 2 IN
BIT 7 IN
BIT 9 IN
REF VCC
43
+
-
6
REF
IN 19.95K
5
REF
GND
3.5K
3K
IREF 0.5mA
712
-VEE PWR
GND MSB LSB
HI-565A
24 . . . . . .13
BIP. OFF8
9.95K
DAC IO
(4X IREF
X CODE)
1120V
SPAN
10V
SPAN
OUT
10
9
2.5K
5K
5K
OUT
+
-
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997 File Number 3109.1
10-13
Absolute Maximum Ratings Thermal Information
VCC to Power GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +18V
VEE to Power GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to -18V
Voltage on DAC Output (Pin 9). . . . . . . . . . . . . . . . . . . .-3V to +12V
Digital Inputs (Pins 13-24) to Power GND . . . . . . . . . . -1V to +7.0V
REF In to REF GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±12V
Bipolar Offset to REF GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±12V
10V Span R to REF GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±12V
20V Span R to REF GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±24V
REF Out . . . . . . . . . . . . . . . . . . . . . . Indefinite Short to Power GND
Momentary Short to VCC
Operating Conditions
Temperature Ranges
HI-565AS,T-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
H1-565AJ, K-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 75oC
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
SBDIP Package. . . . . . . . . . . . . . . . . . 75 30
Maximum Package Power Dissipation
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500mW
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .175oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA = 25oC, VCC = +15V, VEE = -15V, Unless Otherwise Specified
PARAMETER TEST CONDITIONS
HI-565AJ, HI565AS HI-565AK, HI-565AT
UNITSMIN TYP MAX MIN TYP MAX
DATA INPUTS (Pins 13 to 24) (Note 1)
Input Voltage Bit ON Logic “1” (TMlN to TMAX) +2.0 - +5.5 +2.0 - +5.5 V
Input Voltage Bit OFF Logic “0” (TMlN to TMAX) - - +0.8 - - +0.8 V
Logic Current Bit ON Logic “1” (TMlN to TMAX) - 0.01 +1.0 - 0.01 +1.0 µA
Logic Current Bit OFF Logic “0” (TMlN to TMAX) - -2.0 -20 - -2.0 -20 µA
Resolution 12 - - 12 - - Bits
OUTPUT
Unipolar Current (All Bits ON) -1.6 -2.0 -2.4 -1.6 -2.0 -2.4 mA
Bipolar Current (All Bits ON or OFF) ±0.8 ±1.0 ±1.2 ±0.8 ±1.0 ±1.2 mA
Resistance (Exclusive of Span
Resistors) 1.8K 2.5K 3.2K 1.8K 2.5K 3.2K Ω
Unipolar Offset at 25oC±0.07oC
Over Temperature - 0.01 0.05 - 0.01 0.05 % of FS
Bipolar Offset at ±0.2 (T), ±0.25 (S)
Over Temperature (Figure 2, R3= 50Ω
Fixed) - 0.05 0.15 - 0.05 0.1 % of FS
Capacitance - 20 - - 20 - pF
Compliance Voltage (TMIN to TMAX) -1.5 - +10 -1.5 - +10 V
ACCURACY (Error Relative to Full Scale)
Integral Non-Linearity (25oC)
End Point Method -±0.25
(0.006) ±0.50
(0.012) -±0.12
(0.003) ±0.12
(0.006) LSB
% of FS
Integral Non-Linearity (TMIN to TMAX)
End Point Method -±0.50
(0.012) ±0.75
(0.018) -±0.25
(0.006) ±0.50
(0.012) LSB
% of FS
Differential Non-Linearity 25oC-±0.50 ±0.75 - ±0.25 ±0.50 LSB
Differential Non-Linearity TMIN to TMAX MONOTONICITY GUARANTEED
TEMPERATURE COEFFIClENTS
With Internal Reference Unipolar Zero - 1 2 - 1 2 ppm/oC
HI-565A
10-14
With Internal Reference Bipolar Zero - 5 10 - 5 10 ppm/oC
With Internal Reference Gain (Full Scale) - 15 40 - 10 25 ppm/oC
With Internal Reference Differential
Nonlinearity - 2 - - 2 - ppm/oC
SETTLING TIME T0 ±0.5 LSB
With High, Z External Load (Note 2) - 350 500 - 350 500 ns
With 75Ω External Load - 150 250 - 150 250 ns
FULL SCALE TRANSITION From 50% of Logic Input to 90% of Analog Output
Rise Time - 15 30 - 15 30 ns
Fall Time - 30 50 - 30 50 ns
POWER REQUIREMENTS
VCC (+11.4 to +16.5VDC) - 9.0 11.8 - 9.0 11.8 mA
VEE (+11.4 to -16.5VDC) - -9.5 -14.5 - -9.5 -14.5 mA
POWER SUPPLY GAIN SENSITIVITY (Note 3)
VCC (+11.4 to +16.5VDC) - 3 10 - 3 10 ppm of
FS/%
VEE (+11.4 to -16.5VDC) - 15 25 - 15 25 ppm of
FS/%
PROGRAMMABLE OUTPUT RANGES (See Table 2)
Unipolar 5 (Note 1) 0 to +5 0 to +5 V
Bipolar 5 (Note 1) -2.5 to +2.5 -2.5 to +2.5 V
Unipolar 10 (Note 1) 0 to +10 0 to +10 V
Bipolar 10 (Note 1) -5 to +5 -5 to +5 V
Bipolar 20 (Note 1) -10 to +10 -10 to +10 V
EXTERNAL ADJUSTMENTS
Gain Error with Fixed 50Ω Resister
for R2 (Figure 1) -±0.1 ±0.25 - ±0.1 ±0.25 % of FS
Bipolar Zero Error with Fixed 50Ω
Resister for R3 (Figure 2) -±0.05 ±0.15 - ±0.05 ±0.1 % of FS
Gain Adjustment Range (Figure 1) ±0.25 - - ±0.25 - - % of FS
Bipolar Zero Adjustment Range ±0.15 - - ±0.15 - - % of FS
REFERENCE INPUT
Input Impedance 15K 20K 25K 15K 20K 25K -
REFERENCE OUTPUT
Voltage 9.90 10.00 10.10 9.90 10.00 10.10 V
Current (Available for External Loads) 1.5 2.5 - 1.5 2.5 - mA
NOTES:
1. Guaranteed by characterization or design but not tested over the operating temperature range.
2. See settling time discussion and Figure 3.
3. The Power Supply Gain Sensitivity is tested in reference to a VCC, VEE of ±15V.
Electrical Specifications TA = 25oC, VCC = +15V, VEE = -15V, Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS
HI-565AJ, HI565AS HI-565AK, HI-565AT
UNITSMIN TYP MAX MIN TYP MAX
HI-565A
10-15
Definitions of Specifications
Digital Inputs
The HI-565A accepts digital input codes in binary f ormat and
may be user connected for any one of three binary codes.
Straight Binary, Two’s Complement (Note 1), or Offset
Binary, (See Operating Instructions).
Nonlinearity of a D/A conver ter is an impor tant measure of
its accuracy. It describes the deviation from an ideal straight
line transfer curve drawn between zero (all bits OFF) and full
scale (all bits ON) (End Point Method).
Differential Nonllnearlty for a D/A converter, it is the
difference between the actual output voltage change and the
ideal (1 LSB) voltage change for a one bit change in code. A
Diff erential Nonlinearity of ±1 LSB or less guarantees monoto-
nicity; i.e., the output alw ays increases for an increasing input.
Settling Time is the time required for the output to settle to
within the specified error band for any input code transition.
It is usually specified for a full scale or major carry transition,
settling to within ±0.5 LSB of final value.
Gain Drift is the change in full scale analog output over the
specified temperature range, expressed in parts per million
of full scale range per oC (ppm of FSR/oC). Gain error is
measured with respect to 25oC at high (TH) and low (TL)
temperatures. Gain drift is calculated for both high (TH
-25oC) and low ranges (25oC -TL) by dividing the gain error
by the respectiv e change in temper ature. The specification is
the larger of the two representing worst-case drift.
Offset Drift is the change in analog output with all bits OFF
over the specified temperature range expressed in parts per
million of full scale range per oC (ppm of FSR/oC). Offset
error is measured with respect to 25oC at high (TH) and low
(TL) temperatures. Offset Drift is calculated for both high (TH
-25oC) and low (25oC -TL) ranges by dividing the offset error
by the respective change in temperature. The specification
given is the larger of the tw o, representing worst-case drift.
Power Supply Sensitivity is a measure of the change in
gain and offset of the D/A converter resulting from a change
in -15V or +15V supplies. It is specified under DC conditions
and expressed as parts per million of full scale range per
percent of change in power supply (ppm of FSR/%).
Compliance Voltage is the maximum output voltage range
that can be tolerated and still maintain its specified accuracy.
Compliance Limit implies functional operation only, and
makes no claims to accuracy.
Glitch a glitch on the output of a D/A converter is a transient
spike resulting from unequal internal ON-OFF switching
times. Worst case glitches usually occur at half-scale or the
major carry code transition from 011...1 to 100...0 or vice
versa. For example, if turn ON is greater than turn OFF for
011...1 to 100...0, an intermediate state of 000...0 exists,
such that, the output momentarily glitches toward zero out-
put. Matched switching times and fast switching will reduce
glitches considerably.
Detailed Description
Op Amp Selection
The Hl-565As current output may be converted to voltage
using the standard connections shown in Figures 1 and 2.
The choice of operational amplifier should be reviewed for
each application, since a significant trade-off may be made
between speed and accuracy.
For highest precision, use an HA-5130. This amplifier
contributes negligible error, but requires about 11µs to settle
within ±0.1% following a 10V step.
The Harris Semiconductor HA-2600 is the best all-around
choice for this application, and it settles in 1.5µs (also to
±0.1% f ollo wing a 10V step). Remember, settling time f or the
DAC amplifier combination is the square root of tD2 plus tA2,
where tD, tA are settling times for the DAC and amplifier.
No-Trim Operation
The Hl-565A will perform as specified without calibration
adjustments. To operate without calibration, substitute 50Ω
resistors for the 100Ω trimming potentiometers: In Figure 1
replace R2 with 50Ω also remove the network on pin 8 and
connect 50Ω to ground. For bipolar operation in Figure 2,
replace R3 and R4 with 50Ω resistors.
With these changes, performance is guaranteed as shown
under Specifications, “External Adjustments”. Typical unipolar
zero will be ±0.5 LSB plus the op amp offset.
The feedback capacitor, C, must be selected to minimize
settling time.
Calibration
Calibration provides the maximum accuracy from a
conver ter by adjusting its gain and offset errors to zero. For
the Hl-565A, these adjustments are similar whether the
current output is used, or whether an external op amp is
added to convert this current to a voltage. Refer to Table 2
for the voltage output case, along with Figure 1 or Figure 2.
Calibration is a two step process for each of the five output
ranges shown in Table 2. First adjust the negative full scale
(zero for unipolar ranges). This is an offset adjust which
translates the output characteristic, i.e ., affects each code by
the same amount.
Ne xt adjust positive FS. This is a gain error adjustment, which
rotates the output characteristic about the negative FS value.
TABLE 1.
DIGITAL
INPUT
ANALOG OUTPUT
STRAIGHT
BINARY OFFSET
BINARY
(NOTE 1)
TWO'S
COMPLEMENT
MSB...LSB
000...000 Zero -FS
(Full Scale) Zero
100...000 1/2FS Zero -FS
111...111 +FS - 1 LSB +FS - 1 LSB Zero - 1 LSB
011...111 1/2FS - 1 LSB Zero - 1 LSB +FS - 1 LSB
NOTE:
1. Invert MSB with external inverter to obtain Two’ s Complement
Coding.
HI-565A
10-16
For the bipolar ranges, this approach leaves an error at the
zero code , whose maximum value is the same as for integral
nonlinearity error. In general, only two values of output may
be calibrated exactly; all others must tolerate some error.
Choosing the extreme end points (plus and minus full scale)
minimizes this distributed error for all other codes.
TABLE 2. OPERATING MODES AND CALIBRATION
MODE
CIRCUIT CONNECTIONS CALIBRATION
OUTPUT
PRANGE PIN 10 TO PIN 11 TO RESlSTOR (R) APPLY
INPUT CODE ADJUST TO SET
VO
Unipolar
(See Figure 1) 0 to +10V VOPin 10 1.43K All 0’s
All 1’s R1
R2 0V
+9.99756V
0 to +5V VOPin 9 1.1K All 0’s
All 1’s R1
R2 0V
+4.99878V
Bipolar
(See Figure 2) ±10V NC VO1.69K All 0’s
All 1’s R3
R4 -10V
+9.99512V
±5V VOPin 10 1.43K All 0’s
All 1’s R3
R4 -5V
+4.99756V
±2.5V VOPin 9 1.1K All 0’s
All 1’s R3
R4 -2.5V
+2.49878V
REF OUT
x CODE)
(4 x IREF
IO
3.5K
3K CODE
INPUT
DAC
2.5K
5K 9
DAC
OUT
C
9.95K
5K 10
11 20V SPAN
10V SPAN VO
R (SEE
0.5mA
IREF
HI-565A
19.95K
+
-
43
6
5
8
BIP.
OFF.
VCC
71224 13
MSB LSB
REF
GND
REF
IN
10V
-VEE PWR
GND
R4
100Ω
TABLE 2)
+
-
+
-
+15V
-15V
100kΩ
100Ω50kΩ
R1
FIGURE 1. UNIPOLAR VOLTAGE OUTPUT
REF OUT
x CODE)
(4 x IREF
IO
3.5K
3K CODE
INPUT
DAC
2.5K
5K 9
DAC
OUT
C
9.95K
5K 10
11 20V SPAN
10V SPAN VO
R (SEE
0.5mA
IREF
HI-565A
19.95K
+
-
43
6
5
8
BIP.
OFF.
VCC
71224 13
MSB LSB
REF
GND
REF
IN
100Ω
10V
-VEE PWR
GND
R4
100Ω
R3
TABLE 2)
+
-
+
-
FIGURE 2. BIPOLAR VOLTAGE OUTPUT
HI-565A
10-17
Settling Time
This is a challenging measurement, in which the result
depends on the method chosen, the precision and quality of
test equipment and the operating configuration of the DAC
(test conditions). As a result, the different techniques in use
by converter manufacturers can lead to consistently different
results. An engineer should understand the advantage and
limitations of a given test method before using the specified
settling time as a basis for design.
The approach used for several years at Harris Analog
Products Division calls f or a strobed comparator to sense final
perturbations of the D A C output wa v ef orm. This gives the LSB
a reasonable magnitude (814µV for the HI-565A), which pro-
vides the comparator with enough overdrive to establish an
accurate ±0.5 LSB window about the final settled value. Also,
the required test conditions simulate the DACs environment
f or a common application - use in a successive approximation
A/D converter. Considerable experience has shown this to be
a reliable and repeatable way to measure settling time.
The usual specification is based on a 10V step, produced by
simultaneously switching all bits from off-to-on (tON) or on-
to-off (tOFF). The slower of the two cases is specified, as
measured from 50% of the digital input transition to the final
entry within a window of ±0.5 LSB about the settled value.
Four measurements characterize a given type of DAC:
(a) tON, to final value +0.5 LSB
(b) tON, to final value -0.5 LSB
(c) tOFF, to final value +0.5 LSB
(d) tOFF, to final value -0.5 LSB
(Cases (b) and (c) may be eliminated unless the overshoot
exceeds 0.5 LSB). For example, refer to Figure 3 for the
measurement of case (d).
Procedure
As shown in Figure 3B, settling time equals tX plus the
comparator delay (tD = 15ns). To measure tX:
• Adjust the delay on generator No. 2 for a tX of several
microseconds. This assures that the DAC output has
settled to its final value.
• Switch on the LSB (+5V).
• Adjust the VLSB supply for 50% triggering at COMPARATOR
OUT. This is indicated by traces of equal brightness on the
oscilloscope display as shown in Figure 3B. Note DVM
reading.
• Switch the LSB to Pulse (P).
• Readjust the VLSB supply for 50% triggering as before,
and note DVM reading. One LSB equals one tenth the dif-
ference in the DVM readings noted above.
• Adjust the VLSB supply to reduce the DVM reading by 5
LSBs (DVM reads 10X, so this sets the comparator to
sense the final settled value minus 0.5 LSB). Comparator
output disappears.
• Reduce generator No. 2 delay until comparator output
reappears, and adjust for “equal brightness”.
• Measure tX from scope as shown in Figure 3B. Settling
time equals tX + tD, i.e., tX + 15ns.
FIGURE 3A. FIGURE 3B.
OUT PULSE
GENERATOR
NO. 1
PULSE
GENERATOR
NO. 2
20V ±20%
BIAS
TURN ON
TURN OFF
HI-565A
24
23
14
13
8
11
10
9
5
5K
5K
2.5K
9.95K
2mA
LSB 12
10 0.1µF
200K
SCHOTTKY
DIODES
STROBE
COMP
OUT
+5V
DVM
OUT
SYNC
TRIG
90
~100kHz
(A)
(B)
(C)
IN (D)
OUT
IN
NC
P
VLSB
SUPPLY
DIGITAL
INPUT
DAC
OUTPUT
COMP.
STROBE
EQUAL
COMP.
OUT
SETTLING TIME
tD = COMPARATOR DELAY
50%
-0.5 LSB
+3V
0V
0V
-400mV
2V
0.8V
4V
0V
tX
BRIGHTNESS
50%
(B)
(TURN
OFF)
(A)
(C)
(D)
HI-565A
10-18
Other Considerations
Grounds
The Hl-565A has two ground terminals, pin 5 (REF GND)
and pin 12 (PWR GND). These should not be tied together
near the package unless that point is also the system signal
ground to which all returns are connected. (If such a point
exists, then separate paths are required to pins 5 and 12).
The current through pin 5 is near-zero DC (Note 1); but pin
12 carries up to 1.75mA of code - ependent current from bits
1, 2, and 3. The general rule is to connect pin 5 directly to
the system “quiet” point, usually called signal or analog
ground. Connect pin 12 to the local digital or power ground.
Then, of course, a single path must connect the
analog/signal and digital/power grounds.
Layout
Connections to pin 9 (IOUT) on the Hl-565A are most critical
for high speed performance. Output capacitance of the DAC
is only 20pF, so a small change or additional capacitance
may alter the op amp’s stability and affect settling time.
Connections to pin 9 should be short and few. Component
leads should be shor t on the side connecting to pin 9 (as for
feedback capacitor C). See the Settling Time section.
Bypass Capacitors
P o wer supply b ypass capacitors on the op amp will serve the
HI-565A also. If no op amp is used, a 0.01µF ceramic
capacitor from each supply terminal to pin 12 is sufficient,
since supply current variations are small.
Current Cancellation
Current cancellation is a two step process within the
HI-565A in which code dependent variations are eliminated,
then the resulting DC current is supplied internally. First an
auxiliary 9-bit R-2R ladder is driven by the complement of
the DACs input code. Together, the main and auxiliary lad-
ders draw a continuous 2.25mA from the internal ground
node, regardless of input code. Part of this DC current is
supplied by the zener voltage reference, and the remainder
is sourced from the positive supply via a current mirror which
is laser trimmed for zero current through the external
terminal (pin 5).
HI-565A
10-19
Die Characteristics
DIE DIMENSIONS:
179 mils x 107 mils x 19 mils ±1 mil
METALLIZATION:
Type: Al
Thickness: 16kű2kÅ
PASSIVATION:
Type: Nitride Over Silox
Nitride Thickness: 3.5kű0.5kÅ
Silox Thickness: 12kű1.5kÅ
WORST CASE CURRENT DENSITY:
0.75 x 105 A/cm2
TRANSISTOR COUNT:
200
Metallization Mask Layout
HI-565A
V+
(MSB)
BIT 1 BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11BIT 12
(LSB)
POWER
GND
20V
SPAN
10V
SPAN
IDAC
OUT
BIPOLAR
12
-VS
VREF IN
VREF
GND
VREF OUT
HI-565A
