+
–
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY
OPERATIONAL AMPLIFIERS
Check for Samples: TLC080 ,TLC081,TLC082,TLC083,TLC084,TLC085,TLC08xA
1FEATURES DESCRIPTION
The first members of TI’s new BiMOS
23•Wide Bandwidth: 10 MHz general-purpose operational amplifier family are the
•High Output Drive: TLC08x. The BiMOS family concept is simple:
–IOH: 57 mA at VDD –1.5 V provide an upgrade path for BiFET users who are
moving away from dual-supply to single-supply
–IOL: 55 mA at 0.5 V systems and demand higher ac and dc performance.
•High Slew Rate: With performance rated from 4.5 V to 16 V across
–SR+: 16 V/µscommercial (0°C to 70°C) and an extended industrial
temperature range (–40°C to 125°C), BiMOS suits a
–SR–: 19 V/µswide range of audio, automotive, industrial, and
•Wide Supply Range: 4.5 V to 16 V instrumentation applications. Familiar features like
•Supply Current: 1.9 mA/Channel offset nulling pins, and new features like MSOP
PowerPAD™packages and shutdown modes, enable
•Ultralow Power Shutdown Mode: higher levels of performance in a variety of
–IDD: 125 µA/Channel applications.
•Low Input Noise Voltage: 8.5 nV√Hz Developed in TI’s patented LBC3 BiCMOS process,
•Input Offset Voltage: 60 µVthe new BiMOS amplifiers combine a very high input
•Ultra-Small Packages: impedance, low-noise CMOS front end with a
high-drive bipolar output stage, thus providing the
–8- or 10-Pin MSOP (TLC080/1/2/3) optimum performance features of both. AC
performance improvements over the TL08x BiFET
predecessors include a bandwidth of 10 MHz (an
increase of 300%) and voltage noise of 8.5 nV/√Hz
(an improvement of 60%). DC improvements include
an ensured VICR that includes ground, a factor of 4
reduction in input offset voltage down to 1.5 mV
(maximum) in the standard grade, and a power
supply rejection improvement of greater than 40 dB to
130 dB. Added to this list of impressive features is
the ability to drive ±50-mA loads comfortably from an
ultrasmall-footprint MSOP PowerPAD package, which
positions the TLC08x as the ideal high-performance
general-purpose operational amplifier family.
FAMILY PACKAGE TABLE
PACKAGE TYPES
NO. OF UNIVERSAL
DEVICE CHANNELS EVM BOARD
MSOP PDIP SOIC TSSOP SHUTDOWN
TLC080 1 8 8 8 —Yes
TLC081 1 8 8 8 —Refer to the EVM
TLC082 2 8 8 8 — — Selection Guide
TLC083 2 10 14 14 —Yes (Lit# SLOU060)
TLC084 4 14 14 20 —
TLC085 4 16 16 20 Yes
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright ©1999–2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
TLC080 and TLC081 AVAILABLE OPTIONS
PACKAGED DEVICES
TASMALL OUTLINE SMALL OUTLINE PLASTIC DIP
SYMBOL
(D)(1) (DGN)(1) (P)
TLC080CD TLC080CDGN xxTIACW TLC080CP
0°C to 70°CTLC081CD TLC081CDGN xxTIACY TLC081CP
TLC080ID TLC080IDGN xxTIACX TLC080IP
TLC081ID TLC081IDGN xxTIACZ TLC081IP
–40°C to 125°CTLC080AID — — TLC080AIP
TLC081AID — — TLC081AIP
(1) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC080CDR).
TLC082 and TLC083 AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL MSOP PLASTIC PLASTIC
TAOUTLINE DIP DIP
(DGN)(1) SYMBOL(2) (DGQ)(1) SYMBOL(2)
(D)(1) (N) (P)
TLC082CD TLC082CDGN xxTIADZ — — — TLC082CP
0°C to 70°CTLC083CD — — TLC083CDGQ xxTIAEB TLC083CN —
TLC082ID TLC082IDGN xxTIAEA — — — TLC082IP
TLC083ID — — TLC083IDGQ xxTIAEC TLC083IN —
–40°C to 125°CTLC082AID — — — — — TLC082AIP
TLC083AID — — — — TLC083AIN —
(1) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC082CDR).
(2) xx represents the device date code.
TLC084 and TLC085 AVAILABLE OPTIONS
PACKAGED DEVICES
TASMALL OUTLINE PLASTIC DIP TSSOP
(D)(1) (N) (PWP)(1)
TLC084CD TLC084CN TLC084CPWP
0°C to 70°CTLC085CD TLC085CN TLC085CPWP
TLC084ID TLC084IN TLC084IPWP
TLC085ID TLC085IN TLC085IPWP
–40°C to 125°CTLC084AID TLC084AIN TLC084AIPWP
TLC085AID TLC085AIN TLC085AIPWP
(1) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC084CDR).
space
For the most current package and ordering information, see the Package Option Addendum at the end of this
data sheet, or see the TI web site at www.ti.com.
2Submit Documentation Feedback Copyright ©1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
NC - No internal connection
1
2
3
4
8
7
6
5
NULL
IN
IN +
GND
SHDN
VDD
OUT
NULL
TLC080
D, DGN, OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NULL
IN
IN +
GND
NC
VDD
OUT
NULL
TLC081
D, DGN, OR P PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN
1IN+
GND
NC
1SHDN
NC
VDD
2OUT
2IN
2IN+
NC
2SHDN
NC
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN
1IN+
GND
VDD
2OUT
2IN
2IN+
TLC082
D, DGN, OR P PACKAGE
(TOP VIEW)
TLC083
D OR N PACKAGE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1OUT
1IN
1IN+
VDD
2IN+
2IN
2OUT
1/2SHDN
4OUT
4IN
4IN+
GND
3IN+
3IN
3OUT
3/4SHDN
(TOP VIEW)
TLC085
D OR N PACKAGE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN
1IN+
VDD
2IN+
2IN
2OUT
4OUT
4IN
4IN+
GND
3IN+
3IN
3OUT
(TOP VIEW)
TLC084
D OR N PACKAGE
1
2
3
4
5
10
9
8
7
6
1OUT
1IN
1IN+
GND
1SHDN
VDD
2OUT
2IN
2IN+
2SHDN
TLC083
DGQ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
(TOP VIEW)
TLC084
PWP PACKAGE
1OUT
1IN
1IN+
VDD
2IN+
2IN
2OUT
NC
NC
NC
4OUT
4IN
4IN+
GND
3IN+
3IN
3OUT
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OUT
1IN
1IN+
VDD
2IN+
2IN
2OUT
1/2SHDN
NC
NC
4OUT
4IN
4IN+
GND
3IN+
3IN
3OUT
3/4SHDN
NC
NC
(TOP VIEW)
TLC085
PWP PACKAGE
Printed or
Molded Dot Bevel Edges
Pin 1
Molded ”U” Shape
Pin 1
Stripe
Pin 1 Pin 1
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
TYPICAL PIN 1 INDICATORS
Copyright ©1999–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE UNIT
Supply voltage, VDD(2) 17 V
Differential input voltage range, VID ±VDD
Continuous total power dissipation See Dissipation Rating Table
C suffix 0 to 70 °C
Operating free-air temperature range, TA:I suffix −40 to 125 °C
Maximum junction temperature, TJ150 °C
Storage temperature range, Tstg –65 to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
(1) Stresses beyond those listed under “absolute maximum ratings”may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions”is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to GND .
DISSIPATION RATING TABLE
θJC θJA TA≤25°C
PACKAGE (°C/W) (°C/W) POWER RATING
D (8) 38.3 176 710 mW
D (14) 26.9 122.3 1022 mW
D (16) 25.7 114.7 1090 mW
DGN (8) 4.7 52.7 2.37 W
DGQ (10) 4.7 52.3 2.39 W
N (14, 16) 32 78 1600 mW
P (8) 41 104 1200 mW
PWP (20) 1.40 26.1 4.79 W
RECOMMENDED OPERATING CONDITIONS
MIN MAX UNIT
Single supply 4.5 16
Supply voltage, VDD V
Split supply ±2.25 ±8
Common-mode input voltage, VICR GND VDD–2 V
VIH 2
Shutdown on/off voltage level(1) V
VIL 0.8
C-suffix 0 70
Operating free-air temperature, TA°C
I-suffix –40 125
(1) Relative to the voltage on the GND terminal of the device.
4Submit Documentation Feedback Copyright ©1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT
TLC080/1/2/3, 25°C 390 1900
TLC084/5 Full range 3000
VIO Input offset voltage µV
VDD = 5 V, TLC080/1/2/3A, 25°C 390 1400
VIC = 2.5 V,
VO= 2.5 V, TLC084/5A Full range 2000
Temperature coefficient of RS= 50 Ω
∝VIO 1.2 µV/°C
input offset voltage 25°C 1.9 50
IIO Input offset current VDD = 5 V, TLC08XC 100 pA
Full range
VIC = 2.5 V, TLC08XI 700
VO= 2.5 V, 25°C 3 50
IIB Input bias current RS= 50 ΩTLC08XC 100 pA
Full range
TLC08XI 700
25°C 0 to 3.0 0 to 3.5
VICR Common-mode input voltage RS= 50 ΩV
Full range 0 to 3.0 0 to 3.5
25°C 4.1 4.3
IOH =–1 mA Full range 3.9
25°C 3.7 4
IOH =–20 mA Full range 3.5
VOH High-level output voltage VIC = 2.5 V V
25°C 3.4 3.8
IOH =–35 mA Full range 3.2
25°C 3.2 3.6
IOH =–50 mA –40°C to 3
85°C
25°C 0.18 0.25
IOL = 1 mA Full range 0.35
25°C 0.35 0.39
IOL = 20 mA Full range 0.45
VOL Low-level output voltage VIC = 2.5 V V
25°C 0.43 0.55
IOL = 35 mA Full range 0.7
25°C 0.45 0.63
IOL = 50 mA –40°C to 0.7
85°C
Sourcing 25°C 100
IOS Short-circuit output current mA
Sinking 25°C 100
VOH = 1.5 V from positive rail 25°C 57
IOOutput current mA
VOL = 0.5 V from negative rail 25°C 55
25°C 100 120
Large-signal differential
AVD VO(PP) = 3 V, RL= 10 kΩdB
voltage amplification Full range 100
ri(d) Differential input resistance 25°C 1000 GΩ
Common-mode input
CIC f = 10 kHz 25°C 22.9 pF
capacitance
Closed-loop output
zof = 10 kHz, AV= 10 25°C 0.25 Ω
impedance 25°C 80 110
CMRR Common-mode rejection ratio VIC = 0 to 3 V, RS= 50 ΩdB
Full range 80
VDD = 4.5 V to 16 V, VIC = VDD/2, 25°C 80 100
Supply voltage rejection ratio
kSVR dB
(ΔVDD /ΔVIO)No load Full range 80
(1) Full range is 0°C to 70°C for C suffix and –40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
Copyright ©1999–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT
25°C 1.8 2.5
IDD Supply current (per channel) VO= 2.5 V, No load mA
Full range 3.5
Supply current in shutdown 25°C 125 200
IDD(SHDN) mode (per channel) (TLC080, SHDN ≤0.8 V µA
Full range 250
TLC083, TLC085)
OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT
VO(PP) = 0.8 V, CL= 50 pF, 25°C 10 16
Positive slew rate at unity
SR+ V/µs
gain RL= 10 kΩFull range 9.5
VO(PP) = 0.8 V, CL= 50 pF, 25°C 12.5 19
Negative slew rate at unity
SR–V/µs
gain RL= 10 kΩFull range 10
f = 100 Hz 25°C 12
Equivalent input noise
VnnV/√Hz
voltage f = 1 kHz 25°C 8.5
Equivalent input noise
Inf = 1 kHz 25°C 0.6 fA /√Hz
current VO(PP) = 3 V, AV= 1 0.002
Total harmonic distortion
THD + N RL= 10 kΩand 250 Ω, AV= 10 25°C 0.012 %
plus noise f = 1 kHz AV= 100 0.085
t(on) Amplifier turnon time(2) 25°C 0.15 µs
RL= 10 kΩ
t(off) Amplifier turnoff time(2) 25°C 1.3 µs
Gain-bandwidth product f = 10 kHz, RL= 10 kΩ25°C 10 MHz
V(STEP)PP = 1 V, 0.1% 0.18
AV=−1,
CL= 10 pF, 0.01% 0.39
RL= 10 kΩ
tsSettling time 25°Cµs
V(STEP)PP = 1 V, 0.1% 0.18
AV=–1,
CL= 47 pF, 0.01% 0.39
RL= 10 kΩ
RL= 10 kΩ, CL= 50 pF 32
φmPhase margin 25°C°
RL= 10 kΩ, CL= 0 pF 40
RL= 10 kΩ, CL= 50 pF 2.2
Gain margin 25°C dB
RL= 10 kΩ, CL= 0 pF 3.3
(1) Full range is 0°C to 70°C for C suffix and –40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
(2) Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the
supply current has reached half its final value.
6Submit Documentation Feedback Copyright ©1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT
TLC080/1/2/3, 25°C 390 1900
TLC084/5 Full range 3000
VIO Input offset voltage µV
VDD = 12 V, TLC080/1/2/3A, 25°C 390 1400
VIC = 6 V,
VO= 6 V, TLC084/5A Full range 2000
Temperature coefficient of RS= 50 Ω
∝VIO 1.2 µV/°C
input offset voltage 25°C 1.5 50
IIO Input offset current VDD = 12 V, TLC08xC 100 pA
Full range
VIC = 6 V, TLC08xI 700
VO= 6 V, 25°C 3 50
IIB Input bias current RS= 50 ΩTLC08xC 100 pA
Full range
TLC08xI 700
25°C 0 to 10.0 0 to 10.5
VICR Common-mode input voltage RS= 50 ΩV
Full range 0 to 10.0 0 to 10.5
25°C 11.1 11.2
IOH =–1 mA Full range 11
25°C 10.8 11
IOH =–20 mA Full range 10.7
VOH High-level output voltage VIC = 6 V V
25°C 10.6 10.7
IOH =–35 mA Full range 10.3
25°C 10.3 10.5
IOH =–50 mA –40°C to 10.2
85°C
25°C 0.17 0.25
IOL = 1 mA Full range 0.35
25°C 0.35 0.45
IOL = 20 mA Full range 0.5
VOL Low-level output voltage VIC = 6 V V
25°C 0.4 0.52
IOL = 35 mA Full range 0.6
25°C 0.45 0.6
IOL = 50 mA –40°C to 0.65
85°C
Sourcing 25°C 150
IOS Short-circuit output current mA
Sinking 25°C 150
VOH = 1.5 V from positive rail 25°C 57
IOOutput current mA
VOL = 0.5 V from negative rail 25°C 55
25°C 120 140
Large-signal differential
AVD VO(PP) = 8 V, RL= 10 kΩdB
voltage amplification Full range 120
ri(d) Differential input resistance 25°C 1000 GΩ
Common-mode input
CIC f = 10 kHz 25°C 21.6 pF
capacitance
Closed-loop output
zof = 10 kHz, AV= 10 25°C 0.25 Ω
impedance 25°C 80 110
CMRR Common-mode rejection ratio VIC = 0 to 10 V, RS= 50 ΩdB
Full range 80
VDD = 4.5 V to 16 V, VIC = VDD/2, 25°C 80 100
Supply voltage rejection ratio
kSVR dB
(ΔVDD /ΔVIO)No load Full range 80
(1) Full range is 0°C to 70°C for C suffix and –40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
Copyright ©1999–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
at specified free-air temperature, VDD = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT
25°C 1.9 2.9
IDD Supply current (per channel) VO= 7.5 V, No load mA
Full range 3.5
Supply current in shutdown 25°C 125 200
IDD(SHDN) mode (TLC080, TLC083, SHDN ≤0.8 V µA
Full range 250
TLC085) (per channel)
OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA(1) MIN TYP MAX UNIT
VO(PP) = 2 V, CL= 50 pF, 25°C 10 16
Positive slew rate at unity
SR+ V/µs
gain RL= 10 kΩFull range 9.5
VO(PP) = 2 V, CL= 50 pF, 25°C 12.5 19
Negative slew rate at unity
SR–V/µs
gain RL= 10 kΩFull range 10
f = 100 Hz 25°C 14
Equivalent input noise
VnnV/√Hz
voltage f = 1 kHz 25°C 8.5
Equivalent input noise
Inf = 1 kHz 25°C 0.6 fA /√Hz
current VO(PP) = 8 V, AV= 1 0.002
Total harmonic distortion
THD + N RL= 10 kΩand 250 Ω, AV= 10 25°C 0.005 %
plus noise f = 1 kHz AV= 100 0.022
t(on) Amplifier turnon time(2) 25°C 0.47 µs
RL= 10 kΩ
t(off) Amplifier turnoff time(2) 25°C 2.5 µs
Gain-bandwidth product f = 10 kHz, RL= 10 kΩ25°C 10 MHz
V(STEP)PP = 1 V, 0.1% 0.17
AV=−1,
CL= 10 pF, 0.01% 0.22
RL= 10 kΩ
tsSettling time 25°Cµs
V(STEP)PP = 1 V, 0.1% 0.17
AV=–1,
CL= 47 pF, 0.01% 0.29
RL= 10 kΩ
RL= 10 kΩ, CL= 50 pF 37
φmPhase margin 25°C°
RL= 10 kΩ, CL= 0 pF 42
RL= 10 kΩ, CL= 50 pF 3.1
Gain margin 25°C dB
RL= 10 kΩ, CL= 0 pF 4
(1) Full range is 0°C to 70°C for C suffix and –40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
(2) Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the
supply current has reached half its final value.
8Submit Documentation Feedback Copyright ©1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
TYPICAL CHARACTERISTICS
Table of Graphs FIGURE
VIO Input offset voltage vs Common-mode input voltage 1, 2
IIO Input offset current vs Free-air temperature 3, 4
IIB Input bias current vs Free-air temperature 3, 4
VOH High-level output voltage vs High-level output current 5, 7
VOL Low-level output voltage vs Low-level output current 6, 8
ZoOutput impedance vs Frequency 9
IDD Supply current vs Supply voltage 10
PSRR Power supply rejection ratio vs Frequency 11
CMRR Common-mode rejection ratio vs Frequency 12
VnEquivalent input noise voltage vs Frequency 13
VO(PP) Peak-to-peak output voltage vs Frequency 14, 15
Crosstalk vs Frequency 16
Differential voltage gain vs Frequency 17, 18
Phase vs Frequency 17, 18
φmPhase margin vs Load capacitance 19, 20
Gain margin vs Load capacitance 21, 22
Gain-bandwidth product vs Supply voltage 23
vs Supply voltage 24
SR Slew rate vs Free-air temperature 25, 26
vs Frequency 27, 28
THD + N Total harmonic distortion plus noise vs Peak-to-peak output voltage 29, 30
Large-signal follower pulse response 31, 32
Small-signal follower pulse response 33
Large-signal inverting pulse response 34, 35
Small-signal inverting pulse response 36
Shutdown forward isolation vs Frequency 37, 38
Shutdown reverse isolation vs Frequency 39, 40
vs Supply voltage 41
Shutdown supply current vs Free-air temperature 42
Shutdown pulse 43, 44
Copyright ©1999–2011, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
0
-200
-400
-600
0.0 0.5 1.0 1.5 2.0 2.5 3.0
200
400
600
800
1000
3.5 4.0 4.5 5.0
VICR – Common-Mode Input Voltage – V
VDD = 5 V
TA= 25°C
VIO – Input Offset Voltage V–m
300
100
-100
-300
-500
0 1 2 3 456
500
700
900
1100
1500
1300
VICR – Common-Mode Input Voltage – V
VIO – Input Offset Voltage V- m
VDD = 12 V
TA= 25°C
78 9 10 11 12
I /I – Input Bias and Input Offset Current – pA
IB IO
T – Free-Air Temperature – C
A°
-100
-55 -40
50
200
-10 5
150
100
-50
-25 20 35 50
IIB
VDD = 5 V
65 80 95 110 125
250
300
IIO
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 5 10 15 20 25 30 35 40 45 50
IOH - High-Level Output Current - mA
VDD = 5 V
TA= 125°C
TA= 70°C
TA= 25°C
TA= 40 °C
V – High-Level Output Voltage – V
OH
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 5 10 15 20 25 30 35 40 45 50
IOL – Low-Level Output Current – mA
TA= 125°C
TA= 70°C
TA= 25°C
TA= 40 °C
VDD = 5 V
V – Low-Level Output Voltage – V
OL
f – Frequency – Hz
100k
1000
1M10M
10k
100 1k
100
10
1
0.10
0.01
AV= 100
AV= 1
AV= 10
VDD = 5 V and 12 V
TA= 25°C
Z – Output Impedance –
OW
9.0
9.5
10.0
10.5
11.0
11.5
12.0
0 5 10 15 20 25 30 35 40 45 50
IOH – High-Level Output Current – mA
TA= 125°C
TA= 70°C
TA= 25°C
TA= 40 °C
VDD = 12 V
V – High-Level Output Voltage – V
OH
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 5 10 15 20 25 30 35 40 45 50
TA= 125°C
TA= 25°C
TA= 40 °C
VDD = 12 V
TA= 70°C
V – Low-Level Output Voltage –V
OL
I – Low-Level Output Current – mA
OL
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS
INPUT BIAS CURRENT AND
INPUT OFFSET VOLTAGE INPUT OFFSET VOLTAGE INPUT OFFSET CURRENT
vs vs vs
COMMON-MODE INPUT VOLTAGE COMMON-MODE INPUT VOLTAGE FREE-AIR TEMPERATURE
Figure 1. Figure 2. Figure 3.
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE
vs vs vs
FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT
Figure 4. Figure 5. Figure 6.
HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE OUTPUT IMPEDANCE
vs vs vs
HIGH-LEVEL OUTPUT CURRENT LOW-LEVEL OUTPUT CURRENT FREQUENCY
Figure 7. Figure 8. Figure 9.
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Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
0
20
40
60
80
100
120
140
f – Frequency – Hz
100k 1M 10M10k100 1k
CMRR – Common-Mode Rejection Ratio – dB
VDD = 5 V and 12 V
TA= 25°C
40
0 10
80
140
1k 10k
VDD = 12 V
120
100
60
100
20
0
– Power Supply Rejection Ratio – dB
PSRR
100k 1M 10M
VDD = 5 V
f – Frequency – Hz
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
4 5 6 7 8 9 10 11 12 13 14 15
TA= 40 °C
AV= 1
SHDN = VDD
Per Channel
TA= 125°C
TA= 70°C
TA= 25°C
V – Supply Voltage – V
DD
I – Supply Current – mA
DD
0
2
4
6
8
10
12
f – Frequency – Hz
100k 1M 10M10k
THD+N < = 5%
RL= 600 Ω
TA= 25°C
VDD = 12 V
VDD = 5 V
VO(PP) – Peak-to-Peak Output Voltage – V
0
2
4
6
8
10
12
f – Frequency – H
100k 1M 10M10k
VO(PP) – Peak-to-Peak Output Voltage – V
THD+N < = 5%
RL= 10 kΩ
TA= 25°C
VDD = 12 V
VDD = 5 V
0
10 100
10
25
10k 100k
f – Frequency – Hz
VDD = 5 V
40
VDD = 12 V
35
30
20
15
5
1k
nV/ Hz
– Equivalent Input Noise Voltage –
Vn
-120
10 100
-80
-20
10k
f – Frequency – Hz
0
-40
-60
-100
1k
-140
-160
Crosstalk – dB
100k
VDD = 5 V and 12 V
AV= 1
RL= 10 kΩ
VI(PP) = 2 V
For All Channels
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
TYPICAL CHARACTERISTICS
POWER SUPPLY REJECTION
SUPPLY CURRENT RATIO COMMON-MODE REJECTION RATIO
vs vs vs
SUPPLY VOLTAGE FREQUENCY FREQUENCY
Figure 10. Figure 11. Figure 12.
PEAK-TO-PEAK OUTPUT PEAK-TO-PEAK OUTPUT
EQUIVALENT INPUT NOISE
VOLTAGE VOLTAGE VOLTAGE
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 13. Figure 14. Figure 15.
CROSSTALK
vs
FREQUENCY
Figure 16.
Copyright ©1999–2011, Texas Instruments Incorporated Submit Documentation Feedback 11
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0
1k 10k
20
50
1M 10M
f – Frequency – Hz
Gain
80
70
60
40
30
10
100k
-10
-20
– Different Voltage Gain – dB
AVD
100M
-180
-135
0
-45
-90
-225
Phase
VDD =±2.5 V
RL= 10 kΩ
CL= 0 pF
TA= 25°C
Phase –°
0
1k10k
20
50
1M10M
f – Frequency – Hz
Gain
80
70
60
40
30
10
100k
-10
-20
– Different Voltage Gain – dB
AVD
100M
-180
-135
0
-45
-90
-225
Phase
VDD =±6 V
RL= 10 kΩ
CL= 0 pF T
A
= 25°C
Phase –°
10°
10
20°
35°
CL– Load Capacitance – pF
30°
25°
15°
100
5°
0°
Rnull = 0 Ω
Rnull = 20 Ω
Rnull = 50 Ω
Rnull = 100 Ω
VDD = 5 V
RL= 10 kΩ
TA= 25°C
40°
m
φ– Phase Margin
10°
10
20°
35°
CL– Load Capacitance – pF
30°
25°
15°
100
5°
0°
Rnull = 0 Ω
Rnull = 20 Ω
Rnull = 50 Ω
Rnull = 100 Ω
VDD = 12 V
RL= 10 kΩ
TA= 25°C
40°
45°
m
φ– Phase Margin
1
10
2
4
CL– Load Capacitance – pF
3.5
2.5
1.5
100
0.5
0
– Gain Margin – dBG
Rnull = 0 Ω
Rnull = 20 Ω
Rnull = 50 Ω
Rnull = 100 Ω
VDD = 5 V
RL= 10 kΩ
TA= 25°C
3
9.0
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
10.0
4 5 6 7 8 9 10 11 12 13 14 15 16
CL= 11 pF
TA= 25°C
VDD – Supply Voltage – V
GBWP – Gain Bandwidth Product – MHz
RL= 10 kΩ
RL= 600 Ω
12
13
14
15
16
17
18
19
20
21
22
4 5 6 7 8 9 10 11 12 13 14 15 16
VDD – Supply Voltage – V
RL= 600 Ω and 10 kΩ
CL= 50 pF
AV= 1
SR – Slew Rate – V/ms
Slew Rate +
Slew Rate
1
10
2
3.5
CL– Load Capacitance – pF
3
2.5
1.5
100
0.5
0
Rnull = 0 Ω
Rnull = 20 Ω
Rnull = 50 Ω
Rnull = 100 Ω
VDD = 12 V
RL= 10 kΩ
TA= 25°C
4
4.5
5
m
φ– Phase Margin – dB
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS
DIFFERENTIAL VOLTAGE GAIN AND DIFFERENTIAL VOLTAGE GAIN AND
PHASE PHASE
vs vs
FREQUENCY FREQUENCY
Figure 17. Figure 18.
PHASE MARGIN PHASE MARGIN GAIN MARGIN
vs vs vs
LOAD CAPACITANCE LOAD CAPACITANCE LOAD CAPACITANCE
Figure 19. Figure 20. Figure 21.
GAIN MARGIN GAIN BANDWIDTH PRODUCT SLEW RATE
vs vs vs
LOAD CAPACITANCE SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 22. Figure 23. Figure 24.
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Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
0
5
10
15
20
25
-55 -35 -15 5 25 4 565 85 105 125
TA– Free-Air Temperature –°C
VDD = 5 V
RL= 600 Ω and 10 kΩ
CL= 50 pF
AV= 1
SR – Slew Rate – V/ms
Slew Rate +
Slew Rate
0
5
10
15
20
25
-55 -35 -15 5 25 4 565 85 105 125
TA– Free-Air Temperature –°C
VDD = 12 V
RL= 600 Ω and 10 kΩ
CL= 50 pF
AV= 1
SR – Slew Rate – V/ms
Slew Rate +
Slew Rate –
0.001
100 1k
0.01
0.1
10k 100k
f – Frequency– Hz
AV= 100
AV= 10
AV= 1
1
Total Harmonic Distortion + Noise – %
VDD = 5 V
VO(PP) = 2 V
RL= 10 kΩ
Total Harmonic Distortion + Noise – %
0.001
100 1k
0.01
0.1
10k 100k
f – Frequency – Hz
AV= 100
VDD = 12 V
VO(PP) = 8 V
RL= 10 kΩ
AV= 10
AV= 1
Total Harmonic Distortion + Noise – %
0.0001
0.25 0.75
0.01
0.1
1.25 1.75
VO(PP) – Peak-to-Peak Output Voltage – V
2.25 2.75 3.25 3.75
0.001
1
10 VDD = 5 V
AV= 1
f = 1 kHz
RL= 250 Ω
RL= 600 Ω
RL= 10 kΩ
Total Harmonic Distortion + Noise – %
0.0001
0.5 2.5
0.01
0.1
4.5 6.5
VO(PP) – Peak-to-Peak Output Voltage – V
8.5 10.5
0.001
1
10 VDD = 12 V
AV= 1
f = 1 kHz
RL= 250 Ω
RL= 600 Ω
RL= 10 kΩ
t – Time – ms
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
– Output Voltage – V
VO
VI(1 V/Div)
VO(500 mV/Div)
VDD = 5 V
RL= 600 Ω
and 10 kΩ
CL= 8 pF
TA= 25°C
t – Time –
ms
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
– Output Voltage – V
VO
VI(5 V/Div)
VO(2 V/Div)
VDD = 12 V
RL= 600 Ω
and 10 kΩ
CL= 8 pF
TA= 25°C
0 0.1 0.3 0.4
t – Time –
ms
0 .2 0.5 0.6 0.7 0.8 0.9 0.10
VO(50mV/Div)
VI(100mV/Div)
VDD = 5 V and 12 V
RL= 600Ω and 10 kΩ
CL= 8 pF
TA= 25°C
– Output Voltage – V
VO
.0
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
SLEW RATE SLEW RATE PLUS NOISE
vs vs vs
FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE FREQUENCY
Figure 25. Figure 26. Figure 27.
TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION TOTAL HARMONIC DISTORTION
PLUS NOISE PLUS NOISE PLUS NOISE
vs vs vs
FREQUENCY PEAK-TO-PEAK OUTPUT VOLTAGE PEAK-TO-PEAK OUTPUT VOLTAGE
Figure 28. Figure 29. Figure 30.
LARGE SIGNAL FOLLOWER LARGE SIGNAL FOLLOWER SMALL SIGNAL FOLLOWER
PULSE RESPONSE PULSE RESPONSE PULSE RESPONSE
Figure 31. Figure 32. Figure 33.
Copyright ©1999–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
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t – Time – ms
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
– Output Voltage – VVO
VI(2 V/div)
VO(500 mV/Div)
VDD = 5 V
RL= 600 Ω
and 10 kΩ
CL= 8 pF
TA= 25°C
t – Time –
ms
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
– Output Voltage – VVO
VI(5 V/div)
VO(2 V/Div)
VDD = 12 V
RL= 600 Ω
and 10 kΩ
CL= 8 pF
TA= 25°C
t – Time –
ms
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
– Output Voltage – VVO
VI(100 mV/div)
VO(50 mV/Div)
VDD = 5 V and 12 V
RL= 600 Ω and 10 kΩ
CL= 8 pF
TA= 25°C
20
40
60
80
100
120
140
f – Frequency – Hz
100k 1M 10M10k100 1k
Sutdown Forward Isolation – dB
100M
VDD = 12 V
CL= 0 pF
TA= 25°C
VI(PP) = 0.1, 8, 12 V
RL= 600 Ω
RL= 10 kΩ
20
40
60
80
100
120
140
f – Frequency – Hz
100k 1M 10M10k100 1k
Sutdown Reverse Isolation – dB
100M
RL= 600 Ω
RL= 10 kΩ
VDD = 5 V
CL= 0 pF
TA= 25°C
VI(PP) = 0.1, 2.5, and 5 V
20
40
60
80
100
120
140
f – Frequency – Hz
100k 1M 10M10k100 1k
Sutdown Forward Isolation – dB
100M
VDD = 5 V
CL= 0 pF
TA= 25°C
VI(PP) = 0.1, 2.5, and 5 V
RL= 600 Ω
RL= 10 kΩ
118
120
122
124
126
128
130
132
134
136
4 5 6 7 8 9 10 11 12 13 14 15 16
VDD – Supply Voltage – V
IDD(SHDN) – Shutdown Supply Current – Am
Shutdown On
RL= open
VIN = VDD/2
60
80
100
120
140
160
180
–55 –25 535 65 95 125
TA– Free-Air Temperature –°C
VDD = 12 V
AV= 1
VIN = VDD/2
IDD(SHDN) – Shutdown Supply Current – Am
VDD = 5 V
20
40
60
80
100
120
140
f – Frequency – Hz
100k 1M 10M10k100 1k
Sutdown Reverse Isolation – dB
100M
VDD = 12 V
CL= 0 pF
TA= 25°C
VI(PP) = 0.1, 8, 12 V
RL= 600 Ω
RL= 10 kΩ
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS
LARGE SIGNAL INVERTING LARGE SIGNAL INVERTING SMALL SIGNAL INVERTING
PULSE RESPONSE PULSE RESPONSE PULSE RESPONSE
Figure 34. Figure 35. Figure 36.
SHUTDOWN FORWARD SHUTDOWN FORWARD SHUTDOWN REVERSE
ISOLATION ISOLATION ISOLATION
vs vs vs
FREQUENCY FREQUENCY FREQUENCY
Figure 37. Figure 38. Figure 39.
SHUTDOWN REVERSE
ISOLATION SHUTDOWN SUPPLY CURRENT SHUTDOWN SUPPLY CURRENT
vs vs vs
FREQUENCY SUPPLY VOLTAGE FREE-AIR TEMPERATURE
Figure 40. Figure 41. Figure 42.
14 Submit Documentation Feedback Copyright ©1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0 10 20 30 40 50 60 70 80
-2
-4
2
6
t – Time –ms
0
-6
4
Shutdown Pulse
SD Off
VDD = 5 V
CL= 8 pF
TA= 25°C
IDD RL= 600 Ω
IDD RL= 10 kΩ
IDD – Supply Current – mA
Shutdown Pulse - V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0 10 20 30 40 50 60 70 80
-2
-4
2
6
t – Time –
ms
0
-6
4
Shutdown Pulse
SD Off
VDD = 12 V
CL= 8 pF
TA= 25°C
IDD RL= 600 Ω
IDD RL= 10 kΩ
IDD – Supply Current – mA
Shutdown Pulse - V
_
+
Rnull
RLCL
Figure 45
N1
100 kΩ
+
N2
R1
VDD
OUT
IN
IN +
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
TYPICAL CHARACTERISTICS
SHUTDOWN PULSE SHUTDOWN PULSE
Figure 43. Figure 44.
PARAMETER MEASUREMENT INFORMATION
Figure 45.
APPLICATION INFORMATION
Input Offset Voltage Null Circuit
The TLC080 and TLC081 has an input offset nulling function. Refer to Figure 46 for the diagram.
A. R1 = 5.6 kΩfor offset voltage adjustment of ±10 mV. R1 = 20 kΩfor offset voltage adjustment of ±3 mV.
Figure 46. Input Offset Voltage Null Circuit
Copyright ©1999–2011, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
CLOAD
RF
Input
Output
RGRNULL
_
+
VOO VIO 1
RF
RG
IIB RS1
RF
RG
IIB– RF
+
VI
+
RG
RS
RF
IIB–
VO
IIB+
=()
)
(±+()
)
(±
+ +
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
Driving a Capacitive Load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as
shown in Figure 47. A minimum value of 20 Ωshould work well for most applications.
Figure 47. Driving a Capacitive Load
Offset Voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
Figure 48. Output Offset Voltage Model
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Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
_
+
600 Ω22 pF
50 Ω
10 kΩ
10 pF
IN
With
CF= 10 pF
VDD =±5 V
AV= +1
RF= 10 kΩ
RL= 600 Ω
CL= 22 pF
0
0.5
1
1.5
1
0
1
2
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
t - Time - ms
VIN
VOUT
0.5
V – Input Voltage – V
I
V – Output Voltage – V
O
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
High Speed CMOS Input Amplifiers
The TLC08x is a family of high-speed low-noise CMOS input operational amplifiers that has an input capacitance
of the order of 20 pF. Any resistor used in the feedback path adds a pole in the transfer function equivalent to the
input capacitance multiplied by the combination of source resistance and feedback resistance. For example, a
gain of –10, a source resistance of 1 kΩ, and a feedback resistance of 10 kΩadd an additional pole at
approximately 8 MHz. This is more apparent with CMOS amplifiers than bipolar amplifiers due to their greater
input capacitance.
This is of little consequence on slower CMOS amplifiers, as this pole normally occurs at frequencies above their
unity-gain bandwidth. However, the TLC08x with its 10-MHz bandwidth means that this pole normally occurs at
frequencies where there is on the order of 5dB gain left and the phase shift adds considerably.
The effect of this pole is the strongest with large feedback resistances at small closed loop gains. As the
feedback resistance is increased, the gain peaking increases at a lower frequency and the 180°phase shift
crossover point also moves down in frequency, decreasing the phase margin.
For the TLC08x, the maximum feedback resistor recommended is 5 kΩ; larger resistances can be used but a
capacitor in parallel with the feedback resistor is recommended to counter the effects of the input capacitance
pole.
The TLC083 with a 1-V step response has an 80% overshoot with a natural frequency of 3.5 MHz when
configured as a unity gain buffer and with a 10-kΩfeedback resistor. By adding a 10-pF capacitor in parallel with
the feedback resistor, the overshoot is reduced to 40% and eliminates the natural frequency, resulting in a much
faster settling time (see Figure 49). The 10-pF capacitor was chosen for convenience only.
Load capacitance had little effect on these measurements due to the excellent output drive capability of the
TLC08x.
Figure 49. 1-V Step Response
Copyright ©1999–2011, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
VI
VO
C1
+
RGRF
R1
f–3dB
1
2pR1C1
VO
VI
1
RF
RG
1
1 sR1C1
=(+)()
+
=
VI
C2
R2R1
C1
RF
RG
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
(
=1
Q
2)
RGRF
_
+
f–3dB
1
2pRC
–
=
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into theFigure 50 system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see ).
Figure 50. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
Figure 51. 2-Pole Low-Pass Sallen-Key Filter
18 Submit Documentation Feedback Copyright ©1999–2011, Texas Instruments Incorporated
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TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
Shutdown Function
Three members of the TLC08x family (TLC080/3/5) have a shutdown terminal (SHDN) for conserving battery life
in portable applications. When the shutdown terminal is tied low, the supply current is reduced to
125 µA/channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. To enable the
amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left
floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not
inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always
referenced to the voltage on the GND terminal of the device. Therefore, when operating the device with split
supply voltages (e.g. ±2.5 V), the shutdown terminal needs to be pulled to VDD–(not system ground) to disable
the operational amplifier.
The amplifier’s output with a shutdown pulse is shown in Figure 43 and Figure 44. The amplifier is powered with
a single 5-V supply and is configured as noninverting with a gain of 5. The amplifier turnon and turnoff times are
measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the
single, dual, and quad are listed in the data tables.
Figure 37 through Figure 40 show the amplifiers forward and reverse isolation in shutdown. The operational
amplifier is configured as a voltage follower (AV= 1). The isolation performance is plotted across frequency using
0.1 VPP, 2.5 VPP, and 5 VPP input signals at ±2.5 V supplies and 0.1 VPP,8VPP, and 12 VPP input signals at ±6 V
supplies.
Circuit Layout Considerations
To achieve the levels of high performance of the TLC08x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
•Ground planes –It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
•Proper power supply decoupling –Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
•Sockets –Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is
the best implementation.
•Short trace runs/compact part placements –Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the
amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the
input of the amplifier.
•Surface-mount passive components –Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
Copyright ©1999–2011, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
DIE
Side View (a)
End View (b) Bottom View (c)
DIE
Thermal
Pad
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
General PowerPAD Design Considerations
The TLC08x is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 52(a) and Figure 52(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 52(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
A. The thermal pad is electrically isolated from all terminals in the package.
Figure 52. Views of Thermally-Enhanced DGN Package
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications
that have low power dissipation. This soldering provides the necessary thermal and mechanical connection
between the lead frame die pad and the PCB.
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
20 Submit Documentation Feedback Copyright ©1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TA
MAX
D
JA
T -
P =
θ
æ ö
ç ÷
è ø
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
The PowerPAD must be connected to the most negative supply voltage (GND pin potential) of the device.
1. Prepare the PCB with a top side etch pattern (see the landing patterns at the end of this data sheet). There
should be etch for the leads as well as etch for the thermal pad.
2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in
diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the TLC08x IC. These additional vias may be larger than the 13-mil diameter
vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be
soldered so that wicking is not a problem.
4. Connect all holes to the internal plane that is at the same potential as the ground pin of the device.
5. When connecting these holes to this internal plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the TLC08x PowerPAD package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes
of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the
reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the TLC08x IC is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
For a given θJA, the maximum power dissipation is shown in Figure 53 and is calculated by the following formula:
(1)
Where: PD= Maximum power dissipation of TLC08x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA =θJC +θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
Copyright ©1999–2011, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TJ= 150°C
4
3
2
0
-55 -40 -10 20 35
Maximum Power Dissipation – W
5
6
7
65 95 125
1
DGN Package
Low-K Test PCB
θJA = 52.3°C/W
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W2
-25 550 80 110
PWP Package
Low-K Test PCB
θJA = 29.7°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
PDIP Package
Low-K Test PCB
θJA = 104°C/W
T – Free-Air Temperature – C
A°
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
A. Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the device,
especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat
dissipation is at low output voltages with high output currents.
The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a
copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other
hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the
device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in these
graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output currents
and voltages should be used to choose the proper package.
22 Submit Documentation Feedback Copyright ©1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
Macromodel Information
Macromodel information provided was derived using Microsim Parts™, the model generation software used with
Microsim PSpice™. The Boyle macromodel (see (1)) and subcircuit in Figure 54 are generated using the TLC08x
typical electrical and operating characteristics at TA= 25°C. Using this information, output simulations of the
following key parameters can be generated to a tolerance of 20% (in most cases):
•Maximum positive output voltage swing
•Maximum negative output voltage swing
•Slew rate
•Quiescent power dissipation
•Input bias current
•Open-loop voltage amplification
•Unity-gain frequency
•Common-mode rejection ratio
•Phase margin
•DC output resistance
•AC output resistance
•Short-circuit output current limit
(1) G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,”IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
Copyright ©1999–2011, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
Figure 54. Boyle Macromodel and Subcircuit
24 Submit Documentation Feedback Copyright ©1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (April 2006) to Revision F Page
•Updated Figure 9 ................................................................................................................................................................ 10
Copyright ©1999–2011, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC080AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC080AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC080CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080CDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080IDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080IDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC080IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC080IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC081AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC081AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC081CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC081CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC081ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081IDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC081IDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC081IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC081IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC082AID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082AIDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082AIDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082AIDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082AIP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC082AIPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC082CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
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Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC082CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC082ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082IDGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082IDGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082IDGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082IDGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC082IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC082IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC083AID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083AIDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083AIN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC083AINE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC083CD ACTIVE SOIC D 14 TBD Call TI Call TI
TLC083CDG4 ACTIVE SOIC D 14 TBD Call TI Call TI
TLC083CDGQR ACTIVE MSOP-
PowerPAD DGQ 10 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083CDGQRG4 ACTIVE MSOP-
PowerPAD DGQ 10 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083CDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 5
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC083CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC083CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC083IDGQ ACTIVE MSOP-
PowerPAD DGQ 10 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083IDGQG4 ACTIVE MSOP-
PowerPAD DGQ 10 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC083IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC083INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC084AID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084AIDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084AIDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084AIDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084AIN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC084AINE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC084AIPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084AIPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084AIPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084AIPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084CD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084CDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084CDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084CN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
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Addendum-Page 6
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC084CNE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC084CPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084CPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084CPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084CPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084ID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084IDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084IDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC084IPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084IPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084IPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC084IPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC085AID ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085AIDG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085AIDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085AIDRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085AIN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC085AINE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 7
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC085AIPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC085AIPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC085CD ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085CDG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC085CN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC085CNE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC085CPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TLC085CPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 8
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC082, TLC084 :
•Automotive: TLC082-Q1, TLC084-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC080AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC080CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLC080CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC080IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLC080IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC081AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC081CDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLC081CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC081IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLC081IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC082AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC082CDGNR MSOP-
Power DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PAD
TLC082CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC082IDGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLC082IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC083CDGQR MSOP-
Power
PAD
DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLC083CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC084AIDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC084AIPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TLC084CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC084CPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TLC084IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC084IPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TLC085AIDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC080AIDR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC080CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
TLC080CDR SOIC D 8 2500 340.5 338.1 20.6
TLC080IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
TLC080IDR SOIC D 8 2500 340.5 338.1 20.6
TLC081AIDR SOIC D 8 2500 340.5 338.1 20.6
TLC081CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
TLC081CDR SOIC D 8 2500 340.5 338.1 20.6
TLC081IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
TLC081IDR SOIC D 8 2500 340.5 338.1 20.6
TLC082AIDR SOIC D 8 2500 340.5 338.1 20.6
TLC082CDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
TLC082CDR SOIC D 8 2500 340.5 338.1 20.6
TLC082IDGNR MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0
TLC082IDR SOIC D 8 2500 340.5 338.1 20.6
TLC083CDGQR MSOP-PowerPAD DGQ 10 2500 358.0 335.0 35.0
TLC083CDR SOIC D 14 2500 367.0 367.0 38.0
TLC084AIDR SOIC D 14 2500 367.0 367.0 38.0
TLC084AIPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TLC084CDR SOIC D 14 2500 367.0 367.0 38.0
TLC084CPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TLC084IDR SOIC D 14 2500 367.0 367.0 38.0
TLC084IPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TLC085AIDR SOIC D 16 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 3
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