SCBS681G − MARCH 1997 − REVISED OCTOBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DSupport Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
DTypical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
DSupport Unregulated Battery Operation
Down to 2.7 V
DIoff and Power-Up 3-State Support Hot
Insertion
DBus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
DLatch-Up Performance Exceeds 500 mA Per
JESD 17
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
description/ordering information
These octal buffers/drivers are designed
specifically for low-voltage (3.3-V) VCC operation,
but with the capability to provide a TTL interface
to a 5-V system environment.
The ’LVTH540 devices are ideal for driving bus
lines or buffer-memory address registers. These
devices feature inputs and outputs on opposite
sides of the package that facilitate printed circuit
board layout.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
SOIC − DW
Tube SN74LVTH540DW
LVTH540
SOIC − DW Tape and reel SN74LVTH540DWR LVTH540
−40°C to 85°C
SOP − NS Tape and reel SN74LVTH540NSR LVTH540
−40°C to 85°CSSOP − DB Tape and reel SN74LVTH540DBR LXH540
TSSOP − PW
Tube SN74LVTH540PW
LXH540
TSSOP − PW Tape and reel SN74LVTH540PWR LXH540
CDIP − J Tube SNJ54LVTH540J SNJ54LVTH540J
−55°C to 125°CCFP − W Tube SNJ54LVTH540W SNJ54LVTH540W
−55 C to 125 C
LCCC - FK Tube SNJ54LVTH540FK SNJ54LVTH540FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Copyright 2003, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
SN54LVTH540 ...J OR W PACKAGE
SN74LVTH540 . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
Y1
Y2
Y3
Y4
Y5
A3
A4
A5
A6
A7
SN54LVTH540 . . . FK PACKAGE
(TOP VIEW)
A2
A1
OE1
Y7
Y6 OE2
A8
GND
Y8 VCC
SCBS681G − MARCH 1997 − REVISED OCTOBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2)
input is high, all outputs are in the high-impedance state.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When V CC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
FUNCTION TABLE
INPUTS
OUTPUT
OE1 OE2 A
OUTPUT
Y
L L L H
LLH L
HXX Z
X H X Z
logic diagram (positive logic)
OE1
OE2
To Seven Other Channels
A1 Y1
1
19
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