FEATURES
0.25m, five-layer metal, ViaLinkTM epitaxial CMOS
process for smallest die sizes
One-time pro grammable, ViaLink technology for
personalization
Typical performance characteristics -- 120 MHz 16-bit
counters, 120 MHz datapaths, 60+ MHz FIFOs
2.5V core supply voltage, 3.3V I/O supply voltage
Up to 320,000 system gates (non-volatile)
I/Os
- Interfaces with 3.3 volt
- PCI compliant with 3.3 volt
- Full JTAG 1149.1 compliant
- Registered I/O cells with individually controlled enables
Operational environment; total dose irradiati on testi ng to
MIL-STD-883 Test Method 1019
- Total-dose: 300 krad(Si)
- SEL Immune: <120MeV-cm2/mg
- LETTH (0.25) MeV-cm2/mg:
>42 logic cell flip flops
>64 for embedded SRAM
- Saturated Cross Section (cm2) per bit
5.0E-7 logic cell flip flops
2.0E-7 embedded SRAM
Up to 24 dual-port RadTol SRAM modules, organized in
user-configurable 2,304 bit blocks
- 5ns access times, each port independently accessible
- Fast and efficient for FIFO, RAM, and initialized RAM
functions
100% routable with full logic cell utilization and 100% user
fixed I/O
Variable-grain logic cells provide high perfo rm ance and
100% utilization
Typical logic utilization = 65-80% (design dependent)
Comprehensive design tools include high quality Verilog/
VHDL synthesis and simulation
QuickLogic IP available for microcontrollers, DRAM
controllers, USART and PCI
Packaged in a 208-pin CQFP, 288 CQFP, 484 CCGA, 484
CLGA, 208 PQFP, 280 PBGA, and 484 PB GA
Standard Microcircuit Drawing 5962-04229
- QML Q & V
INTRODUCTION
The UT6325 RadTol Eclipse Field Programmable Gate Array
Family (FPGA) offers up to 320,000 syst em gates including
Dual-Port RadTol SRAM modules. It is fabricated on 0.25m
five-layer metal ViaLink CMOS process and contains 1,536
logic cells and 24 dual-port SRAM modules (see Figure 1 Block
Diagram). Each SRAM module has 2,304 RAM bits, for a
maximum total of 55,300 bits. Please reference product family
features chart on page 2.
SRAM modules are Dual Port (one asynchronous/synchronous
read port, one write port) and can be configured into one of four
modes (see Figure 2). Designers can cascade multiple RAM
modules to increase the depth or width allowed in single
modules by connecting corresponding address lines together and
dividing the words between modules (see Fi gure 3). This
approach allows a variety of address depths and word widths to
be tailored to a specific application.
The UT6325 RadTol Eclipse FPGA is available in a 208-pin
Cerquad Flatpack, allowin g access to 99 bidirectional signal I/
O, 1 dedicated clock, 8 programmable clocks and 16 high drive
inputs. Other package options include a 288 CQFP, 484 CCGA
and a 484 CLGA.
Aeroflex uses QuickLogic Corporation’s licensed ESP
(Embedded Standard Products) technology. QuickLogic is a
pioneer in the FPGA semiconductor and software tools field.
Standard Products
UT6325 RadTol Eclipse FPGA
Data Sheeet
November 2013
www.aeroflex.com/FPGA