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DMeets or Exceeds the Requirements of
ANSI EIA/TIA-644 Standard for Signaling
Rates† up to 400 Mbps
DOperates With a Single 3.3-V Supply
D−2-V to 4.4-V Common-Mode Input Voltage
Range
DDifferential Input Thresholds <50 mV With
50 mV of Hysteresis Over Entire
Common-Mode Input Voltage Range
DIntegrated 110-Ω Line Termination
Resistors Offered With the LVDT Series
DPropagation Delay Times 4 ns (typ)
DActive Fail Safe Assures a High-Level
Output With No Input
DRecommended Maximum Parallel Rate of
100 M-Transfers/s
DOutputs High-Impedance With VCC <1.5 V
DAvailable in Small-Outline Package With
1,27 mm Terminal Pitch
DPin-Compatible With the AM26LS32,
MC3486, or µA9637
description
This family of differential line receivers offers
improved performance and features that imple-
ment the electrical characteristics of low-voltage
differential signaling (LVDS). LVDS is defined in
the TIA/EIA-644 standard. This improved perfor-
mance represents the second generation of
receiver products for this standard, providing a
better overall solution for the cabled environment.
The next generation family of products is an
extension to TI’s overall product portfolio and is
not necessarily a replacement for older LVDS
receivers.
Improved features include an input common-
mode voltage range 2 V wider than the minimum
required by the standard. This will allow longer
cable lengths by tripling the allowable ground
noise tolerance to 3 V between a driver and
receiver.
Copyright 2001, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1Y
G
2Y
2A
2B
GND
VCC
4B
4A
4Y
G
3Y
3A
3B
SN65LVDS32A, SN65LVDT32A
1
2
3
4
8
7
6
5
VCC
1Y
2Y
GND
1A
1B
2A
2B
D PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
For Replacement Use SN65LVDS32B or SN65LVDT32B
G
G
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
Logic Diagram
(positive logic)
SN65LVDT32A
ONLY (4 Places)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1Y
1,2EN
2Y
2A
2B
GND
VCC
4B
4A
4Y
3,4EN
3Y
3A
3B
SN65LVDS3486A, SN65LVDT3486A
D PACKAGE
(TOP VIEW)
For Replacement Use SN65LVDS3486B or SN65LVDT3486B
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
Logic Diagram
(positive logic)
SN65LVDT3486A
ONLY (4 Places)
1,2EN
3,4EN
1A
1B
2A
2B
1Y
2Y
SN65LVDT9637A
ONLY
SN65LVDS9637A, SN65LVDT9637A
For Replacement Use SN65LVDS9637B or SN65LVDT9637B
Logic Diagram
(positive logic)
NOT RECOMMENDED FOR NEW DESIGNS
!"#$ % &'!!($ #% )'*+&#$ ,#$(-
!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2 #++ )#!#"($(!%-
†Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
SLLS368E − JULY 1999 − REVISED JUNE 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage
hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more
than ±50 mV over the full input common-mode voltage range.
The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching
resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates
this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available
for multidrop or other termination circuits.
The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 600 ns
after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines,
or powered-down transmitters. This prevents noise from being received as valid data under these fault
conditions. This feature may also be used for wired-OR bus signaling.
The intended application of these devices and signaling technique is for point-to-point baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media may be
printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent
upon the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS32A, SN65LVDT32A, SN65LVDS3486A, SN65LVDT3486A, SN65LVDS9637A, and
SN65LVDT9637A are characterized for operation from -40°C to 85°C.
Function Tables
SN65LVDS32A and SN65LVDT32A
DIFFERENTIAL INPUT ENABLES OUTPUT
A-B G G Y
VID ≥ -70 mV H
XX
LH
H
-100 mV < VID ≤ -70 mV H
XX
L?
?
VID ≤ -100 mV H
XX
LL
L
X L H Z
Open H
XX
LH
H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
SN65LVDS3486A and SN65LVDT3486A
DIFFERENTIAL INPUT ENABLES OUTPUT
A-B EN Y
VID ≥ -70 mV H H
-100 mV < VID ≤ -70 mV H ?
VID ≤ -100 mV H L
X L Z
Open H H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
SLLS368E − JULY 1999 − REVISED JUNE 2001
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Function Tables (Continued)
SN65LVDS9637A and SN65LVDT9637A
DIFFERENTIAL INPUT OUTPUT
A-B Y
VID ≥ -70 mV H
-100 mV < VID ≤ -70 mV ?
VID ≤ -100 mV L
Open H
H = high level, L = low level, ? = indeterminate
equivalent input and output schematic diagrams
VCC
37 Ω
7 V
Y Output
LVDT Only 110 Ω
7 V
300 kΩ
50 Ω
VCC
Enable
Inputs
300 kΩ
(G Only)
(EN and G Only)
7 V
VCC
Attenuation
Network
7 V
A Input
Attenuation
Network
B Input
7 V7 V
VCC
Attenuation
Network
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) −0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range: Enables or Y −0.5 V to VCC + 3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A or B −4 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus-pin (A, B) electrostatic discharge (see Note 2) 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING OPERATING FACTOR‡
ABOVE TA = 25°CTA = 85°C
POWER RATING
D8 725 mW 5.8 mW/°C377 mW
D16 950 mW 7.6 mW/°C494 mW
‡This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 3 3.3 3.6 V
High-level input voltage, VIH Enables 2 V
Low-level input voltage, VIL Enables 0.8 V
Magnitude of differential input voltage, VID0.1 3 V
Common-mode input voltage, VIC −2 4.4 V
Operating free-air temperature, TA−40 85 °C
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electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VITH1 Positive-going differential input voltage threshold
VIB =-2 V or 4.4 V, See Figure 1
50
mV
VITH2 Negative-going differential input voltage threshold VIB =-2 V or 4.4 V, See Figure 1 −50 mV
VITH3 Differential input fail-safe voltage threshold See Figure 2 and Table 1 −70 −100 mV
VID(HYS) Differential input voltage hysteresis,
VITH1 - VITH2 50 mV
VOH High-level output voltage IOH = −8 mA 2.4 V
VOL Low-level output voltage IOL = 8 mA 0.4 V
ICC
Supply current
‘32A or ‘3486A
G or EN at VCC, No load,
Steady-state 16 23
mA
ICC Supply current
‘32A or ‘3486A
G or EN at GND 1.1 5 mA
‘9637A No load, Steady-state 8 12
VI = 0 V, Other input open ±20
SN65LVDS
VI =2.4 V, Other input open ±20
A
SN65LVDS VI =-2 V, Other input open ±40 µA
II
Input current (A or B inputs)
VI = 4.4 V, Other input open ±40
IIInput current (A or B inputs) VI = 0 V, Other input open ±40
SN65LVDT
VI =2.4 V, Other input open ±40
A
SN65LVDT VI =-2 V, Other input open ±80 µA
VI = 4.4 V, Other input open ±80
IID
Differential input current
SN65LVDS VID= 100 mV, VIC= −2 V or 4.4 V,
See Figure 1 ±2µA
IID
Differential input current
(I
IA
- I
IB
)
SN65LVDT
VID= 0.4 V, VIC= −2 V or 4.4 V 3.1 4.5 mA
(IIA - IIB)
SN65LVDT VID= −0.4 V, VIC= −2 V or 4.4 V −3.1 −4.5 mA
II(OFF)
Power-off input current (A or B inputs)
VA or VB =0 or 2.4 V,
VCC= 0 V ±30
A
II(OFF) Power-of f input current (A or B inputs) VA or VB =−2 V or 4.4 V,
VCC= 0 V ±50 µA
IIH High-level input current (enables) VIH = 2 V 10 µA
IIL Low-level input current (enables) VIL = 0.8 V 10 µA
IOZ High-impedance output current ±10 µA
CIN Input capacitance, A or B input to GND VI = 0.4 sin (4E6πt) + 0.5 V 5 pF
†All typical values are at 25°C and with a 3.3 V supply.
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switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
tPLH Propagation delay time, low-to-high-level output 2.5 4 6 ns
tPHL Propagation delay time, high-to-low-level output 2.5 4 6 ns
td1 Delay time, fail-safe deactivate time 6.1 ns
td2 Delay time, fail-safe activate time
CL = 10 pF,
0.3 1 µs
tsk(p) Pulse skew (|tPHL1 – tPLH1|) CL = 10 pF,
See Figure 3
200 ps
tsk(o) Output skew§
See Figure 3
150 ps
tsk(pp) Part-to-part skew‡1 ns
trOutput signal rise time 600 ps
tfOutput signal fall time 600 ps
tPHZ Propagation delay time, high-level-to-high-impedance output 5.5 9 ns
tPLZ Propagation delay time, low-level-to-high-impedance output
See Figure 4
4.4 9 ns
tPZH Propagation delay time, high-impedance -to-high-level output
See Figure 4
3.8 9 ns
tPZL Propagation delay time, high-impedance-to-low-level output 7 9 ns
†All typical values are at 25°C and with a 3.3 V supply.
‡tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
§tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all receivers of a single device with all of their inputs driven together.
PARAMETER MEASUREMENT INFORMATION
VID
A
B
Y
VO
VIB
VIA
VIC
(VIA + VIB)/2 IIB
IIA VO
Figure 1. Voltage and Current Definitions
VID
VO
VIB
VIA CL < 50 pF VID
VO
VIT−
1 µs
VIT+
2 µs
−0.2 V
0.2 V
Figure 2. VITH3 Input Voltage Threshold Test Circuit and Definitions
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PARAMETER MEASUREMENT INFORMATION
Table 1. Receiver Minimum and Maximum Fail-Safe
Input Threshold Test Voltages
APPLIED VOLTAGES†RESULTANT INPUTS
VIA (mV) VIB (mV) VID (mV) VIC (mV) Output
−2050 −1950 −100 −2000 L
−2035 −1965 −70 −2000 H
4350 4450 −100 4400 L
4365 4435 −70 4400 H
†These voltages are applied for a minimum of 1 µs.
VID
VO
VIB
VIA CL = 10 pF
tPHL tPLH
tftr
80%
20%
80%
20%
VIA
VIB
VID
VO
tD1 tD2
1.4 V
1 V
0.4 V
0 V
−0.4 V
VOH
1.4 V
VOL
−0.2 V
>1 µs
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 3. Timing Test Circuit and Waveforms
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PARAMETER MEASUREMENT INFORMATION
B
A
G
G
VO±
500 Ω
VTEST
10 pF
1.2 V
tPZL
tPLZ
tPZL
tPLZ
tPZH
tPHZ
tPZH
tPHZ
2.5 V
1 V
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
2.5 V
1.4 V
VOL +0.5 V
VOL
0
1.4 V
2 V
1.4 V
0.8 V
2 V
1.4 V
0.8 V
VOH
VOH −0.5 V
1.4 V
0
VTEST
A
G, 1,2EN,or 3,4EN
G
Y
VTEST
A
G
Y
Inputs
G, 1,2EN,or 3,4EN
NOTE B: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse
repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture
capacitance within 0,06 mm of the D.U.T.
1,2,EN, or 3,4, EN
Figure 4. Enable/Disable Time Test Circuit and Waveforms
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TYPICAL CHARACTERISTICS
Figure 5
0
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL − Low-Level Output Current − mA
4
3
040 60
2
20
VCC = 3.3 V
TA = 25°C
1
VOL − Low-Level Output Voltage − V
5
10080
Figure 6
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH − High-Level Output Current − mA
VOH − High-Level Output Voltage − V
4
3
0
2
1
−100 −60 −40−80 0−20
VCC = 3.3 V
TA = 25°C
Figure 7
4.5
4
3.5
3
−50 0 50
5
100
TA − Free-Air Temperature − °C
VCC = 3 V
VCC = 3.6 V
VCC = 3.3 V
− Low-To-High Propagation Delay Time − ns
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
tPLH
Figure 8
4.5
4
3.5
3
−50 0 50
5
100
TA − Free-Air Temperature − °C
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
− High-To-Low Propagation Delay Time − ns
tPHL
SLLS368E − JULY 1999 − REVISED JUNE 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
80
60
20
00 100
100
120
SUPPLY CURRENT
vs
FREQUENCY
150 200
40
− Supply Current − mAICC
f − Switching Frequency − MHz
VCC = 3 V
VCC = 3.6 V
VCC = 3.3 V
140
Figure 9
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APPLICATION INFORMATION
1B
1A
1Y
G
2Y
2A
2B
GND
VCC
4B
4A
4Y
G
3Y
3A
3B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
100 Ω
100 Ω
100 Ω
(see Note B)
100 Ω
VCC
See Note C
≈3.6 V
0.1 µF
(see Note A) 1N645
(2 places)
0.01 µF
5 V
NOTES: A. Place a 0.1 µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The
capacitor should be located as close as possible to the device terminals.
B. The termination resistance value should match the nominal characteristic impedance of the transmission media with ±10%.
C. Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 10. Operation with 5-V Supply
related information
IBIS modeling is available for this device. Please contact the local TI sales of fice or the TI W eb site at www.ti.com
for more information.
For more application guidelines, please see the following documents:
DLow-Voltage Differential Signalling Design Notes (TI literature number SLLA014)
DInterface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
DReducing EMI With LVDS (SLLA030)
DSlew Rate Control of LVDS Circuits (SLLA034)
DUsing an LVDS Receiver With RS-422 Data (SLLA031)
DEvaluating the LVDS EVM (SLLA033)
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12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
abstract terminated failsafe
A differential line receiver commonly has a fail-safe circuit to prevent it from switching on input noise. Current
LVDS fail-safe solutions require either external components with subsequent reduction in signal quality or
integrated solutions with limited application. This family of receivers has a new integrated fail-safe that solves
the limitations in present solutions. A detailed theory of operation is presented in the application note The Active
Fail-Safe Feature of the SN65LVDS32A, literature number SLLA082.
Figure 11 shows one receiver channel with active fail-safe. It consists of a main receiver that can respond to
a high-speed input differential signal. Also connected to the input pair are two fail-safe receivers that form a
window comparator. The window comparator has a much slower response than the main receiver and detects
when the input differential falls below 80 mV. A 600-ns fail-safe timer filters the window comparator outputs.
When fail-safe is asserted, the fail-safe logic drives the main receiver output to logic high.
_
+
Main Receiver
_
+
_
+
A > B + 80 mV
B > A + 80 mV
Failsafe
Timer
Failsafe
Output
Buffer
Reset
Window Comparator
A
BR
Figure 11. Receiver With Terminated Failsafe
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APPLICATION INFORMATION
test conditions
DVCC = 3.3 V
DTA = 25°C (ambient temperature)
DAll four channels switching simultaneously with NRZ data. Scope is pulse-triggered simultaneously with
NRZ data.
equipment
DTektronix PS25216 programmable power supply
DTektronix HFS 9003 stimulus system
DTektronix TDS 784D 4-channel digital phosphor oscilloscope − DPO
Tektronix PS25216
Programmable
Power Supply
Bench Test Board
Tektronix HFS 9003
Stimulus System
Tektronix TDS 784D 4-Channel
Digital Phosphor
Oscilloscope − DPO
Trigger
Figure 12. Equipment Setup
Figure 13. Typical Eye Pattern SN65LVDS32A 100 Mbit/s
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14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°−ā8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
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