Nuvoton Bus Termination Regulator W83310G-R2 W83310G-R2 Data Sheet Revision History NO PAGES DATES VERSION 1. All June, 2007 1.0 VERSION ON WEB N.A MAIN CONTENTS Remove non Pb-free part no: W83310S-R2 1. Change to Nuvoton document format 2 All Nov., 2008 1.1 N.A 2. Add performance chart with VIN=1.5V/1.8V/2.5V at VCNTL = 3.0~3.6V 3 4 5 6 Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this datasheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. -I- Publication Date: Nov., 2008 Revision 1.10 W83310G-R2 Table of Content1. GENERAL DESCRIPTION .............................................................................................................. 1 2. FEATURES ...................................................................................................................................... 1 3. APPLICATIONS ............................................................................................................................... 1 4. PIN CONFIGURATION AND DESCRIPTION .................................................................................. 2 5. APPLICATION CIRCUIT .................................................................................................................. 3 6. INTERNAL BLOCK DIAGRAM ........................................................................................................ 3 7. ABSOLUTE MAXIMUM RATINGS................................................................................................... 4 8. RECOMMENDED OPERATING CONDITIONS .............................................................................. 4 9. ELECTRICAL CHARACTERISTICS ................................................................................................ 5 10. TYPICAL OPERATING WAVEFORMS ............................................................................................ 5 11. PACKAGE DIMENSION................................................................................................................. 10 12. ORDERING INFORMATION...........................................................................................................11 13. TOP MARKING SPECIFICATION...................................................................................................11 -II- Publication Date: Nov., 2008 Revision 1.10 W83310G-R2 1. GENERAL DESCRIPTION The W83310G-R2 is a linear regulator provides power with the capability of continuous 1.8Amp bi-directional sinking and driving capability for a high speed bus terminator application. The chip simply implements a stable power supply which tracks dynamically half of the input power for the bus terminator. The W83310G-R2 is promoted with small footprint 8-SOP 150mil package. The design of the W83310G-R2 provides a high integration, high performance, and cost-effective solution. 2. FEATURES z Support DDRI (1.25VTT), DDRII (0.9VTT) and DDRIII (0.75VTT) Requirements z Sink and Source 1.8A Continuous Current z Integrated Power MOSFET z Adjustable VOUT by External Resistors z Low External Component Count z Low Output Voltage Offset z Short Circuit Protection z 0 to 70 Ambient Operating Temperature Range z SOP-8 Package, Lead (Pb) Free 3. APPLICATIONS z Desktop PCs, Notebooks, and Workstations z Graphics Card Memory Termination z DDRI, DDRII and DDRIII Memory Systems -1- Publication Date: Nov., 2008 Revision 1.10 W83310G-R2 4. PIN CONFIGURATION AND DESCRIPTION VIN 1 8 VCNTL GND 2 7 VCNTL VREF 3 6 VCNTL VOUT 4 5 VCNTL W83310G-R2 (Top View) SYMBOL PIN I/O FUNCTION VIN 1 I VREF 3 I VOUT 4 O Voltage output pin which is regulated to the VREF voltage. VCNTL 5, 6, 7, 8 I Power for internal control logic circuitry. GND 2 Main power input pin which supplies current to the output pin. Internal reference voltage source. Reference voltage on the pin will be referred with the pin value. Ground. -2- Publication Date: Nov., 2008 Revision 1.10 W83310G-R2 5. APPLICATION CIRCUIT VRAM VRAM 1 C1 R1 10K 2 1000u 3 3 VOUT Q1 C2 2N7002 1u R2 10K 4 VIN VCNTL GND VCNTL VREF VCNTL VOUT VCNTL C3 C4 1u 1500u W83310G-R2 8 7 3.3V 6 5 C5 1u 2 Enable# 1 U1 6. INTERNAL BLOCK DIAGRAM VCNTL VREF Control Logic Circuit VIN VOUT GND -3- Publication Date: Nov., 2008 Revision 1.10 W83310G-R2 7. ABSOLUTE MAXIMUM RATINGS RATING UNIT Input Voltage ITEM VIN SYMBOL -0.3 to 5 V Control Logic Input Voltage VCNTL -0.3 to 5 V 2 kV Machine Mode 200 V Latch-Up 100 mA JA 160 /W -65 to 150 Human Body Mode Electrostatic discharge protection Package Thermal Resistance Storage Temperature Range Note: Stress listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum ration conditions for extended periods may remain possibility to affect device reliability. 8. RECOMMENDED OPERATING CONDITIONS ITEM MIN MAX 1.5 3.6 3 3.6 Operating Temperature Range 0 70 Junction Temperature Range 0 125 Input Voltage SYMBOL VIN VCNTL -4- UNIT V Publication Date: Nov., 2008 Revision 1.10 W83310G-R2 9. ELECTRICAL CHARACTERISTICS TA = 25, VCNTL= 3.3 V, VIN=2.5V/1.8V/1.5V, VREF=1.25V/0.9V/0.75V, COUT=1000uF, all voltage outputs unloaded (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNITS -- 0.5 1 mA 1 10 uA 230 300 uA mV Input VCNTL Operating Current ICNTL IOUT=0A IVIN Shutdown Current (note 1) (SHDN) IVCNTL VREF<0.2V, IOUT=0.1A (SHDN) Output (DDRI / DDRII / DDRIII) Output Offset Voltage (note 2) VOS Load Regulation (note 3) VL IOUT=0A -5 0 5 IOUT=0 +1.8A -40 -- 40 IOUT=-0 -1.8A -40 -- 40 -- 4 -- mV Protection Short Current Limit ILIM VOUT short to ground VIH Enable 0.4 -- -- VIL Disable -- -- 0.2 A VREF Shutdown Mode Shutdown Threshold V Note 1: Shutdown current is the input current of VIN & VCNTL drawn by a regulator when the output voltage is disabled by a shutdown signal on VREF pin (VIL < 0.2). It is measured with VIN = 1.5V/1.8V/2.5V & VCNTL = 3.3V. Note 2: VOS offset is the voltage measurement as VOUT subtracted from VREF. Note 3: Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 1.8A peak. -5- Publication Date: Nov., 2008 Revision 1.10 W83310G-R2 10. TYPICAL OPERATING WAVEFORMS z Transient Response, VCNTL=3.3V, VIN=2.5V, VREF=1.25V, VOUT=1.25V 1.8A Source 1.8A Sink z Transient Response, VCNTL=3.3V, VIN=1.8V, VREF=0.9V, VOUT=0.9V 1.8A Source 1.8A Sink z Transient Response, VCNTL=3.3V, VIN=1.5V, VREF=0.75V, VOUT=0.75V -6- Publication Date: Nov., 2008 Revision 1.10 W83310G-R2 1.8A Sink 1.8A Source z Maximum Sourcing Current with VCNTL = 3.0V ~ 3.6V Maximum Sourcing Current vs VCNTL 2.7 Output Current (A) 2.5 2.3 DDR1: VOUT=1.25V 2.1 DDR2: VOUT=0.9V DDR3: VOUT=0.75V 1.9 1.7 1.5 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCNTL (V) Note: 3/4 DDR1: VIN = 2.5V, VOUT = 1.25V with 10ms current pulse. 3/4 DDR2: VIN = 1.8V, VOUT = 0.9V with 10ms current pulse. 3/4 DDR3: VIN = 1.5V, VOUT = 0.75V with 10ms current pulse. -7- Publication Date: Nov., 2008 Revision 1.10 W83310G-R2 z Maximum Sinking Current with VCNTL = 3.0V ~ 3.6V Maximum Sinking Current vs VCNTL 2.8 2.7 Output Current (A) 2.6 2.5 2.4 DDR1: VOUT=1.25V 2.3 DDR2: VOUT=0.9V 2.2 DDR3 VOUT=0.75V 2.1 2 1.9 1.8 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCNTL (V) Note: 3/4 DDR1: VIN = 2.5V, VOUT = 1.25V with 10ms current pulse. 3/4 DDR2: VIN = 1.8V, VOUT = 0.9V with 10ms current pulse. 3/4 DDR3: VIN = 1.5V, VOUT = 0.75V with 10ms current pulse. z Output Short Circuit Protection, VCNTL=3.3V, VOUT shorted to ground VIN=2.5V VOUT=1.25V -8- Publication Date: Nov., 2008 Revision 1.10 W83310G-R2 VIN=1.8V VOUT=0.9V VIN=1.5V VOUT=0.75V -9- Publication Date: Nov., 2008 Revision 1.10 W83310G-R2 11. PACKAGE DIMENSION 8 5 c E HE L 4 1 0.25 D O A Y e SEATING PLANE GAUGE PLANE A1 b Control demensions are in milmeters . SYMBOL A A1 b c E D e HE Y L DIMENSION IN MM MIN. MAX. 1.35 1.75 0.10 0.25 0.51 0.33 0.19 0.25 3.80 4.00 4.80 5.00 1.27 BSC 6.20 5.80 0.10 1.27 0.40 0 10 DIMENSION IN INCH MIN. MAX. 0.053 0.069 0.010 0.004 0.020 0.013 0.010 0.008 0.157 0.150 0.188 0.196 0.050 BSC 0.228 0.016 0 -10- 0.244 0.004 0.050 10 Publication Date: Nov., 2008 Revision 1.10 W83310G-R2 3/4 TAPING SPECIFICATION 8 Pin SOP Package 12. ORDERING INFORMATION PART NUMBER W83310G-R2 SUPPLIED AS PACKAGE TYPE 8PIN SOP(Pb-free package) PRODUCTION FLOW E Shape: 100 units/Tube Commercial, 0 to +70 T Shape: 2,500 units/T&R 13. TOP MARKING SPECIFICATION W83 310G-R2 706XY Left line: Winbond logo (Nuvoton) 1st & 2nd line: W83310G-R2 - the part number 3rd line: Tracking code 706 X Y 706: Packages assembled in Year 07', week 06 X: Assembly house ID Code Y: The IC version Code -11- Publication Date: Nov., 2008 Revision 1.10 W83310G-R2 Important Notice Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Nuvoton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. -12- Publication Date: Nov., 2008 Revision 1.10