AM486DX2-133V16BGC - Advanced Micro Devices

This document contains information on a product under development at Advanced Micro Devices. The information is

intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

DISTINCTIVE CHARACTERISTICS

■High-Performance Design

- Industry-standard write-back cache support

- Frequent instructions execute in one clock

- 105.6-million bytes/second burst bus at 33 MHz

- Flexible write-through and write-back address

control

- Advanc ed 0.35 -µ CMOS-process techno logy

- Dynamic bus sizing for 8-, 16-, and 32-bit buses

-Supports “soft reset” capability

■High On-Chip Integration

- 16-Kbyte unified code and data cache

- Floating-point unit

- Paged, virtual memory management

■Enhanced System and Power Management

- Stop clock control for reduced power

consumption

- Industry-standard two-pin System Management

Interrupt (SMI) for power management indepen-

dent of processor operating mode and operating

system

- Static design with Auto Halt power-down support

- Wide range of chipsets supporting SMM avail-

able to allow product differentiation

■Complete 32-Bit Architecture

- Address and data buses

-All registers

- 8-, 16-, and 32-bit data types

■Standard Features

- 3-V core with 5-V tolerant I/O

- Wide range of chipsets and support available

through the AMD FusionE86SM Program

■168-Pin PGA Package or 208-Pin SQFP Package

■IEEE 1149.1 JTAG Boundary-Scan Compatibility

GENERAL DESCRIPTION

The Enhanced Am486®DX Microprocessor Family is an

addition to the AMD E86 family of embedded micropro-

cessors. This new family enhances system performance

by incorporating a 16-Kbyte write-back cache to the ex-

isting flexible clock control and enhanced SMM features

of a 486 CPU.

The Enhanced Am486DX microprocessor family en-

ables write-back configuration through software and

cacheable access control. On-chip cache lines are con-

figurable as either write-through or write-back. The CPU

clock control feature permits the CPU clock to be stopped

under controlled conditions, allowing reduced power

consumption during system inactivity. The SMM function

is imple mented wi th an indus try stand ard two-pi n inter -

face.

Since the Enhanced Am486DX microprocessor family is

supported as an embedded product, customers can rely

on continued cost reduction, a long-term supply, and

extended temperature products.

In addition, cu st omers hav e acces s to a large sel ect ion

of inexpensive development tools, compilers, and

chipset s. A lar ge number of PC operati ng sys tems and

Real Time Op erating S ystem s (RTOS) suppor t the En-

hanced Am486DX microprocessor family. This results in

decreased development costs and improved time to mar-

ket.

Table 1 shows available processors in the Enhanced

Am486DX microprocessor family. See page 54 for in-

formation on how these parts differ from other Am486

processors.

Table 1. Clocking Options

Operating

Frequency Input Clock Available Package

Am486DX5-133 33 MHz 168-pin PGA

Am486DX5-133 33 MHz 208-pin SQFP

Am486DX4-100 33 MHz 168-pin PGA

Am486DX4-100 33 MHz 208-pin SQFP

Am486DX2-66 33 MHz 168-pin PGA

Am486DX2-66 33 MHz 208-pin SQFP

PRELIMINARY

Enhanced Am486®DX

Microprocessor Family

Publication # 20736 Rev: B Amendment/0

Issue Date: March 1997

2 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

BLOCK DIAGRAM

A31–A2

BE3–BE0

ADS, W/R , D/C,

M/IO, PCD, PWT ,

RDY, LOCK,

PLOCK, BOFF,

A20M, BRE Q,

HOLD, HLDA,

RESET, INTR,

NMI, FERR, UP,

IGNNE, SMI,

SMIACT, SRESET

VOLDET

VCC, Vss

CLK

STPCLK

CLKMUL

32-Bit Linear Address

32-Bit Data Bus

Central and

Protection

Test Unit

Control

ROM

Instruction

Decode

Barrel Shifter

ALU

Segmentation

Unit

Descriptor

Registers

Paging Unit

Limit and

Attribute

PLA

Cache Unit

Prefetcher

Address

Drivers

Bus Control

Request

Sequencer

Data Bus

Transceivers

Burst Bus

Control

Bus Size

Control

Cache

Control

Parity

Generation

and Control

232

128

Decoded

Instruction

Path

Code

Stream

Physical

Address

PCD, PWT

Displacement Bus

Bus Interface

D31–D0

BRDY, BLAST

BS16, BS8

KEN, FLUSH,

AHOLD, CACHE,

EADS, INV,

WB/WT, HITM

PCHK,

DP3–DP0

TDI, TCK,

TDO, TMS

Power

Plane

Micro-instruction

Clock

Generator

Write

Buffers

4x32

Copyback

Buffers

4x32

Writeback

Buffers

4x32

Translation

Lookaside

Buffer

16-Kbyte

Cache

32-Byte

Code Queue

2x16 Bytes

JTAG

Clock

Interface

Physical

Address

Floating

Point

Unit

Floating

Point

File

Enhanced Am486DX Microprocessor Family 3

P R E L I M I N A R Y

LOGIC SYMBOL

DP3–DP0

A31–A4

CLK

A20M

M/IO

Enhanced Am486DX

CPU

W/R

D/C

LOCK

4BE3–BE0

Clock

Address Bus

Bus Cycle

Definition

Address

PLOCK

BS8

BS16

ADS

RDY

Bus Cycle

Control

INTR

NMI

RESET

Interrupts

PCHK

A3–A2 BRDY

BLAST

PWT

PCD

KEN

FLUSH

EADS

AHOLD

Data Parity

Data Bus

Burst

Control

Page

Cacheability

Invalidation

Cache Control /

D31–D0

TMSTDI TDO

TCK

IEEE Test

Port Access

FERRIGNNE

Numeric Error

Reporting

Bus Arbitration

BREQ

HOLD

HLDA

BOFF

CACHE

CLKMUL

Clock Multiplier

Mask

HITM

INV

SMI

SMIACT SMM

SRESET

STPCLK

Stop Clock

Upgrade

VOLDET

Voltage De tect

Present

WB/WT

4 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is

formed by a combinati on of the e lements below.

–133AM486

Package Type

Speed Option

Valid Combinations

Valid Combinations list configura-

tions pla nned to be supp orted in vol-

ume for this device. Consult the local

AMD sales office to confirm avail-

ability of specific valid combinations

and to check on newly released

combinations.

H =208-lead Shrink Quad Flat Pack (PDE-208)

G = 168-pin Pin Grid Array (CGM-168)

–133 =133 MHz (5-class performance)

–100 =100 MHz

– 66 = 66 MHz

Temperature Range

C =Commercial (Tcase = 0°C to +85°C)

I = Industrial (Tcase = –40°C to +100°C)

DX 5

Voltage Range

V = 3.3 V ± 0.3 V

W = 3.45 V ± 0.15 V

Cache Type

B = Write-back (also supports write-through)

Valid Combinations

AM486DX2-66V16B HC

AM486DX4-100V16B HC

AM486DX5-133W16B HC

AM486DX5-133V16B HC

Cache Size

16 = 16 Kbyte

Processor Type

DX2 =Clock-doubled with FPU

DX4 =Clock-tripled with FPU

DX5 =Clock-quadrupled with FPU

Processor Family

Am486 high-performance CPU

Enhanced Am486DX Microprocessor Family 5
P R E L I M I N A R Y
TABLE OF CONTENTS
Distinctive Characteristics......................................................................................................................................... 1
General Description .................................................................................................................................................. 1
Block Diagram........................................................................................................................................................... 2
Logic Symbol  ........................................................................................................................................................... 3
Ordering Information................................................................................................................................................. 4
Connection Diagrams and Pin Designations ............................................................................................................ 8
168-Pin PGA (Pin Grid Array) Package ............................................................................................................. 8
168-Pin PGA Designations (Functional Grouping) ............................................................................................ 9
208-Pin SQFP (Shrink Quad Flat Pack) Package ........................................................................................... 10
208-Pin SQFP Designations (Functional Grouping) ........................................................................................ 11
Pin Description ....................................................................................................................................................... 12
Functional Description  ........................................................................................................................................... 17
Overview ... ............. ............. ............ ............. ............. ............. ............. ............. ....... ............ ............. ............. ... 17
Memory ........... .................... ................... ............. ................... .................... ................... ................... ................ 17
Modes of Operation ......................................................................................................................................... 17
Cache Archite cture ................... ................... ....... ...... .................... ...... ....... ................... ...... ....... ................... ... 17
Write-Back Cache Protocol  ............................................................................................................................. 18
Cache Replaceme nt Desc rip tio n ................. ....... ...... ....... ...... ....... ...... ....... ................... ...... ....... ................... ... 19
Memory Configu ratio n . ....... ...... ...... ....... ................... ....... ...... .................... ...... ....... ................... ...... ....... ......... 19
Cache Functionality in Write-Back Mode ......................................................................................................... 19
Cache Invalidation and Flushing in Write-Back Mode ..................................................................................... 31
Burst Write ....................................................................................................................................................... 32
Clock Control  ......................................................................................................................................................... 34
Clock Generation ............................................................................................................................................. 34
Stop Clock  ....................................................................................................................................................... 34
Stop Grant Bus Cycle ...................................................................................................................................... 35
Pin State During Stop Grant ............................................................................................................................ 35
Clock Control State Diagram ........................................................................................................................... 36
SRESET Function .................................................................................................................................................. 38
System Managem ent Mode ............ ...... ....... ...... .................... ...... ....... ................... ....... ...... ................... ....... ...... ... 38
Overview ... ............. ............. ............ ............. ............. ............. ............. ............. ....... ............ ............. ............. ... 38
Terminology ..................................................................................................................................................... 38
System Management Interrupt Processing  ..................................................................................................... 39
Entering System Management Mode  .............................................................................................................. 43
Exiting System Management Mode ................................................................................................................. 43
Processor Environment ................................................................................................................................... 43
Executing Sy st em Mana gem ent Mod e Handler . ...... .................... ...... ....... ................... ...... ....... ................... ... 44
SMM System Design Considerations .............................................................................................................. 47
SMM Software Considerations ........................................................................................................................ 51
Test Registers 4 and 5 Modifications ..................................................................................................................... 51
TR4 Definition................................................................................................................................................... 52
TR5 Definition................................................................................................................................................... 53
Using TR4 and TR5 for Cache Testing ............................................................................................................ 53
Am486 Microprocessor Functional Differences  ..................................................................................................... 54
Enhanced  Am486 DX CPU Iden tific ati on ................... ...... ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ... 55
DX Register at RESET  .................................................................................................................................... 55
CPUID Instruction ............................................................................................................................................ 55
Electrical Data  .................... ....... ...... ...... ....... ...... .................... ...... ....... ................... ....... ...... ................... ....... ...... ... 56
Power and Grounding ...................................................................................................................................... 56
Absolute Maximum Ratings .................................................................................................................................... 57
Operating Ranges......... ...... ....... ...... ...... ....... ...... ....... ...... ....... ................... ....... ...... ................... ....... ...... ................ 57
DC Characteristics Over Commercial and Industrial Operating Ranges ................................................................ 57
Switching Characteristics Over Commercial and Industrial Operating Ranges...................................................... 58
AC Characteristics for Boundary Scan Test Signals at 25 MHz ............................................................................. 59
Switching Waveforms ............................................................................................................................................. 60
Package Thermal Specifications ............................................................................................................................ 64
Physical Dimensions .............................................................................................................................................. 65

6 Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
LIST OF FIGURES
Figure 1 Processor-Induced Line Transitions in Write-Back Mode .................................................................... 20
Figure 2 Snooping State Transitions .................................................................................................................. 20
Figure 3 Typical System Block Diagram for HOLD/HLDA Bus Arbitration ......................................................... 21
Figure 4 External Read ...................................................................................................................................... 22
Figure 5 External Write  ...................................................................................................................................... 22
Figure 6 Snoop of On-Chip Cache That Does Not Hit a Line  ............................................................................ 23
Figure 7 Snoop of On-Chip Cache That Hits a Non-Modified Line .................................................................... 24
Figure 8 Snoop That Hits a Modified Line (Write-Back) ..................................................................................... 24
Figure 9 Write-Back and Pending Access .......................................................................................................... 25
Figure 10 Valid HOLD Assertion During Write-Back ............................................................................................ 26
Figure 11 Closely Coupled Cache Block Diagram ............................................................................................... 27
Figure 12 Snoop Hit Cycle with Write-Back ......................................................................................................... 28
Figure 13 Cycle Reordering with BOFF (Write-Back) .......................................................................................... 29
Figure 14 Write Cycle Reordering Due to Buffering ............. ...... .................... ...... ....... ................... ...... ....... ......... 30
Figure 15 Latest Snooping of Copy-Back  ............................................................................................................ 32
Figure 16 Burst Write ........................................................................................................................................... 33
Figure 17 Burst Read with BOFF Assertion ......................................................................................................... 33
Figure 18 Burst Write with BOFF Assertion ......................................................................................................... 33
Figure 19 Entering Stop Grant State .................................................................................................................... 36
Figure 20 Stop Clock State Machine .................................................................................................................... 37
Figure 21 Recognition of Inputs when Exiting Stop Grant State .......................................................................... 37
Figure 22 Basic SMI Interrupt Service  ................................................................................................................. 39
Figure 23 Basic SMI Hardware Interface.............................................................................................................. 40
Figure 24 SMI Timing for Servicing an I/O Trap ................................................................................................... 40
Figure 25 SMIACT Timi ng  ....... ...... ................... ....... ...... .................... ...... ....... ................... ...... ....... ................... ... 41
Figure 26 Redirecting System Memory Address to SMRAM ............................................................................... 41
Figure 27 Transition to and from SMM ................................................................................................................. 43
Figure 28 Auto HALT Restart Register Offset....................................................................................................... 45
Figure 29 I/O Instruction Restart Register Offset ................................................................................................. 46
Figure 30 SMM Base Slot Offset .......................................................................................................................... 46
Figure 31 SRAM Usage ....................................................................................................................................... 47
Figure 32 SMRAM Location ................................................................................................................................. 47
Figure 33 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Through Mode
with Caching Enabled During SMM...................................................................................................... 48
Figure 34 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Back Mode 
with Caching Enabled During SMM...................................................................................................... 48
Figure 35 SMM Timing in Systems Using Non-Overlaid Memory Space and Write-Back Mode 
with Caching Disabled During SMM ..................................................................................................... 48
Figure 36 SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode 
with Caching Enabled During SMM...................................................................................................... 49
Figure 37 SMM Timing in Systems Using Overlaid Memory Space and Write-Through Mode 
with Caching Disabled During SMM ..................................................................................................... 49
Figure 38 SMM Timing in Systems Using Overlaid Memory Space and Configured in Write-Back Mode ........... 49
Figure 39 CLK Waveforms ................................................................................................................................... 60
Figure 40 Output Valid Delay Timing ................................................................................................................... 60
Figure 41 Maximum Float Delay Timing  .............................................................................................................. 61
Figure 42 PCHK Valid Dela y Timi ng ... ....... ...... ....... ...... ....... ...... ....... ...... ....... ................... ...... ....... ................... ... 61
Figure 43 Input Setup and Hold Timing  ............................................................................................................... 62
Figure 44 RDY and BRDY Input Setup and Hold Timing ..................................................................................... 62
Figure 45 TCK Waveforms ................................................................................................................................... 63
Figure 46 Test Signal Timing Diagram ................................................................................................................. 63

Enhanced Am486DX Microprocessor Family 7
P R E L I M I N A R Y
LIST OF TABLES
Table 1 Clocking Options .................................................................................................................................... 1
Table 2 CLKMUL Settings ................................................................................................................................. 13
Table 3 EADS Sampl e Time ............ ....... ...... ....... ...... ....... ................... ....... ...... ................... ....... ...... ................ 14
Table 4 Cache Line Organization  ..................................................................................................................... 18
Table 5 Legal Cache Line States ...................................................................................................................... 18
Table 6 MESI Cache Line Status ...................................................................................................................... 19
Table 7 Key to Switching Waveforms ............................................................................................................... 21
Table 8 WBINVD/INVD Special Bus Cycles ..................................................................................................... 32
Table 9 FLUSH Special Bus Cycles  ................................................................................................................. 32
Table 10 Pin State During Stop Grant Bus State ................................................................................................ 35
Table 11 SMRAM State Save Map ..................................................................................................................... 42
Table 12 SMM Initial CPU Core Register Settings  ............................................................................................. 44
Table 13 Segment Register Initial States ............................................................................................................ 44
Table 14 SMM Revision Identifier ....................................................................................................................... 45
Table 15 SMM Revision Identifier Bit Definitions ................................................................................................ 45
Table 16 HALT Auto Restart Configuration  ........................................................................................................ 46
Table 17 I/O Trap Word Configuration ................................................................................................................ 46
Table 18 Test Register TR4 Bit Descriptions ...................................................................................................... 52
Table 19 Test Register TR5 Bit Descriptions ...................................................................................................... 52
Table 20 Am486 Family Functional Differences.................................................................................................. 54
Table 21 CPU ID Codes  ..................................................................................................................................... 55
Table 22 CPUID Instruction Description ............................................................................................................. 55
Table 23 Thermal Resistance (°C/W) θJC and θJA for the Enhanced Am486DX CPU in 168-Pin PGA Package  64
Table 24 Maximum TA at Various Airflows in °C for Commercial Temperatures (85°C)...................................... 64
Table 25 Maximum TA at Various Airflows in °C for Industrial Temperatures (100°C) ........................................ 64

8 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

1 CONNECTION DIAGRAMS AND PIN DESIGNATIONS

1.1 168-Pin PGA (Pin Grid Array) Package

PIN SIDE VIEW

Enhanced Am486DX Microprocessor Family 9

P R E L I M I N A R Y

1.2 168-Pin PGA Designations (Functional Grouping)

Address Data Control Test INC Vcc Vss

Name Pin

No. Pin

Name Pin

No. Pin

Name Pin

No. Pin

Name Pin

No. Pin

No.

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

Q-14

R-15

S-16

Q-12

S-15

Q-13

R-13

Q-11

S-13

R-12

S-7

Q-10

S-5

R-7

Q-9

Q-3

R-5

Q-4

Q-8

Q-5

Q-7

S-3

Q-6

R-2

S-2

S-1

R-1

P-2

P-3

Q-1

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

P-1

N-2

N-1

H-2

M-3

J-2

L-2

L-3

F-2

D-1

E-3

C-1

G-3

D-2

K-3

F-3

J-3

D-3

C-2

B-1

A-1

B-2

A-2

A-4

A-6

B-6

C-7

C-6

C-8

A-8

C-9

B-8

A20M

ADS

AHOLD

BE0

BE1

BE2

BE3

BLAST

BOFF

BRDY

BREQ

BS8

BS16

CACHE

CLK

CLKMUL

D/C

DP0

DP1

DP2

DP3

EADS

FERR

FLUSH

HITM

HLDA

HOLD

IGNNE

INTR

INV

KEN

LOCK

M/IO

NMI

PCD

PCHK

PLOCK

PWT

RDY

RESET

SMI

SMIACT

SRESET

STPCLK

VOLDET

WB/WT

W/R

D-15

S-17

A-17

K-15

J-16

J-15

F-17

R-16

D-17

H-15

Q-15

D-16

C-17

B-12

C-3

R-17

M-15

N-3

F-1

H-3

A-5

B-17

C-14

C-15

A-12

P-15

E-15

A-15

A-16

A-10

F-15

N-15

N-16

B-15

J-17

Q-17

Q-16

L-15

F-16

C-16

B-10

C-12

C-10

G-15

C-11

S-4

B-13

N-17

TCK

TDI

TDO

TMS

A-3

A-14

B-16

B-14

A-13

C-13

J-1

B-7

B-9

B-11

C-4

C-5

E-2

E-16

G-2

G-16

H-16

K-2

K-16

L-16

M-2

M-16

P-16

R-3

R-6

R-8

R-9

R-10

R-11

R-14

A-7

A-9

A-11

B-3

B-4

B-5

E-1

E-17

G-1

G-17

H-1

H-17

K-1

K-17

L-1

L-17

M-1

M-17

P-17

Q-2

R-4

S-6

S-8

S-9

S-10

S-11

S-12

S-14

Notes:

1. VOLDET is connected internally to V

2. INC = Internal No Connect

10 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

1.3 208-Pin SQFP (Shrink Quad Flat Pack) Package

TOP VIEW

Enhanced Am486DX Microprocessor Family 11

P R E L I M I N A R Y

1.4 208-Pin SQFP Designations (Functional Grouping)

Address Data Control Test INC Vcc Vss

Pin Name Pin

No. Pin Name Pin

No. Pin

Name Pin

No. Pin

Name Pin

No. Pin

No.

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

202

197

196

195

193

192

190

187

186

182

180

178

177

174

173

171

166

165

164

161

160

159

158

154

153

152

151

149

148

147

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

144

143

142

141

140

130

129

126

124

123

119

118

117

116

113

112

108

103

101

100

A20M

ADS

AHOLD

BE0

BE1

BE2

BE3

BLAST

BOFF

BRDY

BREQ

BS8

BS16

CACHE

CLK

CLKMUL

D/C

DP0

DP1

DP2

DP3

EADS

FERR

FLUSH

HITM

HLDA

HOLD

IGNNE

INTR

INV

KEN

LOCK

M/IO

NMI

PCD

PCHK

PLOCK

PWT

RDY

RESET

SMI

SRESET

STPCLK

SMIACT

WB/WT

W/R

203

204

145

125

109

207

206

194

TCK

TDI

TDO

TMS

168

167

127

102

106

111

114

121

128

131

133

134

136

137

139

150

155

162

163

169

172

176

179

183

185

188

191

198

200

205

104

105

107

110

115

120

122

132

135

138

146

156

157

170

175

181

184

189

199

201

208

Note:

INC = Internal No Connect

12 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

2 PIN DESCRIPTION

The Enhanced Am486DX microprocessors provide the

complete interface support offered by the Enhanced

Am486 family. However, the CLKMUL pin settings have

changed to a ccommodate the highe r operating speed

selection. For more information on how all Am486 pro-

cessors differ, see section 8 on page 54.

A20M

Address Bit 20 Mask (Active Low; Input)

A Low signal on the A20M pin causes the microproces-

sor to mask address line A20 before performing a lookup

to the internal cache, or driving a memory cycle on the

bus. Asserting A20M causes the processor to wrap the

address at 1 Mbyte, emulating Real mode operation.

The signal i s asynchronous, but must me et setup and

hold times t20 and t21 for recognition during a specific

clock. Durin g nor mal op eration, A20M shoul d be s am-

pled High at the falling edge of RESET.

A31–A4/A3–A2

Address Lines (Inputs/Outputs)/(Outputs)

Pins A31–A2 define a physical area in memory or indi-

cate an input/output (I/O) device. Address lines A31–A4

drive addresses into the microprocessor to perform

cache line invalidations. Input signals must meet setup

and hold times t22 and t23. A31–A2 are not driven during

bus or address hold.

ADS

Address Status (Active Low; Output)

A Low output from this pin indicates that a valid bus

cycle def ini tio n a nd addre ss a r e a vailable o n the cy cle

definition lines and address bus. ADS is driven active by

the same clo ck as th e addr esses. A DS is active Low and is

not driven during bus hold.

AHOLD

Address Hold (Active High; Input)

The external system ma y assert AHOLD to perform a

cach e snoop. In respo nse to the asserti on of AHOLD,

the microprocessor stops driving the address bus A31–

A2 in t he nex t cl ock. The da ta bus r emai ns acti ve a nd

data can be transferred for previously issued read or

write bus cycles during address hold. AHOLD is recog-

nized even during RESET and LOCK. The ea rlie st t hat

AHOLD can be deasserted is two clock cycles after

EADS is asserted to start a cache snoop. If HITM is

activated due to a cache snoop, the microprocessor

completes the current bus activity and then asserts ADS

and drives the address bus while AHOLD is active. This

starts the write-back of the modified line that was the

target of the snoop.

BE3–BE0

Byte Enable (Active Low; Outputs)

The byte enable pins indicate which bytes are enabled

and active during read or write cycles. During the first

cache fill cycle, however, an external system should

ignore these signals and assume that all bytes are

active.

■BE3 for D31–D24

■BE2 for D23–D16

■BE1 for D15–D8

■BE0 for D7–D0

BE3–BE0 are active Low and are not driven during bus

hold.

BLAST

Burst Last (Active Low; Output)

Burst Last goes Low to tell the CPU that the next BRDY

signal completes the burst bus cycle. BLAST is active

for both burst and non-burst cycles. BLAST is active

Low and is not driven during a bus hold.

BOFF

Back Off (Active Low; Input)

This input signal forces the microprocessor to float all

pins no rmally floated d uring hold, but HLDA is not as-

serted in response to BOFF. BOFF has h igher prio rity

than RDY or BRDY; if both are returned in the same

clock, BO FF takes effect. The microprocessor remains

in bus hold until BOFF goes High. If a bus cycle is in

progress when BOFF is asserted, the cycle restarts.

BOFF must meet setup an d hold times t18 and t19 for

proper operation. BOFF has an internal weak pull-up.

BRDY

Burst Ready Input (Active Low; Input)

The BRDY sign al p erfor ms the same functi on d uring a

burst cycle that RDY performs during a non-burst cycle.

BRDY indicates that the external system has presented

valid data in response to a read, or that the external

system has accepted data in response to a write. BRDY

is ignored when the bus is idle and at the end of the first

clock in a bus cycle. BRDY is sampled in the second

and subs equent cloc ks of a burst cyc le. The data pr e-

sented on the data bus is strobed into the microproces-

sor w hen BRDY is sampled a ctive. If RDY is returned

simultaneously with BRDY, BRDY is ignored and the

cycle is converted to a non-burst cycle. BRDY is active

Low an d has a small pu ll-up resi stor, and must satis fy

the setup and hold times t16 and t17.

BREQ

Internal Cycle Pending (Active High; Output)

BREQ indicates that the microprocessor has generated

a bus request internally, whether or not the micropro-

Enhanced Am486DX Microprocessor Family 13

P R E L I M I N A R Y

cessor is driving the bus. BREQ is active High and is

floated only during three-state Test mode (see FLUSH).

BS8/BS16

Bus Size 8 (Active Low; Input)/

Bus Size 16 (Active Low; Input)

The BS8 a nd BS16 s ignals al low the proc essor to op-

erate with 8-bit and 16-bit I/O devices by running multiple

bus cycles to respond to data requests: four for 8-bit

devices, and two for 16-bit devices. The bus sizing pins

are sampled every clock. The microprocessor samples

the pins every clock be fore RDY to determine the ap-

propriate bus size for the requesting device. The signals

are active Low input with internal pull-up resistors, and

must satisfy setup and hold times t14 and t15 for c orr ect

operation. Bus sizing is not permitted during copy-back

or write-back operation. BS8 and BS16 are ignored dur-

ing copy-back or write-back cycles.

CACHE

Internal Cacheability (Active Low; Output)

In Write-through mode, this signal always floats. In

Write-bac k mode for pr ocessor-initi ated cycles, a L ow

output on this p in indica tes that the curre nt read c ycle

is cachea ble, or that the current c ycle is a burst write-

back or copy-back cycle. If the CACHE signal is driven

High during a read, the processor will not cache the data

even if the KEN pin signal is asserted. If the processor

determines that the data is cacheable, CACHE goes

active whe n ADS is asserted and remains in that state

until the next RDY or BRDY is asserted. CACHE floats

in respons e to a BOFF or HOLD request.

CLK

Clock (Input)

The CLK input provides the basic microprocessor timing

signal. The CLKMUL inp ut selects the multiplier v alue

used to generate the internal operating frequency for

the Enhanced Am486DX microprocessors. All external

timing parameters are specified with respect to the rising

edge of CLK. The clock signal passes through an inter-

nal Phase-Lock Loop (PLL).

CLKMUL

Clock Multiplier (Input)

The microprocessor samples the CLKMUL input signal

at RESET to determine the design operating frequency.

Table 2 shows the effects CLKMUL has on system con-

figurations for various Enhanced Am486DX micropro-

cessors.

2x indicates that the CPU runs at twice the system bus speed.

3x indicates that the CPU runs at three times the system bus speed.

4x indicates that the CPU runs at four times the system bus speed.

D31–D0

Data Lines (Inputs/Outputs)

Lines D31–D0 define the data bus. The signals must

meet setup and hold times t22 and t23 for prope r read

operations. These pins are driven during the second

and subsequent clocks of write cycles.

D/C

Data/Control (Output)

This bus cycle definition pin distinguishes memory and

I/O data cycles from control cycles. The control cycles

are:

■Interrupt Acknowledge

■Halt/Special Cycle

■Code Read (instruction fetching)

DP3–DP0

Data Parity (Inputs/Outputs)

Data parity is generated on all write data cycles with the

same timing as the data driven by the microprocessor.

Even parity information must be driven back into the

microprocessor on the data parity pins with the same

timing as read information to ensure that the processor

uses the correct parity check. The signals read on these

pins do not affect program execution. Input signals must

meet setup and hold times t22 and t23. DP3–DP0 should

be conne cted to VCC through a pull-up resist or in sys-

tems not using parity. DP3–DP0 are active High and are

driven during the second and subsequent clocks of write

cycles.

EADS

External Address Strobe (Active Low; Input)

This si gnal indicate s that a valid ex ternal address has

been driv en on the address p ins A 31– A4 of the mic r o-

proce ssor to be use d fo r a cac he s no op. This s ign al is

recognized while the processor is in hold (HLDA is driv-

en active), while forced off the bus with the BOFF input,

or while AHOLD is asserted. The microprocessor ig-

nores E ADS at all other times. EADS is not rec ogniz ed

if HITM is active, nor during the clock after ADS, nor

during the clock after a valid assertion of EADS. Snoops

to the on-chip cache must be completed before another

snoop cycle is initiated. Table 3 describes EADS when

firs t sam ple d. EADS can be asserted every other clock

cycle as l ong a s the h old remains acti ve a nd HITM re-

Table 2. CLKMUL Settings

Processor CLKMUL=1 CLKMUL=0

Am486DX2-66 Undefined 2x

Am486DX4-100 3x Undefined

Am486DX5-133 Undefined 4x

14 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

mains inactive. INV is sampled in the same clock period

that EADS is asserted. EADS has an internal weak pull-

up.

Note:

The triggeri ng signal (AHOLD, H OLD, or BOFF) must

remain active for at least 1 clock after EADS to ensure

proper opera tion .

FERR

Floating-Point Error (Active Low; Output)

Driven active when a floating-point error occurs, FERR

is similar to the ERROR pin on a 387 math coprocessor.

FERR is included for compatibility with systems using

DOS-type floating-point error reporting. FERR is active

Low, and i s not flo ated during bus hold , except dur ing

three-state Test mode (see FLUSH).

FLUSH

Cache Flush (Active Low; Input)

In Write-back mode, FLUSH forces the microprocessor

to write-back all modified cache lines and invalidate its

internal cache. The microprocessor generates two flush

acknowledge special bus cycles to indicate completion

of the write-back and invalidation. In Write-through

mode, FLUSH invali dates the cache without issuing a

special bus cycle. FLUSH is an active Low input that

needs to be asserted only for one clock. FLUSH is asyn-

chronous, but setup and hold times t20 and t21 must be

met for recognition in any specific clock. Sampling

FLUSH Low in the clock before the falling edge of

RESET causes the microprocessor to enter three-state

Test mode.

HITM

Hit Modified Line (Active Low; Output)

In Write-back mode (WB/WT=1 at RESET), HITM indi-

cates that a n ex ternal sn oop cac he tag c omp aris on hi t

a modified line. When a snoop hits a modified line in the

internal cache, the microprocessor asserts HITM two

clocks after EADS is asserted. The HITM signa l stays

asserted (Low) until the last BRDY for the corresponding

write-back cycle. At all other times, HITM is deasserted

(High). During RESET, the HITM signal can be used to

detect whether the CPU is operating in Write-back

mode. In Write-back mode (WB/WT=1 at RESET), HITM

is deasserted (driven High) until the first snoop that hits

a modifie d line. In Write-throug h mode, HITM floa ts at

all times.

HLDA

Hold Acknowledge (Active High; Output)

The HLD A sig nal is a ctiv ated in re sp onse to a hol d r e-

quest presented on the HOLD pin. HLDA indicates that

the m icroproces sor has gi ven th e bus to an other loc al

bus master. HLDA is driven active in the same clock in

which the microprocessor floats its bus. HLDA is driven

inactive when leaving bus hold. HLDA is active High and

remains driven during bus hold. HLDA is floated only

during three-state Test mode (see FLUSH).

HOLD

Bus Hold Request (Active High; Input)

HOLD gives control of the microprocessor bus to anoth-

er bus m aster. In response to HOLD going act ive, the

microprocessor floats most of its output and input/output

pins. HLDA is asserted after completing the current bus

cycle, burst cycle, or sequence of locked cycles. The

microprocessor remains in this state until HOLD is deas-

serte d. HOLD i s active High and does not h ave a n in-

ternal pull-down resistor. HOLD must satisfy setup and

hold times t18 and t19 for proper operation.

IGNNE

Ignore Numeric Error (Active Low; Input)

When this pin is asserted, the Enhanced Am486DX mi-

croprocessors will ignore a numeric error and continue

executing non-control floating-point instructions. When

IGNNE is deasserted, the Enhanced Am486DX micro-

processors will freeze on a non-control floating-point

instruction if a previous floating-point instruction caused

an error. IGNNE has no effect when the NE bit in Control

Registe r 0 is set. IG NNE is active Low and is provided

with a small internal pullup resistor. IGNNE is asynchro-

nous but must meet setup and hold times t20 and t21 to

ensure recognition in any specific clock.

INTR

Maskable Interrupt (Active High; Input)

When asserted, this signal indicates that an external

interrupt has been generated. If the internal interrupt

flag is set in EFLAGS, active interrupt processing is ini-

tiated. The microprocessor generates two locked inter-

rupt ac knowledge bus cycles in response to t he INTR

pin goi ng active. INTR must r emain acti ve until the in-

terru pt acknowled ges have bee n performed to ensure

that the interrupt is recognized. INTR is active High and

is not provided with an internal pull-down resistor. INTR

is asynchronou s, but must meet setup and hold times

t20 and t21 for recognition in any specific clock.

INV

Invalidate (Active High; Input)

The external system asserts INV to invalidate the cache-

line state when an external bus master proposes a write.

It is s ample d toget her wi th A31 –A4 d uring the clock in

Table 3. EADS Sample Time

Trigger EADS First Sampled

AHOLD Second clock after AHOLD asserted

HOLD First clock after HLDA asserted

BOFF Second clock after BOFF asserted

Enhanced Am486DX Microprocessor Family 15

P R E L I M I N A R Y

which EADS is active. INV has an internal weak pull-up.

INV is ignored in Write-through mode.

KEN

Cache Enable (Active L ow; Input)

KEN determines whether the current cycle is cacheable.

When the microprocessor generates a cacheable cycle

and KEN is active one clock before RDY or BRDY during

the first transfer of the cycle, the cycle becomes a cache

line fill cycle. Returning KEN active one clock before

RDY during the last read in the cache line fill causes the

line to be placed in the on-chip cache. KEN is active

Low and is provided with a small internal pull-up resistor.

KEN must satisfy setup and hold times t14 and t15 for

proper opera tion .

LOCK

Bus Lock (Active Low; Output)

A Low output on th is pin i ndica tes that the cu rrent bus

cycle is locked. The microprocessor ignores HOLD

when LOCK is asserted (although it does acknowledge

AHOLD and BOFF). LOCK goes active in the first clock

of the first locked bus cycle and goes inactive after the

last clock of the last locked bus cycle. The last locked

cycle ends when RDY is returned. LOCK is active Low

and is n ot driven during bus hold. Lock ed read cyc les

are not transformed into cache fill cycles if KEN is active.

M/IO

Memory/Input-Output (Active High/Active Low;

Output)

A High output i ndi ca tes a mem ory c ycl e. A Lo w outp ut

indicates an I/O cycle.

NMI

Non-Maskable Interrupt (Active High; Input)

A High NMI input signal indicates that an external non-

maskable interrupt has occurred. NMI is rising-edge

sensiti ve. NMI must be held Low for at leas t four CLK

periods before this rising edge. The NMI input does not

have an internal pull-down resistor. The NMI input is

asynchronous, but must meet setup and hold times t20

and t21 for recognition in any specific clock.

PCD

Page Cache Disable (Active High; Output)

This pin reflects the state of the PCD bit in the page

table entry or page directory entry (programmable

through th e PCD bi t in CR3). If paging is di sabl ed, the

CPU ignores the PCD bit and drives the PCD output

Low. PCD has the same timing as the cycle definition

pins (M/IO, D/C, and W/R). P CD is active High and is

not driven during bus hold. PCD is masked by the Cache

Disable bit (CD) in Control Register 0 (CR0).

PCHK

Parity Status (Active Low; Output)

Parit y status is drive n on the PCHK pin the cloc k after

RDY for read operations. The parity status reflects data

sampled at the end of the previous clock. A Low PCHK

indicates a parity error. Parity status is checked only for

enabled bytes as is indicated by the byte enable and

bus size sign als. PCHK is valid only in the clock imme-

diately after read data is returned to the microprocessor;

at all other times PCHK is inactive High. PCHK is floated

only during three-state Test mode (see FLUSH).

PLOCK

Pseudo-Lock (Active Low; Output)

In Write-back mode, the processor forces the output

High and the signal is always read as inactive. In Write-

through mode, PLOCK operates normally. When

asserted, PLOCK indicates that the current bus

transaction requires more than one bus cycle. Examples

of suc h ope r atio ns a re s egm ent ta ble d es crip tor reads

(8 byte s) and cache line fill s (16 by tes). The m icro pro-

cessor dri ves PLO CK active until the addresses for the

last bus cycle of the transaction have been driven,

whether or not RDY or BRD Y is returned. PLOCK is a

function of the BS8, BS16, and KEN inputs. PLOCK

should be sampled on the clock when RDY is returned.

PLOCK is active Low and is not driven during bus hold.

PWT

Page Write-Through (Active High; Output)

This pin reflects the state of the PWT bit in the page

table entry or page directory entry (programmable

through the PWT bi t i n CR3 ). If pa gi ng i s dis ab led , th e

CPU ignores the PWT bit and drives the PWT output

Low. PWT has the sa me timing as the cycle defini tion

pins (M/IO, D /C, and W/R) . PWT is a ctive High and is

not driven during bus hold.

RESET

Reset (Active High; Input)

RESET forces the microprocessor to initialize. The mi-

croprocessor cannot begin execution of instructions un-

til a t leas t 1 ms af ter VCC and CLK h ave reac hed the ir

proper DC and AC specifications. To ensure proper mi-

croproc ess or ope ratio n, the RESE T pi n shoul d r em ai n

active dur ing this time. RES ET is active High. RE SET

is asynchronous but must meet setup and hold times

t20 and t21 to ensure recognition on any specific clock.

RDY

Non-Burst Ready (Active Low; Input)

A Low input on this pin indicates that the current bus

cycle is complete, that is, either the external system has

presented valid data on the data pins in response to a

read, or the external system has accepted data from the

micropr oc ess or in res po nse to a wr ite . RD Y is i gnored

when the bus is i dle and at the end of th e bus cycle’s

16 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

first cl ock. RDY is active during address hold. Data can

be returned to the processor while AHOLD is active.

RDY is active Low and does not have an internal pull-

up resistor. RDY must satis fy se tup and ho ld times t16

and t17 for proper chip operation.

SMI

SMM Interrupt (Active Low; Input)

A Low signal on the SMI pin signals the processor to

enter System Management mode (SMM). SMI is the

highest level processor interrupt. The SMI signal is rec-

ognized on an instruc ti on bou nda ry , si mi lar t o th e N MI

and INTR signals. SMI is sampled on every rising clock

edge. SMI is a falling-edge sensitive input. The SMI input

has an internal pull-up resister. Recognition of SMI is

guarantee d i n a s pec ifi c c lock if it is as s er ted sy nc hro-

nously and meets the setup and hold times. If SMI is

asserted asynchronously, it must go High for a minimum

of two clocks before going Low, and it must remain Low

for at least two clock s to guarantee re cognitio n. When

the CPU recognizes SMI, it enters SMM before execut-

ing the next instructio n and saves internal registers in

SMM space.

SMIACT

SMM Interrupt Activ e (Active Low; Output)

SMIACT goes Low in response to SMI. It indicates that

the processor is operating under SMM control. SMIACT

remains Low until the processor receives a RESET sig-

nal or executes the Resume Instruction (RSM) to leave

SMM. This signal is always driven. It does not float dur-

ing bus HOLD or BOFF.

Note: Do not use SRESET to exit from SMM. The sys-

tem should block SRESET during SMM.

SRESET

Soft Reset (Active High; Input)

The CPU samples SRESET on every rising clock edge.

If SRESET is sampled active, the SRESET sequence

begins on the next instruction boundary. SRESET

resets the processor, but, unlike RESET, does not cause

it to sample UP or WB/WT, or affect the FPU, cache, CD

and NW bits in CR0, and SMBASE. SRESET is asyn-

chronous and must meet the same timing as RESET.

The SRESET input has an internal pull-down resistor.

STPCLK

Stop Clock (Active Low; Input)

A Low input signal indicates a request has been made

to turn off the CLK inp ut. When the CPU reco gnizes a

STPCLK, the processor:

■Stops execution on the next instruction boundary

(unless superseded by a higher priority interrupt)

■Empties all internal pipelines and write buffers

■Generates a Stop Grant acknowledge bus cycle

STPCLK is active Low a nd has an internal pull-up re-

sistor. STPCLK is asynchronous, but it must meet setup

and hol d ti mes t20 a nd t 21 to ensure r ec ogn iti on in any

specific clock. STPCLK must remain active until the Stop

Clock special bus cycle is issued and the system returns

either RDY or BRDY.

TCK

Test Clock (Input)

Test Clock provides the clocking function for the JTAG

boundary scan feature. TCK clocks state information

and data into the component on the rising edge of TCK

on TMS and TDI, respectively. Data is clocked out of

the component on the falling edge of TCK on TDO. TCK

uses an internal weak pull-up.

TDI

Test Data Input (Input)

TDI is the serial input that shifts JTAG instructions and

data into the tested component. TDI is sampled on the

rising edge of TCK during the SHIFT-IR and the

SHIFT-DR TAP (Test Access Port) controller states.

During all other TAP controller states, TDI is ignored.

TDI uses an internal weak pull-up.

TDO

Test Data Output (Active High; Output)

TDO is the serial output that shifts JTAG instructions

and data out of the component. TDO is driven on the

falling edge of TCK during the SHIFT-IR and SHIFT-DR

TAP controller states. Otherwise, TDO is three-stated.

TMS

Test Mode Select (Active High; Input)

TMS is decoded by the JTAG TAP to select the operation

of the t est log ic. TMS is sa mpled o n the risi ng edge o f

TCK. To guarantee deterministic behavior of the TAP

controller, the TMS pin has an internal pull-up resistor.

Write/Read (Input)

The proc essor s amples the U pgrade Prese nt (UP ) pi n

in the clock before the falling edge of RESET. If it is Low,

the processor three-states its outputs immediately. UP

must remain asserted to keep the processor inactive.

The pin uses an internal pull-up resis tor.

VOLDET—(168-Pin PGA Package Only)

Voltage Detect (Output)

VOLDET provides an external signal to allow the system

to determine the CPU input power level (3 V or 5 V). For

the Enhanced Am486DX microprocessors, the pin ties

internally to VSS.

Enhanced Am486DX Microprocessor Family 17

P R E L I M I N A R Y

WB/WT

Write-Back/Write-Through (Input)

If the processor samples WB/WT High at RESET, t he

processor is configured in Write-back mode and all sub-

sequent cache line fills sample WB/WT on the same

clock edge in which it finds either RDY or the first BRDY

of a burst transfer to determine if the cache line is des-

ignated as Write-back mode or Write-through. If the sig-

nal is L ow on the firs t BRDY or RDY, the c ache l ine i s

write-through. If the signal is High, the cache line is write-

back. If WB/WT is sampled Low at RESET, all cache

line fills are write-through. WB/WT has an internal weak

pull-down.

W/R

Write/Read (Output)

A High output in dicat es a writ e cycle. A Lo w output in-

dicates a read cycle.

Note: The Enhanced Am486DX microprocessors do

not use the V

CC5

pin used by some 3-V,

486

-based

processors. The corresponding pin on the Enhanced

Am486DX m icroprocess ors is an Interna l No Connect

(INC).

3 FUNCTIONAL DESCRIPTION

3.1 Overview

The Enhanced Am486DX microprocessors use a 32-bit

architecture with on-chip memory management and

cache memory units. The instruction set includes the

complete 486 microprocessor instruction set along with

extensions to serve the new extended applications. All

applications written for the 486 microprocessor and pre-

vious mem bers of the x86 a rchitec tural family ca n run

on the Enhanced Am486DX microprocessors without

modification.

The on-chip Memory Management Unit (MMU) is com-

pletely compatible with the 486 MMU. The MMU in-

cludes a segmentation unit and a paging unit.

Segmentation allows management of the logical ad-

dress sp ac e b y prov idi ng easy d ata and c ode r elo cati-

bility and efficient sharing of global resources. The

paging mechanism operates beneath segmentation and

is transparent to the segmentation process. Paging is

optional and can be disabled by system software. Each

segment can be divided into one or more 4-Kbyte seg-

ments. To implement a virtual memory system, the En-

hanced Am486DX microprocessors support full

restartability for all page and segment faults.

3.2 Memory

Memory is organize d into one or more vari able length

segments, each up to 4 Gbytes (232 bytes). A segment

can have attributes a ssociated with it, includi ng its lo-

cation, size, type (i.e., stack, code, or data), and protec-

tion characteristics. Each task on a microprocessor can

have a maximum of 16,381 segments, each up to

4 Gbytes. Thus, each task has a maximum of 64 Tbytes

of virtual memory.

The segmentation unit provides four levels of protection

for isolating and protecting applications and the operat-

ing system from each other. The hardware-enforced

protection allows high-integrity system designs.

3.3 Modes of Operation

The Enhanced Am486DX microprocessors have four

modes o f ope ratio n: Rea l A ddr ess mod e (R eal mod e),

Virtual 8086 Address mode (Virtual mode), Protected

Address mode (Protected mode), and System Manage-

ment mode (SMM).

3.3.1 Real Mode

In Real mode, the Enhanced Am486DX microproces-

sors operate as a fast 8086. Real mode is required pri-

marily to set up the processor for Protected mode

operation.

3.3.2 Virtual Mode

In Virtual mode, the processor appears to be in Real

mode, but can use the extended memory accessing of

Protected mode.

3.3.3 Protected M ode

Protected mode provides access to the sophisticated

memory management paging and privilege capabilities

of the processor.

3.3.4 System Management Mode

SMM is a special operating mode described in detail in

Section 6, beginning on page 38.

3.4 Cache Architecture

The Enhanced Am486DX microprocessors support a

superset architecture of the standard 486DX cache im-

plementation. This architectural enhancement improves

not only CPU performance, but total system perfor-

mance.

3.4.1 Write-Through Cache

The stand ard 486DX write- through cache architectur e

is characterized by the following:

■External read accesses are placed in the cache if

they meet proper caching requirements.

■Subsequent reads to the data in the cache are made

if the address is stored in the cache tag array.

■Write operations to a valid address in the cache are

updated in the cache

and

to exter nal mem or y. This

data writing technique is called

write-through

The write-through cache implementation forces all

writes to flow through to the external bus and back to

main memory. Consequently, the write-through cache

generates a large amount of bus traffic on the external

data bus.

18 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

3.4.2 Write-Back Cache

The microprocessor write-back cache architecture is

characterized by the following:

■External read accesses are placed in the cache if

they meet proper caching requirements.

■Subsequent reads to the data in the cache are made

if the address is stored in the cache tag array.

■Write operations to a valid address in the cache that

is in the write-through (shared) state is updated in

the cache and to external memory.

■Write operations to a valid address in the cache that

is in the write-back (exclusive or modified) state is

updated

only

in the c ache. Extern al memory is

not

updated at the time of the cache update.

■Modified data is written back to external memory

when the modified cache line is being replaced with

a new cache line (copy-back operation) or an exter-

nal bus mas ter has snooped a mo dified ca che line

(write-back).

The write-bac k cache feat ure significan tly reduces the

amount of bus traffic on the external bus; however, it

also adds co mplex ity to the sy stem des ign to mai ntain

memory coherency. The write-back cache requires en-

hanced system support because the cache may contain

data that is not identical to data in main memory at the

same address location.

3.5 Write-Bac k Ca che Protocol

The Enhanced Am486DX microprocessor write-back

cache coherency protocol reduces bus activity while

maintaining data coherency in a multimaster environ-

ment. The cache coherency protocol offers the following

advantages:

■No unnecessary bus traffic. The protocol dynamical-

ly identifies shared data to the granularity of a cache

line. This dynamic identification ensures that the traf-

fic on the external bus is the minimum necessary to

ensure coherency.

■Software-transparent. Because the protocol gives

the appearance of a single, unified memory, soft-

ware does not have to maintain coherency or identify

shared data. Application software developed for a

system without a cache can run without modification.

Software support is required only in the operating

system to identify non-cacheable data regions.

The Enhance d Am486DX m icroprocesso rs impleme nt

a modified MESI protocol on systems with write-back

cache support. MESI allows a cache line to exist in four

states: modified, exclusive, shared, and invalid. The En-

hanced Am486DX microprocessors allocate memory in

the cache due to a read miss. Write allocation is not

implemented. To maintain coherency between cache

and main memory, the MESI protocol has the following

characteristics:

■The system memory is always updated during a

snoop when a modified line is hit.

■If a modified line is hit by another master during

snooping, the master is forced off the bus and the

snoope d cach e writ es bac k the m odifie d line to the

system memory. After the snooped cache completes

the wri te, the forc ed-of f bus mast er re starts t he ac-

cess and reads the modified data from memory.

3.5.1 Cache Line Overview

To implement the Enhanced Am486DX microprocessor

cache-coherency protocol, each tag entry is expanded

to 2 bi ts : S 1 and S 0. E ac h tag en try is as soc ia ted wit h

a cache line. Table 4 shows the cache line organization.

Table 4. Cache Line Organization

3.5.2 Line Status and Line State

A cache line can occupy one of four legal states as

indicated by bits S0 and S1. The line states are shown

in Table 5. Each line in the cache is in one of these

states. The state transition is induced either by the pro-

cessor or during snooping from an external bus master.

3.5.2.1 Invalid

An invalid cache line does not contain valid data for any

external memory location. An invalid line does not par-

ticipate in the cache coherency protocol.

3.5.2.2 Exclusive

An exclusive line contains valid data for some external

memory location. The data exactly matches the data in

the external memory location.

3.5.2.3 Shared

A shared line contains valid data for an external memory

locati on, the data i s shar ed by another c ache, and th e

share d data matches the data i n the external memor y

exactly; or the cache line is in Write-through mode.

Data Words (32 Bits) Address Tag and Status

D0 Address Tag, S1, S0

Table 5. Legal Cache Line States

S1 S0 Line State

0 0 Invalid

0 1 Exclusive

1 0 Modified

1 1 Shared

Enhanced Am486DX Microprocessor Family 19

P R E L I M I N A R Y

3.5.2.4 Modified

A modified line contains valid data for an external mem-

ory location. However, the data does not match the data

in the external location because the processor has mod-

ified the data since it was loaded from the external mem-

ory. A cache that contains a modified line is responsible

for ensu ring that the da ta is proper ly maintain ed. This

means that in the case of an external access to that line

from another external bus maste r, the modified line is

first written back to the external memory before the other

external bus master can complete its access. Table 6

shows the MESI cache line states and the correspond-

ing availability of data.

3.6 Cache Replacement Description

The cache line replacement algorithm uses the standard

Am486 CPU pseudo LRU (Least-Recently Used) strat-

egy. When a line must be placed in the internal cache,

the micr opro ces sor fi rst c he cks to see if ther e is an in-

valid line available in the set. If no invalid line is available,

the LRU algorithm replaces the least-recently used

cache line in the four-way set with the new cache line.

If the cache line for replacement is modified, the modi-

fied cache line is placed into the copy-back buffer for

copying back to exter nal memory, and the new c ache

line is placed into the cache. This copy-back ensures

that the ex ternal memor y is updat ed with the m odified

data upon replacement.

3.7 Memory Configuration

In compute r sy st ems , m emo ry regi ons r eq uire s pe cif ic

caching and memory write methods. For example, some

memory regions are non-cacheable while others are

cacheable but are write-through. To allow maximum

memory configuration, the microprocessor supports

specific memory region requirements. All bus masters,

such as DMA controllers, must reflect all data transfers

on the microproce ssor local bus so that the micropro-

cessor can resp ond appropr iat ely .

3.7.1 Cacheability

The Enhanced Am486DX microprocessors cache data

based on the state of the CD and NW bits in CR0, in

conju nction wi th the KEN s ignal, at th e time of a bu rst

read access from memory. If the WB/WT signal is Low

during the first BRDY, KE N meets the standard setup

and hold requirements and the four 32-bit doublewords

are still placed in the cache. However, all cacheable

accesses in this mode are considered write-through.

When the WB/WT is High during the first BRDY, the

entire four 32-bit doubleword transfer is considered

write-back.

Note: The CD bit in CR0 enables (0) or disables (1) the

internal cache. The NW bit in CR0 enables (0) or dis-

ables (1) write-through and snooping cycles. RESET

sets CD and NW to 1. Unlike RESET, however, SRESET

does not invalidate the cache nor does it modify the

values of CD and NW in CR0.

3.7.2 Write-Through/Write-Back

If the CPU is operating in Write-back mode (i.e., the

WB⁄WT pin was sampled High at RESET), the WB⁄WT

pin indicates whether an individual write access is exe-

cuted as write-through or write-back. The Enhanced

Am486DX microprocessors do this on an access-by-

access basis. Once the cache line is in the cache, the

STATUS bit is tested each time the processor writes to

the cac he line or a tag c ompare results i n a hit during

Bus-watching mode. If the WB⁄WT signal is Low during

the first BRDY of the cache li ne read acce ss, the cache

line is considered a write-through access. Therefore, all

writes to this loc at ion i n the c ache ar e r eflected on th e

external bus, even if the cache line is write protected.

3.8 Cache Functionality in Write-Back

Mode

The description of cache functionality in Write-back

mode is divided into two sections: processor-initiated

cache functions and snooping actions.

3.8.1 Processor-Initiated Cache Functions and

State Transitions

The Enhanced Am486DX microprocessors contain two

new buffers for use with the MESI protocol support: the

copy-back buffer and the write-back buffer. The proces-

sor uses the copy-back buffer for cache line replacement

of modified lines. The write-back buffer is used when an

external bus master hits a modified line in the cache

during a snoop operation and the cache line is desig-

nated for write-back to main memory. Each buffer is four

doublew ords in size. Fig ure 1 shows a diagra m of the

state tr ans it ion s i ndu ce d by the loc al pr oc essor . W he n

a read miss occurs, the line selected for replacement

remains in the modified state until overwritten. A copy

of the modified line is sent to the copy-back buffer to be

written back after repl acement. Whe n reload has s uc-

cessfully completed, the line is set either to the exclusive

or the shared state, depending on the state of PWT and

WB/WT signals.

Table 6. MESI Cache Line Status

Situation Modified Exclusive Shared Invalid

Line valid? Yes Yes Yes No

External

memory

is...

out-of-

date valid valid status

unknown

A write to

this cache

line...

does not

go to the

bus

does not go

to the bus

goes to

the bus

and

updates

goes

directly to

the bus

20 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

If the PWT si gnal is 0, the e xternal WB/WT s ignal de-

termines the new state of the line. If the WB/WT signal

was asserted to 1 during reload, the line transits to the

exclusive state. If the WB/WT signal was 0, the line

transits to the shared state. If the PWT signal is 1, it

overrides the WB/WT signal, forcing the line into the

shared s tate. Therefor e, if pagi ng is enable d, the soft-

ware program med PW T bit can overr ide the ha rdware

signal WB/WT.

Until the line is reallocated, a write is the only processor

action that c an c hang e the state of the line. If the write

occurs to a line in the exclusive state, the data is simply

written in to the cache and the line state is c hanged to

modified. The modified state indicates that the contents

of the line require copy-back to the main memory before

the line is reallocated.

If the write occurs to a line in the shared state, the cache

performs a write of the data on the external bus to update

the external memory. The line remains in the shared

state until it is replaced with a new cache line or until it

is flushed. In the modified state, the processor continues

to write the line without any further e xternal acti ons or

state transitions.

If the PWT or PCD bits are changed for a specified mem-

ory location, the tag bits in the cache are assum ed to

be correct. To avoid memory inconsistencies with re-

spect to cacheability and write status, a cache copy-

back and invalidation should be invoked either by using

the WBINVD instruction or asserting the FLUSH signal.

3.8.2 Snooping Actions and State Transitions

To maintain cache coherency, the CPU must allow

snooping by the current bus master. The bus master

initiates a snoop cycl e to che ck whether an addr ess is

cached in the inte rnal cache of the microprocessor. A

snoop cycl e dif fer s from any other cy c le in t hat i t is ini-

tiated e xternally to the microproces sor, and the s ignal

for beginning the cycle is EADS instead of ADS. The

address bus of the microprocessor is bidirectional to

allow the address of the snoop to be driven by the sys-

tem. A snoop acc es s ca n begin duri ng any ho ld sta te:

■While HOLD and HLDA are asserted

■While BOFF is asserted

■While AHOLD is asserted

In the clock in which EADS is asserted, the micropro-

cessor sample s the INV input to qu alify th e type o f in-

quiry . INV speci fie s wh ethe r th e line ( if fo und) mu st be

inval idated (i .e., the M ESI st atus chang es to In vali d or

I). A line is invalidated if the snoop access was generated

due to a write of an other bus maste r. This is indicate d

by INV set to 1. In the case of a read, the line does not

have to be invalidated, which is indicated by INV set to 0.

The core system logic can generate EADS by watc hing

the ADS from the current bus master, and INV by watch-

ing the W/R signal. The micr opro cess or comp ares the

address of the snoop request with addresses of lines in

the cache and of any line in the copy-back buffer waiting

to be transferred on the bus. It does not, however, com-

pare with the address of write-miss data in the write

buffer s. Two cloc k cycles afte r sampling EADS, the mi-

croprocessor drives the results of the snoop on the HITM

pin . If HITM is active, the line was found in the modified

state; if inactive, the line was in the exclusive or shared

state, or was not found.

Figure 2 shows a diagram of the state transitions in-

duced by sno opi ng ac ce ss es .

Invalid

Shared

Modified

Exclusive

Read_Hit

Read_Miss

(WB/WT = 1) •

(PWT = 0)

Read_Miss

[(WB/WT = 0) + (PWT = 1

)

Write_Hit

Write_Hit + Read_Hit

Shared

Read_Hit

+ Write_Hit

Figure 1. Processor-Induced Line Transitions in

Write-Back Mode

Note: Write_Hit

generates external

bus cycle.

Figure 2. Snooping State Transitions

Invalid

Modified

Exclusive Shared

(HITM asserted

+ write-back)

(EADS = 0 * INV = 1)

+ FLUSH = 0 (EADS = 0 * INV = 1)

+ FLUSH = 0

EADS = 0 * INV = 0

* FLUSH = 1

EADS = 0 * INV = 0

* FLUSH = 1

(HITM asserted

+ write-back) EADS = 0 * INV = 0

* FLUSH = 1

EADS = 0 * INV = 1

+ FLUSH = 0

Enhanced Am486DX Microprocessor Family 21

P R E L I M I N A R Y

3.8.2.1 Difference Between Snooping

Access Cases

Snooping accesses are external accesses to the micro-

processor. As described earlier, the snooping logic has

a set of signals independent from the processor-related

signals. Those signals are:

■EADS

■INV

■HITM

In addition to these signals, the address bus is required

as an in put. This is achi eved by setting AHOLD, HOLD,

or BOFF active.

Snooping can occur in parallel with a processor-initiated

access that has already been started. The two accesses

depend on each other only when a modified line is writ-

ten back. In this case, the snoop requires the use of the

cycle control signals and the data bus. The following

sections describe the scenarios for the HOLD, AHOLD,

and BOFF implementations.

3.8.2.2 HOLD Bus Arbitration Implementation

The HOLD/HLDA bus arbitration scheme is used prima-

rily in systems where all memory transfers are seen by

the microprocessor. The HOLD/HLDA bus arbitration

scheme permits s imple wr ite-bac k cache design w hile

maintaining a relatively high performing system. Figure

3 shows a typical system block diagram for HOLD/HLDA

bus arbitration.

Note: To maintain proper system timing, the HOLD

signal must remain active for one clock cycle after HITM

transitions active. Deassertion of HOLD in the same

clock cycle as HITM assertion may lead to unpredictable

processor behavior.

3.8.2.2.1 Processor-Induced Bus Cycles

In the following scenarios, read accesses are assumed

to be cache line fills. The cases also assume that the

core system logic does not return BRDY or RDY un til

HITM is sampled. The addition of wait states follows the

standar d 486 bu s protoco l. For de monstrat ion pur pos-

es, only the zero wait state approach is shown. Table 7

explains t he key t o switching waveforms.

3.8.2.2.2 External Read

Scenario

: The data r esides in exter nal memory (se e

Figure 4).

Step 1 The pr ocesso r sta rts the ex terna l read acce ss

by asserting ADS = 0 and W/R = 0.

Step 2 WB/WT is sampled in the same cycle as BRDY.

If WB/WT = 1, the data resides in a write-back

cacheable memory location.

Step 3 The processor completes its burst read and as-

serts BLAST.

3.8.2.2.3 External Write

Scenario:

The data is written to the external memory

(see Figure 5).

Step 1 The processor starts the external write access

by asserting ADS = 0 and W/R = 1.

Step 2 The processor complet es its write to the core

system logic.

3.8.2.2.4 HOLD/HLDA External Access TIming

In systems with two or more bus masters, each bus

master is equipped with individual HOLD and HLDA con-

trol signals. These signals are then centralized to the

core s ystem logi c that co ntrol s indivi dual bus master s,

depending on bus request signals and the HITM signal.

CPU

L2 Cache

DRAM

Local Bus

Peripheral

I/O Bus

Interface

Slow

Peripheral

Address Bus

Data Bus

Address Bus

Data Bus

Figure 3. Typical System Block Diagram

for HOLD/HLDA Bus Arbitration

Table 7. Key to Switching Waveforms

Waveform Inputs Outputs

Must be steady Will be steady

May change from

H to L Will change

from H to L

May change from

L to H Will change

from L to H

Don’t care; any

change permitted Changing;

state unknown

Does not apply Center lin e is

High-impedance

“Off” state

22 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

BOFF

WB/WT

KEN

Data nn+8

n+4

BLAST

BRDY

ADS 1

ADR

M/IO

W/R

CLK

nn+8n+4

n+12

Note:

The circled numbers in this figure represent the steps in section 4.8.2.2.2.

Figure 4. External Read

BOFF

WB/WT

Data n

ADS

BLAST

BRDY

M/IO

W/R

ADR

CLK

Note:

The circled numbers in this figure represent the steps in section 4.8.2.2.3.

Figure 5. External Write

Enhanced Am486DX Microprocessor Family 23

P R E L I M I N A R Y

3.8.3 External Bus Master Snooping Actions

The followi ng s cenar i os des c ribe t he s no opi ng a cti ons

of an external bus master.

3.8.3.1 Snoop Miss

Scenario

: A snoop of the on-chip cache does not hit a

line, as shown in Figure 6.

Step 1 The microprocessor is placed in Snooping

mode with HOLD. HLDA must be High for a

minimum of one clock cycle before EADS as-

sertion. In the fastest case, this means that

HOLD was asserted one clock cycle before the

HLDA response.

Step 2 EADS and INV are applied to the microproces-

sor. If INV is 0, a read access caused the snoop-

ing cycle. If INV is 1, a write access caused the

snooping cycle.

Step 3 Two clock c ycles after EADS is asserted, HITM

becomes valid . Beca use the addre ssed line i s

not in the snooping ca ch e, HITM is 1.

3.8.3.2 Snoop Hit to a Non-Modified Line

Scenario

: The sn oop of the on-chip cache hits a line,

and the line is not modified (see Figure 7).

Step 1 The microprocessor is placed in Snooping

mode with HOLD. HLDA must be High for a

minimum of one clock cycle before EADS as-

sert ion.

In the fastest case, this means that HOLD was

asserted one clock cycl e before the HLDA re-

sponse.

Step 2 EADS and INV are applied to the microproces-

sor. If INV is 0, a read access caused the snoop-

ing cycle. If INV is 1, a write access caused the

snoopi ng cy cl e.

Step 3 Two clock cycles aft er EADS is asserted, HITM

becomes valid. In this case, HITM is 1.

3.8.4 Wri te-Ba ck Case

Scenario

: Write-back accesses are always burst writes

with a lengt h of four 32-bi t words. Fo r burst write s, the

burst always sta rts w ith the microp rocessor l ine offse t

at 0. HOLD mus t be deasserted be fore the write-back

can be performed (see Figure 8).

Step 1 HOL D places the m icro proces sor in Sn oopin g

mode. HLDA must be High for a minimum of

one clock cycle bef ore EADS assertio n. In the

fastest case, this means that HOLD asserts one

clock cycle before the HLDA response.

Step 2 EADS and INV are asserted. If INV is 0, snoop-

ing is caused by a read access. If INV is 1,

snooping is caused by a write access. EADS is

not sampl ed again until af ter the modifi ed line

is writ ten back to m emo ry. It i s de tect ed ag ai n

as early as in Step 11.

Step 3 Two clock cycles aft er EADS is asserted, HITM

becomes valid, and is 0 because the line is mod-

ified.

HLDA

EADS

HOLD

HITM

ADR

INV

CLK

valid

Figure 6. Snoop of On-Chip Cache That Does Not Hit a Line

Note:

The circled numbers in this figure represent the steps in section 4.8.3.1.

➀

➁➂

24 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

HLDA

HOLD

HITM

EADS

INV

ADR

CLK

Note:

The circled numbers in this figure represent the steps in section 4.8.3.2.

Figure 7. Snoop of On-Chip Cache That Hits a Non-Modified Line

valid

➀

➁➂

EADS

External

bus master’s

BOFF signal

HLDA

Data

HOLD

HITM

ADS

INV

BRDY

BLAST

W/R

M/IO

ADR

CLK

valid

nn+4 n+8 n+12

n+1

valid

Note:

The circled numbers in this figure represent the steps in section 4.8.4.

floating/three-stated

CACHE floating/three-stated

n+8n+4

Figure 8. Snoop That Hits a Modified Line (Write-Back)

Enhanced Am486DX Microprocessor Family 25

P R E L I M I N A R Y

Step 4 In the next clock, the core system logic deas-

serts the HOLD signal in response to the

HITM = 0 si gnal. The c ore syste m logic bac ks

off the current bus master at the same time so

that the microprocessor can access the bus.

HOLD can be reasserted immediately after

ADS is asserted for burst cycles.

Step 5 The snooping cache starts its write-back of the

modified line by asserting ADS = 0, CACHE =0,

and W/R = 1. The write access is a burst write.

The number of clock cycles between deassert-

ing HOLD to the snooping cache and first

asserting ADS for the write-back cycles can

vary. In this example, it is one clock cycle, which

is the shortest possible time. Regardless of the

number of clock cycles, the start of the write-

back is seen by ADS going Low.

Step 6 The write-back access is finished when BLAST

and BRDY both are 0.

Step 7 In the clock cycle after the final write-back ac-

cess, the processor drives HITM back to 1.

Step 8 HOLD is sampled by the microprocessor.

Step 9 One cycle after sampli ng HOLD High, the mi-

croprocessor transitions HLDA transitions to 1,

acknowledging the HOLD request.

Step 10The core system logic removes hold-off control

to the external bus master. This allows the ex-

ternal bus master to immediately retry the abort-

ed access. ADS is strobed Low, which

generates EADS Low in the same clock cycle.

Step 11 The bus master restarts the aborted access.

EADS and INV are applied to the microproces-

sor as before. This starts another snoop cycle.

The status of the addressed line is n ow either share d

(INV = 0) or is changed to invalid (INV = 1).

3.8.5 Write -Back and Pendi ng Access

Scenario

: The following occurs when, in addition to the

write-back operation, other bus accesses initiated by

the pr ocessor a ssociated w ith the snoo ped cache are

pend ing. The microp rocessor gives the write-back ac-

cess priority. This implies that if HOLD is deasserted,

the microprocessor first writes back the modified line

(see Figure 9).

Figure 9. Write-Back and Pending Access

Note:

The circled numbers in this figure represent the steps in section 4.8.5.

EADS

External

bus master’s

BOFF signal

HLDA

Data

HOLD

HITM

ADS

INV

BRDY

BLAST

W/R

M/IO

ADR

CLK

valid

n n+4 n+8 n+12

n+12

valid

floating/three-stated

CACHE

n+8

n+4

26 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

Step 1 HO LD pla ces the micropr ocess or in S noopi ng

mode. HLDA must be High for a minimum of

one clock cycle before EADS assertion. In the

fastest case, this means that HOLD asserts one

clock cycle before the HLDA response.

Step 2 EADS and INV are asserted. If INV is 0, snoop-

ing is caused by a read access. If INV is 1,

snoo ping is caused by a wri te access . EADS is

not sample d again until after the m odified line

is written back to mem ory. It is detec ted agai n

as early as in Step 11.

Step 3 Two clock c ycles after EADS is asserted, HITM

becomes valid, and is 0 because the line is mod-

ified.

Step 4 In the next clock the core system logic deasserts

the HOLD signal in respons e to the HITM = 0.

The core system logic backs off the current bus

master at the same time so that th e micropro-

cessor can access the bus. HOLD can be re-

asserted immediately after ADS is asserte d for

burst cycles.

Step 5 The snooping cache starts its write-back of the

modified line by asserting ADS = 0, CACHE =0,

and W/R = 1. The write access is a burst write.

The number of clock cycles between deassert-

ing HOLD to the snooping cache a nd first as-

serting ADS for the write-ba ck cycles can var y.

In this example, it is one clock cycle, which is

the shortest possible time. Regardless of the

number of clock cycles, the start of the write-

back is seen by ADS going Low.

Step 6 The write-back access is finished when BLAST

and BRDY both are 0.

Step 7 In the clock cycle after the final write-back ac-

cess, the processor drives HITM back to 1.

Step 8 HOLD is sampled by the microprocessor.

Step 9 A minimum of 1 clock cycle after the completion

of the pending access, HLDA transitions to 1,

acknowledging the HOLD request.

Step 10The core system logic removes hold-off control

to the external bus master. This allows the ex-

ternal bus master to immediately retry the abort-

ed access. ADS is strobed Low, which

generates EADS Low in the same clock cycle.

Step 11 The bus master restarts the aborted access.

EADS and INV are applied to the microproces-

sor as before. This starts another snoop cycle.

The status of the addressed line is n ow either share d

(INV = 0) or is changed to invalid (INV = 1).

3.8.5.1 HOLD/HLDA Write-Back Design

Considerations

When d esigning a write-back cache system that uses

HOLD/HLDA as t he bus arbitration method, the follo w-

ing consid erati ons must be obs erved to en sure proper

operation (see Figure 10).

Step 1 During a snoop to the on-chip cache that hits a

modified cache line, the HOLD signal cannot

be deasserted to the microprocessor until the

next cl ock cycle after HITM transitions active.

Step 2 After the write-back has commenced, the HOLD

signal should be asserted no earlier than the

next cloc k cycle after ADS goes active, and no

later than in the final BRDY of the last write.

Asserting HOLD later than the final BRDY may

allow the microprocessor to permit a pending

access to begin.

HLDA

CLK

ADS

BLAST

BRDY

HOLD Valid Ho ld Assertion

Figure 10. Valid HOLD Assertion During Write-Back

HITM

Enhanced Am486DX Microprocessor Family 27

P R E L I M I N A R Y

Step 3 If RDY is returned instead of BRDY during a

write-back, the HOLD signal can be reasserted

at any ti me startin g one cloc k after AD S goes

active in the first transfer up to the final transfer

when RDY is assert ed. A sse rti ng RDY instead

of BRDY will not break the write-back cycle if

HOLD is asserted. The processor ignores

HOLD until the final write cycle of the write-back.

3.8.5.2 AHOLD Bus Arbitration Implementation

The use of AHO LD as the control m echanism is oft en

found in systems where an external second-level cache

is closely coupled to the microprocessor. This tight cou-

pling allows the microprocessor to operate with the least

amount of stalling from external snooping of the on-chip

cache. Additionally, snooping of the cache can be per-

formed concurrently with an access by the microproces-

sor. This feature further improves the performance of

the total system (see Figure 11).

Note : To maintain proper system timing, the AHOLD

signal must remain active for one clock cycle after HITM

transition s active. Deassertio n of AHOLD in the same

clock cycle as HITM assertion may lead to unpredictable

processor behavior.

The following sections describe the snooping scenarios

for the AHOLD implementation.

3.8.5.3 Normal Write-Back

Scenario

: This scenario assumes that a processor-ini-

tiated access has already started and that the external

logic can finish that access even without the address

being applied after the first clock cycle. Therefore, a

snoop ing acce ss wit h AH OLD ca n be don e in parallel .

In this case, the processor-initiated access is finished

first, then the write-back is executed (see Figure 12).

The sequence is as follows:

Step 1 The processor initiates an external, simple,

non-c ac hea ble rea d ac ce ss , s trobi ng A D S = 0

and W/R = 0. The address is driven from the

CPU.

Step 2 I n the same cycl e, AH OLD i s a sserted to i ndi-

cate the start of snooping. The address bus

floats a nd becomes an input in the next clock

cycle.

Step 3 During the next clock cycles, the BRDY or RDY

signal is not strobed Low. Therefore, the pro-

cessor-initiated access is not finished.

Step 4 Two clock cycles a fter AHOLD is a sserte d, the

EADS signal is activated to start an actual

snoopi ng c ycle, a nd INV is v alid . If IN V is 0, a

read a cce ss ca us ed th e s no o pin g c ycl e . If I NV

is 1, a write access caused the snooping cycle.

Addi tion al EADS are ignored due to the hit of a

modified line. It is detected after HITM goes in-

active.

Step 5 Two clock cycles after EADS is asserted, the

snooping signal HITM becomes valid . The line

is modified; therefore, HITM is 0.

Step 6 In this cycle, the processor-initiated access is

finish ed.

Step 7 Two clock cycles after the end of the processor-

initiated access, the cache immediately starts

writing back the modified line. This is indicated

by ADS = 0 and W/R = 1. Note that AHOLD is

still active and the address bus is still an input.

However, the write-back access can be execut-

ed without any address. This is because the

corresponding address must have been on the

bus when EADS was strobed. Therefore, in the

case of the core s ystem log ic, the addr ess for

the write-back must be latched with EADS to

be available later. This is required only if

AHOLD is not removed if HITM becomes 0.

Otherwise, the address of the write-back is put

onto the address bus by the microprocessor.

Step 8 As an example, AHOLD is now removed. In the

next clock cycle, the current address of the

write-back access is driven onto the address

bus.

Step 9 The write-back access is finished when BL AS T

and BRDY both transition to 0.

Step 10In the clock cycle after the final write-back

access, the snooping cache drives HITM back

to 1 .

The status of the snooped and written-back line is now

either shared (INV = 0) or is changed to invalid (INV = 1).

DRAM

Address Bus

Data Bus

L2 Cache

Address Bus

Data Bus

I/O Bus

Interface

Slow

Peripheral

CPU

Address Bus

Data Bus

Figure 11. Closely Coupled Cache Block Diagram

28 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

3.8.6 Reordering of Write-Backs (AHOLD) with

BOFF

As seen pr eviously, the Bus Interfa ce Unit (BIU) com-

pletes the processor-initiated access first if the snooping

access occurs after t he star t of the processo r-init iated

access. If the HITM signal occurs one clock cycle before

the ADS = 0 of the processor-initiated access, the write-

back receives priority and is executed first.

Howeve r, if the snoop ing acce ss is executed aft er the

start of the processor-initiated access, there is a

methodology to reorder the access order. The BOFF

signal delays outstanding processor-initiated cycles so

that a snoop write-back can occur immediately (see

Figure 13).

Scenario

: If there are outstanding processor-initiated

cycles on the bus, asserting BOFF clears the bus pipe-

line. If a snoop causes HITM to be asserted, the first

cycle issued by the microprocessor after deassertion of

BOFF is the write-back cycle. After the write-back cycle,

it reissues the aborted cycles. This translates into the

following sequence:

Step 1 The processor starts a cacheable burst read

cycle.

Step 2 One clock cycle later, AHOLD is asserted. This

switches the address bus into an input one clock

cycle after AHOLD is asserted.

Step 3 Two clock cycles a fter AHOLD is a sserte d, the

EADS and INV signals are asserted to start the

snoopi ng cy cl e.

Step 4 Two clock cycles aft er EADS is asserted, HITM

become s valid . The line is m odified, ther efore

HITM = 0.

Step 5 Note tha t the process or-initiat ed access is no t

completed because BLAST = 1.

Step 6 With HITM going Low, the core system logic

asserts BOFF in the next clock cycle to the

snooping processor to reorder the access.

BOFF overrides BRDY. Therefore, the partial

read is not used. It is reread later.

Step 7 One clock cycle later BOFF is deasserted. The

write-back access starts one clock cycle later

because the BOFF has cleared the bus pipe-

line.

Step 8 AHOLD is deasserted. In th e next clock cycle

the addr ess for the wr ite-bac k is dr iven on th e

address bus.

Data

HITM

EADS

INV

Read

BRDY

AHOLD

BLAST

ADS

W/R

M/IO

ADR

CLK

W n+4W n W n+8 W n+C

Figure 12. Snoop Hit Cycle with Write-Back

Note:

The circled numbers in this figure represent the steps in section 4.8.5.3.

CACHE

from CPU

to CPU

from CPU

Enhanced Am486DX Microprocessor Family 29

P R E L I M I N A R Y

Step 9 One cycle after BOFF is deasserted, the cache

immediately starts writing back the modified

line. This is indicated by ADS = 0 and W/R = 1.

Step 10The write-back access is finished when BLAST

and BRDY go active 0.

Step 11The BIU restarts the aborted cache line fill with

the previous read. This is indicated by ADS = 0

and W/R = 0.

Step 12In the same clock cycle, the snooping cache

drives HITM back to 1.

Step 13The previous read is now reread.

3.8.7 Special Scenarios for AHOLD Snooping

In addition to the previously described scenarios, there

are special scenarios regarding the time of th e EADS

and AHOLD assertion. The final result depends on the

time EADS and AHOLD are asserted relative to other

processor-initiated operations.

3.8.7.1 Write Cycle Reordering Due to Buffering

Scenario

: The MESI cache protocol and the ability to

perform and respond to snoop cycles guarantee that

writes to th e cach e are logic ally equ ival ent to writes to

memory. In particular, the order of read and write oper-

ations on ca ch ed data is the same as if the oper ati ons

were on data in memory. Even non-cached memory

read and write requests usually occur on the external

bus in the same order that they were issued in the pro-

gram. For example, when a write m iss is followed by a

read miss, the write data goes on the bus before the

read request is put on the bus. However, the posting of

writes in write buffers coupled with snooping cycles may

cause the order of writes seen on the external bus to

differ from the order t hey ap pear in the progra m. Con-

sider the following example, which is illustrated in Figure

14. For simplicity, snooping signals that behave in their

usual man ner are not shown.

Step 1 AHOLD is asserted. No further processor-initi-

ated accesses to the external bus can be start-

ed. No other access is in progress.

Step 2 The processo r writes data A to the cach e, re-

sulting in a write miss. Therefore, the data is put

into the write buffers, assuming they are not full.

No external access can be started because

AHOLD is still 1.

Step 3 The next write of the processor hits the cache

and the line is non-shared. Therefore, data B is

written into the cache. The cache line transits

to the modified state.

BOFF

Data

HITM

EADS

INV

AHOLD

BRDY

BLAST

ADS

W/R

M/IO

ADR

CLK

W1 to CPU don’t care

W1 W2 W3 W4

W1 from CPU W3 W4

Figure 13. Cycle Reordering with BOFF (Write-Back)

Note:

The circled numbers in this figure represent the steps in section 4.8.6.

R2 from CPU

➄

➃

➅➇

➉

CACHE

➀

R1 from CPU

➈

➆

➂

➁

30 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

Step 4 In the same clock cycle, a snoop request to the

same ad dress whe re data B resi des is sta rted

because EADS = 0. The snoop hits a modified

line. EADS is ignored due to the hit of a modified

line, but is detected again as early as in step 10.

Step 5 Two clock cycles af ter EADS asserts, HITM be-

comes valid.

Step 6 Because the processor-initiated access cannot

be finished (AHOLD is still 1), the BIU gives

priority to a write-back access that does not re-

quire the use of the address bus. Therefore, in

the clock cycle, the cache starts the write-back

sequence indicated by ADS = 0 and W/R = 0.

Step 7 During the write-back sequence, AHOLD is

deasserted.

Step 8 The write-back access is finished when BLAST

and BRDY transition to 0.

Step 9 After the last write-back access, the BIU starts

writing data A from the write buffers. This is

indicated by ADS = 0 and W/R = 0.

Step 10In the same clock cycle, the snooping cache

drives HITM back to 1.

Step 11The write of d ata A is finishe d if BRDY trans i-

tions to 0 (BLAST = 0), because it is a single

word.

The software write sequence was first data A and then

data B. But on the external bus the data appear first as

data B and then data A. The order of writes is changed.

In most cases, it is unnecessary to strictly maintain the

ordering of writes. However, some cases (for example,

writing to hardware control registers) require writes to

be observed externally in the same order as pro-

grammed. There are two options to ensure serialization

of writes, both of which drive the cache to Write-through

mode:

1. Set the PWT bit in the page table entries.

2. Drive the WB/WT signal Low when accessing these

memory locations.

Option 1 is an operating-system-level solution not di-

rectly implemented by user-level code. Option 2, the

hardware solution, is implemented at the system level.

3.8.7.2 BOFF Write-Back Arbitration

Implementation

The use of BOFF to perform snooping of the on-chip

cache is used in systems where more than one cache-

able bus master resides on the microprocessor bus. The

BOFF signal forces the microprocessor to relinquish the

bus in the follo wing c lock c ycle , regar dles s of t he typ e

of bus cycle it was performing at the time. Consequently,

the use of BOFF as a bus arbitrator should be imple-

mented with care to avoid system problems.

3.8.8 BOFF Design Considerations

The use of BOFF as a bus arbitration control mechanism

is immediate. BOFF forces the microprocessor to abort

an access in the following clock cycle after it is asserted.

The following design issues must be considered.

BLAST

Data

BRDY

EADS

ADS

HITM

Cached Data

AHOLD

CLK

Write Buffer

B original

B modified

BB+4 B+8 B+12

Ignored

XXX

Note:

The circled numbers in this figure represent the steps in section 4.8.7.1.

Figure 14. Write Cycle Reordering Due to Buffering

Enhanced Am486DX Microprocessor Family 31

P R E L I M I N A R Y

3.8.8.1 Cache Line Fills

The microprocessor aborts a cache line fill during a burst

read if BOFF is asserted during the access. Upon re-

gaining th e bus, th e read access comm ences wher e it

left off when BOFF was recognized. External buffers

should take this cycle continuation into consideration if

BOFF is allowed to abort burst read cycles.

3.8.8.2 Cache Line Copy-Backs

Similar to the burst read, the burst write also can be

aborted at any time with the BOFF signal. Upon regain-

ing access to the bus, the write continues from where it

was aborte d. External buffe rs and co ntrol logic sh ould

take into consideration the necessary control, if any, for

burst write continuations.

3.8.8.3 Locked Accesses

Locked bu s cycles occu r in var ious forms. L ocked ac-

cesses occur during read-modify-write operations, in-

terrupt acknowledges, and page table updates.

Although as serting BOFF duri ng a locked cycle is per-

mitted, extreme care should be taken to ensure data

coherency for semaphore updates and proper data or-

dering.

3.8.9 BOFF During Write-Back

If BOFF is as se rt ed du ri ng a wri te-back, the pr oce ss or

performing the write-bac k goes off the bus in the next

clock cycle. If BOFF is released, the processor restarts

that write-back access from the point at which it was

aborted. The beh avior is ide ntical to the no rmal BOFF

case that includes the abort and restart behavior.

3.8.10 Snooping Characteristics During a Cache

Line Fill

The microprocessor takes responsibility for responding

to snoop cycles for a cache line only during the time that

the line is actually in the cache or in a copy-back buffer.

There are times during the cache line fill cycle and during

the cache replacement cycle when the line is “in transit”

and snooping responsibility must be taken by other sys-

tem components.

The following cases apply if snooping is invoked via

AHOLD, and neither HOLD nor BOFF is asserted.

■System designers should consider the possibility

that a snooping cycle may arrive at the same time

as a c ache line fi ll or r ep lacem ent fo r th e s am e ad-

dress. If a snoo ping cycle arriv es at the same time

as a cache line fill with the same address, the C P U

uses the cache line fill, but does not place it in the

cache.

■If a snooping cycle occurs at the same time as a

cache line fill with a different address, the cache line

fill is placed into the cache unless EADS is recog-

nized before the first BRDY but after ADS is assert-

ed, or EADS is r ec ogn iz ed on t he l ast B RDY of the

cache line fill. In these cases, the line is not placed

into the cache.

3.8.11 Snooping Characteristics During a

Copy-Back

If a copy-back is occurring because of a cache line re-

placement, the address being replaced can be matched

by a snoop until assertion of the last BRDY of the copy-

back. This is when the modified line resides in the copy-

back buffer. An EADS as late as two clocks before the

last BRDY can cause H ITM to be asserted.

Figure 15 illustrates the microprocessor relinquishing

responsibility of recognizing snoops for a line that is

copied back. It shows the latest EADS assertion that

can cause HITM assertion. HITM remains active for only

one clock period in that example. HITM remains ac t ive

through the last BRDY of the corresponding write-back;

in that case, the write-back has already completed. This

is the latest point where snooping can start, because

two clock cycles later, the final BRDY of the write-back

is appli ed.

If a snoop cycle hits the copy-back address after the first

BRDY of the copy-back and ADS has been issued, the

microprocessor asserts HITM. Keep in mind that the

write-back was initiated due to a read miss and not due

to a snoop to a modified line. In the second case, no

snooping is recognized if a modified line is detected.

3.9 Cache Invalidat ion and Flushing in

Write-Back Mode

The Enhanced Am486DX microprocessors support

cache invalidation and flushing, much like the standard

486DX microprocessor Write-through mode. However,

the addition of the write-back cache adds some com-

plexity.

3.9.1 Cache Invalidation through Software

To invalidate the on-chip cache, the Enhanced

Am486DX micropr ocessors use th e same instr uctions

as the Am486 microprocessors. The two invalidation in-

structions, INVD and WBINVD, while similar, are slightly

different for use in the write-back environment.

The WB INVD instr uction first performs a write-back of

the modified data in the cache to external memory. Then

it invalidates the cache, followed by two special bus

cycles. The INVD instruction only invalidates the cache,

regardless of whether modified data exists, and follows

with a special bus cycle. The utmost care should be

taken when executing the INVD instruction to ensure

memory coherency. Oth erwise, modifie d data may be

invalidated prior to writing back to main memory. In

Write-back mode, WBINVD requires a minimum of 4100

internal clocks to search the cache for modified data.

Writing back mo difie d data adds to th is mi nim um ti me .

WBINVD can only be stopped by a RESET.

32 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

Two special bus cycles follow the write-back of modified

data upon execution of the WBINVD instruction: first the

write-back, and then the flush special bus cycle. The

INVD operates identically to the standard 486 micropro-

cessor in that the flush speci al bus cycle i s generated

when the on-chip cache is invalidated. Table 8 specifies

the special bus cycle states for the instructions WBINVD

and INVD.

3.9.2 Cache Invalidation through Hardware

The other mechanism for cache invalidation is the

FLUSH pin. The FLUSH pin operates similarly to the

WBINVD com mand, writing back modifi ed cache lines

to main memory. After the entire cache has copied back

all the modified data, the microprocessor generates two

special bus cycles. These special bus cycles signal to

the external caches that the microprocessor on-chip

cache has completed its copy-back and that the second

level cache may begin its copy-back to memory, if so

required.

Two flush acknowl edge cy cles ar e generated after the

FLUSH pin is asserted and the modified data in the

cache is written back. As with the WBINVD instruction,

in Write-back mode, a flush requires a minimum of 4100

internal clocks to test the cache for modified data. Writ-

ing back modified data adds to this minimum time. The

flush operation can only be stopped by a RESET. Table

9 shows the special flush bus cycle configuration.

3.9.3 Snooping During Cache Flushing

As with snooping during normal operation, snooping is

permitted during a cache flush, whether initiated by the

FLUSH pin or WBINVD instruction. After completion of

the snoop, and write-back, if needed, the microproces-

sor completes the copy-back of modified cache lines.

3.10 Burst Write

The Enhanced Am486DX microprocessors improve

system performance by implementing a burst write fea-

ture for cache line write-backs and copy-backs. Stan-

dard write operations are still supported. Burst writes

are always four 32-bit words and start at the beginning

of a cache line address of 0 for the starting access. The

timing of the BLAST and BRDY signals is identical to

the burst read. Figure 16 shows a burst write a ccess.

(See Figure 1 7 and Figur e 18 for b urst read a nd burs t

write acces s with BOFF asser ted.) In additi on to usin g

BLAST, the CACHE signal indicates burstable cycles.

Table 8. WBINVD/INVD Special Bus Cycles

A32–A2 M/IO D/C W/R BE3 BE2 BE1 BE0 Bus Cycle

0000 0000 h 0 0 1 0 1 1 1 Write-back1

0000 0000 h 0 0 1 1 1 0 1 Flush1, 2

Notes:

1. WBINV D generates first write-bac k, then flus h.

2. INVD generates only flush.

Table 9. FLUSH Special Bus Cycles

A32–A2 M/IO D/C W/R BE3 BE2 BE1 BE0 B us C ycl e

0000 0001h 0 0 1 0 1 1 1

First

Flush

Acknowl-

edge

0000 0001h 0 0 1 1 1 0 1

Second

Flush

Acknowl-

edge

BRDY

BLAST

ADS

HITM

EADS

AHOLD

ADR

CLK

n S

Figure 15. Latest Snooping of Copy-Back

CACHE

Address B

Enhanced Am486DX Microprocessor Family 33

P R E L I M I N A R Y

W/R

BRDY

ADS

BLAST

ADR

M/IO

XX4

Data XX0

XX0

XX4 XX8 XXC

Figure 16. Burst Write

CLK

CACHE

XXCXX8

Data

to CPU

BRDY

BOFF

XX0 XX4 don’t care

ADR XX0

ADS

BLAST

M/IO

W/R

CLK

XX4

XX4 XX8 XXC

Figure 17. Burst Read with BOFF Assertion

CACHE

Data

from CPU

BRDY

BOFF

XX4

ADR

ADS

BLAST

M/IO

W/R

CLK

Figure 18. Burst Write with BOFF Assertion

CACHE

XX0 XX4 XX4 XX8 XXC

XX0 XX8 XXC

XX4

34 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

CACHE is a cycle definition pin used when in Write-back

mode (CACHE floats i n Wr it e-thr oug h mod e) . Fo r pr o-

cessor-initiated cycles, the signal indicates:

■For a read cycle, the internal cacheability of the cycle

■For a write cycle, a burst write-back or copy-back, if

KEN is asserted (for linefills).

CACHE is asserted for cacheable reads, cacheable

code fetches, and write-backs/copy-backs. CACHE is

deasserted for non-cacheable reads, translation looka-

side buf fer (TLB ) replaceme nts, locke d cycles ( except

for write-back cycles generated by an external snoop

operation that interrupts a locked read/modify/write se-

quence), I/O cycles, special cycles, and write-throughs.

CACHE is d r iv en t o it s v a l id lev el in the same cl ock as

the assertion of ADS and remains valid until the next

RDY or BRDY assertion. The CACHE output pin floats

one clock after BOFF is asserted. Additionally, the signal

floats when HLDA is asserted.

The following steps describe the burst write sequence:

1. The access is st arted by as ser tin g: AD S = 0, M/IO

= 1, W/R = 1, CACHE = 0. The address offset always

is 0, so the bu rst write a lways start s on a cach e line

boundary . CACHE transition s High (inactiv e) after

the first BRDY.

2. In the second clock cycle, BLAST is 1 to indicate

that the burst is not finished.

3. The burst write access is finished when BLAST is

0 and BRDY is 0.

When the RDY signal is r eturned ins tead of the BRD Y

signal, the Enhanced Am486DX microprocessors halt

the burst cycle and proceeds with the standard non-

burst cycle.

3.10.1 Locked Accesses

Locked accesses of Enhanced Am486DX microproces-

sors occur for read-modify-write operations and inter-

rupt acknow led ge cycles . The timi ng is ide ntical to the

standard 486DX microprocessor, although the state

transitions differ. Unlike processor-initiated accesses,

state transitions for locked accesses are seen by all

processors in the system. Any locked read or write gen-

erates an external bus cycle, regardless of cache hit or

miss. During locked cycles, the processor does not rec-

ognize a HOLD request, but it does recognize BOFF

and AHOLD requests.

Locked read ope ratio ns always read dat a from the ex-

ternal memory, regardless of whether the data is in the

cache. In the event that the data is in the cache and

unmodified, the cache line is invalidated and an external

read operation is performed. The data from the external

memory i s used ins tead of the dat a in the cache , thus

ensuring that the locked read is seen by all other bus

masters. If a locked read occurs, the data is in the cache,

and it is modified. The microprocessor first copies back

the data to external memory, invalidates the cache line,

and then performs a read operation to the same location,

thus ens uring that th e locked read is see n by all other

bus mas ters. At no time is the data in th e cache used

direc tly by the mi c ropr oc es so r or a lo ck ed r ead op er a-

tion before reading the data from external memory.

Since locked cycles always begin with a locked read

access, and locked read cycles always invalidate a

cache line, a locked write cycle to a valid cache line,

either modified or unmodified, does not occur.

3.10.2 Serialization

Locked accesses are totally serialized:

■All reads and writes in the write buffer that precede

the locked access are issued on the bus before the

first locked ac ces s is executed.

■No read or write after the last locked access is issued

internally or on the bus until the final RDY or BRDY

for all lock ed accesses.

■It is possible to get a locked read, write-back, locked

write cycle.

3.10.3 PLOCK Operation in Write-Through Mode

As described on page 15, PLOCK is only used in Write-

through mode; the signal is driven inactive in Write-back

mode. In Write-through mode, the processor drives

PLOCK Low to indicate that the current bus transaction

requires more than one bus cycle. The CPU continues

to drive the signal Low until the transaction is completed,

whether or not RDY or BRD Y is returned . Refer to the

pin description for additional information.

4 CLOCK CONTR O L

4.1 Clock Generation

The Enhanced Am486DX microprocessors are driven

by a 1x clock that relies on phased-lock loop (PLL) to

generate the two internal clock phases: phase one and

phase t wo. The risi ng e dge of CLK co r resp onds t o th e

start of phase one (ph1). All external timing parameters

are specifie d relati ve to the rising edge of CLK.

4.2 Stop Clock

The Enhanced Am486DX microprocessors also provide

an interrupt mechanism, STPCLK, that allows system

hardware to control the power consumption of the CPU

by st opp ing th e i nte rn al c lock to th e CP U co re i n a se-

quenced manner. The first low-power state is called the

Stop Grant state. If the CLK input is completely stopped,

the CPU enters into the Stop Clock state (the lowest

powe r sta te) . Wh en t he CP U r eco gniz es a STPC LK in-

terrupt, the processor:

■Stops execution on the next instruction boundary

(unless superseded by a higher priority interrupt)

■Waits for completion of cache flush

■Stops the pre-fetch unit

Enhanced Am486DX Microprocessor Family 35

P R E L I M I N A R Y

■Empties all internal pipelines and write buffers

■Generates a Stop Grant bus cycle

■Stops the internal clock

At this point the CPU is in the Stop Grant state.

The CPU cannot respond to a STPCLK request from an

HLDA state because i t cannot empty t he write buffe rs

and, therefore, cannot generate a Stop Grant cycle. The

rising edge of STPCLK signals the CPU to return to

program execution at the instruction following the inter-

rupted instruction. Unlike the normal interrupts (INTR

and NMI), STPCLK does not initiate interrupt acknowl-

edge cycles or interrupt table reads.

4.2.1 External Interrupts in Order of Priority

In Write-through mode, the priority order of external in-

terrupts is:

1. RESET/SRESET

2. FLUSH

3. SMI

4. NMI

5. INTR

6. STPCLK

In Write-back mode, the priority order of external inter-

rupts is:

1. RESET

2. FLUSH

3. SRESET

4. SMI

5. NMI

6. INTR

7. STPCLK

STPCLK is active Low and has an int ernal pull-up re-

sistor. STPCLK is asynchronous, but setup and hold

times must be met to ensure recognition in any specific

clock. STPCLK must rema in activ e unti l the Sto p Grant

special bus cycle is asserted and the system responds

with either RDY or BRDY. When the CPU enters the

Stop Grant state, the internal pull-up resistor is disabled,

reducing the CPU power consumption. The STPCLK

input mus t be dr iv en Hig h (not floated) to exi t the Stop

Grant state. STPCLK must be deasserted for a minimum

of five clocks after RDY or BRDY is returned activ e for

the St op Gr an t bu s cy c le be for e b ein g assert e d a gai n.

There are tw o regio ns for the Lo w-powe r m ode sup ply

current:

Low Power:

Stop Grant state (fast wake-up, frequency-

and voltage-dependent)

Lowest Power:

Stop Clock state (slow w ake-up, volt-

age-dependent)

4.3 Stop Gran t Bus Cycle

The processor drives a special Stop Grant bus cycle to

the bus after recognizing the STPCLK interrupt. This

bus cycle is the same as the HALT cycle used by a

standard Am486 microprocessor, with the exception

that the Stop Grant bus cycle drives the value 0000

0010h on the address pins.

■M/lO = 0

■D/C = 0

■W/R =1

■Address Bus = 0000 0010h (A4 = 1)

■BE3–BE0 = 1011

■Data bus = undefined

The system har dwar e must ackn owledge this cy cle by

returning RDY or BRDY, or th e pr oc esso r wil l not ente r

the Sto p Grant state (see Figure 19). The latency be-

tween a STPCLK request and the Stop Grant bus cycle

depends on the current instruction, the amount of data

in the CPU wr ite buf fers, and th e sys tem memo ry per-

formance.

4.4 Pin State During Stop Grant

Table 10 shows the pin states during Stop Grant Bus

states. During the Stop Grant state, most output and

input/output signals of the microprocessor maintain the

level they held when entering the Stop Grant state. The

data and data parity signals are three-stated. In re-

sponse to HOLD being driven active during the Stop

Grant s tate (when th e CLK input i s running), the CPU

genera tes HLDA an d three-st ates all outp ut and inpu t/

output signals that are three-stated during the HOLD/

HLDA state. After HOLD is deasserted, all signals return

to the same state they were before the HOLD/HLDA

sequence.

Table 10. Pin State During Stop Grant Bus State

Signal Type State

A3–A2 OPrevious State

A31–A4 I/O Previous State

D31–D0 I/O Floated

BE3–BE0 OPrevious State

DP3–DP0 I/O Floated

W/R, D/C, M/IO, CACHE OPrevious State

ADS OInactive

LOCK, PLOCK OInactive

BREQ OPrevious State

HLDA OAs per HOLD

BLAST OPrevious State

FERR OPrevious State

PCHK OPrevious State

SMIACT OPrevious State

HITM OPrevious State

36 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

To achieve the lowest possible power consumption dur-

ing the Stop Grant state, the system designer must en-

sur e tha t the in put sign als wi th pu ll-u p resi sto rs ar e not

driven Low , and the input si gnals with pull-do wn resi s-

tors are not driven High.

All inputs except data bus pins must be driven to the

power supply rails to ensure the lowest possible current

consump tion during Sto p Grant or S top Clock modes .

For compatibility, data pins must be driven Low to

achieve the lowest possible power consumption.

4.5 Clock Control State Di agram

Figure 20 shows the state transitions during a Stop

Clock cycle.

4.5.1 Normal State

This is the normal operating state of the CPU. While in

the normal state, the CLK input can be dynamically

changed within the specified CLK period stability limits.

4.5.2 Stop Grant State

The Stop Grant state provides a low-power state that

can be entered by simply asserting the external STPCLK

interrupt pin. When the Stop Grant bus cycle has been

placed on the bus, and either RDY or BRDY is returned,

the CPU is in this state. The CPU returns to the normal

execution state 10–20 cloc k cycles after ST PCLK has

been deasserted.

While in the Stop Grant state, the pull-up resi stors on

STPCLK and UP are disabled internally. The system

must continue to drive these inputs to the state they

were in imm ediately before the CPU e ntered the Stop

Grant State. For minimum CPU power consumption, all

other in put pin s sh ould b e dri ven to their i nacti ve le vel

while the CPU is in the Stop Grant state.

A RESET or SRESET brings the CPU from the Stop

Grant state to the Normal state. The CPU recognizes

the inputs required for cache invalidations (HOLD,

AHOLD, BOFF, and EADS) as explained later. The CPU

does not recognize any other inputs while in the Stop

Grant state. Input signals to the CPU are not recognized

until 1 clock after STPCLK is deasserted (see Figure 21).

While in the Stop Grant state, the CPU does not recog-

nize transitions on the interrupt signals (SMI, NMI, and

INTR). Driving an active edge on either SMI or NMI does

not guarantee recognition and service of the interrupt

reques t following e xit from the Stop Grant state. How-

ever, if one of the interrupt signals (SMI, NMI, or INTR)

is driven active while the CPU is in the Stop Grant state,

and held active for at least one CLK after STPCLK is

deasserted, the corresponding interrupt will be serviced.

The Enhanced Am486DX microprocessors require

INTR to be held active until the CPU issues an interrupt

acknowledge cycle to guarantee recognition. This con-

dition als o applie s to the exis ti ng Am 486 CPUs.

In the Stop Grant state, the system can stop or change

the CLK in put. When the clock stops, the CPU enters

the Stop Clock state. The CPU returns to the Stop Grant

state immediately when the CLK input is restarted. You

must hold the STPCLK input Lo w un til a s ta bil iz ed fre-

quency has been maintained for at least 1 ms to ensure

that the PLL has had sufficient time to stabilize.

The CPU generates a Stop Grant bus c ycle when en-

tering the state from the Normal or the Auto HALT Power

Down state. When the CPU enters the Stop Grant state

from the Stop Clock state or the Stop Clock Snoop state,

the CPU does not generate a Stop Grant bus cycle.

t20 t21

Figure 19. Entering Stop Grant State

RDY

ADDR

STPCLK

CLK

Stop Grant Bus cycle

Enhanced Am486DX Microprocessor Family 37

P R E L I M I N A R Y

Figure 20. Stop Clock State Machine

(valid for Write-back mode only)

Figure 21. Recognition of Inputs when Exiting Stop Grant State

t20 t21

CLK

STPCLK

NMI

SMI A

STPCLK

Sampled

Note: A = Earliest time at which NMI or SMI is recognized.

38 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

4.5.3 Stop Clock State

Stop Clock state is entered from the Stop Grant state

by stopping the CLK input (either logic High or logic

Low). None of the CPU input signals should change

state w hil e t he CLK input is s topp ed. Any t ra ns iti on on

an input signal (except INTR) before the CPU has re-

turned to the Stop Gran t state may result in unpredi ct-

able behavior. If INTR goes active while the CLK input

is stopped, and stays active until the CPU issues an

interrupt acknowledge bus cycle, it is serviced in the

normal m anner. System design must e nsure the CPU

is in the correct state prior to asserting cache invalidation

or interrupt signals to the CPU.

4.5.4 Auto Halt Power Down State

A HALT instruction causes the CPU to enter the Auto

HALT Power Down state. The CPU issues a normal

HALT bus cycle, and only transitions to the Normal state

when INTR, NMI, SMI, RESET, or SRESET occurs.

The system c an ge ner ate a STP CLK whi le the CP U is

in the Auto HA LT Power Down state. The CP U gener-

ates a Stop Grant bus cycle when it enters the Stop

Grant state from the HALT state. When the system deas-

serts the STPCLK interrupt, the CPU returns execution

to the HALT state. The CPU generates a new HALT bus

cycle when it re-enters the HALT state from the Stop

Grant st ate.

4.5.5 Stop Clock Snoop State

(Cache Invalidations)

When the CPU is in the Stop Grant state or the Auto

HALT Power Down state, the CPU recognizes HOLD,

AHOLD, BOFF, and EADS for cache invalidation. When

the system asserts HOLD, AHOLD, or BOFF, the CPU

floats the bus accordingly. When the system asserts

EADS, the CPU transparently enters Stop Clock Snoop

state and powers up for one full clock to perform the

required cache snoop cycle. If a modified line is

snooped, a cache write- back occ urs with HITM transi-

tioning active until the completion of the write-back. It

then powers down and returns to the previous state. The

CPU does no t generate a bus cycle whe n it returns to

the previou s state.

4.5.6 Cache Flush State

When configured in Write-back mode, the processor

recognizes FLUSH for copying back modified cache

lines to mem ory in the A ut o Hal t P owe r D own S tat e or

Normal St ate. Up on th e co mpl eti on o f the c ache fl us h,

the processor returns to its prior state, and regenerates

a special bus cycle, i f necessary.

5 SRE SET FUNCTION

The Enhanced Am486DX microprocessors support a

soft res et function thr ough the SRES ET pin. SRES ET

forces the processor to begin execution in a known state.

The processor state after SRESET is the same as after

RESET except that the internal caches, CD and NW in

CR0, write buffers, SMBASE registers, and floating-

point registers retain the values they had prior to SRE-

SET, and cache snooping is allowed. The processor

starts execution at physical address FFFFFFF0h. SRE-

SET can be used to help performance for DOS extend-

ers written for the 80286 processor. SRESET provides

a method to switch from Protected to Real mode while

maintaining the internal caches, CR0, and the FPU

state. SRESET may not be used in place of RESET after

power-up.

In Write -bac k mode, on ce SRES ET is sa mpled active ,

the SRESET sequen ce begins on the next instruction

boundary (unless FLUSH or RESET occurs before that

boundary). When started, the SRESET sequence con-

tinues to completion and then normal processor execu-

tion resumes, independent of the deassertion of

SRESET. If a snoop hits a modified line during SRESET,

a normal write-back cycle occurs. ADS is asserted to

drive the bus cycles even if SRESET is not deasserted.

6 SYSTEM MANAGEMENT MODE

6.1 Overview

The Enhanced Am486DX microprocessors support four

modes: Re al, Vi rtual, Pr otected, an d Sys tem Manag e-

ment mode (SMM). As an operating mode, SMM has a

distinct processor environment, interface, and hard-

ware/software features. SMM lets the system designer

add new software-controlled features to the computer

products that always operate transparent to the operat-

ing system (OS) and software applications. SMM is in-

tended for use only by system firmware, not by

applications software or general-purpose systems soft-

ware.

The SMM architectural extension consists of the follow-

ing elemen ts :

■System Management Interrupt (SMI) hardware in-

terface

■Dedicated and secure memory space (SMRAM) for

SMI handler code and CPU state (context) data with

a statu s signal for the syste m to dec ode access t o

that memory space, SMIACT

■Resume (RSM) instruction, for exiting SMM

■Special features, such as I/O Restart and I/O instruc-

tion information, for transparent power management

of I/O peripherals, and Auto HALT Restart

6.2 Terminology

The following terms are used throughout the discussion

of System Management mode.

■SMM: System Management mode. The operating

environment that the processor (system) enters

when servicing a System Management Interrupt.

Enhanced Am486DX Microprocessor Family 39

P R E L I M I N A R Y

■SMI: System Management Interrupt. This is the trig-

ger mechanism for the SMM interface. When SMI is

asse rted (SMI pin asserted Low ) it causes the pr o-

cessor to invoke SMM. The SMI pin is the only

means of entering SMM.

■SMI handler : System Managem ent mode handler.

This is the code that is executed when the processor

is in SMM. Example applications that this code might

implement are a power management control or a

system control function.

■RSM: Resume instruction. This instruction is used

by the SMI handler to exit the SMM and return to the

interrupted OS or application process.

■SMRAM: This is the ph ysic al mem ory dedic ated to

SMM. The SMI handler code and related data reside

in this memory. The processor also uses this mem-

ory to store its context before executing the SMI han-

dler. The operating system and applications should

not have access to this memory space.

■SMBASE: This is a control register that contains the

base address that defines the SMRAM space.

■Context: This term refers to the processor state. The

SMM discussion refers to the context, or processor

state, just before the processor invokes SMM. The

context n orma lly con sists of the C PU re gisters that

fully represent the processor state.

■Context Switch: A context sw itch is the process of

either saving or restoring the context. The SMM dis-

cussio n re fers to th e con text switc h as the process

of saving/restoring the context while invoking/exiting

SMM, respectively.

■SMSAVE: A mechanism that saves and restores all

internal registers to and from SMRAM.

6.3 System Manag ement Interrupt

Processing

The system interrupts the normal program execution

and invokes SMM by generating a System Management

Interrupt (SMI) to the CPU. The CPU services the SMI

by executing the following sequence (see Figure 22).

1. The CPU asserts the SMIACT signal, instructing the

system to enable the SMRAM.

2. The CPU saves its state (internal register) to SM-

RAM. It start s at th e SMBAS E r elative addre ss lo-

cation (see Section 7.3.3), and proceeds downward

in a stack-like fashion.

3. The CPU switc he s to the SM M proc es so r en viro n-

ment (an external pseudo-real mode).

4. The CPU then jumps to the absolute address of

SMBASE + 8000h in SMRAM to execute th e SMI

handler. This SMI handler performs the system

managem ent ac tiv ities .

Note: If the SMRAM shares the same physical address

location with part of the system RAM, it is “overlaid”

SMRAM. To preserve cache consistency and correct

SMM operation in systems using overlaid SMRAM, the

cache must be flushed via the FLUSH pin when entering

SMM.

5. The SMI handler then executes the RSM instruction

which restores the CPU’s context from SMRAM,

deasserts the SMIACT signal, and then returns con-

trol to the previously interrupted program execution.

For uses such as fast enabling of external I/O devices,

the SMSAVE mode permits the restarting of the I/O in-

structions and the HALT instruction. This is accom-

plished through I/O Trap Restart and Halt/Auto HALT

Restar t slot s. Onl y I/O and HA LT opc odes ar e r estart-

able. A ttempts to resta rt any other opcode may result

in unpredictable behavior.

The System Management Interrupt hardware interface

consists of the SMI request input and the SMIACT output

used by the system to decode the SMRAM (see Figure

23).

SMI

#1 #2 #3

Instr Instr Instr

State Save SMI Handler State Restore #4 #5

Instr Instr

SMI

SMIACT

Figure 22. Basic SMI Interrupt Service

RSM

40 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

6.3.1 System Management Interrupt Processing

SMI is a falling-edge-triggered, non-maskable interrupt

request signal. SMI is an asynchronous signal, but setup

and hold times must be met to guarantee recognition in

a specific clock. The SMI input does not have to remain

active until the interrupt is actually serviced. The SMI

input needs to remain active for only a single clock if the

required setup and hold times are met. SMI also wo rks

correctly if it is held active for an arbitrary number of

clocks (see Figure 24).

The SMI input must be held inactive for at least four

clocks after it is asserted to reset the edge-triggered

logic. A s ubsequent SM I may not be re cognized if the

SMI input is not held inactive for at least four clocks after

being asserted. SMI, like NMI, is not affected by the IF

bit in the EFLA GS r eg is ter a nd i s recognize d on an in-

struction boundary. SMI does not break locked bus cy-

cles. SMI has a higher priority than NMI and is not

masked during an NMI. After SMI is recognized, the SMI

signal is masked int ernally unti l the RSM instr uction is

executed and the interrupt service routine is complete.

Masking SMI prevents recursive calls. If another SMI

occurs while SMI is masked, the pending SMI is recog-

nized and executed on the next instruction boundary

after the current SMI completes. This instruction bound-

ary occurs before execution of the next instruction in the

interrupted application code, resulting in back-to-back

SMI handlers. Only one SMI signal can be pending while

SMI is masked. The SMI signal is synchronized inter-

nally and must be asserted at least three clock cycles

prio r to as sert ing the RD Y signal to guarantee recogni-

tion on a specific instruction boundary. This is important

for servicing an I/O trap with an SMI handler.

6.3.2 SMI Active (SMIACT)

SMIACT indicates that the CPU is operating in SMM.

The CPU asserts SMIACT in response to an SMI inter-

rupt request on the SMI pin. SMIACT is driven active

after the CPU has completed all pending write cycles

(including emptying the write buffers), and before the

first access to SMRAM when the CPU saves (writes) its

state ( or context) to S MRAM. SMIA CT remains active

until the last access to SMRAM when the CPU restores

(reads) its state from SMRAM. The SMIACT signal does

not float in response to HOLD. The SMIACT signal is

used by the system logic to decode SMRAM. The num-

ber of clocks required to complete the SMM state save

and restore is dependent on system memory perfor-

mance. The values shown in Figure 25 assume 0 wait-

state memory writes (2 clock cycles), 2–1–1–1 burst

read cycles, and 0 wait-state non-burst reads (two clock

cycles). Additionally, it is assumed that the data read

during the SMM state restore sequence is not cache-

able. The minimu m time required to enter a SMSAVE

SMI handler r outine for the CP U (from the c ompletion

of the interrupted instruction) is given by:

Latency to start of SMl handler = A + B + C = 161 clocks

and the minimum time required to return to the interrupt-

ed applicatio n (following the fi nal SMM instruction be-

fore RSM) is given by:

Latency to co ntinue a pp lic ation = E + F + G = 258 c lo ck s

CPU

SMIACT

SMI SMI Interface

}

Figure 23. Basic SMI Hardware Interface

tsu thd

SMI Sampled

CLK

CLK2

SMI

RDY

Figure 24. SMI Timing for Servicing an I/O Trap

Enhanced Am486DX Microprocessor Family 41

P R E L I M I N A R Y

6.3.3 SMRAM

The CPU uses the SMRAM space for state save and

state re store operati ons during an SMI. The SMI han-

dler, which also resides in SMRAM, uses the SMRAM

space to store cod e, data, and stacks. In additio n, the

SMI han dle r can u se the S MRA M for s ys tem mana ge-

ment information such as the system configuration, con-

figuration of a powered-down device, and system

designer-specific information.

Note : Access to SMRAM is throug h the CPU interna l

cache. To ensure cache consistency and correct oper-

ation, alwa ys assert the FLUSH pi n in the sa me clock

as SMI for systems using overlaid SMRAM.

The CPU asserts SMIACT to indicate to the memory

controller that it is operating in System Management

mode. The system logic should ensure that only the

CPU and SMI ha ndler hav e access to th is area. A lter-

nate bus mas ter s or DM A dev ic es tr y ing to acc ess t he

SMRAM space when SMIACT is active should be di-

rected to syst em RAM in the respective ar ea. The sys-

tem logic is minimal ly required to decode the p hysical

memory address range 38000h–3FFFFh as SMRAM

area. The CPU saves its state to the state save area

from 3FFFFh downward to 3FE00h. After saving its

state, the CPU jumps to the address location 38000h to

begin executing the SMI handler. The system logic can

choose to decode a larger area of SMRAM as needed.

The size of this SMRAM can be between 32 Kbyte and

4 Gbyte.The system logic should provide a manual

method for switching the SMRAM into system memory

space when the CPU is not in SMM. This enabl es ini-

tializ ation of the SMRA M s pace ( i.e ., lo adi ng S MI han-

dler) before executing the SMI handler during SMM (see

Figure 26).

CLK

CLK2

SMI

SMIACT

ADS

RDY

T1 T2

Normal State State

Save SMM

Handler State

Restore Normal

State

Clock-Doubled CPU Clock-Tripled CPU Clock-Quadrupled CPU

A: Last RDY from non-SMM transfer to SMIACT assertion2 CLKs minimum 2 CLKs minimum 2 CLKs minimum

B: SMIACT assertion to first ADS for SMM state save 20 CLKs minimum 15 CLKs minimum 10 CLKs minimum

C: SMM state save (dependent on memory performance) 140 CLKs 100 CLKs 70 CLKs

D: SMI handler User-determined User-determined User-determined

E: SMM state restore (dependent on memory performance)240 CLKs 180 CLKs 120 CLKs

F: Last RDY from SMM transfer to deassertion of SMIACT2 CLKs minimum 2 CLKs minimum 2 CLKs minimum

G: SMIACT deassertion of first non-SMM ADS 20 CLKs minimum 20 CLKs minimum 20 CLKs minimum

Figure 25. SMIACT Timing

SMRAM

System memory

accesses redirected

to SMRAM

System memory

accesses not

redirected to SMRAM

CPU

accesses to

syste m

address

space used for

SMRAM Normal

Memory

Space

Figure 26. Redirecting System Memory

Address to SMRAM

42 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

6.3.4 SMRAM State Save Map

When SMI is recognized on an instruction boundary, the

CPU core first se ts the S MIACT s ignal L ow, indic ating

to the system logic that accesses are now being made

to the system-defined SMRAM areas. The CPU then

writes its state to the state save area in the SMRAM.

The state save area starts at SMBASE + [8000h +

7FFFh]. The default CS Base is 30000h; therefore, the

default state save area is at 3FFFFh. In this case, the

CS Base is also referred to as the SMBASE.

If the SMBASE relocation feature is enabled, the

SMRAM addresses can change. The following formula

is used to determine the relocated addresses where the

context is saved: SMBASE + [8000h + Register Offset],

where the default initial SMBASE is 30000h and the

are for new registers in future CPUs. Some registers in

the SMRAM state save area may be read and changed

by the SM I handler , with the c hanged value s restor ed

to the processor register by the RSM instruction. Some

(Modifying these registers results in unpredictable

behavior.) The values stored in the “reserved” areas

may change in future CPUs. An SMI handler should not

rely on values stored in a reserved area.

The following registers are written out during SMSAVE

mode to the RESERVED memory locations (7FA7h–

7F98h, 7F93h–7F8Ch, and 7F87h–7F08h), but are not

visible to the system software programmer:

■DR3–DR0

■CR2

■CS, DS, ES, FS, GS, and SS hidden descriptor

registers

■EIP_Previous

■GDT Attri but es and Limit s

■IDT Attributes and Limits

■LDT Attributes, Base, and Limits

■TSS Attributes, Base, and Limits

If an SMI request is issued to power down the CPU, the

values of all reserv ed loc ations in th e SMM s tate save

area must be saved to non-volatile memory.

The following registers ar e not automaticall y saved and

restored by SMI and RSM:

■TR7–TR3

■FPU regi sters:

—STn

—FCS

—FSW

— Tag Word

— FP instruction pointer

— FP opcode

— Operand pointer

Note: You can save the FPU state by using an FSAVE

or FNSAVE instruction.

For all SMI reque sts except for p ower down su spend/

resume, these registers do not have to be saved be-

cause their contents will not change. During a power

down suspend/resume, however, a resume reset clears

these registers back to their default values. In this case,

the suspend SMI handler should read these registers

directly to save them and restore them during the power

up resume. Anytime the SMI handler changes these

registers in the CPU, it must also save and restore them.

Table 11. SMRAM State Save Map

Offset* Register Writable?

7FFCh CRO No

7FF8h CR3 No

7FF4h EFLAGS Yes

7FF0h EIP Yes

7FECh EDI Yes

7FE8h ESI Yes

7FE4h EBP Yes

7FE0h ESP Yes

7FDCh EBX Yes

7FD8h EDX Yes

7FD4h ECX Yes

7FD0h EAX Yes

7FCCh DR6 No

7FC8h DR7 No

7FC4h TR* No

7FC0h LDTR* No

7FBCh GS* No

7FB8h FS* No

7FB4h DS* No

7FB0h SS* No

7FACh CS* No

7FA8h ES* No

7FA7h–7F98h Reserved No

7F94h IDT Base No

7F93h–7F8Ch Reserved No

7F88h GDT Base No

7F87h–7F08h Reserved No

7F04h I/O Trap Word No

7F02h Halt Auto Restart Yes

7F00h I/O Trap Restart Yes

7EFCh SMM Revision Identifier Yes

7EF8h State Dump Base Yes

7EF7h–7E00h Reserved No

Note:

*Upper 2 bytes are not modified.

Enhanced Am486DX Microprocessor Family 43

P R E L I M I N A R Y

6.4 Entering System Management Mode

SMM is one of the major operat ing modes, along wi th

Protect ed mo de, Real mod e, an d Vi r tual mode. Figur e

27 shows how the proces s or ca n enter S MM from any

of the three modes and then return.

The external signal SMI causes the pr ocesso r to swi tch

to SMM. The RSM instruction exits SMM. SMM is trans-

parent to applications, programs, and operating sys-

tems for the following reasons:

■The only way to enter SMM is via a type of non-

maskable interrupt triggered by an external signal

■The process or begins ex ecuting SMM code fro m a

separate address s pace, refer red to earlier as sys-

tem management RAM (SMRAM)

■Upon entry into SMM, the processor saves the reg-

ister state of the interrupted program (depending on

the save mode) in a part of SMRAM called the SMM

context save space

■All interrupts normally handled by the operating sys-

tem or applications are disabled upon SMM entry

■A special instruction, RSM, restores processor reg-

isters from the SMM context save space and returns

control to the interrupted program

Similar to Real mode, SMM has no privile ge levels or

address mapping. SMM programs c an execute all I/O

and other system instructions and can address up to

4 Gbyte of memory.

6.5 Exiting System Management Mode

The RSM instruction (opcode 0F AAh) leaves SMM and

returns control to the interrupted program. The RSM

instruction can be executed only in SMM. An attempt to

execute the RSM instruction outside of SMM generates

an invalid opcode exception. When the RSM instruction

is execu ted and the proc essor detec ts invali d state in-

formation during the reloading of the save state, the

processor enters the shutdown state. This occurs in the

followi ng si tuations:

■The value in the State Dump base field is not a

32-Kbyte aligned address

■A combination of bits in CR0 is illegal: (PG=1 and

PE=0) or (NW=1 and CD=0)

In Shu tdown mode, the processor stops executing in-

structions until an NMI interrupt is received or reset ini-

tialization is invoked. The processor generates a

shutdown bus cycle.

Three SMM features can be enabled by writing to control

slots in the SMRAM state save area:

1. Auto HALT Restart. It is possible for the SM I re-

quest to interrupt the HALT state. The SMI handler

can tell the RSM instruction to return control to the

HALT instr uct ion or to retur n co ntr ol t o the in struc -

tion following the HALT instruction by appropriately

setting the Auto HALT Restart slot. The default op-

eration is to restart the HALT instruction.

2. I/O Trap Re start. If the S MI was generated on an

I/O access to a powered-down device, the SMI han-

dler can in str uc t the RSM instructi on to re-exec ut e

that I/O instruction by setting the I/O Trap Rest art

slot.

3. SMBASE Relocation. The system can relocate the

SMRAM by setting the SMBASE Relocation slot in

the state save area. The RSM instruction sets

SMBASE in the processor based on the value in the

SMBASE relocation slot. The SMBASE must be

aligned on 32-Kbyte boundaries.

A RESET also causes execution to exit from SMM.

6.6 Processor Environment

When an SMI signal is recognized on an instruction ex-

ecutio n boundary, the pr ocessor wait s for all stores to

complete, including emptying the write buffers. The final

write cycle is complete when the system returns RDY

or BRDY. The processor then drives SMIACT active,

saves its register state to SMRAM space, and begins to

execute the SMI handler.

SMI has greater priority than debug exceptions and ex-

ternal interrupts. This means that if more than one of

these conditions occur at an instruction boundary, only

the SM I processing occurs. Subsequent SMI requests

are no t acknowledged while the proc essor is in S MM.

The first SMI request that occurs while the processor is

in SMM is latched, and serviced when the processor

exits SMM with the RSM instruction. Only one SMI signal

is latched by the CPU while it is in SMM. When the CPU

invokes SMM, the CPU core registers are initialized as

indicated in Table 12.

Virtual

mode

System

Management

mode

Reset

RSM

SMI

RSM

VM=1

PE=1

Reset

PE=0

VM=0

Figure 27. Transition to and from SMM

Real

mode

Protected

mode

SMI

44 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

Note:

Interrupts from INT and NMI are disabled on SMM entry.

The following is a summary of the key features in the

SMM environment:

■Real mode style address calculation

■4-Gbyte limit checking

■IF flag is cleared

■NMI is disabled

■TF flag in EFLAGS is clear ed; singl e step tr aps ar e

disabled

■DR7 is cleared; debug traps are disabled

■The RSM instruction no longer generates an invalid

opcode error

■Default 16-bit opcode, register, and stack use

■All bus arbitration (HOLD, AHOLD, BOFF) inputs,

and bus sizing (BS8, BS16) inputs operate normally

while the CPU is in SMM

6.7 Executing System Management

Mode Handler

The proce ssor begin s execu tion of the SMI handler at

offset 8000h in the CS segment. The CS Base is initially

30000h, as shown in Table 13.

The CS Base can be changed using the SMM Base

relocation feature

When the SMI handler is invoked,

the CPU’s PE and PG bi ts in CR0 are reset to 0. The

processor is in an environment similar to Real mode,

but without the 64-Kbyte limit checking. However, the

default op erand size and the default address size are

set to 16 bits. The EM bit is cleared so that no exceptions

are generated. (If the SMM was entered from Protected

mode, the Real mode interrupt and exception support

is no t ava il abl e.) The SM I handler should not use float-

ing-poi nt unit instr uctions un til the FPU is proper ly de-

tected (within the SMI handler) and the exception

suppo rt is initi al iz ed.

Notes:

1. The segment limit check is 4 Gbytes instead of the usual

64 Kbyte.

2. The Selector value for CS remains at 3000h even if the

SMBASE is changed.

Because the segment bases (other than CS) are cleared

to 0 and the segment limits are set to 4 Gbytes, the

address space may be treated as a single flat 4-Gbyte

linear space that is unsegmented. The CPU is still in

Real mode and when a segment selector is loaded with

a 16-bit value, that value is then shifted left by 4 bits and

loaded into the segment base cache.

In SMM, the CPU can access or jump anywhere within

the 4-G byte logical address space. The CP U can also

indirectly access or perform a near jump anywhere with-

in the 4-Gbyte logical address space.

6.7.1 Exceptions and Interrupts with System

Management Mode

When the CPU enters SMM, it disables INTR interrupts,

debug, an d sing le step traps by cleari ng the E FLAGS,

DR6, and DR7 r egisters . This prevents a de bug ap pli-

cation from acc identally br eaking i nto an SMI handler .

This is necessary because the SMI handler operates

from a distinct address space (SMRAM) and the debug

trap does not represent the normal system memory

space.

For an SMI handler to use the debug trap feature of the

processor to debug SMI handler cod e, it m ust firs t en-

sure that an SMM-compliant debug handler is available.

The SMI handler must also ensure DR3–DR0 is saved

to be restored later. The debug registers DR3–DR0 and

DR7 must then be initialized with the appropriate values.

For the process or to u se the singl e step fe ature of the

processor, it must ensure that an SMM-compliant single

step handler is available and then set the trap flag in the

EFLAGS register. If the system design requires the pro-

cessor to r espond to h ardware INTR reques ts while i n

SMM, i t must ensure that an SM M-compliant i nterrupt

handler is available, and then set the interrupt flag in the

Table 12. SMM Initial CPU Core Register Settings

General Purpose

Registers Unmodified

EFLAGS 0000 000 2h

CR0 Bits 0, 2, 3, and 31 cleared (PE, EM, TS,

and PG); rest unmodified

DR6 Unpredictable state

DR7 0000 0400h

GDTR, LDTR,

IDTR, TSSR Unmodified

EIP 0000 8000h

Table 13. Segment Register Initial States

Segment

CS23000h 30000h 16-bit,

expand up 4 Gb yte s

DS 0000h 00000000h 16-bit,

expand up 4 Gb yte s

ES 0000h 00000000h 16-bit,

expand up 4 Gb yte s

FS 0000h 00000000h 16-bit,

expand up 4 Gb yte s

GS 0000h 00000000h 16-bit,

expand up 4 Gb yte s

SS 0000h 00000000h 16-bit,

expand up 4 Gb yte s

Enhanced Am486DX Microprocessor Family 45

P R E L I M I N A R Y

EFLAGS re gister (using th e STI instru ction). Softwar e

interrupts are not blocked on entry to SMM, and the

system soft ware de signe r must pr ovide an SMM-c om-

pliant interrupt handler before attempting to execute any

software interrupt instructions. Note that in SMM mode,

the inter rupt vector ta ble has th e same prope rties a nd

location as the Real mode vector table.

NMI interrupts are blocked on entry to the SMI handler.

If an NMI request occurs during the SMI handler, it is

latched and serviced after the processor exits SMM.

Only one NMI request is latched during the SMI handler.

If an NMI reque st is pending wh en the proces sor exe-

cutes the RSM instruction, the NMI is serviced before

the next instruction of the interrupted code sequence.

Although NMI requests are blocked when the CPU en-

ters SMM, they may be enabled through software by

executing an IRET instruction. If the SMI handler re-

quires the use of NMI interrupts, it should invoke a dum-

my interrupt service routine to execute an IRET

instruction. When an IRET instruction is executed, NMI

interrupt requests are serviced in the same Real mode

manner in which they are handled outside of SMM.

6.7.2 SMM Revisions Identifier

The 32-bit SMM Revision Identifier specifies the version

of SMM and the extensions that are available on the

processor. The fields of the SMM Revision Identifiers

and bit definitions are shown in Table 14 and Table 15.

Bit 17 or 16 i ndi ca tes wheth er the fea tur e is su ppo rt ed

(1=supported, 0=not supported). The processor always

reads the SMM Revision Identifier at the time of a re-

store. The I/O Tr ap E xte nsio n and SMM Bas e Re loc a-

tion bits are fixed. The proce ssor writes these bits out

at the time it performs a save state.

Note: Changing the state of the reserved bits may result

in unpredictable processor behavior.

6.7.3 Auto HALT Restart

The Auto HAL T Res tart slot at register offset (word lo-

cation ) 7F02h i n SMRAM i ndica tes to th e SMI ha ndler

that the SMI interrupted the CPU during a HALT state;

bit 0 of slot 7F02h is set to 1 if the previous instruction

was a HALT (see Figure 28). If the SMI did not interrupt

the CPU in a HALT state, then the SMI microcode sets

bit 0 of the Auto HA LT Res tart sl ot to 0. If the pr evi ous

instruct ion was a HALT, the SMI handler can choose to

either set or reset bit 0. If this bit is set to 1, the RSM

microcode execution forces the processor to re-enter

the HALT state. If this bit is set to 0 when the RSM

instruction is executed, the processor continues execu-

tion with the ins tructio n just after th e interr upted HA LT

instruction. If the HALT instruction is restarted, the CPU

will generate a memory access to fetch the HALT in-

struc tio n ( if it is not in the internal ca ch e) , an d ex ec ut e

a HALT bus cycle.

Table 16 shows the possible restart configurations. If

the interrupted instruction was not a HALT instruction

(bit 0 is set to 0 in the Auto HALT Restart slot upon SMM

entry), setting bit 0 to 1 will cause unpredictable behavior

when the RSM instruction is executed.

Table 14. SMM Revision Identifier

Table 15. SMM Revision Identifier Bit Definitions

HALT Auto Restart

Reserved

15 1 0

Figure 28. Auto HALT Restart Register Offset

31–18 17 16 15–0

Reserved SMM Base

Relocation I/O Trap

Extension SMM Revision Level

00000000000000 1 1 0000h

Bit Name Description Default

State

State at

SMM

Entry

State at

SMM Exit Notes

SMM Base

Relocation 1=SMM Bas e Relocation Avail able

0=SMM Base Relocation

Unavailable 11

0No Change in State

No Change in State

I/O Trap Extension 1=I/O Trapping Available

0=I/O Trapping Unavailable 11

0No Change in State

No Change in State

46 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

6.7.4 I/O Trap Restart

The I/O instruction restart slot (register offset 7F00h in

SMRAM) gives the SMI handler the option of causing

the RSM instruction to automatically re-execute the in-

terrupted I/O instruction (see Figure 29).

When the RSM instruction is executed—if the I/O in-

struction restart slot contains the value 0FFh—the CPU

automatically re-executes the l/O instruction that the

SMI signal trapped. If the I/O instruction restart slot con-

tains the value 00h when the RSM instruction is execut-

ed, then the CPU does not re-execute the I/O instruction.

The CPU automatically initializes the I/O instruction re-

start slot to 00 h during SMM e ntry. The I/O instructi on

restart s lot should be w ritten only when the proce ssor

has gene rated an S MI on an I/O instr uction bou ndary.

Processor operation is unpredictable when the I/O in-

struction restart slot is set when the processor is servic-

ing an SMI that originated on a non-I/O instruction

boundary.

If the system executes back-to-back SMI requests, the

second SMI handler must not set the I/O instruction re-

start slot. The second back-to-back SMI signal will n ot

have the I/O Trap Word set.

6.7.5 I/O Trap Word

The I/O Trap W or d c onta in s the a ddr es s of the I/O a c-

cess that forced the external chipset to assert SMI,

whether it was a read or write access, and whether the

instruction that caused the access to the I/O address

was a valid I/O instruction. Table 17 shows the layout.

Bits 31 –16 contain the I/O address th at was being ac-

cessed at the time SMI became active. Bits 15–2 are

reserved.

If the ins truction tha t caused th e I/O trap to oc cur was

a valid I/O instruction (IN, OUT, INS, OUTS, REP INS,

or REP OUTS), the Valid I/O Instruction bit is set. If it

was not a valid I/O instruc tion, the b it is sav ed as a 0 .

For REP instructions, the external chip set should return

a valid SM I within the first access.

Bit 0 indicates whether the opcode that was accessing

the I/O location was performing either a read (1) or a

write (0) operation as indicated by the R/W bit.

If an SMI occurs and it does not trap an I/O instruction,

the contents of the I/O address and R/W bit are unpre-

dictable and should not be used.

6.7.6 SMM Base Relocation

The Enhanced Am486DX microprocessors provide a

new control register, SMBASE. The SMRAM address

space can be m odifie d by c hangin g the SMBA SE reg-

ister before exiting an SMI handler routine. SMBASE

can be changed to any 32K-aligned value. (Values that

are no t 32K-aligned cause the CPU to enter the shut-

down stat e when exec uting the RSM in struction. ) SM-

BASE is set to the default value of 30000h on RESET.

If SMBASE is changed by an SMI handler, all subse-

quent SMI requests initiate a state save at the new SM-

BASE.

The SMBASE slot in the SMM state save area indicates

and changes the SMI jump vector location and SMRAM

save area. Wh en bit 17 o f th e S MM Rev isi on I dentifier

is set, then this feature exists and the SMRAM base and

conse que ntly , the jump ve ctor, ar e as i ndi ca ted by th e

SMM Base slot (see Figure 30). During the execution

of the RSM instruction, the CPU reads this slot and ini-

tializes the CPU to use the new SMBASE during the

next SMI. During an SMI, the CPU does its context save

to the new SMRAM area pointed to by the SMBASE,

stores the current SMBASE in the SMM Base slot (offset

7EF8h), and then starts execution of the new jump vec-

tor based on the current SMBASE (see Figure 31).

Table 16. HALT Auto Restart Configuration

Value at

Entry Value

at Exit Processor Action on Exit

0 0 Returns to next instruction in interrupt-

ed program

0 1 Unpredictable

1 0 Returns to instruction after HALT

1 1 Returns to interrupted HALT instruction

15 0

I/O instruction restart slot

Figure 29. I/O Instruction Restart Register Offset

Table 17. I/O Trap Word Configuration

31–16 15–2 1 0

I/O Address Reserved Valid I/O Instruction R/W

Figure 30. SMM Base Slot Offset

31 0

SMM Base

Enhanced Am486DX Microprocessor Family 47
P R E L I M I N A R Y
The SMBASE must be a 32-Kbyte aligned, 32-bit integer
that indic ates a bas e address for th e SMRAM co ntext
save area and the SMI jump vector. For example, when
the processor first powers up, the range for the SMRAM
area is from 38000h–3FFFFh. The default value for SM-
BASE is 30000h. 
As illustrated in Figure 31, the starting address of the
jump vector is calculated by:
SMBASE + 8000h
The starting address for the SMRAM state save area is
calculated by:
SMBASE + [8000h + 7FFFh]
When this feature is enabled, the SMRAM register map
is addressed according to the above formula.
To change the SMRAM base address and SMI jump
vector location, SMI handler modifies the SMBASE slot.
Upon executing an RSM instruction, the processor
reads the SMBASE slot and stores it internally. Upon
recognition of the next SMI request, the processor uses
the new  SMBASE s lot for the  SMRAM  dump and  SMI
jump vector. If the modified SMBASE slot does not con-
tain a 32-Kbyte aligned value, the RSM microcode caus-
es the CPU to enter the shutdown state.
6.8 SMM Sy st em  De sign Cons idera ti ons
6.8.1 SMRAM Interface
The hardware designed to control the SMRAM space
must follow these guidelines:
■Initialize SMRAM space during system boot up. Ini-
tialization must occur before the first SMI occurs.
Initialization of SMRAM space must include installa-
tion of an SM I hand ler and  may  includ e ins tall ation
of related data structures necessary for particular
SMM appl ications. The mem ory control ler interfac-
ing SMRAM should provide a means for the initial-
ization code to open the SMRAM space manually.
■The memory controller must decode a minimum ini-
tial SMRAM address space of 38000h–3FFFFh.
■Alternate bus masters (such as DMA controllers)
must not be able to access SMRAM space. The sys-
tem shou ld all ow only  the CP U, either th rough  SMI
or during initialization, to access SMRAM.
■To implement a 0-V suspend function, the system
must have access to all normal system memory from
within an S MI handle r routine. I f the SMRA M over-
lays normal  system mem ory (see Figure  32), there
must be a method to access overlaid system mem-
ory independently.
The recommended configuration is to use a separate
(non-overlaid) physical address for SMRAM. This non-
overlaid scheme prevents the CPU from improperly ac-
cessin g the SMRA M or syst em RAM dire ctly or  through
the cache. Figure 33 shows the relative SMM timing for
non-ov erlaid SMRA M for sys tems confi gured in Wri te-
through mode. For systems configured in Write-back
mode, WB/WT must be driven Low (as shown in Figure
34) to force caching during SMM to be write-through.
Alternately, caching can be disabled during SMM by
deasserting KEN with SMI (as shown in Figure 35).
When the default SMRAM location is used, however,
SMRAM is overlaid with system main memory (at
38000h–3FFFFh). For simplicity, system designers may
want to use this default address, or they may select
another  o verlai d  addre ss r an ge.  Ho wev er, i n  this  c ase
the system control circuitry must use SMIACT to distin-
guish between SMRAM and main system memory, and
must restrict SMRAM space access to the CPU only.
To maintain cache coherency and to ensure proper
system operation in systems configured in Write-
through mode, the system must flush both the CPU inter-
nal ca ch e and a ny  seco nd- l eve l cac hes in resp ons e to
SMIACT going L ow. A system t hat uses cach e during
SMM must flush the cache a second time in response
to SMI ACT going High (see Figure 36). If KEN is driven
High when FLUSH is asserted, the cache is disabled
and a second flush is not required (see Figure 37). If the
system is configured in Write-back mode, the cache
must be flushed when SMI is asserted and then disabled
(see Figure 38).
SMI Handler Entry Point
SMBASE + 8000h
+ 7FFFh
SMRAM
SMBASE + 8000h
SMBASE
Start of State Save
Figure 31. SRAM Usage Non-overlaid
(no need to flush
caches)
Overlaid
(caches must
be flushed)
Normal
memory
Normal
memory
SMRAM Normal
memory
Figure 32. SMRAM Location 
Overlaid region
SMRAM

48 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

State

Save SMI Handler State Resume

Normal

Cycle

RSM

SMI

SMIACT

Figure 33. SMM Timing in Systems Using Non-Overlaid Memory Space

and Write-Through Mode with Caching Enabled During SMM

Figure 34. SMM Timing in Systems Using Non-Overlaid Memory Space

and Write-Back Mode with Caching Enabled During SMM

State

Save SMI Handler State Resume

Normal

Cycle

RSM

SMI

SMIACT

Note:

For proper operation of systems configured in Write-back mode when caching during SMM is allowed, force WB/WT Low to force

all caching to be write-through during SMM.

WB/WT

Figure 35. SMM Timing in Systems Using Non-Overlaid Memory Space

and Write-Back Mode with Caching Disabled During SMM

State

Save SMI Handler State Resume

Normal

Cycle

RSM

SMI

SMIACT

KEN

Enhanced Am486DX Microprocessor Family 49

P R E L I M I N A R Y

Figure 36. SMM Timing in Systems Using Overlaid Memory Space and

Write-Through Mode with Caching Enabled During SMM

State

Save SMI Handler State

Resume Normal

Cycle

RSM

SMI

SMIACT

FLUSH

SMI

Instruction x

Instruction x+1

Cache contents

invalidated Cache contents

invalidated

State

Save SMI Handler State

Resume Normal

Cycle

RSM

SMI

SMIACT

FLUSH

SMI

Instruction x

Instruction x+1

Cache contents

invalidated

KEN

Figure 37. SMM Timing in Systems Using Overlaid Memory Space and

Write-Through Mode with Caching Disabled During SMM

SMI

SMIACT

KEN

FLUSH

RSM

State

Save SMI Handler State

Resume Normal Cycle

Cache Flush State

Cache must

be empty

Figure 38. SMM Timing in Systems Using Overlaid Memory Space

and Configured in Write-Back Mode

50 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

6.8.2 Cache Flushes

The CPU does not unconditionally flush its cache before

entering SMM. Therefore, the designer must ensure

that, for syste ms using overlai d SMRAM, the cac he is

flushed upon SMM entry and SMM exit if caching is

enabled.

Note: A cache flush in a system configured in Write-

back mode requires a minimum of 4100 internal clocks

to test the cache for modified data, whether invoked by

the FLUSH pin input or the WBINVD instruction, and

therefore invokes a performance penalty. There is no

flush penalty for systems configured in Write-through

mode.

If the flush at SMM entry is not done, the first SMM read

could hit in a cache that contains normal memory space

code/data instead of the required SMI handler, and the

handler c ould not be ex ecuted. If th e cache is n ot dis-

abled and i s not flushed at SMM exit, th e normal re ad

cycles after SMM may hit in a cach e that may contain

SMM code/ data ins te ad of the n or mal sy stem m emory

contents .

In Write-thr ough mode , assert the FLUS H s ig nal i n re-

sponse to the assertion of SMIACT at SMM entry, and,

if required because the cache is enabled, assert FLUSH

again in response to the deassertion of SMIACT at SMM

exit (see Figure 36 and Figure 37). For systems config-

ured in Write-back mode, assert FLUSH with SMI (see

Figure 38).

Reloading the state registers at the end of SMM restores

cache functionality to its pre-SMM state.

6.8.3 A20M Pin

Systems based on the MS-DOS operating system con-

tain a feature that enables the CPU address bit A20 to

be forced to 0. This limits p hysical memory to a maxi-

mum of 1 Mbyte, and is provided to ensure compatibility

with those programs that relied on the physical address

wraparound functionality of the original IBM PC. The

A20M pin on the Enhanced Am486DX microprocessors

provide this function. When A20M is active, all external

bus cycles drive A20 Low, and all internal cache access-

es are performed with A20 Low.

The A20M pi n is r eco gni zed whi le the CPU is i n SM M.

The functionality of the A20M input must be recognized

in two instances:

1. If the SMI handler needs to access system memory

space above 1 Mbyte (for example, when saving mem-

ory to d isk fo r a 0-V sus pe nd) , th e A2 0M pin must be

deasserted before the memory above 1 Mbyte is ad-

dressed.

2. If SMRAM has been relocated to address space above

1 Mbyte, and A20M is active upon entering SMM, the

CPU attempts to access SMRAM at the relocated ad-

dress, but with A20 Low. This could cause the system

to crash, because there would be no valid SMM inter-

rupt handler at the accessed location.

To account for these two situations, the system designer

must ensure that A20M is deasserted on entry to SMM.

A20M must be driven inactive before the first cycle of

the SMM state save, and must be returned to its original

level after the last cycle of the SM M state restore. This

can be done by blocking the asse rtion of A20M when

SMIACT is active.

6.8.4 CPU Reset During SMM

The sy stem de signe r should take i nto a ccount the fol-

lowing restrictions while implementing the CPU Reset

logic:

1. When running software written for the 80286 CPU,

a CPU RESET switches the CPU from Protected

mode to R eal mo de. R ES ET a nd S RE SET hav e a

higher priority than SMI. When the CPU is in SMM,

the SRESET to the CPU during SMM should be

blocked until the CPU exits SMM. SRESET must

be blocked beginning from the time when SMI is

driven active. Care should be taken not to block the

global system RESET, which may be necessary to

recover from a system crash.

2. During execution of the RSM instruction to exit

SMM, there is a small time window between the

deassertion of SMI ACT and the completion of the

RSM microcode. If a Protected mode to Real mode

SRESET is asserted during this window, it is

possible that the SMRAM space will be violated.

The system designer must guarantee that SRESET

is bl ocked until at least 20 CPU cloc k cycles af ter

SMIACT has be en dr iven inact ive o r until the st art

of a bus cycle.

3. Any request for a CPU RESET for the purpose of

switching the CPU from Protected mode to Real

mode must be acknowledged after the CPU has

exited SMM. To maintain software transparency,

the system logic must latch any SRESET signals

that are blocked during SMM.

For these reasons, the SRESET signal should be used

for any soft resets, and the RESET signal should be

used for all hard resets.

6.8.5 SMM and Second-Level Write Buffers

Before the processor enters SMM, it empties its internal

write buffers. This is to ensure that the data in the write

buffers is written to normal memory space, not SMM

space. When the CPU is ready to begin writing an SMM

state save to SMRAM, it asserts SMIACT. SMIACT may

be driven active by the CPU before the system memory

contr oller has had an o pportuni ty to em pty the s econd

level write buffers.

To prevent the data from these second level write buffers

from being written to the wrong location, the system

memory controller needs to direct the memory write cy-

Enhanced Am486DX Microprocessor Family 51

P R E L I M I N A R Y

cles to either SMM space or normal memory space. This

can be accomp lished by saving the stat us of S MIACT

with the address for each word in the write buffers.

6.8.6 Nested SMI and I/O Restart

Special care must be taken when executing an SMI han-

dler for the purpose of restarting an l/O instruction. When

the CPU executes a Resume (RSM) instruction with the

l/O restart slot set, the restored EIP is modified to point

to the instruction immediately preceding the SMI re-

quest, so that the l/O instruction can be re-executed. If

a new SMI request is received while the CPU is execut-

in g an SMI handler, the CPU services this SMI request

before restarting the original I/O instruction. If the I/O

restart slo t is set when the CP U execu tes the RS M in-

structi on for the second S MI handler, the RS M micro-

code decrements the restored EIP again. EIP then

points to an address d ifferent from t he originally inter-

rupted instruction, and the CPU begins execution at an

incorrect entry point. To prevent this from occurring, the

SMI handler routine must not set the I/O restart slot

during the second of two consecutive SMI handlers.

6.9 SMM Software Considerations

6.9.1 SMM Code Considerations

The defaul t oper and s ize an d the defaul t addr ess s ize

are 16 bits; however, operand-size override and ad-

dress-size override prefixes can be used as needed to

directly access data anywhere within the 4-Gbyte logical

address space.

With operand-size override prefixes, the SMI handler

can use jumps, calls, and returns to transfer a control

to any location within the 4-Gbyte space. Note, however,

the following restrictions:

1. Any control transfer that does not have an operand-

size override prefix truncates EIP to 16 Low-order bits.

2. Due to the Real mode style of base-address formation,

a long jump or call cannot transfer control segment

with a base address of more than 20 bits (1 Mbyte).

6.9.2 Exception Handling

Upon entry into SMM, external interrupts that require

handlers are disabled (the IF in EFLAGS is cleared).

This is necessary because, while the processor is in

SMM, it is running i n a separate memor y space. Con-

sequently, the vectors stored in the interrupt descriptor

table (IDT) for the prior mode are not applicable. Before

allowing exception handling (or software interrupts), the

SMM pr ogr am m us t i ni tia li ze new interrup t and ex cep-

tion vectors. The interrupt vector table for SMM has the

same format as for Real mode. Until the interrupt vector

table is correctly initialized, the SMI handler must not

generate an exception (or software interrupt). Even

though hardware interrupts are disabled, exceptions

and software interrupts can still occur. Only a correctly

written SMI handler can prevent internal exceptions.

When new exception vectors are initialized, internal ex-

ceptions can be serviced. Restrictions are as follows:

1. Due to the Real mode style of base address forma-

tion, an in ter rupt or exc epti on c anno t tran sfer co n-

trol to a segment with a base address of more than

20 bits.

2. An interrupt or exception cannot transfer control to

a segment offset of more than 16 bits.

3. If exceptions or interrupts are allowed to occur, only

the Low order 16 bits of the return address are

pushed onto the stack. If the offset of the interrupted

procedure is greater than 64 Kbyte, it is not possible

for the interru pt/exception handler to return control

to that proc edure. (One wor k-around is to pe rform

software adjustment of the return address on the

stack.)

4. The SMBASE Relocation feature affects the way

the CPU returns from an interrupt or exception dur-

ing an SMI handle r.

Note: The execution of an IRET instruction enables

Non-Maskable Interrupt (NMI) processing.

6.9.3 Halt During SMM

HALT shou ld not be executed dur ing SMM, unles s in-

terrupts have been enabled. Interrupts are disabled on

entry to SMM. IN TR and NMI are the on ly events that

take the CPU out of HALT within SMM.

6.9.4 Relocating SMRAM to an Address Above

1 Mbyte

Within SMM (or Real mode), the segment base registers

can be updated only by changing the segment register.

The segment registers contain only 16 bits, which allows

only 20 bits to be used for a segment base address (the

segment register is sh ifted left 4 bit s to determine the

segment base address). If SMRAM is relocated to an

addres s above 1 Mbyte, the seg ment regi sters c an no

longer be initialized to point to SMRAM.

These areas can still be accessed by using address

override prefixes to generate an offset to the correct

address. For example, if the SMBASE has been relo-

cated immediately below 16 Mbyte, the DS and ES reg-

isters are still initialized to 0000 0000h. Data in SMRAM

can still be accessed by using 32-bit displacement reg-

isters.

move esi,OOFFxxxxh ;64K segment

immediately below 16M

move ax,ds:[esi]

7 TEST REGISTERS 4 AND 5

MODIFICATIONS

The Cache Test Registers for the Enhanced Am486DX

microprocessors are the same test registers (TR3, TR4,

and TR5) provided in all Am486 microprocessors. TR3

is the cache test data register. TR4, the cache test status

ate together with TR3.

52 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

If WB/WT meets the necessary setup timing and is sam-

pled Low o n the fa llin g edge of RES ET, the p roce ssor

is placed in Write-through mode and the test register

function is identi cal to Am 486 mic roproc esso rs. If WB/

WT meets the nece ssary s etup timin g and is s ampled

High on the falling edge of RESET, the processor is

placed i n Write-back mode and the test registers TR4

and TR5 ar e m odi fi ed to support the add ed wr ite-b ack

cache functionality. Tables 18 and 19 show the individ-

ual bit functions of these registers. Sections 8.1 and 8.2

provide a detailed description of the field functions.

Note: TR3 has the same functions in both Write-through

and Write-back modes.These functions are identical to

the TR3 register functions provided by

Am486

micro-

processors.

7.1 TR4 Definition

This section includes a detailed description of the bit

fields defined for TR4.

Note: Bits listed in Table 18 as Reserved or Not used

are not included in these descriptions.

■

Tag (bits 31–12):

Read/Write, always available in

Write-through mode. Available only when EXT=0 in

TR5 in Wr ite-back mo de. For a cac he write, this is

the tag tha t spec ifies the a ddress in m emory. On a

cache look-up, this is tag for the selected entry in the

cache.

■

STn (bits 30–29):

Read Only, available only in Write-

back mode when Ext=1 in TR5. STn returns the sta-

tus of the set (ST3, ST2 , ST1, or ST0) spec ified by

the TR5 Set State field (bits 18–17) during cache

look-ups. Returned values are

— 00 = invalid

— 01 = exclusive

— 10 = modified

— 11 = shared

■

ST3 (bits 27–26):

Read Only, available only in Write-

back mode when Ext=1 in TR5. ST3 returns the sta-

tus of Set 3 during cache look-ups. Returned values

are

— 00 = invalid

— 01 = exclu sive

— 10 = modified

— 11 = shared

■

ST2 (bits 25–24):

Read Only, available only in Write-

back mode when Ext=1 in TR5. ST2 returns the sta-

tus of Set 2 during cache look-ups. Returned values

are

— 00 = invalid

— 01 = exclu sive

— 10 = modified

— 11 = shared

■

ST1 (bits 23–22):

Read Only, available only in Write-

back mode when Ext=1 in TR5. ST1 returns the sta-

tus of Set 1 during cache look-ups. Returned values

are

— 00 = invalid

— 01 = exclu sive

— 10 = modified

— 11 = shared

■

ST0 (bits 21–20):

Read Only, available only in Write-

back mode when Ext=1 in TR5. ST0 returns the sta-

tus of Set 0 during cache look-ups. Returned values

are

— 00 = invalid

— 01 = exclu sive

— 10 = modified

— 11 = shared

Table 18. Test Register TR4 Bit Descriptions

31 30–29 28 27–26 25–24 23–22 21–20 19–16 15–12 11 10 9–7 6–3 2–0

EXT=0 Tag 0 Valid LRU Valid

(rd) Not

used

EXT=1 Not

used STn Rsvd. ST3 ST2 ST1 ST0 Reserved Not used Valid LRU Valid

(rd) Not

used

Table 19. Test Register TR5 Bit Descriptions

31–20 19 18–17 16 15–12 11–4 3–2 1–0

Write-Back Not used Ext Set State Reserved Not used Index Entry Control

Write-Through Not used Index Entry Control

Notes:

1. Bit 19 in TR5 is EXT. If EXT = 0, TR4 has the

standard 486

processor definition for write-through cache.

2. The values of Set State are: 00 = Invalid; 01 = Exclusive; 10 = Modified; 11 = Shared.

Enhanced Am486DX Microprocessor Family 53

P R E L I M I N A R Y

■

Valid (bit 10):

Read/Write, independent of the Ext bit

in TR5. This is the Vali d bit for the access ed entry.

On a cache look-up, Valid is a copy of one of the bits

reported in bits 6–3. On a cache write in Write-

through mod e, Valid become s the new Vali d bit for

the selected entry and set. In Write-back mode, writ-

ing to the V al id b it h as no e ffect and is igno r ed; t he

Set State bit locations in TR5 are used to set the

Valid bit for the selected entry and set.

■

LRU (bits 9– 7):

Read Onl y, independe nt of the Ext

bit in TR5. O n a c ac he loo k-up , the se ar e t he th ree

LRU bits of the accessed set. On a cache write, these

bits ar e ignored; the LRU bits in the cache ar e up-

dated by the pseudo-LRU cache replacement algo-

rithm. Write operations to these locations have no

effect on the device.

■

Valid (b its 6–3 ):

Read Only, independent of the Ext

bit in TR5. On a cache look-up, these are the four

Valid b its o f th e a cces s ed se t. I n W r ite -bac k mod e,

these valid bits are set if a cache set is in the exclu-

sive, mod ified, or shar ed state. Write oper ations to

these locations have no effect on the device.

7.2 TR5 Definition

This section includes a detailed description of the bit

fields in the TR5.

Note: Bits li st ed in Tab l e 19 a s Rese r v ed or Not Used

are not included in the descriptions.

■

Ext (bit 19):

Read/Write, available only in Write-back

mode. Ext, or extension, determines which bit fields

are defined for TR4: the address TAG field, or the

STn and ST3–ST0 status bit fields. In Write-through

mode, the Ext bit is not accessible. The following

describes the two states of Ext:

— Ext = 0, bits 31–11 of TR4 contain the TAG ad-

dress

— Ext = 1, bits 30–29 of TR4 contain STn, bits 27–

20 contain ST3–ST0

■

Set State (bits 18–17):

Read/Write, available only in

Write-back mode. The Set State field is used to

change the MESI state of the set specified by the

Index and Entry bits. The state is set by writing one

of the following combinations to this field:

— 00 = invalid

— 01 = exclusive

— 10 = modified

— 11 = shared

■

Index (bits 11–4):

Read/Write, independent of Write-

through or Write-back mode. Index selects one of

the 256 cache lines.

■

Entry (b its 3– 2):

Read/Write, indepen dent of W rite-

through or Write-back mode. Entry selects between

one of the four entrie s in the set addressed by the

Set Select during a cache read or write. During cache

fill buffer writes or cache read buffer reads, the value

in the Entry field selects one of the four doublewords

in a cache line.

■

Control (bits 1–0):

Read/Write, independent of

Write -throug h or Wri te-back mode. The con trol b its

determine which operation to perform. The following

is a definition of the control operations:

— 00 = Write to cache fill buffer, or read from cache

read buffer

— 01 = Perform cache write

— 10 = Perform cache read

— 11 = Flush the cache (mark al l entries invalid)

7.3 Using TR4 and TR5 for Cache Testing

The following parag raphs provide examp les of testing

the cache using TR4 and TR5.

7.3.1 Example 1: Reading The Cache (Write-Back

Mode Only)

1. Disable caching by setting the CD bit in the CR0

2. In TR5, load 0 into the Ext field (bit 19), the required

index into the Index field (bits 10–4), the required

entry value into the Entry field (bits 3–2), and 10 into

the Control field (bits 1–0). Loading the values into

TR5 triggers the cache read. The cache read loads

the TR4 register with the TAG for the read entry,

and the LRU and Valid bits for the entire set that

was re ad. Th e c ach e read loads 12 8 dat a bi ts int o

the cache read buffer. The entire buffer can be read

by plac ing each of the four bi nary com bination s in

the Entr y field and se tting the Contr ol field in TR 5

to 00 (binary). Read each doubleword from the

cache read buffer through TR3.

3. Reading the Set State fields in TR4 during Write-

back mode is accomplished by setting the Ext field

in TR5 to 1 and rereading TR4.

7.3.2 Example 2: Writing The Cache

1. Disable the cache by setting the CD bit in the CR0

2. In TR5, load 0 into the Ext field (bit 19), the required

entry value into the Entry field (bits 3–2), and 00 into

the Control field (bits 1–0).

3. Load the TR3 regi ster with the da ta to write to the

cache fill buffer. The cache fill buffer write is trig-

gered by loading TR3.

4. Repeat s teps 2 a nd 3 for the remai ni ng th r ee do u-

blewords in the cache fill buffer.

5. In TR4, load the required values into TAG field (bits

31–11) and the Valid field (bit 10). In Write-back

mode, the Valid bit is ignored since the Set State

field in TR5 is used in place of the TR4 Valid bit.

54 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

The other bits in TR4 (9:0) have no effect on the

cache write.

6. In TR5, load 0 into the Ext field (bit 19), the required

value into the Set State field (bits 18–17) (Write-

back mode only), the required index into the Index

field (bits 10–4), the required entry value into the

Entry field (bits 3–2), and 01 into the Control field

(bits 1–0). Loading the values into TR5 triggers the

cache wr ite. In Write-th rough mode, the Se t State

field is ignored, and the V alid bit ( bit 10) i n TR4 is

used instead to define the state of the specified set.

7.3.3 Example 3: Flushing The Cache

The cache flush mechanism functions in the same way

in Write-back and Write-through modes. Load 11 into

the Control field (bits 1–0) of TR5. All other fields are

ignored, except for Ext in Write-back mode. The cache

flush is triggered by loading the value into TR5. All of

the LRU bits, Valid bits, and Set State bits are cleared.

8 Am486 MICROPROCESSOR

FUNCTIONAL DIFFERENCES

In addition to the new Enhanced Am486DX micropro-

cessors, Am486 microprocessors include the standard

Am486DX, the Am486DE2, and the Enhanced Am486

microprocessor families. Major differences in these pro-

cessors are highlighted in Table 20, and described be-

low.

8.1 Standard Am486DX Processors

The standard Am486DX processor supports an 8-Kbyte

write-through cache. Several important differences exist

between the standard Am486DX processors and the

Am486DE2 and Enhanced processors:

■The ID register contains a different version signa-

ture.

■The EADS function performs cache line write-backs

of modified lines to memory in Write-back mode.

■A burst write feature is available for copy-backs. The

FLUSH pin and WBINVD instruction copy back all

modified data to external memory prior to issuing the

special bus cycle or reset.

■The RESET state is invoked either after power up or

after the RESET signal is applied according to the

standard 486DX microprocessor specification.

■After reset, the STATUS bits of all lines are set to 0.

The LRU bits of each set are placed in a starting

state.

8.2 Am486DE2 Microprocessors

The Am486DE2 processors also provide a 8-Kbyte

write-through cache, and add flexible clock control and

enhanced SMM.

■Nine signals were added to support new features:

CACHE, HITM, INV, SMI, SMIACT, SRESET,

STPCLK, VOLDET, and WB/WT.

8.3 Enhanced Am486 Microprocessors

The Enhanced Am486 microprocessors add support for

write-ba ck cache a nd 3x cloc k mode ( running at thr ee

times the system bus speed).

■The CLKMUL signal was added to support clock-

tripled mode.

■The following pins have new functions to implement

write-back cache protocol: AHOLD, BLAST, CLK,

EADS, FLUSH, and PLOCK.

8.4 Enhanced Am486DX Microprocessor

Family

The Enhanced Am486DX microprocessors add support

for 4x clock mode and 16-Kbyte cache. The Enhanced

Am486DX microprocessors are functionally identical to

the Am486DE2 and Enhanced Am486 family proces-

sors except for:

■The function of the CLKMUL pin (see page 13) to

set the new clock speed.

■The redef inition of TR4 and TR5 to acce ss the 16-

Kbyte cache (see section 7 on page 51).

Table 20. Am486 Family Functional Differences

Processor Cache Clock Major Enhancements to Standard

Standard Am486DX processors 8-Kbyte write-through 1x, 2x

Am486DE2 processors 8-Kbyte write-through 2x Flexible clock control, enhanced SMM

Enhanced Am486 Microprocessor Family

(Am486DX2, Am486DX4 ) 8-Kbyte wr ite-b ac k 2x, 3x Above plus wr ite- bac k cac he

Enhanced Am486DX Microprocessor Family

(Am486DX2, Am486DX4, Am486DX5) 16-Kbyt e write-b ack 2x, 3x, 4x Above plus 16-Kbyte write-back cache,

extended temperature

Enhanced Am486DX Microprocessor Family 55

P R E L I M I N A R Y

9 ENHANCED Am486DX CPU IDENTIFICATION

The Enhanced Am486DX microprocessors support two

standard methods for identifying the CPU in a system.

The reported values are assigned based on the RESET

status of the WB/WT pin input (Low = Write-through;

High = Write-back).

9.1 DX Register at RESET

The DX register always contains a component identifier

at the conclusion of RESET. The upper byte of DX (DH)

contains 04 and the lower byte of DX (DL) contains a

CPU type/stepping identifier (see Table 21).

9.2 CPUID Instruction

The Enhance d Am486DX m icroprocesso rs impleme nt

the CPUID instruction that makes information available

to software about the family, model and stepping of the

processor on which it is executing. Support of this in-

struction is indicated by the presence of a user-modifi-

able bit in position EFLAGS.21, referred to as the

EFLAGS.ID bit. This bit is reset to zero at device reset

(RESET or SRESET) for compatibility with existing pro-

cessor designs.

9.2.1 CPUID Timing

CPUID execution timing depends on the selected EAX

parameter values (see Table 22).

9.2.2 CPUID Operation

The CPUID instruction requires the user to pass an input

parameter to the CPU in the EAX register. The CPU

response is returned to the user in registers EAX, EBX,

ECX, and EDX. When the parameter passed in EAX is

zero, the register values returned upon instruction exe-

cution are:

The values in EBX, ECX, and EDX indicate an AMD

microprocessor. When taken in the proper order:

■EBX (least significant bit to most significant bit)

■EDX (least significant bit to most significant bit)

■ECX (least significant bit to most significant bit)

they decode to

AuthenticAMD

When the parameter passed in EAX is 1, the register

values returned are

The value retur ned in EAX afte r CPUID ins truction ex-

ecutio n is identica l to the valu e loaded into EDX upon

device reset. Software must avoid any dependency

upon the stat e of reser ved processo r bits.

When the parameter passed in EAX is greater than one,

regi st er v al ue s re t ur ne d u pon in s tr uc t io n ex ec ut i o n are

Table 21. CPU ID Codes

Processor CLKMUL Write-

Back

Mode

Write-

Through

Mode

Am486DX2-66 0 (x2) 0474h 0434h

Am486DX4-100 1 (x3) 0494h 0484h

Am486DX5-133 0 (x4) 04F4h 04E4h

Table 22. CPUID Instruction Description

Code Instruction EAX

Input

Value

CPU

Core

Clocks Description

0F A2 CPUID 0

AMD string

CPU ID Register

null registers

EAX[31:0] 00000001h

EBX[31:0] 68747541h

ECX[31:0] 444D4163h

EDX[31:0] 69746E65h

EAX[3:0] 4h or 0100

EAX[7:4] model:

Enhanced Am486DX CPU:

Write-through mode = Eh

Write-back mode = Fh

EAX[11:8] Family:

486 Instruction Set = 4h

EAX[15:12] 0000

EAX[31:16] RESERVED

EBX[31:0] 00000000h

ECX[31:0] 00000000h

EDX[31:0] 00000001h = all versions

The 1 in bit 0 indicates that the FPU

is present

EAX[31:0] 00000000h

EBX[31:0] 00000000h

ECX[31:0] 00000000h

EDX[31:0] 00000000h

Flags affected: No flags are affected.

Exceptions: None

56 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

10 ELEC T R IC AL DA T A

The followi ng sections describe recommend ed electri-

cal connections and electrical specifications for the En-

hanced Am486DX microprocessors.

10.1 Power and Grounding

10.1.1 Power Connections

With 16 Kbyte of cache, the Enhanced Am486DX mi-

croprocessors have modest power requirements. How-

ever, the high clock frequency output buffers can cause

power surges as multiple output buffers drive new signal

levels simultaneou sly. For clea n, on-chip power distri-

bution at high frequency, 23 VCC pins and 28 VSS pins

feed the m icroproces sor in th e 168-pin PG A packag e.

The 208-pin SQFP package includes 53 VCC pins and

38 VSS pins.

Power and ground connections must be made to all

external VCC and VSS pins of the microprocessors. On a

circuit board, all VCC pins must connect to a VCC plane.

Likewise, all VSS pins must connect to a common GND

plane.

The Enhanced Am486DX microprocessors require only

3.3 V as inpu t powe r. Unli ke other 3-V pr o cess or s, the

Enhanced Am486DX microprocessors do not require a

VCC5 input of 5 V to indicate the presence of 5-V I/O

devices on the system motherboard. For socket com-

patibility, this pin is INC, allowing the Enhanced

Am486DX microprocessors to operate in 3-V sockets

in systems that use 5-V I/O.

10.1.2 Power Decoupling Recommendations

Liber al dec oupl ing c apaci tance shou ld be plac ed ne ar

the microprocessor. The microprocessor, driving its 32-

bit parallel address and data buses at high frequencies,

can cause transient power surges, particularly when

driving large capacitive loads.

Low inductance capacitors and interc onnects are rec-

ommended for best high-frequency electrical perfor-

mance. Inductance can be reduced by shortening

circuit- board traces between the microprocessor and

the decoupling capacitors. Capacitors designed specif-

ically for use with PGA packages are commercially avail-

able.

10.1.3 Other Connection Recommendations

For reliable operation, always connect unused inputs to

an appropriate signal level. Active Low inputs should be

connected to VCC through a pull-up resistor. Pull-ups in

the rang e of 20 KΩ ar e recom mended . Activ e High in-

puts should be connected to GND.

Enhanced Am486DX Microprocessor Family 57

P R E L I M I N A R Y

ABSOLUTE MAXIMUM RATINGS

Case Temperature under Bias . . . – 65°C to +110°C

Storage Temperature . . . . . . . . . . – 65°C to +150°C

Voltage on any pin

with respect to ground . . . . . . – 0.5 V to Vcc +2.6 V

Supply voltage with

respect to VSS . . . . . . . . . . . . . . – 0.5 V to +4.6 V

Stresses above those listed under Absolute Maximum Ratings

may cause permanent device failure. Functionality at or above

these limits is not implied. Exposure to Absolute Maximum

Ratings for extended periods may affect device reliability.

OPERATING RANGES

TCASE (Commercial) . . . . . . . . . . . . . . . 0°C to +85°C

TCASE (Industrial) . . . . . . . . . . . . . . –40°C to +100°C

VCC . . . . . . . . . . . . . . . . . . 3.3 V ±0.3 V (see Note 7)

Operating Ranges define those limits between which the func-

tionality of the device is guaranteed.

DC CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges

VCC = 3.3 V ± 0.3 V (see Note 7); TCASE = 0°C to + 85°C (Commercial); TCASE = –40°C to + 100°C (Industrial)

Preliminary Info

Symbol Parameter Min Max Notes

VIL Input Low Voltage – 0.3 V +0.8 V

VIH Input High Voltage 2.0 V VCC + 2.4 V

VOL Outpu t Low Voltage 0.45 V Note 1

VOH Output High Voltage 2.4 V Note 2

ICC Power Supply Current 7 mA/MHz Outputs unloaded.

ICCSTOPGRANT

or ICCAUTOHALT Input Current in Stop Grant or Auto Halt mode: 0.7 mA/MHz Typical supply current for Stop Grant or

Auto Halt mode: 50 mA @ 133 MHz.

ICCSTPCLK Input Current in Stop Clock mode 5 mA Typical supply current in Stop Clock

mode is 600 µA.

ILI Input Leakage Current: VCC

5 V ±15 µA

±50 µA Note 3

IIH Input Leakage Current 200 µA Note 4

IIL Input Leakage Current – 400 µA Note 5

ILO Output Leakage Current: VCC

5 V ±15 µA

±50 µA

CIN Input Capacitance 10 pF FC = 1 MHz (Note 6)

COI/O or Output Capacitance 14 pF FC = 1 MHz (Note 6)

CCLK CLK Capaci tanc e 12 pF FC = 1 MHz (Note 6)

Notes:

1. This parameter is measured at: Address, Dat a, BE3–BE0 = 4.0 mA; Definition, Control = 5.0 mA

2. This parameter is measured at: Address, Dat a, BE3–BE0 = –1.0 mA; Definition, Control = –0.9 mA

3. This parameter is for inputs without internal pull-ups or pull-downs and 0

≤

IN ≤

4. This parameter is for inputs with internal pul l-downs and V

= 2.4 V.

5. This parameter is for inputs with internal pull-ups and V

= 0.45 V.

6. Not 100% tested.

7. The V

range for the AM486DX5-133V16BHC and BGC products is (3.15 V

≤

3.6 V).

58 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

The AC spec i ficati ons , prov i ded in th e AC cha r act er is-

tics table, consist of output delays, input setup require-

ments, and input hold requirements. All AC specifica-

tions are relative to the rising ed ge of the CLK signal.

AC specifications measurement is defined by Figure 39.

All timings are referenced to 1.5 V unless otherwise

specified. Enhanced Am486DX microprocessor output

delays are specified with minimum and maximum limits,

measured as shown. The minimum microprocessor de-

lay times are hold ti mes provided to external circuitry.

Input setup and hold times are specified as minimums,

defining the smallest acceptable sampling window.

Within the sampling window, a synchronous input signal

must be stable for correct microprocessor operation.

SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges

33-MHz Bus

VCC = 3.3 V ±0.3 V (see Note 6); TCASE = 0°C to +85°C (Commercial); TCASE = –40°C to +100°C (Industrial);

CL = 50 pF unless otherwise specified Preliminary Info

Symbol Parameter Min Max Unit Figure Notes

Frequency 833 MHz Note 2

t1CLK Period 30 125 ns 39

t1a CLK Period Stability 0.1% ∆Adjacent Clocks

Notes 3 and 4

t2CLK High Time at 2 V 11 ns 39 Note 3

t3CLK Low Time at 0.8 V 11 ns 39 Note 3

t4CLK Fall Time (2 V–0.8 V) 3ns 39 Note 3

t5CLK Rise Time (0.8 V–2 V) 3ns 39 Note 3

A31–A2, PWT, PCD, BE3–BE0, M/IO, D/ C, CACHE,

W/R, ADS, LOCK, FERR, BREQ, HLDA,

SMIACT, HITM Valid Delay 3 14 ns 40 Note 5

t7A31–A2, PWT, PCD, BE3–BE0, M/IO, D/ C, CACHE,

W/R, ADS, LOCK Float Delay 320 ns 41 Note 3

t8PCHK Valid Delay 314 ns 42

t8a BLAST, PLOCK, Valid Delay 3 14 ns 40

t9BLAST, PLOCK, Float Delay 320 ns 41 Note 3

t10 D31–D0, DP3–DP0 Write Data Valid Delay 314 ns 40

t11 D31–D0, DP3–DP0 Write Data Float Delay 320 ns 41 Note 3

t12 EADS, INV, WB/WT Setup Time 5ns 43

t13 EADS, INV, WB/WT Hold Time 3ns 43

t14 KEN, BS16, BS8 Setup Time 5ns 43

t15 KEN, BS16, BS8 Hold Time 3ns 43

t16 RDY, BRDY Setup Time 5 ns 44

t17 RDY, BRDY Hold Time 3ns 44

t18 HOLD, AHOLD Setup Time 6ns 43

t18a BOFF Setup Time 7 ns 43

t19 HOLD, AHOLD, BOFF Hold Time 3ns 43

t20 RESET, FLUSH, A20M , NMI, INTR, IGNNE,

STPCLK, SRESET, SMI Setup Time 5ns 43 Note 5

t21 RESET, FLUSH, A20M , NMI, INTR, IGNNE,

STPCLK, SRESET, SMI Hold Time 3ns 43 Note 5

t22 D31–D0, DP3–DP0, A31–A4 Read Setup Time 5ns 43, 44

t23 D32–D0, DP3–DP0, A31–A4 Read Hold Time 3ns 43, 44

Notes:

1. Specification s assume C

= 50 pF. I/O Buffer m odel must be u sed to dete rmine del ays due to load ing (trace a nd compo nent).

First Order I/O b uffer models for th e process or are avai lable.

2. 0-MHz operation g uaran teed during stop clock o peration.

3. Not 100% tes ted. Guaranteed by d esign ch aracteriza tion.

4. For faster transiti ons (> 0.1% between adjacent c locks), use the Stop Cl ock proto col to switc h operating frequency .

5. All timings a re referenced at 1.5 V (as il lustrated in the l isted figu res) unles s otherwise noted.

6. The V

range for the AM486DX5-133V16BHC and BGC products is (3.15 V

≤

3.6 V).

Enhanced Am486DX Microprocessor Family 59

P R E L I M I N A R Y

AC Characteristics for Boundary Scan Test Signals at 25 MHz

VCC = 3.3 V ± 0.3 V (see Note 4); TCASE = 0°C to +85°C (Commercial); TCASE = –40°C to +100°C (Industrial);

CL = 50 pF unless otherwise specified

Preliminary Info

Symbol Parameter Min Max Unit Figure Notes

t24 TCK Frequen cy 25 MHz 1x Clock

t25 TCK Period 40 ns 45, 46 Note 1

t26 TCK High Time at 2 V 10 ns 45

t27 TCK Low Time at 0.8 V 10 ns 45

t28 TCK Rise Time (0.8 V–2 V) 4ns 45 Note 2

t29 TCK Fall Time (2 V–0.8 V) 4ns 45 Note 2

t30 TDI, TMS Setup Time 8ns 46 Note 3

t31 TDI, TMS Hold Time 7ns 46 Note 3

t32 TDO Valid Delay 325 ns 46 Note 3

t33 TDO Float Delay 36 ns 46 Note 3

t34 All Outputs (Non-Test) Valid Delay 325 ns 46 Note 3

t35 All Outputs (Non-Test) Float Delay 30 ns 46 Note 3

t36 All Inputs (Non-Test) Setup Delay 8ns 46 Note 3

t37 All Inputs (Non-Test) Hold Time 7ns 46 Note 3

Notes:

1. TCK period

≥

CLK period.

2. Rise/Fall times ca n be relax ed by 1 ns per 10 -ns increa se in TC K period.

3. Parameter measured from TCK.

4. The V

range for the AM486DX5-133V16BHC and BGC products is (3.15 V

≤

3.6 V).

60 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

SWITCHING WAVEFORMS

Key to Switching Waveforms

Waveform Inputs Outputs

Must be steady Will be steady

May change from

H to L Will change

from H to L

May change from

L to H Will change

from L to H

Don’t care; any

change permitted Changing;

state unknown

Does not apply Center line is

High-impedance

“Off” state

Figure 39. CLK Waveforms

Figure 40. Output Valid Delay Timing

Enhanced Am486DX Microprocessor Family 61

P R E L I M I N A R Y

Figure 41. Maximum Float Delay Timing

Figure 42. PCHK Valid Delay Timing

62 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

t18, t18a

Figure 43. Input Setup and Hold Timing

Figure 44. RDY and BRDY Input Setup and Hold Timing

Enhanced Am486DX Microprocessor Family 63

P R E L I M I N A R Y

Figure 45. TCK Waveforms

Figure 46. Test Signal Timing Diagram

64 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

12 PACKAGE THERM AL SPECIFICATIONS

The Enhanced Am486DX microprocessors are speci-

fied for operation when TCASE (the case temperature) is

within the range of 0°C to +85°C. TCASE can be measured

in any environment to determine whether the Enhanced

Am486DX microprocessors are within specified operat-

ing rang e. The c ase tempe rature s hould be me asur ed

at the center of the top surface opposite the pins.

The ambient temperature (TA) is guaranteed as long as

TCASE is not viol ated. The ambie nt temp eratu re can be

calculated from θJC and θJA and from these equations:

TJ = TCASE + P • θJC

TA = TJ – P • θJA

TCASE = TA + P • [θJA – θJC]

where:

TJ, TA, TCASE = Junction, Ambient, and Case Temperature

θJC, θJA = Junction-to-Case and Junction-to-Ambient

Thermal Resistance, respectively

P = Maxi mu m Po w er Consumpt io n

The values for θJA and θJC are given in Table 23 for the

1.75 sq. in., 168-pin, ceramic PGA. For the 208-pin

SQFP plastic package, θJA = 14.0 and θJC = 1.5.

Table 24 an d Table 2 5 show th e T A allo wable (wi thout

exceeding TCASE of 85°C and 100°C, respectively) at

various airflows and operating frequencies (Clock). Note

that TA is greatly improve d by attachin g fins or a heat

sink to the package. P (the maximum power consump-

tion) is calculated by using the maximum ICC at 3.3 V as

tabulated in the

DC Characteristics

Note:

*0.350

″

high unidirectional heat sink (Al alloy 6063-T5, 40 mil fin width, 155 mil center-to-center fin spacing)

Table 23. Thermal Resistance (°C/W) θJC and θJA for the Enhanced Am486DX CPU in 168-Pin PGA Package

Cooling

Mechanism θJC

θJA vs. Airflow-Linear ft/min. (m/sec)

(0) 200

(1.01) 400

(2.03) 600

(3.04) 800

(4.06) 1000

(5.07)

No Heat Sink 1.5 16.5 14.0 12.0 10.5 9.5 9.0

Heat Sink* 2.0 12.0 7.0 5.0 4.0 3.5 3.25

Heat Sin k* and fan 2.0 5.0 4.6 4.2 3.8 3.5 3.25

Table 24. Maximum TA at Various Airflows in °C for Commercial Temperatures (85°C)

TA by Cooling Type Clock PGA: Airflow- ft/Min (m/sec) SQFP: No

Airflow

0 (0) 200 (1.01) 400 (2.03) 600 (3.0 4) 800 (4.06) 1000 (5.07)

TA without Heat Sink 133 MHz 38.9 46.6 52.7 57.3 60.4 62.0 45

TA with Heat Sink 133 MHz 54.3 69.6 75.8 78.9 80.4 81.2 66

TA with Heat Sink and Fan 133 MHz 75.8 77.0 78.2 79.5 80.4 81.2 82

TA without Heat Sink 100 MHz 50.4 56.1 60.7 64.2 66.5 67.7 55

TA with Heat Sink 100 MHz 61.9 73.5 78.1 80.4 81.5 82.1 71

TA with Heat Sink and Fan 100 MHz 78.1 79.0 79.9 80.8 81.5 82.1 83

TA without Heat Sink 66 MHz 62.1 65.9 69.0 71.3 72.8 73.6 65

TA with Heat Sink 66 MHz 69.8 77.4 80.4 82.0 82.7 83.1 75

TA with Heat Sink and Fan 66 MHz 80.4 81.0 81.6 82.3 82.7 83.1 83

Table 25. Maximum TA at Various Airflows in °C for Industrial Temperatures (100°C)

TA by Cooling Type Clock PGA: Airflow- ft/Min (m/sec) SQFP: No

Airflow

0 (0) 200 (1.01) 400 (2.03) 600 (3.0 4) 800 (4.06) 1000 (5.07)

TA without Heat Sink 100 MHz 65.4 71.1 75.7 79.2 81.5 82.7 70

TA with Heat Sink 100 MHz 76.9 88.5 93.1 95.4 96.5 97.1 86

TA with Heat Sink and Fan 100 MHz 93.1 94 94.9 95.8 96.5 97.1 98

TA without Heat Sink 66 MHz 77.1 80.9 84 86.3 87.8 88.6 80

TA with Heat Sink 66 MHz 84.8 92.4 95.4 97 97.7 98.1 90

TA with Heat Sink and Fan 66 MHz 95.4 96 96.6 97.3 97.7 98.1 98

Enhanced Am486DX Microprocessor Family 65

P R E L I M I N A R Y

13 PHYSICAL DIMENSIONS

168- Pin PGA ( C GM-168)

1.600

BSC

1.735

1.765

1.735

1.765

Bottom View (Pins Facing Up)

Base Plane

Seating Plane

0.140

0.180

0.110

0.140

0.105

0.125

0.017

0.020

Side View

0.025

0.045

1.600

BSC

Index

Corner

0.090

0.100

Notes:

1. All measurements are in inches.

2. Not to scale. For reference only.

3. BSC is an ANSI standard for Basic Space Centering.

66 Enhanced Am486DX Microprocessor Family

P R E L I M I N A R Y

208-Lead SQFP (PDE-208)

16-038-PRE-4

DY112

3-6-97 lv

Pin 1 I.D.

25.50

REF

27.90

28.10

30.40

30.80

Pin 104

Pin 208

3.29

3.45

0.50 BASIC

Pin 52

Pin 156

Pin 1

SEATING PLANE

0.25

0.42

3.70

MAX

27.90

28.10

30.40

30.80



18.00

3.0 R

REF. TYP

25.50

REF

Trademarks

AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.

Am486 is a registered trademark; and FusionE86 is a service mark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.