4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
1
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
4 MEG x 4 EDO DRAM PART NUMBERS
PART NUMBER Vcc REFRESH PACKAGE REFRESH
MT4LC4M4E8DJ 3.3V 2K SOJ Standard
MT4LC4M4E8DJS 3.3V 2K SOJ Self
MT4LC4M4E8TG 3.3V 2K TSOP Standard
MT4LC4M4E8TGS 3.3V 2K TSOP Self
MT4LC4M4E9DJ 3.3V 4K SOJ Standard
MT4LC4M4E9DJS 3.3V 4K SOJ Self
MT4LC4M4E9TG 3.3V 4K TSOP Standard
MT4LC4M4E9TGS 3.3V 4K TSOP Self
MT4C4M4E8DJ 5V 2K SOJ Standard
MT4C4M4E8DJS 5V 2K SOJ Self
MT4C4M4E8TG 5V 2K TSOP Standard
MT4C4M4E8TGS 5V 2K TSOP Self
MT4C4M4E9DJ 5V 4K SOJ Standard
MT4C4M4E9DJS 5V 4K SOJ Self
MT4C4M4E9TG 5V 4K TSOP Standard
MT4C4M4E9TGS 5V 4K TSOP Self
MT4LC4M4E8, MT4C4M4E8
MT4LC4M4E9, MT4C4M4E9
DRAM
FEATURES
• Industry-standard x4 pinout, timing, functions and
packages
• State-of-the-art, high-performance, low-power CMOS
silicon-gate process
• Single power supply (+3.3V ±0.3V or +5V ±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-
BEFORE-RAS# (CBR)
• Optional Self Refresh (S) for low-power data retention
• 11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)
• Extended Data-Out (EDO) PAGE MODE access cycle
• 5V-tolerant inputs and I/Os on 3.3V devices
OPTIONS MARKING
• Voltages
3.3V LC
5V C
• Refresh Addressing
2,048 (i.e. 2K) Rows E8
4,096 (i.e. 4K) Rows E9
• Packages
Plastic SOJ (300 mil) DJ
Plastic TSOP (300 mil) TG
• Timing
50ns access -5
60ns access -6
• Refresh Rates
Standard Refresh None
Self Refresh (128ms period) S
• Part Number Example: MT4LC4M4E8DJ-6
Note: The 4 Meg x 4 EDO DRAM base number differentiates the offerings in
two places - MT4LC4M4E8. The third field distinguishes the low voltage
offering: LC designates VCC = 3.3V and C designates VCC = 5V. The fifth field
distinguishes various options: E8 designates a 2K refresh and E9 designates a
4K refresh for EDO DRAMs.
PIN ASSIGNMENT (Top View)
24/26-Pin SOJ
(DA-2)
VCC
DQ1
DQ2
WE#
RAS#
*NC/A11
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
VSS
DQ4
DQ3
CAS#
OE#
A9
A8
A7
A6
A5
A4
VSS
V
CC
DQ1
DQ2
WE#
RAS#
*NC/A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
V
SS
DQ4
DQ3
CAS#
OE#
A9
A8
A7
A6
A5
A4
V
SS
24/26-Pin TSOP
(DB-2)
* NC on 2K refresh and A11 on 4K refresh options.
GENERAL DESCRIPTION
The 4 Meg x 4 DRAM is a randomly accessed, solid-state
memory containing 16,777,216 bits organized in a x4 con-
figuration. RAS# is used to latch the row address (first 11
bits for 2K and first 12 bits for 4K). Once the page has been
opened by RAS#, CAS# is used to latch the column address
KEY TIMING PARAMETERS
SPEED tRC tRAC tPC tAA tCAC tCAS
-5 84ns 50ns 20ns 25ns 13ns 8ns
-6 104ns 60ns 25ns 30ns 15ns 10ns
Note: The “#” symbol indicates signal is active LOW.
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
2
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
GENERAL DESCRIPTION (continued)
(the latter 11 bits for 2K and the latter 10 bits for 4K, address
pins A10 and A11 are “don’t care”). READ and WRITE
cycles are selected with the WE# input.
A logic HIGH on WE# dictates READ mode, while a logic
LOW on WE# dictates WRITE mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. An EARLY WRITE occurs
when WE# is taken LOW prior to CAS# falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE# falls
after CAS# is taken LOW. During EARLY WRITE cycles,
the data outputs (Q) will remain High-Z regardless of the
state of OE#. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE# must be taken HIGH to disable the data
outputs prior to applying input data. If a LATE WRITE or
READ-MODIFY-WRITE is attempted while keeping OE#
LOW, no write will occur, and the data outputs will drive
read data from the accessed location.
The four data inputs and the four data outputs are routed
through four pins using common I/O, and pin direction is
controlled by WE# and OE#.
PAGE ACCESS
PAGE operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row address-
defined page boundary. The PAGE cycle is always initiated
Figure 1
OE# CONTROL OF DQs
with a row address strobed-in by RAS#, followed by a
column address strobed-in by CAS#. CAS# may be
toggled-in by holding RAS# LOW and strobing-in different
column addresses, thus executing faster memory cycles.
Returning RAS# HIGH terminates the PAGE MODE of
operation, i.e., closes the page.
EDO PAGE MODE
The 4 Meg x 4 EDO DRAM provides EDO PAGE MODE,
which is an accelerated FAST PAGE MODE cycle. The
primary advantage of EDO is the availability of data-out
even after CAS# returns HIGH. EDO allows CAS# precharge
time (tCP) to occur without the output data going invalid.
This elimination of CAS# output control allows pipeline
READs.
FAST PAGE MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO PAGE MODE DRAMs operate like FAST
PAGE MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, pro-
vided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z (refer to
,,
,,,
V
VIH
IL
CAS#
V
VIH
IL
RAS#
V
VIH
IL
ADDR
,,
ROW
,,
,
COLUMN (A)
,,
,,,
,,
COLUMN (B)
,
,,,,
,,
DON’T CARE
UNDEFINED
,
,
,,
,,
V
VIH
IL
OE#
V
VIOH
IOL OPEN
DQ
tOD
VALID DATA (B)
VALID DATA (A)
,
COLUMN (C)
,,,
,,,
VALID DATA (A)
tOE
,,
VALID DATA (C)
,
COLUMN (D)
,,,
,,
,
VALID DATA (D)
tOD
tOEHC
tOD
tOEP
tOES
The DQs go back to
Low-Z if
t
OES is met. The DQs remain High-Z
until the next CAS# cycle
if
t
OEHC is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEP is met.
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
3
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
Figure 1). WE# can also perform the function of disabling
the output devices under certain conditions, as shown in
Figure 2.
During an application, if the DQ outputs are wire OR’d,
OE# must be used to disable idle banks of DRAMs. Alter-
natively, pulsing WE# to the idle banks during CAS# high
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after tOFF, which is refer-
enced from the rising edge of RAS# or CAS#, whichever
occurs last.
REFRESH
Preserve correct memory cell data by maintaining power
and executing any RAS# cycle (READ, WRITE) or RAS#
refresh cycle (RAS#-ONLY, CBR or HIDDEN) so that all
combinations of RAS# addresses (2,048 for 2K and 4,096 for
4K) are executed within tREF (MAX), regardless of se-
quence. The CBR and Self Refresh cycles will invoke the
internal refresh counter for automatic RAS# addressing.
An optional Self Refresh mode is also available on the S
version. The “S” option allows the user the choice of a fully
static, low-power data retention mode or a dynamic refresh
mode at the extended refresh period of 128ms. The optional
Self Refresh feature is initiated by performing a CBR Re-
fresh cycle and holding RAS# LOW for the specified tRASS.
Additionally, the “S” option allows for an extended refresh
period of 128ms, or 31.25µs per row for a 4K refresh and
62.5µs per row for a 2K refresh if using distributed CBR
Refresh. This refresh rate can be applied during normal
operation, as well as during a standby or BATTERY BACKUP
mode.
The Self Refresh mode is terminated by driving
RAS#
HIGH for a minimum time of tRPS. This delay allows for the
completion of any internal refresh cycles that may be in
process at the time of the
RAS# LOW-to-HIGH transition.
If the DRAM controller uses a distributed refresh se-
quence, a burst refresh is not required upon exiting
Self Refresh
. However, if the DRAM controller utilizes
a
RAS#-ONLY or
burst refresh sequence, all rows must be
refreshed within the average internal refresh rate
, prior to
the resumption of normal operation.
STANDBY
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is preconditioned for the next cycle during the
RAS# HIGH time.
Figure 2
WE# CONTROL OF DQs
,,
,,
V
VIH
IL
CAS#
V
VIH
IL
RAS#
V
VIH
IL
ADDR
,,
ROW
,,
,
COLUMN (A)
,,
,,,
,
DON’T CARE
UNDEFINED
,
,,
,,
,,
V
VIH
IL
WE#
V
VIOH
IOL OPEN
DQ
,
,
,
,,,
,
,,
,,
,,
,,
tWPZ
The DQs go to High-Z if WE# falls and, if
t
WPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
V
VIH
IL
OE#
,
,
VALID DATA (B)
tWHZ
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
tWHZ
COLUMN (D)
,,
,,,
,,,
VALID DATA (A)
COLUMN (B) COLUMN (C)
INPUT DATA (C)
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
4
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
FUNCTIONAL BLOCK DIAGRAM - 2K REFRESH
2048
2048
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
RAS#
11
11
11
NO. 2 CLOCK
GENERATOR
REFRESH
CONTROLLER
NO. 1 CLOCK
GENERATOR VDD
VSS
11
WE#
CAS#
10
COLUMN
ADDRESS
BUFFER(11)
ROW
ADDRESS
BUFFERS (11)
2048
ROW
DECODER
2048
1024
COLUMN
DECODER
OE#
DQ1
DQ2
DQ3
DQ4
4
4
4
4
REFRESH
COUNTER
1
ROW TRANSFER
(1 OF 2)
ROW TRANSFER
(1 OF 2)
1024
4096 x 1024 x 4
MEMORY
ARRAY
SENSE AMPLIFIERS
I/O GATING
DATA-OUT
BUFFER
DATA-IN
BUFFER
COMPLEMENT
SELECT
2048
ROW SELECT
(2 of 4096)
FUNCTIONAL BLOCK DIAGRAM - 4K REFRESH
4096
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
RAS#
12
12
10
NO. 2 CLOCK
GENERATOR
REFRESH
CONTROLLER
NO. 1 CLOCK
GENERATOR V
DD
V
SS
12
WE#
CAS#
10
COLUMN
ADDRESS
BUFFER(10)
ROW
ADDRESS
BUFFERS (12)
ROW
DECODER
4096
1024
COLUMN
DECODER
OE#
DQ1
DQ2
DQ3
DQ4
4
4
4
4
REFRESH
COUNTER
1024
4096 x 1024 x 4
MEMORY
ARRAY
SENSE AMPLIFIERS
I/O GATING
DATA-OUT
BUFFER
DATA-IN
BUFFER
COMPLEMENT
SELECT
4096
ROW SELECT
(1 of 4096)
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
5
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
TRUTH TABLE
ADDRESSES DATA-IN/OUT
FUNCTION RAS# CAS# WE# OE# tRtC DQ1-DQ4
Standby H H→XXXXX High-Z
READ L L H L ROW COL Data-Out
EARLY WRITE L L L X ROW COL Data-In
READ WRITE L L H→LL→H ROW COL Data-Out, Data-In
EDO-PAGE-MODE 1st Cycle L H→L H L ROW COL Data-Out
READ 2nd Cycle L H→L H L n/a COL Data-Out
EDO-PAGE-MODE 1st Cycle L H→L L X ROW COL Data-In
EARLY WRITE 2nd Cycle L H→L L X n/a COL Data-In
Any Cycle L L→H H L n/a n/a Data-Out
EDO-PAGE-MODE 1st Cycle L H→LH→LL→H ROW COL Data-Out, Data-In
READ-WRITE 2nd Cycle L H→LH→LL→H n/a COL Data-Out, Data-In
HIDDEN READ L→H→L L H L ROW COL Data-Out
REFRESH WRITE L→H→L L L X ROW COL Data-In
RAS#-ONLY REFRESH L H X X ROW n/a High-Z
CBR REFRESH H→L L H X X X High-Z
SELF REFRESH H→L L H X X X High-Z
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
6
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Pin Relative to VSS:
3.3V ................................................................ -1V to +4.6V
5V ...................................................................... -1V to +7V
Voltage on NC, Inputs or I/O Pins Relative to VSS:
3.3V ................................................................ -1V to +5.5V
5V ...................................................................... -1V to +7V
Operating Temperature, TA (ambient) .......... 0°C to +70°C
Storage Temperature (plastic).................... -55°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
*Stresses greater than those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1)
3.3V 5V
PARAMETER/CONDITION SYMBOL MIN MAX MIN MAX UNITS NOTES
Supply Voltage VCC 3.0 3.6 4.5 5.5 V
Input High Voltage:
Valid Logic 1; all inputs, I/Os and any NC VIH 2.0 5.5 2.4 VCC +1 V
Input Low Voltage:
Valid Logic 0; all inputs, I/Os and any NCVIL-1.00.8-0.5 0.8V
Input Leakage Current:
Any input at VIN (0V ≤ VIN ≤ VIH [MAX]);II-2 2 -2 2 µA 4
all other pins not under test = 0V
Output High Voltage:
IOUT = -2mA (3.3V), -5mA (5V) VOH 2.4 - 2.4 - V
Output Low Voltage:
IOUT = 2mA (3.3V), 4.2mA (5V) VOL - 0.4 - 0.4 V
Output Leakage Current:
Any output at VOUT (0V ≤ VOUT ≤ 5.5V); IOZ -5 5 -5 5 µA
DQ is disabled and in High-Z state
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
7
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
Icc OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3)
3.3V 5V
2K 4K 2K 4K
PARAMETER/CONDITION SYM SPEED Refresh Refresh Refresh Refresh UNITS NOTES
STANDBY CURRENT: TTL ICC1ALL1111mA
(RAS# = CAS# = VIH)
STANDBY CURRENT: CMOS (non-S version only) ICC2ALL 500 500 500 500 µA
(RAS# = CAS# = other inputs = VCC -0.2V)
STANDBY CURRENT: CMOS (S version only) ICC2ALL 150 150 150 150 µA
(RAS# = CAS# = other inputs = VCC -0.2V)
OPERATING CURRENT: Random READ/WRITE -5 110 90 140 120 mA 5, 6
Average power supply current ICC3-6 100 80 130 110
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
OPERATING CURRENT: EDO PAGE MODE -5 110 100 110 100 mA 5, 6
Average power supply current (RAS# = VIL,ICC4-6 100 90 100 90
CAS#, address cycling: tPC = tPC [MIN])
REFRESH CURRENT: RAS#-ONLY -5 110 90 140 120 mA 5, 6
Average power supply current ICC5-6 100 80 130 110
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
REFRESH CURRENT: CBR -5 110 90 140 120 mA 5, 7
Average power supply current ICC6-6 100 80 130 110
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
REFRESH CURRENT: Extended (S version only)
Average power supply current: CAS# = 0.2V or ALL 300 300 300 300 µA 5, 7
CBR cycling; RAS# = tRAS (MIN); WE# = ICC7
VCC -0.2V; A0-A11,OE# and DIN = VCC -0.2V or tRC 62.5 31.25 62.5 31.25 µs25
0.2V (DIN may be left open)
REFRESH CURRENT: Self (S version only)
Average power supply current: CBR with
RAS# ≥ tRASS (MIN) and CAS# held LOW; WE# = ICC8ALL 300 300 300 300 µA 5, 7
VCC -0.2V; A0-A11, OE# and DIN = VCC -0.2V
or 0.2V (DIN may be left open)
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
8
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
AC ELECTRICAL CHARACTERISTICS
(Notes: 2, 3, 9, 10, 11, 12, 17) (VCC [MIN] ≤ VCC ≤ VCC [MAX])
AC CHARACTERISTICS -5 -6
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Access time from column address tAA 25 30 ns
Column address setup to CAS# precharge tACH 12 15 ns
Column address hold time (referenced to RAS#) tAR 38 45 ns
Column address setup time tASC 0 0 ns
Row address setup time tASR 0 0 ns
Column address to WE# delay time tAWD 42 49 ns 13
Access time from CAS# tCAC 13 15 ns 14
Column address hold time tCAH 8 10 ns
CAS# pulse width tCAS 8 10,000 10 10,000 ns
CAS# LOW to “don’t care” during Self Refresh tCHD 15 15 ns
CAS# hold time (CBR Refresh) tCHR 8 10 ns 7
CAS# to output in Low-Z tCLZ 0 0 ns
Data output hold after next CAS# LOW tCOH 3 3 ns
CAS# precharge time tCP 8 10 ns 15
Access time from CAS# precharge tCPA 28 35 ns
CAS# to RAS# precharge time tCRP 5 5 ns
CAS# hold time tCSH 38 45 ns
CAS# setup time (CBR Refresh) tCSR 5 5 ns
CAS# to WE# delay time tCWD 28 35 ns 13
Write command to CAS# lead time tCWL 8 10 ns
Data-in hold time tDH 8 10 ns 16
Data-in setup time tDS 0 0 ns 16
Output disable tOD 0 12 0 15 ns
Output Enable tOE 12 15 ns 17
OE# hold time from WE# during tOEH 8 10 ns 18
READ-MODIFY-WRITE cycle
OE# HIGH hold from CAS# HIGH tOEHC 5 10 ns 18
OE# HIGH pulse width tOEP 5 5 ns
OE# LOW to CAS# HIGH setup time tOES 4 5 ns
Output buffer turn-off delay tOFF 0 12 0 15 ns 20
CAPACITANCE
PARAMETER SYMBOL MAX UNITS NOTES
Input Capacitance: Address pins CI15pF8
Input Capacitance: RAS#, CAS#, WE#, OE# CI27pF8
Input/Output Capacitance: DQ CIO 7pF8
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
9
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
AC ELECTRICAL CHARACTERISTICS
(Notes: 2, 3, 9, 10, 11, 12, 17) (VCC [MIN] ≤ VCC ≤ VCC [MAX])
AC CHARACTERISTICS -5 -6
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
OE# setup prior to RAS# during tORD 0 0 ns
HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time tPC 20 25 ns
EDO-PAGE-MODE READ-WRITE cycle time tPRWC 47 56 ns
Access time from RAS# tRAC 50 60 ns 19
RAS# to column address delay time tRAD 9 12 ns 21
Row address hold time tRAH 9 10 ns
RAS# pulse width tRAS 50 10,000 60 10,000 ns
RAS# pulse width (EDO PAGE MODE) tRASP 50 125,000 60 125,000 ns
RAS# pulse width during Self Refresh tRASS 100 100 µs
Random READ or WRITE cycle time tRC 84 104 ns
RAS# to CAS# delay time tRCD 11 14 ns 22
Read command hold time (referenced to CAS#) tRCH 0 0 ns 23
Read command setup time tRCS 0 0 ns
Refresh period (2,048 cycles) tREF 32 32 ms
Refresh period (4,096 cycles) tREF 64 64 ms
Refresh period S version tREF 128 128 ms
RAS# precharge time tRP 30 40 ns
RAS# to CAS# precharge time tRPC 5 5 ns
RAS# precharge time exiting Self Refresh tRPS 90 105 ns
Read command hold time (referenced to RAS#) tRRH 0 0 ns 23
RAS# hold time tRSH 13 15 ns
READ WRITE cycle time tRWC 116 140 ns
RAS# to WE# delay time tRWD 67 79 ns 13
Write command to RAS# lead time tRWL 13 15 ns
Transition time (rise or fall) tT250250ns
Write command hold time tWCH 8 10 ns
Write command hold time (referenced to RAS#) tWCR 38 45 ns
WE# command setup time tWCS 0 0 ns 13
Output disable delay from WE# tWHZ 0 12 0 15 ns
Write command pulse width tWP 5 5 ns
WE# pulse to disable at CAS# HIGH tWPZ 10 10 ns
WE# hold time (CBR Refresh) tWRH 8 10 ns
WE# setup time (CBR Refresh) tWRP 8 10 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
10
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
NOTES
1. All voltages referenced to VSS.
2. The minimum specifications are used only to indicate
cycle time at which proper operation over the full
temperature range (0˚C ≤ TA ≤ 70˚C) is ensured.
3. An initial pause of 100µs is required after power-up,
followed by eight RAS# refresh cycles (RAS#-ONLY
or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the tREF refresh
requirement is exceeded.
4. NC pins are assumed to be left floating and are not
tested for leakage.
5. ICC is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
6. Column address changed once each cycle.
7. Enables on-chip refresh and address counters.
8. This parameter is sampled. VCC = VCCMIN; f = 1 MHz.
9. AC characteristics assume tT = 2.5ns.
10. VIH (MIN) and VIL (MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between VIH and VIL (or between VIL
and VIH).
11. In addition to meeting the transition rate specifica-
tion, all input signals must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
12. Measured with a load equivalent to two TTL gates
and 100pF; and VOL = 0.8V and VOH = 2V.
13. tWCS, tRWD, tAWD and tCWD are not restrictive
operating parameters. tWCS applies to EARLY
WRITE cycles. tRWD, tAWD and tCWD apply to
READ-MODIFY-WRITE cycles. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If tWCS < tWCS (MIN) and tRWD ≥
tRWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥
tCWD (MIN), the cycle is a READ-MODIFY-WRITE
and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE# held HIGH
and WE# taken LOW after CAS# goes LOW results in
a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD,
tCWD and tAWD are not applicable in a LATE
WRITE cycle.
14. Requires that tAA and tRAC are not violated.
15. If CAS# is LOW at the falling edge of RAS#, Q will be
maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for tCP.
16. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading edge
in LATE WRITE or READ-MODIFY-WRITE cycles.
17. If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not permis-
sible and should not be attempted. Additionally, WE#
must be pulsed during CAS# HIGH time in order to
place I/O buffers in High-Z.
18. LATE WRITE and READ-MODIFY-WRITE cycles
must have both tOD and tOEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE cycle.
The DQs will provide the previously read data if
CAS# remains LOW and OE# is taken back LOW
after tOEH is met. If CAS# goes HIGH prior to OE#
going back LOW, the DQs will remain open.
19. Requires that tAA and tCAC are not violated.
20. tOFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to VOH or VOL. It is referenced from the
rising edge of RAS# or CAS#, whichever occurs last.
21. The tRAD (MAX) limit is no longer specified. tRAD
(MAX) was specified as a reference point only. If
tRAD was greater than the specified tRAD (MAX)
limit, then access time was controlled exclusively by
tAA (tRAC and tCAC no longer applied). With or
without the tRAD (MAX) limit, tAA, tRAC and tCAC
must always be met.
22. The tRCD (MAX) limit is no longer specified. tRCD
(MAX) was specified as a reference point only. If
tRCD was greater than the specified tRCD (MAX)
limit, then access time was controlled exclusively by
tCAC (tRAC [MIN] no longer applied). With or
without the tRCD limit, tAA and tCAC must always
be met.
23. Either tRCH or tRRH must be satisfied for a READ
cycle.
24. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# is LOW and
OE# is HIGH.
25. The refresh period is extended from 32ms (2K refresh)
or 64ms (4K refresh) to 128ms (both 2K and 4K
refreshes). For 4K refresh, tRC = 31.25µs (128ms/
4,096 rows = 31.25µs) and for 2K refresh, tRC = 62.5µs
(128ms/2,048 rows = 62.5µs).
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
11
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
READ CYCLE
,,
,
,,
,,
,,,
,,
,
,
tRRH
,
,,,
,,
tCLZ
tCAC
tRAC
tAA
VALID DATA OPEN
tOFF
tRCH
ROW
tRCS
tASC
tRAH
tRAD
tAR
tCAH
tRCD tCAS
tRSH
tCSH
tRP
tRC
tRAS
tCRP
tASR
ROW
OPEN
RAS# V
VIH
IL
V
VIH
IL
ADDR V
VIH
IL
DQ V
VOH
OL
V
VIH
IL
,,,
,,,,
,,,
,,
tOD
tOE
OE# V
VIH
IL
COLUMN
,,,
,,,,
,,
CAS#
WE#
,,
,,,
,,,
NOTE 1
tACH
DON’T CARE
UNDEFINED
,
,
,
NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tOFF 0 12 0 15 ns
tRAC 50 60 ns
tRAD 9 12 ns
tRAH 9 10 ns
tRAS 50 10,000 60 10,000 ns
tRC 84 104 ns
tRCD 11 14 ns
tRCH 0 0 ns
tRCS 0 0 ns
tRP 30 40 ns
tRRH 0 0 ns
tRSH 13 15 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tAA 25 30 ns
tACH 12 15 ns
tAR 38 45 ns
tASC 0 0 ns
tASR 0 0 ns
tCAC 13 15 ns
tCAH 8 10 ns
tCAS 8 10,000 10 10,000 ns
tCLZ 0 0 ns
tCRP 5 5 ns
tCSH 38 45 ns
tOD 0 12 0 15 ns
tOE 12 15 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
12
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EARLY WRITE CYCLE
DON’T CARE
UNDEFINED
,
,,
,,,
,,,
,,,
,,,
,,
,,
V
VIH
IL
,,
,
,
,,,
,,
,,
,,,
,,,
,,
VALID DATA
ROW
COLUMNROW
tDS
tWP
tWCH
tWCS
tWCR
tRWL
tCWL
tCAH
tASC
tRAH
tASR
tRAD
tAR
tCAS
tRSH
tCSH
tRCD
tCRP
tRAS
tRC tRP
V
VIH
IL
ADDR V
VIH
IL
V
VIH
IL
DQ V
VIOH
IOL
V
VIH
IL
RAS#
OE#
,,
,,,
,,
,,,
,,,
,,,
,,,
,,,
,,
,,
,,,
,,,
,,,
tDH
WE#
CAS#
tACH
,,,
,,,
,,
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tRAH 9 10 ns
tRAS 50 10,000 60 10,000 ns
tRC 84 104 ns
tRCD 11 14 ns
tRP 30 40 ns
tRSH 13 15 ns
tRWL 13 15 ns
tWCH 8 10 ns
tWCR 38 45 ns
tWCS 0 0 ns
tWP 5 5 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tACH 12 15 ns
tAR 38 45 ns
tASC 0 0 ns
tASR 0 0 ns
tCAH 8 10 ns
tCAS 8 10,000 10 10,000 ns
tCRP 5 5 ns
tCSH 38 45 ns
tCWL 8 10 ns
tDH 8 10 ns
tDS 0 0 ns
tRAD 9 12 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
13
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
,,,
,,,
,
,
,
VALID DOUT VALID DIN
,,
,,
,,
,,
ROW
,,,
,,,
,,
COLUMN ROW
,,
,,,
,,,
,,,,
,
V
VIH
IL
V
VIH
IL
ADDR V
VIH
IL
V
VIH
IL
DQ V
VIOH
IOL
V
VIH
IL
RAS#
OPENOPEN
tOE tOD
tCAC
tRAC
tAA
tCLZ tDS tDH
tAWD tWP
tRWL
tCWL
tCWD
tRWD
tRCS
tASC tCAH
tAR
tASR
tRAD
tCRP tRCD tCAS
tRSH
tCSH
tRAS
tRWC tRP
tRAH
OE#
tOEH
,
,,,
,,,
WE#
tACH
CAS#
DON’T CARE
UNDEFINED
,,
,,
,
,,
,,,,
,,
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tOD 0 12 0 15 ns
tOE 12 15 ns
tOEH 8 10 ns
tRAC 50 60 ns
tRAD 9 12 ns
tRAH 9 10 ns
tRAS 50 10,000 60 10,000 ns
tRCD 11 14 ns
tRCS 0 0 ns
tRP 30 40 ns
tRSH 13 15 ns
tRWC 116 140 ns
tRWD 67 79 ns
tRWL 13 15 ns
tWP 5 5 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tAA 25 30 ns
tACH 12 15 ns
tAR 38 45 ns
tASC 0 0 ns
tAWD 42 49 ns
tASR 0 0 ns
tCAC 13 15 ns
tCAH 8 10 ns
tCAS 8 10,000 10 10,000 ns
tCLZ 0 0 ns
tCRP 5 5 ns
tCSH 38 45 ns
tCWD 28 35 ns
tCWL 8 10 ns
tDH 8 10 ns
tDS 0 0 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
14
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE READ CYCLE
,
,
,,,
,,,
,,,
,,,
,,
,
,
VALID
DATA
,,
,,
VALID
DATA
,
,
VALID
DATA
,,
,
,,
,
,,
,,
,
,,
,,,
,
COLUMNCOLUMNCOLUMNROW ROW
DON’T CARE
UNDEFINED
,,
,
tOD
tCAH
tASC
tCP
tRSH
tCP
tCP
tCAS
tRCD
tCRP
tPC
tCSH
tRASP tRP
tCAH
tASC
tCAH
tASC
tAR
tRAH
tRAD
tASR
tRCS
tRRH
tRCH
tOFF
tCAC
tCPA
tAA
tCLZ
tCAC
tCPA
tAA
tCAC
tRAC
tAA
tCLZ
tOE tOD tOE tOD
OPENOPEN
V
VIH
IL
V
VIH
IL
ADDR V
VIH
IL
V
VIH
IL
DQ V
VOH
OL
V
VIH
IL
RAS#
OE#
tCAS tCAS
CAS#
WE#
tCOH
tOEP
tOEHC
tOES
tOES
tACH
tACH tACH
,,
,,,,
,,
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tOEHC 5 10 ns
tOEP 5 5 ns
tOES 4 5 ns
tOFF 0 12 0 15 ns
tPC 20 25 ns
tRAC 50 60 ns
tRAD 9 12 ns
tRAH 9 10 ns
tRASP 50 125,000 60 125,000 ns
tRCD 11 14 ns
tRCH 0 0 ns
tRCS 0 0 ns
tRP 30 40 ns
tRRH 0 0 ns
tRSH 13 15 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tAA 25 30 ns
tACH 12 15 ns
tAR 38 45 ns
tASC 0 0 ns
tASR 0 0 ns
tCAC 13 15 ns
tCAH 8 10 ns
tCAS 8 10,000 10 10,000 ns
tCLZ 0 0 ns
tCOH 3 3 ns
tCP 8 10 ns
tCPA 28 35 ns
tCRP 5 5 ns
tCSH 38 45 ns
tOD 0 12 0 15 ns
tOE 12 15 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
15
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE EARLY WRITE CYCLE
,,
,,,
,
,,
,,
,,
,,
,,
,
,,
,,
,
,
,,
,
,,
,
,,,
,,
,,
,
,
,,
,,,
,,,
,
tDS tDH tDS tDH tDS tDH
tWCR
VALID DATA VALID DATA VALID DATA
tRWL
tWP
tCWL
tWCH
tWCS
tWP
tCWL
tWCH
tWCS
tWP
tCWL
tWCH
tWCS
tCAH
tASC
tCAH
tASC
tCAH
tASC
tRAH
tASR
tRAD tACH tACH tACH
tAR
COLUMNCOLUMNCOLUMNROW ROW
tCP
tCAS
tRSH
tCP
tCAS
tCP
tCAS
tRCD
tCRP
tPC
tCSH
tRASP tRP
V
VIH
IL
CAS# V
VIH
IL
ADDR V
VIH
IL
WE# V
VIH
IL
DQ V
VIOH
IOL
RAS#
OE# V
VIH
IL
,,,
,,,
,,,
,,,,
,,,,
,,,
,,,
,,
DON’T CARE
UNDEFINED
,
,
,
,
,
,,,
,,
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tPC 20 25 ns
tRAD 9 12 ns
tRAH 9 10 ns
tRASP 50 125,000 60 125,000 ns
tRCD 11 14 ns
tRP 30 40 ns
tRSH 13 15 ns
tRWL 13 15 ns
tWCH 8 10 ns
tWCR 38 45 ns
tWCS 0 0 ns
tWP 5 5 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tACH 12 15 ns
tAR 38 45 ns
tASC 0 0 ns
tASR 0 0 ns
tCAH 8 10 ns
tCAS 8 10,000 10 10,000 ns
tCP 8 10 ns
tCRP 5 5 ns
tCSH 38 45 ns
tCWL 8 10 ns
tDH 8 10 ns
tDS 0 0 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
16
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
,,
,,,
,,,,
,
,,
,,
,,
,,
,
,
,
,
,,
,,
,,
,,
,,
,,,
,
DON’T CARE
UNDEFINED
,,
,,
,
,,
,,
tOE
tOE
tOE
OPEN
DOUT
VALID DIN
VALID DOUT
VALID DIN
VALID DOUT
VALID DIN
VALID
OPEN
tDH
tDS
tAA
tCPA
tCLZ
tCAC
tDH
tDS
tAA
tCPA
tCLZ
tCAC
tDH
tDS
tAA
tCLZ
tCAC
tRAC
tWP
tCWL
tRWL
tCWD
tAWD
tWP
tCWL
tCWD
tAWD
tWP
tCWL
tCWD
tAWD
tRCS
tRWD
tASR tRAH tASC
tRAD
tAR
tCAH tASC tCAH tASC tCAH
tCP tCAS
tRSH tCP
tRP
tRASP
tCAS
tCP
tCAS
tRCD
tCSH tPC
tCRP
ROW COLUMN COLUMN COLUMN ROW
V
VIH
IL
CAS# V
VIH
IL
ADDR V
VIH
IL
V
VIH
IL
DQ V
VIOH
IOL
V
VIH
IL
RAS#
OE#
WE#
tPRWC
,
,,,
tOEH
tOD tOD tOD
NOTE 1
,,
,,,
,
NOTE: 1. tPC is for LATE WRITE cycles only.
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tOD 0 12 0 15 ns
tOE 12 15 ns
tOEH 8 10 ns
tPC 20 25 ns
tPRWC 47 56 ns
tRAC 50 60 ns
tRAD 9 12 ns
tRAH 9 10 ns
tRASP 50 125,000 60 125,000 ns
tRCD 11 14 ns
tRCS 0 0 ns
tRP 30 40 ns
tRSH 13 15 ns
tRWD 67 79 ns
tRWL 13 15 ns
tWP 5 5 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tAA 25 30 ns
tAR 38 45 ns
tASC 0 0 ns
tASR 0 0 ns
tAWD 42 49 ns
tCAC 13 15 ns
tCAH 8 10 ns
tCAS 8 10,000 10 10,000 ns
tCLZ 0 0 ns
tCP 8 10 ns
tCPA 28 35 ns
tCRP 5 5 ns
tCSH 38 45 ns
tCWD 28 35 ns
tCWL 8 10 ns
tDH 8 10 ns
tDS 0 0 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
17
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
V
VIH
IL
V
VIH
IL
RAS#
V
VIH
IL
ADDR
V
VIH
IL
WE#
,,
tRASP tRP
ROW
,,
COLUMN (A)
,,
,
COLUMN (N)
,,
,,
ROW
V
VIH
IL
OE#
V
VIOH
IOL
tCRP
tCSH
tCAS
tRCD
tASR tRAH
tRAD tASC
tAR
tCAH tASC tCAH tASC tCAH
tCP
tRSH
VALID DATA
IN
,,,
,,,,
,,
,
,,
,
tRCS tRCH tWCS
tOE
VALID
DATA (B)
VALID DATA (A)
tWHZ
tCAC
tCPA
tAA
tCAC
tAA
OPEN
DQ
tPC
RAC
t
tCOH
tWCH
tDS tDH
tPC
COLUMN (B)
tACH
CAS#
tCAS
tCAS
tCP tCP
DON’T CARE
UNDEFINED
,,
,
,,
,,,
,
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tOE 12 15 ns
tPC 20 25 ns
tRAC 50 60 ns
tRAD 9 12 ns
tRAH 9 10 ns
tRASP 50 125,000 60 125,000 ns
tRCD 11 14 ns
tRCH 0 0 ns
tRCS 0 0 ns
tRP 30 40 ns
tRSH 13 15 ns
tWCH 8 10 ns
tWCS 0 0 ns
tWHZ 0 12 0 15 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tAA 25 30 ns
tACH 12 15 ns
tAR 38 45 ns
tASC 0 0 ns
tASR 0 0 ns
tCAC 13 15 ns
tCAH 8 10 ns
tCAS 8 10,000 10 10,000 ns
tCOH 3 3 ns
tCP 8 10 ns
tCPA 28 35 ns
tCRP 5 5 ns
tCSH 38 45 ns
tDH 8 10 ns
tDS 0 0 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
18
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
READ CYCLE
(With WE#-controlled disable)
,,
,
,,
,
,
,
,,,
,,
tCLZ
tCAC
tRAC
tAA
VALID DATA OPEN
tRCH
tRCS
tASC
tRAH
tRAD
tAR
tCAH
tRCD tCAS
tCSH
tCRP
tASR
ROW
OPEN
RAS# V
VIH
IL
V
VIH
IL
ADDR V
VIH
IL
DQ V
VOH
OL
V
VIH
IL
,,,
,,,,
,,,
,,
tOD
tOE
OE# V
VIH
IL
COLUMN
,,,
,,,,
,
WE#
tWHZ
tWPZ
tCP
tASC
tRCS
COLUMN
,
tCLZ
DON’T CARE
UNDEFINED
,,
,
CAS#
,,
,,,
,,,
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tAA 25 30 ns
tAR 38 45 ns
tASC 0 0 ns
tASR 0 0 ns
tCAC 13 15 ns
tCAH 8 10 ns
tCAS 8 10,000 10 10,000 ns
tCLZ 0 0 ns
tCP 8 10 ns
tCRP 5 5 ns
tCSH 38 45 ns
tOD 0 12 0 15 ns
tOE 12 15 ns
tRAC 50 60 ns
tRAD 9 12 ns
tRAH 9 10 ns
tRCD 11 14 ns
tRCH 0 0 ns
tRCS 0 0 ns
tWHZ 0 12 0 15 ns
tWPZ 10 10 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
19
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
RAS#-ONLY REFRESH CYCLE
(OE# and WE# = DON’T CARE)
,,,
,,,
,,,,
,
,,
ROW
V
VIH
IL
CAS# V
VIH
IL
ADDR V
VIH
IL
RAS#
tRC
tRAS tRP
tCRP
tASR tRAH
ROW
OPEN
DQ V
VOH
OL
tRPC
CBR REFRESH CYCLE
(Addresses and OE# = DON’T CARE)
tRP
V
VIH
IL
RAS#
tRAS
OPEN
tCHR
tCSR
V
VIH
IL
V
VOH
OL
CAS#
DQ
tRP tRAS
tRPC
tCSR
tRPC tCHR
tCP
V
VIH
IL
tWRP tWRH
,
,,,
,,,
,
,,,
,,
,,
,,,
,,
WE#
tWRP tWRH
DON’T CARE
UNDEFINED
,,
,,
,
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tRAS 50 10,000 60 10,000 ns
tRC 84 104 ns
tRP 30 40 ns
tRPC 5 5 ns
tWRH 8 10 ns
tWRP 8 10 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tASR 0 0 ns
tCHR 8 10 ns
tCP 8 10 ns
tCRP 5 5 ns
tCSR 5 5 ns
tRAH 9 10 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
20
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
HIDDEN REFRESH CYCLE 24
(WE# = HIGH; OE# = LOW)
,
,
DON’T CARE
UNDEFINED
,,
,
tCLZ
tOFF
,
,,,
,,,
,,,
,,,
,,
,,
,,
,
,
OPENVALID DATAOPEN
COLUMNROW
tCAC
tRAC
tAA
tCAH
tASC
tRAH
tASR
tRAD
tAR
tCRP tRCD tRSH
tRAS tRP
tCHR
tRAS
DQ V
VOH
OL
V
VIH
IL
ADDR
V
VIH
IL
V
VIH
IL
RAS#
,
,,,
,,,,
,,,
V
VIH
IL
tOE tOD
OE# tORD
,
,,,
,,
CAS#
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tOE 12 15 ns
tOFF 0 12 0 15 ns
tORD 0 0 ns
tRAC 50 60 ns
tRAD 9 12 ns
tRAH 9 10 ns
tRAS 50 10,000 60 10,000 ns
tRCD 11 14 ns
tRP 30 40 ns
tRSH 13 15 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tAA 25 30 ns
tAR 38 45 ns
tASC 0 0 ns
tASR 0 0 ns
tCAC 13 15 ns
tCAH 8 10 ns
tCHR 8 10 ns
tCLZ 0 0 ns
tCRP 5 5 ns
tOD 0 12 0 15 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
21
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
SELF REFRESH CYCLE
(Addresses and OE# = DON’T CARE)
V
VIH
IL
RAS#
tRASS
OPEN
V
VIH
IL
V
VOH
OL
DQ
tRPC
tCHD
tRPS
tRPC
tRP
tCP
CAS#
,
,,,
,,
WE# V
VIH
IL
tWRH
tWRP
,,
,,
,,,
,,,,
,,,,
,,
tWRH
tWRP
()()
()()
()()
()()
()()()()
NOTE 1
tCSR
,,
,,,,
,,,
,,,
,,,
,
,,
,,
DON'T CARE
UNDEFINED
tCP
NOTE 2
()()
()()
NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter Self Refresh mode.
2. Once tRPS is satisfied, a complete burst of all rows should be executed.
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tRPC 5 5 ns
tRPS 90 105 ns
tWRH 8 10 ns
tWRP 8 10 ns
TIMING PARAMETERS
-5 -6
SYMBOL MIN MAX MIN MAX UNITS
tCHD 15 15 ns
tCP 8 10 ns
tCSR 5 5 ns
tRASS 100 100 µs
tRP 30 40 ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
22
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
24/26-PIN PLASTIC SOJ (300 mil)
DA-2
R
.299 (7.59)
.305 (7.75)
.679 (17.25)
.673 (17.09)
.340 (8.64)
.330 (8.38)
.050 (1.27) TYP
.600 (15.24) TYP
PIN #1 INDEX
.020 (0.51)
.015 (0.38)
.132 (3.35)
.142 (3.61)
.109 (2.77)
.094 (2.39) .260 (6.60)
.275 (6.99)
.030 (0.76)
.040 (1.02)
SEATING PLANE
.025 (0.64)
MIN
.037 (0.94) MAX
DAMBAR PROTRUSION .026 (0.66)
.032 (0.81)
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
23
4 MEG x 4
EDO DRAM
TECHNOLOGY, INC.
24/26-PIN PLASTIC TSOP (300 mil)
DB-2
.047 (1.20)
MAX
.367 (9.32)
.359 (9.12)
.302 (7.67)
.298 (7.57)
.050 (1.27)
TYP
.678 (17.23)
.672 (17.07)
.020 (0.50)
.012 (0.30)
PIN #1 INDEX
.037 (0.95)
SEE DETAIL A
.007 (0.18)
.005 (0.13)
.004 (0.10)
.024 (0.60)
.016 (0.40)
.006 (0.15)
.002 (0.05)
DETAIL A
.010 (0.25)
.032 (0.80)
TYP
GAGE PLANE
SEATING PLANE
NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900, Micron DataFax: 208-368-5800
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
